Compal LA-8711P PAGANI, ENVY M6 Schematic

A

1 1

B

C

D

E

2 2

Compal Confidential

PAGANI M/B Schematics Document

Intel Ivy Bridge Processor with DDRIII + Panther Point

Date : 2011/11/22

3 3

Version 0.1

4 4

Security Classification

Security Classification

Security Classification

Issued Date

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Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/06/29 2011/06/29

2011/06/29 2011/06/29

2011/06/29 2011/06/29

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

LA-8711

LA-8711

LA-8711

E

0.1

0.1

1 57Sunday, November 27, 2011

1 57Sunday, November 27, 2011

1 57Sunday, November 27, 2011

0.1

A

Compal Confidential

Model Name : Zonda

B

C

D

E

1 1

File Name : LA8711P

2011/11/22

64Mx16
128Mx16

VRAMx8pcs

DDRIII

page27 ~ 29

128Bit

AMD

Chelsea Pro

25W

page21 ~ 26

PEG 2.0 x16

Intel

IVY Bridge

SV Processor

rPGA 988B

31mm*24mm

page4 ~ 10

DMI x4FDI x8

Accelerometer

page42

HP3DC2

HDMI Conn.

page29 page32

FAN conn.

2 2

page37

X1

X1

LVDS Conn.

PCI-Express x 2 (PCIE2.0 5GT/s)

SATAx3

X1

GEN1 1.5Gb/S GEN3 6Gb/S

LVDS(1Ch)

HDMI

X1

GEN3 6Gb/S

100MHz

100MHz

X1

100MHz

2.7GT/s

Intel

Panther Point

PCH

989pin BGA

25mm*25mm

100MHz

5GT/s

page13 ~ 20

DDR3 1333/1600MHz 1.5V
DDR3L 1333MHz 1.35V

Dual Channel

USB3.0 x2

3.0 port1,2

X2

USB 3.0 x3

USB 2.0 x4

HD Audio

SPI

page35

HD webcam

DDR3-SO-DIMM X 2

BANK 0, 1, 2, 3

page11 ~ 12

HDD LED & PWR LED

USB3.0 x1

3.0 port3

X1

X1

port8

D-MIC(daul)

ModuleModule

Daughter board

USB2.0 x1
USB charger

X1

X1

port3

Finger print

port9

HDA Codec

port2

Card Reader
/LAN controller
RTL8411

3 3

RJ45

page34 page34

SD socket

WLAN&BT
(mini card)

port 10

JMINI1

page31

X1

port2

SATA ODD

page33 page33 page33page34

port1

m-SATA
(mini card)

JMINI2

port0port1

SATA HDD

USB 2.0 x1

LPC BUS

33MHz

BIOS SPI ROM,
8MB

page33

SPK conn HP Amp

IDT 92HD91

page41

page38

Sub Woofer Amp
HPA2011

page40

Sub Woofer
conn

page35

page39

HPA00929

HP&MIC
Combo jack

page41

ENE KB932

page36

CRT

page30

SM bus

PS2 SPI

LED

RTC CKT.

DC/DC interface CKT.

4 4

ODD connector board

A

page37

page14

page43

Daughter board

Lid switch FAN/LED

Power On/Off CKT.

& PWR BTN LED

B

Daughter board

Touch Pad

TP BTN on daughter board

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

Int.KBD

2011/06/29 2011/06/29

2011/06/29 2011/06/29

2011/06/29 2011/06/29

EC ROM,
256kB

page36 page37page37page37

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

LA-8711

LA-8711

LA-8711

E

2 57Sunday, November 27, 2011

2 57Sunday, November 27, 2011

2 57Sunday, November 27, 2011

0.1

0.1

0.1

A

B

C

D

E

Voltage Rails

V

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON

ONONON ON

ON

OFF

OFF

Address

1010 0110b

HIGH HIGH HIGH HIGH

LOW

LOW

LOW LOW LOW LOW

Address

0001 011X b

0101001b

1010 0000b

HP AMP

LOW

HIGHHIGHHIGH

HIGH

HIGH

LOWLOWLOW

HIGH

EC SM Bus2 address

Device

PCH (Reserve)

V

SATA

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

UMA

DIS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

DESTINATION

HDD,JHDD1

m-SATA,JMINI2

ODD, JODD1

None

None

None

CONN@@Option

X

X

XX

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

PX@

X

V

ON

LOW

OFF

OFF

OFF

OFF

OFF

OFF

USB Port Table

USB 2.0 USB 1.1 Port

0
1
2
3
4
5
6
7
8

9
10
11
12
13

EHCI1

EHCI2

UHCI0

UHCI1

UHCI2

UHCI3

UHCI4

UHCI5

UHCI6

USB 3.0 Port

0

1

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

1 External
USB Port

USB3.0
USB3.0
USB3.0
USB2.0 FRP
X
m-SATA
X
X
Camera
USB2.0 and sleep charger
minPCIE-WLAN/BT
X
X
X

3 External
USB Port

USB3.0
USB3.0
USB3.0(SB)

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-8711

LA-8711

LA-8711

E

3 57Sunday, November 27, 2011

3 57Sunday, November 27, 2011

3 57Sunday, November 27, 2011

0.1

0.1

0.1

S1

Power Plane Description

VIN

BATT+

B+

+CPU_CORE

1 1

+VGFX_CORE Core voltage for UM A graphic

+0.75VS

+1.05VS_VCCP

+VCCP

+1.5V

+1.5VS

+1.8VS

+3VALW

+3VALW_EC

+LAN_VDD_3V3

+3V_PCH

+3VS

+5VALW

+5V_PCH

+5VS

2 2

+VSB

+RTCVCC

Note : ON* means that t his power plane is ON only with AC power av ailable, otherwise it is OFF.

SMBUS Control Table

EC_SMB_CK1
EC_SMB_DA1

EC_SMB_CK2
EC_SMB_DA2

PCH_SMBCLK
PCH_SMBDATA

PCH_SML0CLK

3 3

PCH_SML0DATA

PCH_SML1CLK
PCH_SML1DATA

Adapter power supply (19V)

Battery power supply (12.6V)

AC or battery power rail f or power circuit.

Core voltage for CPU

+0.75VP to +0.75VS switched power rail for DDR terminator

+V1.05SP to +1.05VS_VCCP switched power r ail for CPU

+VCCP (1.05V ) power for PCH

+1.5VP to +1.5V power rail for DDRIII (1.35V OR 1.5V)

+1.5VS switched power rail

(+5VALW ) to 1.8V switched power rail to PCH

+3VALW always on power rail

+3VALW always to KBC

+3VALW to +LAN_VDD_3V3 power rail for LAN

+3VALW to +3V_PCH power rail for PCH (Short Jumper)

+3VALW to +3VS power rail

+5VALWP to +5VALW power rail

+5VALW to +5V_PCH power rail for PCH (Short resister)

+5VALW to +5VS switched power rail OFFONOFF

B+ to +VSB always on power rail f or sequence control

RTC power

BATT

SOURCE

KB930

KB930

PCH

PCH

PCH

WLAN

Charger

MIINI1

V

TP

V

V

DESTINATIONDIFFERENTIAL

S3 S5

N/A N/A N/A

N/A N/A N/A

ON

ON

ON

ON

ON

ON ON

ON

ON

ON

ON ON ON*

ON ON

ON ON

ON

ON

ON ON

ON

ON

SODIMMBATT

N/AN/AN/A

OFF

OFF

OFF OFF

OFF OFF

OFF OFF

OFF OFF

OFF

OFF OFF

OFF

OFF

ON ON*

ON*

ON*

OFF

OFF

ON ON*

ON*

ON ON*

ONON

EC_SMB_CK2

EC_SMB_DA2

PCH_SML1CLK

PCH_SML1DATA

V

V

V

FLEX CLOCKS DESTINATION

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

EC SM Bus1 address

Device

Smart Battery

G-sensor

PCH SM Bus address

Device Address

DDR DIMM0

DDR DIMM1

Mini Card1

Mini Card2

TP module

G-Sensor GPU

V

CLKOUT_PCIE0 CR+ Giga LAN CLKOUTFLEX0 None

CLKOUT_PCIE1

CLKOUT_PCIE2

CLK

CLKOUT_PCIE3

CLKOUT_PCIE4

4 4

CLKOUT_PCIE5

WLAN

None

None

None

None

NoneCLKOUT_PCIE6

CLKOUTFLEX1

CLKOUTFLEX2

CLKOUTFLEX3

Symbol Note :

: means Digital Ground

: means Analog Ground

None

None

None

CLKOUT_PCIE7 None

CLKOUT_PEG_B

A

None

B

5

D D

C C

+1.05VS

12

RC2

RC2

24.9_0402_1%

24.9_0402_1%

eDP_COMPIO and ICOMPO signals
should be shorted near balls

B B

and routed with typical
impedance <25 mohms

NOTE:eDP_COMPIO and eDP_ICOMPO
should not be l eft floating ev en if Internal
Graphic is disa bled since they are shared
with other inte rfaces

4

JCPUA

JCPUA

EDP_COMP

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

PEG_RCOMPO

DMI

DMI

Intel(R) FDI

Intel(R) FDI

PCI EXPRESS* - GRAPHICS

PCI EXPRESS* - GRAPHICS

eDP

eDP

DMI_CRX_PTX_N015
DMI_CRX_PTX_N115
DMI_CRX_PTX_N215
DMI_CRX_PTX_N315

DMI_CRX_PTX_P015
DMI_CRX_PTX_P115
DMI_CRX_PTX_P215
DMI_CRX_PTX_P315

DMI_CTX_PRX_N015
DMI_CTX_PRX_N115
DMI_CTX_PRX_N215
DMI_CTX_PRX_N315

DMI_CTX_PRX_P015
DMI_CTX_PRX_P115
DMI_CTX_PRX_P215
DMI_CTX_PRX_P315

FDI_CTX_PRX_N015
FDI_CTX_PRX_N115
FDI_CTX_PRX_N215
FDI_CTX_PRX_N315
FDI_CTX_PRX_N415
FDI_CTX_PRX_N515
FDI_CTX_PRX_N615
FDI_CTX_PRX_N715

FDI_CTX_PRX_P015
FDI_CTX_PRX_P115
FDI_CTX_PRX_P215
FDI_CTX_PRX_P315
FDI_CTX_PRX_P415
FDI_CTX_PRX_P515
FDI_CTX_PRX_P615
FDI_CTX_PRX_P715

FDI_FSYNC015
FDI_FSYNC115

FDI_INT15

FDI_LSYNC015
FDI_LSYNC115

T20 PADT20 PAD

PEG_ICOMPI

PEG_ICOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

3

PEG_ICOMPI and RCOMPO signals should be

+1.05VS

shorted and routed
with - max length = 500 mils - typical

12

RC1

RC1

24.9_0402_1%

24.9_0402_1%

PEG_COMP

J22
J21
H22

PEG_GTX_C_HRX_N15

K33

PEG_GTX_C_HRX_N14

M35

PEG_GTX_C_HRX_N13

L34

PEG_GTX_C_HRX_N12

J35

PEG_GTX_C_HRX_N11

J32

PEG_GTX_C_HRX_N10

H34

PEG_GTX_C_HRX_N9

H31

PEG_GTX_C_HRX_N8

G33

PEG_GTX_C_HRX_N7

G30

PEG_GTX_C_HRX_N6

F35

PEG_GTX_C_HRX_N5

E34

PEG_GTX_C_HRX_N4

E32

PEG_GTX_C_HRX_N3

D33

PEG_GTX_C_HRX_N2

D31

PEG_GTX_C_HRX_N1

B33

PEG_GTX_C_HRX_N0

C32

PEG_GTX_C_HRX_P15

J33

PEG_GTX_C_HRX_P14

L35

PEG_GTX_C_HRX_P13

K34

PEG_GTX_C_HRX_P12

H35

PEG_GTX_C_HRX_P11

H32

PEG_GTX_C_HRX_P10

G34

PEG_GTX_C_HRX_P9

G31

PEG_GTX_C_HRX_P8

F33

PEG_GTX_C_HRX_P7

F30

PEG_GTX_C_HRX_P6

E35

PEG_GTX_C_HRX_P5

E33

PEG_GTX_C_HRX_P4

F32

PEG_GTX_C_HRX_P3

D34

PEG_GTX_C_HRX_P2

E31

PEG_GTX_C_HRX_P1

C33

PEG_GTX_C_HRX_P0

B32

PEG_HTX_GRX_N15 PEG_HTX_C_GRX_N15

M29

PEG_HTX_GRX_N14 PEG_HTX_C_GRX_N14

M32

PEG_HTX_GRX_N13 PEG_HTX_C_GRX_N13

M31

PEG_HTX_GRX_N12 PEG_HTX_C_GRX_N12

L32

PEG_HTX_GRX_N11 PEG_HTX_C_GRX_N11

L29

PEG_HTX_GRX_N10 PEG_HTX_C_GRX_N10

K31

PEG_HTX_GRX_N9 PEG_HTX_C_GRX_N9

K28

PEG_HTX_GRX_N8 PEG_HTX_C_GRX_N8

J30

PEG_HTX_GRX_N7 PEG_HTX_C_GRX_N7

J28

PEG_HTX_GRX_N6 PEG_HTX_C_GRX_N6

H29

PEG_HTX_GRX_N5 PEG_HTX_C_GRX_N5

G27

PEG_HTX_GRX_N4 PEG_HTX_C_GRX_N4

E29

PEG_HTX_GRX_N3 PEG_HTX_C_GRX_N3

F27

PEG_HTX_GRX_N2 PEG_HTX_C_GRX_N2

D28

PEG_HTX_GRX_N1 PEG_HTX_C_GRX_N1

F26

PEG_HTX_GRX_N0 PEG_HTX_C_GRX_N0

E25

PEG_HTX_GRX_P15 PEG_HTX_C_GRX_P15

M28

PEG_HTX_GRX_P14 PEG_HTX_C_GRX_P14

M33

PEG_HTX_GRX_P13 PEG_HTX_C_GRX_P13

M30

PEG_HTX_GRX_P12 PEG_HTX_C_GRX_P12

L31

PEG_HTX_GRX_P11 PEG_HTX_C_GRX_P11

L28

PEG_HTX_GRX_P10 PEG_HTX_C_GRX_P10

K30

PEG_HTX_GRX_P9 PEG_HTX_C_GRX_P9

K27

PEG_HTX_GRX_P8 PEG_HTX_C_GRX_P8

J29

PEG_HTX_GRX_P7 PEG_HTX_C_GRX_P7

J27

PEG_HTX_GRX_P6 PEG_HTX_C_GRX_P6

H28

PEG_HTX_GRX_P5 PEG_HTX_C_GRX_P5

G28

PEG_HTX_GRX_P4 PEG_HTX_C_GRX_P4

E28

PEG_HTX_GRX_P3 PEG_HTX_C_GRX_P3

F28

PEG_HTX_GRX_P2 PEG_HTX_C_GRX_P2

D27

PEG_HTX_GRX_P1 PEG_HTX_C_GRX_P1

E26

PEG_HTX_GRX_P0 PEG_HTX_C_GRX_P0

D25

CU33 0.1U_0402_10V6KPX@CU33 0.1U_0402_10V6KPX@
CU34 0.1U_0402_10V6KPX@CU34 0.1U_0402_10V6KPX@
CU35 0.1U_0402_10V6KPX@CU35 0.1U_0402_10V6KPX@
CU36 0.1U_0402_10V6KPX@CU36 0.1U_0402_10V6KPX@
CU37 0.1U_0402_10V6KPX@CU37 0.1U_0402_10V6KPX@
CU38 0.1U_0402_10V6KPX@CU38 0.1U_0402_10V6KPX@
CU39 0.1U_0402_10V6KPX@CU39 0.1U_0402_10V6KPX@
CU40 0.1U_0402_10V6KPX@CU40 0.1U_0402_10V6KPX@
CU41 0.1U_0402_10V6KPX@CU41 0.1U_0402_10V6KPX@
CU42 0.1U_0402_10V6KPX@CU42 0.1U_0402_10V6KPX@
CU43 0.1U_0402_10V6KPX@CU43 0.1U_0402_10V6KPX@
CU44 0.1U_0402_10V6KPX@CU44 0.1U_0402_10V6KPX@
CU45 0.1U_0402_10V6KPX@CU45 0.1U_0402_10V6KPX@
CU46 0.1U_0402_10V6KPX@CU46 0.1U_0402_10V6KPX@
CU47 0.1U_0402_10V6KPX@CU47 0.1U_0402_10V6KPX@
CU48 0.1U_0402_10V6KPX@CU48 0.1U_0402_10V6KPX@

CU49 0.1U_0402_10V6KPX@CU49 0.1U_0402_10V6KPX@
CU50 0.1U_0402_10V6KPX@CU50 0.1U_0402_10V6KPX@
CU51 0.1U_0402_10V6KPX@CU51 0.1U_0402_10V6KPX@
CU52 0.1U_0402_10V6KPX@CU52 0.1U_0402_10V6KPX@
CU53 0.1U_0402_10V6KPX@CU53 0.1U_0402_10V6KPX@
CU54 0.1U_0402_10V6KPX@CU54 0.1U_0402_10V6KPX@
CU55 0.1U_0402_10V6KPX@CU55 0.1U_0402_10V6KPX@
CU56 0.1U_0402_10V6KPX@CU56 0.1U_0402_10V6KPX@
CU57 0.1U_0402_10V6KPX@CU57 0.1U_0402_10V6KPX@
CU58 0.1U_0402_10V6KPX@CU58 0.1U_0402_10V6KPX@
CU59 0.1U_0402_10V6KPX@CU59 0.1U_0402_10V6KPX@
CU60 0.1U_0402_10V6KPX@CU60 0.1U_0402_10V6KPX@
CU61 0.1U_0402_10V6KPX@CU61 0.1U_0402_10V6KPX@
CU62 0.1U_0402_10V6KPX@CU62 0.1U_0402_10V6KPX@
CU63 0.1U_0402_10V6KPX@CU63 0.1U_0402_10V6KPX@
CU64 0.1U_0402_10V6KPX@CU64 0.1U_0402_10V6KPX@

impedance = 43 mohms
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 mohms

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

2

<PEG>

10/05 Change to 0.22uF.

Typ- suggest 220nF. The change in AC capacitor value from
180nF to 265nF is to enable compatibility with future platforms
having PCIE Gen3 (8GT/s)
11/23 AC-coupling capacitor is 0.1u.Chelsea only support GEN2.

PEG_GTX_C_HRX_N[0..15]

PEG_GTX_C_HRX_P[0..15]

PEG_HTX_C_GRX_N[0..15]

PEG_HTX_C_GRX_P[0..15]

<PEG>

1

PEG_GTX_C_HRX_N[0..15] 21

PEG_GTX_C_HRX_P[0..15] 21

PEG_HTX_C_GRX_N[0..15] 21

PEG_HTX_C_GRX_P[0..15] 21

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

PROCESSOR(1/7) DMI,FDI,PEG

LA-8551P

1

4 57Sunday, November 27, 2011

4 57Sunday, November 27, 2011

4 57Sunday, November 27, 2011

0.1

0.1

0.1

5

D D

PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this
signal. System board designers may use this

+1.05VS

C C

Processor Pullups

RC8 62_0402_5%RC8 62_0402_5%

RC11 10K_0402_5%RC11 10K_0402_5%

H_PROCHOT#

12

12

12

C4680

C4680

47P_0402_50V8J

47P_0402_50V8J

H_PROCHOT#

H_CPUPWRGD_R

signal to determine if the processor is present

H_SNB_IVB#17

H_PECI17,36 H_DRAMRST# 6

H_PROCHOT#36,47

H_THEMTRIP#17

H_PM_SYNC15

H_CPUPWRGD17

SI# 10/02 Change to Pull High +3VS

+3VS

B B

RC81

RC81
10K_0402_5%

10K_0402_5%

1 2

SYS_PWROK15

PM_DRAM_PWRGD15

+3V_PCH

@ RC27

@

0_0402_5%

0_0402_5%

1 2

+3VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

RC27

RC28

RC28

@

@

1 2

200_0402_5%

200_0402_5%

RC30

RC30

1 2

200_0402_5%

200_0402_5%

1

CC2

CC2

2

1

2

Part Number = SA00003Y000

Part Number = SA00003Y000

+3VALW

UC2

UC2
74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

5

P

B

4

O

A

G

3

PM_SYS_PWRGD_BUF

+1.5V_CPU_VDDQ

12

RC25

RC25
200_0402_5%

200_0402_5%

Remove mos for layout

4

+3VS

Check circuit!!!

5

@ UC1

@

1

P

NC

PLT_RST#

PLT_RST#16,21,31,34,36

This pin is for compability with future
platforms. A pull up resistor to VCCIO is
required if connected to the DF_TVS strap
on the PCH.

@

@

1 2

RC7 10K_0402_5%

RC7 10K_0402_5%

1 2

RC9 0_0402_5%RC9 0_0402_5%

H_PROCHOT#

RC10 56_0402_5%RC10 56_0402_5%

H_THEMTRIP# H_THEMTRIP#_R

UNCOREPWRGOOD:

RC18 130_0402_5%RC18 130_0402_5%

SM_DRAMPWROK:DRAM power ok

H_PROCHOT#_R

1 2

1 2

RC12 0_0402_5%RC12 0_0402_5%

1 2

RC13 0_0402_5%RC13 0_0402_5%

RC16

RC16

0_0402_5%

0_0402_5%

H_CPUPWRGD_R

1 2

非非非非

CORE

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

1 2

BUF_CPU_RST#

T5PAD @T5PAD @

H_PM_SYNC_R

外外外外外外外外外外外外

H_PECI_ISO

OK

C26

AN34

AL33

AN33

AL32

AN32

AM34

AP33

V8

AR33

DDR3 Compensation Signals

SM_RCOMP0

RC23 140_0402_1%RC23 140_0402_1%

SM_RCOMP1

RC24 25.5_0402_1%RC24 25.5_0402_1%

SM_RCOMP2

RC26 200_0402_1%RC26 200_0402_1%

12

12

12

PU/PD for JTAG signals

XDP_TMS

XDP_TDI

XDP_TDO

XDP_TCK

XDP_TRST#

2011.10.18 dele te all reserved XDP conponent.
Just reserve te st point for XDP.

T40 PAD@T40 PAD@

T41 PAD@T41 PAD@

T42 PAD@T42 PAD@

T43 PAD@T43 PAD@

T46 PAD@T46 PAD@

2

A

3

R956

R956

0_0402_5%

0_0402_5%

1 2

JCPUB

JCPUB

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

SM_DRAMPWROK

RESET#

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

XDP_TRST#

PLT_RST#

PM_SYS_PWRGD_BUF

BUF_CPU_RST#

G

3

Buffered reset to CPU

1

CC1

@ CC1

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

UC1

BUFO_CPU_RST#

4

Y

SN74LVC1G07DCKR_SC70-5

SN74LVC1G07DCKR_SC70-5

MISCTHERMALPWR MANAGEMENT

MISCTHERMALPWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

C263 0.1U_0402_16V7KC263 0.1U_0402_16V7K

1 2

C264 220P_0402_50V7KC264 220P_0402_50V7K

1 2

C265 100P_0402_50V8J@C265 100P_0402_50V8J@

1 2

C266 220P_0402_50V7KC266 220P_0402_50V7K

1 2

+1.05VS

12

@

@

RC3

RC3
75_0402_5%

75_0402_5%

1.5K_0402_1%

1.5K_0402_1%

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

MISC

MISC

Reset# signal is driven by the PCH to multiple agents on the platform.
PCH Reset# output DC levels are 0-V and 3.3 V,
processor Reset input DC levels are 0V and 1.0 V.
Processor high-voltage level is lower than PCH high v oltage level,
therefore a voltage level shifter is required on the R eset# signal.
In order for Reset# to meet the signal quality requirement at the input to
the processor OD buffer must be plac ed on the motherboard between
the PCH and the processor.

RC4

RC4

BCLK

BCLK#

11/21 follow QAZ60 cost down CPU_RST#

BUF_CPU_RST#

12

12

RC6

RC6

750_0402_1%

750_0402_1%

Requires a series resistor of 43±5% between processor and PC H.
It also a needs an Rtt of 75±5% to VCCP after the OD
buffer and before the series resistor.

A28
A27

A16
A15

CLK_CPU_DMI 14
CLK_CPU_DMI# 14

RC84 1K_0402_5%RC84 1K_0402_5%
RC85 1K_0402_5%RC85 1K_0402_5%

12
12

ITP CLK change to part E.

H_DRAMRST#

R8

SM_RCOMP0

AK1

SM_RCOMP1

A5

SM_RCOMP2

A4

PAD

PAD

T35

T35

PAD

PAD

@

@

T39

T39

@

@

AP29

PRDY#

AP27

PREQ#

XDP_TCK

AR26

TCK

XDP_TMS

AR27

TMS

XDP_TRST#

AP30

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

XDP_TDI

AR28

TDI

XDP_TDO

AP26

TDO

AL35

AT28
AR29
AR30
AT30

XDP_BPM#4_R

AP32

XDP_BPM#5_R

AR31

XDP_BPM#6_R

AT31

XDP_BPM#7_R

AR32

SI# 8/16 Reserve RC81~RC85 by ESD request

RC17 0_0402_5%RC17 0_0402_5%

1 2

2011.10.18 dele te all reserved XDP conponent.
Just reserve te st point for XDP.

XDP_DBRESET#_R

H_CPUPWRGD_R

SI# 8/19 BOM
C118 220P
C266 220P
C264 220P
C263 0.1u
CC4 0.1u ok

2

100MHz

+1.05VS

6/27 Add ESD solution

XDP_DBRESET#XDP_DBRESET#_R

T60 PAD@T60 PAD@
T61 PAD@T61 PAD@
T62 PAD@T62 PAD@
T63 PAD@T63 PAD@

CC4 0.1U_0402_16V7K

CC4 0.1U_0402_16V7K

12

<BOM Structure>

<BOM Structure>

C118 220P_0402_50V7KC118 220P_0402_50V7K

1 2

6/27 Add ESD solution

XDP_DBRESET#

XDP_DBRESET# 15

RC5 1K_0402_5%RC5 1K_0402_5%

circuit check 10k

12

1

+3VS

Sharing add for module desige

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Title

Title

Title

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

LA-8041P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

5 57Sunday, November 27, 2011

5 57Sunday, November 27, 2011

5 57Sunday, November 27, 2011

0.1

0.1

0.1

5

JCPUC

JCPUC

4

3

JCPUD

JCPUD

2

1

DDR_A_D[0..63]11

D D

C C

DDR_A_BS01 1

B B

DDR_A_BS11 1
DDR_A_BS21 1

DDR_A_CAS#11
DDR_A_RAS#11
DDR_A_WE#11

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AP11
AN11

AL12
AM12
AM11

AL11

AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10

AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8

AK9
AH8
AH9
AL9
AL8

AE8
AD9
AF9

F10

AJ5
AJ6
AJ8

AJ9

C5
D5
D3
D2
D6
C6
C2
C3

F8

G9

F9

F7
G8
G7

K4

K5

K1

K2
M8

N8

N7

M9

N9
M7

V6

J1
J5
J4
J2

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

RSVD_TP[10]

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]
SA_ODT[1]

RSVD_TP[9]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

M_CLK_DDR0 11
M_CLK_DDR#0 11
DDR_CKE0_DIMMA 11

M_CLK_DDR1 11
M_CLK_DDR#1 11
DDR_CKE1_DIMMA 11

DDR_CS0_DIMMA# 11
DDR_CS1_DIMMA# 11

M_ODT0 11
M_ODT1 11

DDR_A_DQS#[0..7] 11

DDR_A_DQS[0..7] 11

DDR_A_MA[0..15] 11

DDR_B_D[0..63]12

DDR_B_BS012
DDR_B_BS112
DDR_B_BS212

DDR_B_CAS#12
DDR_B_RAS#12
DDR_B_WE#12

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

D10

K10

AM5
AM6
AR3

AP3
AN3
AN2
AN1

AP2

AP5
AN9

AT5

AT6

AP6
AN8
AR6
AR5
AR9

AJ11

AT8

AT9

AH11

AR8

AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15

AA9
AA7

AA10

AB8
AB9

J10

C9
A7

C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2

J7
J8

K9

J9

K8
K7
M5
N4
N2
N1
M4
N5
M2
M1

R6

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

RSVD_TP[17]
RSVD_TP[18]

RSVD_TP[19]
RSVD_TP[20]

SB_CLK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

M_CLK_DDR2 12
M_CLK_DDR#2 12
DDR_CKE0_DIMMB 12

M_CLK_DDR3 12
M_CLK_DDR#3 12
DDR_CKE1_DIMMB 12

10/05 change net name.

DDR_CS0_DIMMB# 12
DDR_CS1_DIMMB# 12

M_ODT2 12
M_ODT3 12

DDR_B_DQS#[0..7] 12

DDR_B_DQS[0..7] 12

DDR_B_MA[0..15] 12

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

RC35

@RC35

@

0_0402_5%

RC38

RC38

0_0402_5%

1 2

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

13

QC2

QC2
BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

9/7 Folllow PAJ80 BOM by Light
del: SB501380020

1 2

add: SB00000QO00

1

CC3

CC3

0.047U_0402_16V4Z

0.047U_0402_16V4Z

2

CPU通通DIMM做reset

H_DRAMRST#5

4.99K_0402_1%

4.99K_0402_1%

A A

DRAMRST_CNTRL_PC H9,14

5

RC39

RC39

0_0402_5%

0_0402_5%

1 2

DRAMRST_CNTRL

RC36

RC36

1K_0402_5%

1K_0402_5%

+1.5V

12

1 2

RC37

RC37
1K_0402_5%

1K_0402_5%

S0
DRAMRST_CNTRL_P CH hgih ,MOS O N
H_DRAMRST# HIGH ,DDR3_DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_P CH Low ,MOS OF F
H_DRAMRST# lo,D DR3_DRAMRST# HI GH
Dimm not reset
S4,5
DRAMRST_CNTRL_P CH Low ,MOS OF F
H_DRAMRST# lo,D DR3_DRAMRST# lo w
Dimm reset

4

DDR3_DRAMRST# 11,12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

PROCESSOR(3/7) DDRIII

LA-8041P

1

6 57Sunday, November 27, 2011

6 57Sunday, November 27, 2011

6 57Sunday, November 27, 2011

0.1

0.1

0.1

5

4

3

2

1

CFG Straps for Processor

CFG2

D D

change to install

12

RC40

RC40
1K_0402_1%

1K_0402_1%

Change to part G.

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

JCPUE

JCPUE

T3PAD T3PAD

CLK_RES_ITP 14
CLK_RES_ITP# 14

ITP CLK change from part C.

T64PAD T64PAD

RSVD28
RSVD29
RSVD30
RSVD31

RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD51
RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH27
AH26

L7
AG7
AE7
AK2

W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

AN35
AM35

AT2
AT1
AR1

B1

CPU_RSVD6
CPU_RSVD7

RESERVED

RESERVED

VCC_DIE_SENSE
VSS_DIE_SENSE

RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5

RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9

RSVD_NCTF10

RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13

CFG0

T9T9

CFG1

T6T6

CFG2

T10T10

CFG3

T11T11

CFG4
CFG5

1 2

12

T12T12
T13T13
T7T7
T8T8
T14T14
T15T15
T16T16
T47T47
T48T48
T58T58
T59T59
T17T17
T18T18

49.9_0402_1%

49.9_0402_1%

12

VSSAXG_VAL_SENSE

CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17

VCC_VAL_SENSE

VSS_VAL_SENSE

VAXG_VAL_SENSE

C C

2011.10.18 delete XDP resistor
just reserve test point for XDP.

+VGFX_CORE

+CPU_CORE

Just modify PWR to correct ,
didn't change net-name to save layout time;must modify on SI phase

B B

A A

RC42 4 9.9_0402_1%RC42 4 9.9_0402_1%

RC44 49.9_0402_1%RC44 49.9_0402_1%

RC43

RC43

1 2

RC45 4 9.9_0402_1%RC45 4 9.9_0402_1%

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

CFG

CFG

change to install

T21T21
T22T22

Display Port Presence Strap

CFG4

PCIE Port Bifurcation Straps

CFG[6:5]

PEG DEFER TRAINING

CFG7

1: Normal Operation; Lane # definition matches
socket pin map definition

*

0:Lane Reversed

CFG4

*

1K_0402_1%

1K_0402_1%

12

RC41

RC41
1K_0402_1%

1K_0402_1%

1 : Disabled; No Physical Display Port
attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

CFG6

CFG5

RC48

RC48

12

12

RC49

UMA@RC49

UMA@

1K_0402_1%

1K_0402_1%

@

@

11: (Default) x16 - Device 1 functions 1 and 2 disabled

10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled

01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)

*

00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

*

12

RC50

@RC50

@

1K_0402_1%

1K_0402_1%

1: (Default) PEG Train immediately following
xxRESETB de assertion

0: PEG Wait for BIOS for training

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

PROCESSOR(4/7) RSVD,CFG

LA-8041P

1

7 57Sunday, November 27, 2011

7 57Sunday, November 27, 2011

7 57Sunday, November 27, 2011

0.1

0.1

0.1

5

D D

C C

B B

A A

4

+CPU_CORE

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26

3

POWER

JCPUF

JCPUF

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

POWER

CORE SUPPLY

CORE SUPPLY

PEG AND DDR

PEG AND DDR

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

SENSE LINES SVID

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

VIDALERT#

VIDSCLK
VIDSOUT

AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK

AJ30

H_CPU_SVIDDAT

AJ28

VCCSENSE_R

AJ35

VSSSENSE_R

AJ34

VCCIO_SENSE_R

B10

VSS_SENSE_VCCIO

A10

+1.05VS

RC61 0_0402_5%RC61 0_0402_5%

1 2

RC62 0_0402_5%RC62 0_0402_5%

1 2

RC63

RC63

1 2

10_0402_1%

10_0402_1%

RC65 0_0402_5%RC65 0_0402_5%

1 2

12

RC66

RC66
10_0402_1%

10_0402_1%

10/05 mount.
(follow check list)

2

+1.05VS

12

RC55

RC55
130_0402_5%

130_0402_5%

RC57 43_0402_1%RC57 43_0402_1%

1 2

RC58 0_0402_5%RC58 0_0402_5%

1 2

RC59 0_0402_5%RC59 0_0402_5%

1 2

+1.05VS

RC121

RC121

1 2

100_0402_1%~D

100_0402_1%~D

@

@

VCCIO_SENSE 50
VSS_SENSE_VCCIO 50

+1.05VS

12

RC56

RC56

75_0402_5%

75_0402_5%

1 2

RC60 1 00_0402_1%RC60 1 00_0402_1%

12

RC64

RC64
100_0402_1%

100_0402_1%

Place the PU
resistors close to VR

VR_SVID_ALRT# 55
VR_SVID_CLK 55
VR_SVID_DAT 55

+CPU_CORE

Place the PU
resistors close to CPU

VCCSENSE 55
VSSSENSE 55

1

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

5

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

PROCESSOR(5/7) PWR,BYPASS

LA-8041P

1

8 57Sunday, November 27, 2011

8 57Sunday, November 27, 2011

8 57Sunday, November 27, 2011

0.1

0.1

0.1

5

4

3

2

1

+1.5V_CPU_VDDQ +1.5V

CC74 0.1U_0402_10V7KCC74 0.1U_0402_10V7K

CC75 0.1U_0402_10V7KCC75 0.1U_0402_10V7K

D D

+V_DDR_REFA

+V_DDR_REFB

C C

+VGFX_CORE

RC15

RC15

1 2

0_0402_5%@

0_0402_5%@

RC82

RC82

1 2

0_0402_5%@

0_0402_5%@

QC7

QC7

SB000002X00

SB000002X00

13

D

D

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

S

S

QC8

QC8

SB000002X00

SB000002X00

13

D

D

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

S

S

12

12

DRAMRST_CNTRL_PC H

2

G

G

+V_DDR_REFA_R

RC14

RC14

1 2

1K_0402_1%@

1K_0402_1%@

DRAMRST_CNTRL_PC H

2

G

G

+V_DDR_REFB_R

RC83

RC83

1 2

1K_0402_1%@

1K_0402_1%@

DRAMRST_CNTRL_PC H 6,14

For Chief River only

M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

10/03 add +V_DDR_REFB

+1.8VS

RC77

B B

SI# 7/29 Add CC 26 10uF and res erve 330U on 1. 8V power Rail

RC77

0_0805_5%

0_0805_5%

1 2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC26

CC26

+

+

2

2

330U_D2_2VM_R6M

330U_D2_2VM_R6M

Can connect to GND if motherboard only

‧‧‧‧

supports external graphics and if GFX VR is not
stuffed in a common motherboard design,

VAXG can be left floating in a common

‧‧‧‧

motherboard design (Gfx VR keeps VAXG from
floating) if the VR is stuffed

JCPUG

JCPUG

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

+1.8VS_VCCPLL

CC121

1U_0402_6.3V6K

CC121

1U_0402_6.3V6K

CC122

1U_0402_6.3V6K

CC122

CC120

CC120

@

@

1U_0402_6.3V6K

1

1

2

2

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

POWER

POWER

SENSE

SENSE

GRAPHICS

GRAPHICS

1.8V RAIL

1.8V RAIL

VAXG_SENSE

VSSAXG_SENSE

LINES

LINES

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VREFMISC

VREFMISC

DDR3 -1.5V RAILS

DDR3 -1.5V RAILS

SA RAIL

SA RAIL

VCCSA_SENSE

VCCSA_VID[0]
VCCSA_VID[1]

VCCIO_SEL

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

RC157 100_0402_1%~D@RC157 100_0402_1%~D@

AK35
AK34

AL1

B4
D1

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

VCCSA_SENSE

H23

0_0402_5%

0_0402_5%

C22
C24

RC80 0_0402_5%RC80 0_0402_5%

A19

100±5% pull-up to VCC;

1 2

+V_SM_VREF_CNT

+V_DDR_REFA_R
+V_DDR_REFB_R

100±5% pull-down to GND.

VCC_AXG_SENSE 55
VSS_AXG_SENSE 55

QC4 Change to SA0000JA00 for small package
1016

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC22

CC22

2

11/21 follow PBL22 design remove 10u*2, 1U*5

1 2

RC78 0 _0402_5%@RC78 0_0402_5%@

VCCSA_VID0

RC79

RC79

1 2
1 2

VCCP_PWRCTR L_R

VCCSA_VID1

VCCSA_VID0 52
VCCSA_VID1 52

10K_0402_5%

10K_0402_5%

1 2

RC53

RC53

@

@

CPU EDS descript as follow:

+V_SM_VREF should
have 20 mil trace width

1

CC79

CC79

0.1U_0402_16V4Z

0.1U_0402_16V4Z

11/21 follow PBL22 design remove 10u*2, 1U*8;
keep 10U*5

+VCCSA

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CC21

CC21

VCCSA_SENSE 52

+1.05VS

1

CC24

CC24

2

12

RC52
75_0402_5%

75_0402_5%

1

2

@RC52

@

2

+VCCSA

Delete CC25 330U cap 10.19
(after check with power)

+1.5V_CPU_VDDQ

12

RC68

RC68
1K_0402_1%

1K_0402_1%

12

RC69

RC69
1K_0402_1%

1K_0402_1%

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC95

CC95

2

1

1

1

CC97

CC97

CC96

CC96

2

2

2

+1.5V_CPU_VDDQ Source

+1.5V_CPU_VDDQ

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC99

CC99

CC98

CC98

2

1

+

+

330U_D2_2V_Y

330U_D2_2V_Y

2

CC100

CC100

For Chief River platforms this pin

+1.5V +1.5V_CPU_VDDQ

QC4

+VSB

+3VALW

12

RC72

RC72
100K_0402_5%

RC74

RC74

0_0402_5%

A A

CPU1.5V_S3_GATE36

SUSP#36,43,50,51,52,53

0_0402_5%

1 2

RC75

@RC75

@

0_0402_5%

0_0402_5%

1 2

100K_0402_5%

RUN_ON_CPU1.5VS3#

61

2

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6
QC5A

QC5A

12

34

5

RC70

RC70
100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6
QC5B

QC5B

330K_0402_5%

330K_0402_5%

SI# BOM Change CC118 0.1u 25V form 0.1u 16V

Follow DG 0.71 page 6

5

QC4
AON6718L_DFN8-5

AON6718L_DFN8-5

5

RC73

RC73

4

12

1
2
3

4

@

@

1

CC118

CC118

2

0.1U_0402_25V6

0.1U_0402_25V6

12

R78

R78

20K_0402_5%

20K_0402_5%

RC71

RC71
470_0603_5%

470_0603_5%

1 2

61

RUN_ON_CPU1.5VS3#

2

Q10A

Q10A
2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

should not be used.

VID[0] VID[1] 2011 2012
0 0 0.90 V Yes Yes
0 1 0.80 V Yes Yes
1 0 0.725 V No Yes
1 1 0.675 V No Yes

Compal Secret Data

Compal Secret Data

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

PROCESSOR(6/7) PWR

LA-8041P

1

9 57Sunday, November 27, 2011

9 57Sunday, November 27, 2011

9 57Sunday, November 27, 2011

0.1

0.1

0.1

5

D D

C C

B B

4

JCPUH

JCPUH

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

VSS14

AR22

VSS15

AR19

VSS16

AR16

VSS17

AR13

VSS18

AR10

VSS19

AR7

VSS20

AR4

VSS21

AR2

VSS22

AP34

VSS23

AP31

VSS24

AP28

VSS25

AP25

VSS26

AP22

VSS27

AP19

VSS28

AP16

VSS29

AP13

VSS30

AP10

VSS31

AP7

VSS32

AP4

VSS33

AP1

VSS34

AN30

VSS35

AN27

VSS36

AN25

VSS37

AN22

VSS38

AN19

VSS39

AN16

VSS40

AN13

VSS41

AN10

VSS42

AN7

VSS43

AN4

VSS44

AM29

VSS45

AM25

VSS46

AM22

VSS47

AM19

VSS48

AM16

VSS49

AM13

VSS50

AM10

VSS51

AM7

VSS52

AM4

VSS53

AM3

VSS54

AM2

VSS55

AM1

VSS56

AL34

VSS57

AL31

VSS58

AL28

VSS59

AL25

VSS60

AL22

VSS61

AL19

VSS62

AL16

VSS63

AL13

VSS64

AL10

VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68

AK33

VSS69

AK30

VSS70

AK27

VSS71

AK25

VSS72

AK22

VSS73

AK19

VSS74

AK16

VSS75

AK13

VSS76

AK10

VSS77

AK7

VSS78

AK4

VSS79

AJ25

VSS80

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

3

JCPUI

JCPUI

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS

2

VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

1

F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

TYCO_2013620-2_IVY BRIDGE

TYCO_2013620-2_IVY BRIDGE

@

@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

PROCESSOR(7/7) VSS

LA-8041P

1

0.1

0.1

10 57Sunday, November 27, 2011

10 57Sunday, November 27, 2011

10 57Sunday, November 27, 2011

0.1

5

4

3

2

1

DDR3 SO-DIMM A

+V_DDR_REFA

D D

DDR_A_D[0..63]6

DDR_A_DQS[0..7]6

DDR_A_DQS#[0..7]6

DDR_A_MA[0..15]6

All VREF traces should
have 20 mil trace width

0.1U_0402_16V7K

0.1U_0402_16V7K

CD2

2.2U_0603_6.3V6K

CD2

2.2U_0603_6.3V6K

CD1

CD1

1

1

2

2

Delete DDR_A_DM[0..7]

+1.5V

12

RD1

RD1
1K_0402_1%

1K_0402_1%

RD2

RD2
1K_0402_1%

1K_0402_1%

C C

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

11/18 for layout spacing: remove CD5/CD6/CD9

+0.75VS

11/21 1U*4 only

CD4

1U_0402_6.3V6K

CD4

1U_0402_6.3V6K

CD3

1U_0402_6.3V6K

CD3

1U_0402_6.3V6K

1

1

2

2

B B

Layout Note:
Place near JDIMM1

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD13

CD13

CD12

CD12

1

1

1

2

2

2

DDR3 SO-DIMM A

A A

5

+V_DDR_REFA

12

CD6

1U_0402_6.3V6K

CD6

1U_0402_6.3V6K

CD5

1U_0402_6.3V6K

CD5

1U_0402_6.3V6K

1

1

2

2

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD14

CD14

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD15

CD15

1

2

+1.5V

@

@

10U_0603_6.3V6M

CD16

CD16

CD17

CD17

1

1

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CD26

CD26

CD27

CD27

1

2

1

1

@

@

@

@

2

2

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue

DDR_CKE0_DIMMA6

DDR_A_BS26

M_CLK_DDR06
M_CLK_DDR#06

DDR_A_BS06

DDR_A_WE#6
DDR_A_CAS#6

DDR_CS1_DIMMA#6

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD18

CD18

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K
CD28

CD28

@

@

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD19

CD19

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K
CD25

CD25

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

CD20

CD20

CD21

CD21

1

2

1

+

+

CD22

CD22
330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

2

SGA00004400

SGA00004400

4

+3VS

RD5 10K_0402_5%RD5 10K_0402_5%

1 2

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD24

CD24

CD23

CD23

1

1

2

2

1

2

+1.5V +1.5V

3.56A@+1.5V

+V_DDR_REFA

DDR_A_D0
DDR_A_D1

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

3
5
7

11
13
15
17
19
21
23

27

33
35

39
41

45

51

57

63

67
69

73
75
77
79
81

85
87
89
91
93
95
97

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

RD6

10K_0402_5%

RD6

10K_0402_5%

12

205

JDDRL1

JDDRL1

VREF_DQ1VSS1
VSS2
DQ0
DQ1
VSS49DQS#0
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS925VSS10
DQS#1
DQS129RESET#
VSS1131VSS12
DQ10
DQ11
VSS1337VSS14
DQ16
DQ17
VSS1543VSS16
DQS#2
DQS247VSS17
VSS1849DQ22
DQ18
DQ1953VSS19
VSS2055DQ28
DQ24
DQ2559VSS21
VSS2261DQS#3
DM3
VSS2365VSS24
DQ26
DQ27
VSS2571VSS26

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#83A11
A9
VDD5
A8
A5
VDD7
A3
A1
VDD999VDD10
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

G1

LCN_DAN06-K4806-0102

LCN_DAN06-K4806-0102
CONN@

CONN@

Standard
<Address(SA1,SA0):00>

2

DDR_A_D4

4

3

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

DQ4
DQ5

DQ6
DQ7

DM1

DM2

A15
A14

CK1

BA1

S0#

NC2

DM4

DM6

SDA
SCL

LA-8711

LA-8711

LA-8711

G2

DDR_A_D5

6
8

DDR_A_DQS#0

10

DDR_A_DQS0

12
14

DDR_A_D6

16

DDR_A_D7

18
20

DDR_A_D12

22

DDR_A_D13

24
26
28

DDR3_DRAMRST#

30
32

DDR_A_D14

34

DDR_A_D15

36
38

DDR_A_D20

40

DDR_A_D21

42
44
46
48

DDR_A_D22

50

DDR_A_D23

52
54

DDR_A_D28

56

DDR_A_D29

58
60

DDR_A_DQS#3

62

DDR_A_DQS3

64
66

DDR_A_D30

68

DDR_A_D31

70
72

DDR_CKE1_DIMMA

74
76

DDR_A_MA15

78

DDR_A_MA14

80
82

DDR_A_MA11

84

DDR_A_MA7

86

A7

88

DDR_A_MA6

90

A6

DDR_A_MA4

92

A4

94

DDR_A_MA2

96

A2

DDR_A_MA0

98

A0

100

M_CLK_DDR1

102

M_CLK_DDR#1

104
106

DDR_A_BS1

108

DDR_A_RAS#

110
112

DDR_CS0_DIMMA#

114

M_ODT0

116
118

M_ODT1

120
122
124

+VREF_CA

126
128

DDR_A_D36

130

DDR_A_D37

132
134
136
138

DDR_A_D38

140

DDR_A_D39

142
144

DDR_A_D44

146

DDR_A_D45

148
150

DDR_A_DQS#5

152

DDR_A_DQS5

154
156

DDR_A_D46

158

DDR_A_D47

160
162

DDR_A_D52

164

DDR_A_D53

166
168
170
172

DDR_A_D54

174

DDR_A_D55

176
178

DDR_A_D60

180

DDR_A_D61

182
184

DDR_A_DQS#7

186

DDR_A_DQS7

188
190

DDR_A_D62

192

DDR_A_D63

194
196
198

PCH_SMBDATA

200

PCH_SMBCLK

202
204

206

0.6A@+0.75VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

DDR3_DRAMRST# 6,12

DDR_CKE1_DIMMA 6

M_CLK_DDR1 6
M_CLK_DDR#1 6

DDR_A_BS1 6
DDR_A_RAS# 6

DDR_CS0_DIMMA# 6
M_ODT0 6

M_ODT1 6

1

2

+0.75VS

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

0.1U_0402_16V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

CD10

CD10

1

2

Compal Secret Data

Compal Secret Data

Compal Secret Data

+VREF_CA

CD11

CD11

Deciphered Date

Deciphered Date

Deciphered Date

2

+1.5V

RD3

RD3
1K_0402_1%

1K_0402_1%

RD4

RD4
1K_0402_1%

1K_0402_1%

PCH_SMBDATA 12,14,37,40
PCH_SMBCLK 12,14,37,40

12

12

Title

Title

Title

DDRIII DIMM

DDRIII DIMM

DDRIII DIMM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet of

Date: Sheet of

Date: Sheet of

LA-8041P

1

11 61Sunday, November 27, 2011

11 61Sunday, November 27, 2011

11 61Sunday, November 27, 2011

0.1

0.1

0.1

5

All VREF traces should

DDR_B_D[0..63]6

D D

DDR_B_DQS[0..7]6

DDR_B_DQS#[0..7]6

DDR_B_MA[0..15]6

have 20 mil trace width

Delete DDR_B_DM[0..7]

+1.5V

12

RD12

RD12
1K_0402_1%

1K_0402_1%

RD11

RD11
1K_0402_1%

1K_0402_1%

C C

Layout Note:
Place near JDIMM1.203 & JDIMM1.204

11/18 for layout spacing: remove CD51/CD54/CD53

+0.75VS

11/21 keep 1u*4 only -Kenny

CD53

CD53

CD51

1U_0402_6.3V6K

CD51

1U_0402_6.3V6K

CD41

1U_0402_6.3V6K

CD41

1U_0402_6.3V6K

1

1

1

2

2

2

B B

Layout Note:
Place near JDIMM1

+1.5V

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD37

CD37

1

1

2

2

CD46

CD46

1

2

+V_DDR_REFB

10/03 change to +V_DDR_REFB

12

1U_0402_6.3V6K

1U_0402_6.3V6K

CD48

CD48

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD45

CD45

CD40

CD40

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

CD56

CD56

CD42

CD42

1

1

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CD44

CD44

CD43

CD43

1

1

2

2

DDR3 SO-DIMM B

+1.5V

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD34

CD34

CD33

CD33

1

A A

1

@

@

@

@

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD32

CD32

CD35

CD35

1

1

@

@

@

@

2

2

4

10/03 change to +V_DDR_REFB

0.1U_0402_16V7K

0.1U_0402_16V7K
CD47

CD47

1

2

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K
CD39

CD39

+V_DDR_REFB

1

+

+

CD36

CD36
330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M

2

SGA00004400

SGA00004400

+3VS

0.1U_0402_16V7K

0.1U_0402_16V7K

CD29

2.2U_0603_6.3V6K

CD29

2.2U_0603_6.3V6K

CD50

CD50

1

1

2

2

DDR_CKE0_DIMMB6

DDR_B_BS26

M_CLK_DDR26
M_CLK_DDR#26

DDR_B_BS06

DDR_B_WE#6
DDR_B_CAS#6

DDR_CS1_DIMMB#6

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

CD31

CD31

1

2

10/05 change to PH.

+1.5V +1.5V

+V_DDR_REFB

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

M_CLK_DDR2
M_CLK_DDR#2

DDR_B_MA10
DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

DDR_B_MA13
DDR_CS1_DIMMB#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

RD7 10K_0402_5%RD7 10K_0402_5%

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K
CD38

CD38

1

2

+3VS

RD9

10K_0402_5%

RD9

10K_0402_5%

12

3

DDR3 SO-DIMM B

3.56A@+1.5V

JDDRL2

JDDRL2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1
VSS49DQS#0

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9
VSS925VSS10

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2
DQS247VSS17
VSS1849DQ22

51

DQ18
DQ1953VSS19
VSS2055DQ28

57

DQ24
DQ2559VSS21
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3
A12/BC#83A11

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1
VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102
CONN@

CONN@

Standard
<Address(SA1,SA0):10>

VSS3

DQS0

VSS6

VSS8
DQ12
DQ13

DQ14
DQ15

DQ20
DQ21

DQ23

DQ29

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

VTT2

2
4

DQ4

6

DQ5

8
10
12
14
16

DQ6

18

DQ7

20
22
24
26
28

DM1

30
32
34
36
38
40
42
44
46

DM2

48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84
86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102

CK1

104
106
108

BA1

110
112
114

S0#

116
118
120
122

NC2

124
126
128
130
132
134
136

DM4

138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170

DM6

172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SDA

202

SCL

204

206

G2

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3
DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDR_CKE1_DIMMB

DDR_B_MA15
DDR_B_MA14

DDR_B_MA11
DDR_B_MA7

DDR_B_MA6
DDR_B_MA4

DDR_B_MA2
DDR_B_MA0

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_BS1
DDR_B_RAS#

DDR_CS0_DIMMB#
M_ODT2

M_ODT3

+VREF_CB

DDR_B_D36
DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PCH_SMBDATA
PCH_SMBCLK

0.6A@+0.75VS

+0.75VS

DDR3_DRAMRST# 6,11

DDR_CKE1_DIMMB 6

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_B_BS1 6
DDR_B_RAS# 6

DDR_CS0_DIMMB# 6
M_ODT2 6

M_ODT3 6

0.1U_0402_16V7K

0.1U_0402_16V7K

CD55

CD55

1

2

2

+1.5V

12

RD8

RD8
1K_0402_1%

+VREF_CB

CD30

2.2U_0603_6.3V6K

CD30

2.2U_0603_6.3V6K

1

2

1K_0402_1%

12

RD10

RD10
1K_0402_1%

1K_0402_1%

PCH_SMBDATA 11,14,37,40
PCH_SMBCLK 11,14,37,40

10/03 change to +VREF_CB

1

Security Classification

Security Classification

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue

5

4

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDRIII-DDRH

DDRIII-DDRH

DDRIII-DDRH

1

12 61Sunday, November 27, 2011

12 61Sunday, November 27, 2011

12 61Sunday, November 27, 2011

0.1

0.1

0.1

5

PCH_RTCX1

1 2

RH115 10M_0402_5%RH115 10M_0402_5%

Y2

Y2

1 2

32.768KHZ_12.5PF_CM31532768DZFT

32.768KHZ_12.5PF_CM31532768DZFT
18P_0402_50V8J

18P_0402_50V8J

1

CH2

CH2

2

D D

DB# 11/1 Reserv e 10pF by RF re quest

HDA_BIT_CLK

HDA_BITCLK_AUDIO38

HDA_RST_AUDIO#38

HDA_SYNC_AUDIO38

C C

+3V_PCH +3V_PCH+3V_PCH

12

RH127

@RH127

@

200_0402_5%

200_0402_5%

PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS

12

RH133

RH133

100_0402_1%

100_0402_1%

B B

SPI ROM FOR ME (8MByte )

+3V_PCH

RH141

RH141

1 2

RH145

RH145

1 2

RH144

RH144

1 2

+3V_SPI

20mils

1

CH6

CH6

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

PCH_RTCX2

1

CH3

CH3
18P_0402_50V8J

18P_0402_50V8J

2

@

@

CH82

CH82

1 2

10P_0402_50V8J

10P_0402_50V8J

1M_0402_5%

1M_0402_5%

1 2

RH119 33_0402_5%RH119 33_0402_5%

1 2

RH120 33_0402_5%RH120 33_0402_5%

1 2

RH121 33_0402_5%RH121 33_0402_5%

1 2

+RTCBATT

RH117 20K_0402_5%RH117 20K_0402_5%

RH118 20K_0402_5%RH118 20K_0402_5%

HDA_BIT_CLK

HDA_RST#

RH158

RH158

+RTCBATT

RH116

RH116

CH4

CH4

1U_0603_10V4Z

1U_0603_10V4Z

1 2

1 2

CH5

CH5

1U_0603_10V4Z

1U_0603_10V4Z

+5VS

G

G

QH1

QH1

S

S

SB000002X00

SB000002X00

BSS138W-7-F_SOT323-3

BSS138W-7-F_SOT323-3

1 2

RH122 0_0402_5%@RH122 0_0402_5%@

Follow intel ME update requirement

1 2

RH123 0_0402_5%RH123 0_0402_5%

1 2

RH125 33_0402_5%RH 125 33_0402_5%

12

RH128

@RH128

@

200_0402_5%

200_0402_5%

12

RH134

RH134
100_0402_1%

100_0402_1%

HDA_SDO36

HDA_SDOUT_AUDIO38

12

RH129

@RH129

@

200_0402_5%

200_0402_5%

12

RH135

RH135

100_0402_1%

100_0402_1%

PCH_JTAG_TCK

12

RH15051_0402_5% RH15051_0402_5%

8MByte SPI ROM PN SA000039A00

@

@

PCH_SPI_CS0#_R

3.3K_0402_5%

3.3K_0402_5%

PCH_SPI_WP#

3.3K_0402_5%

3.3K_0402_5%

PCH_SPI_HOLD#

3.3K_0402_5%

3.3K_0402_5%

+3V_SPI

1

CH8

CH8
22P_0402_50V8J

22P_0402_50V8J

2

@

@

DB# 11/1 Reserv e for RF please close to UH2

+3V_PCH +3V_SPI

PCH_SPI_CS0#

RH142 0_0402_5%RH142 0_0402_5%

PCH_SPI_CLK

RH146 0_0402_5%RH146 0_0402_5%

PCH_SPI_SI

RH147 0_0402_5%RH147 0_0402_5%

1 2

1M_0402_5%

1M_0402_5%

1

12

CMOS

CLRP1

CLRP1

SHORT PADS

SHORT PADS

2

1

12

CLRP2

CLRP2

SHORT PADS

SHORT PADS

2

ME CMOS

CLP1 & CLP2 place near DIMM

2

HDA_SPKR38

HDA_SYNCHDA_SYNC_R

13

D

D

HDA_SDIN038

HDA_SDOUT

HDA_SDOUT

R213 0_0402_5%R213 0_0402_5%

1 2

PCH_SPI_WP#

PCH_SPI_HOLD#

1 2

1 2

12

SM_INTRUDER#

PCH_SPI_CS0#_R

PCH_SPI_CLK_R

PCH_SPI_SI_R

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

HDA_SDOUT

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_SPI_CLK

PCH_SPI_CS0#

PCH_SPI_SI

PCH_SPI_SO

4

UH1A

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST # / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

UH2

CONN@UH2

CONN@

8

3

7

1

6

5

64M MX25L6405DZNI-12G WSON 8P

64M MX25L6405DZNI-12G WSON 8P

VCC

W

HOLD

S

C

D

4

VSS

PCH_SPI_SO_R

2

Q

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

LPC

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

RTCIHDA

RTCIHDA

JTAG

JTAG

SPI

SPI

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP

SATA 6G

SATA 6G

SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

&UH2

&UH2

@

@

64M MX25L6405DZNI-12G WSON 8P

64M MX25L6405DZNI-12G WSON 8P

PCH_SPI_SO

12

RH1430_0402_5% RH1430_0402_5%

C38
A38
B37
C37

D36

E36
K36

V5

AM3
AM1
AP7
AP5

AM10
AM8
AP11
AP10

AD7
AD5
AH5
AH4

AB8
AB10
AF3
AF1

Y7
Y5
AD3
AD1

Y3
Y1
AB3
AB1

Y11

Y10

AB12

AB13

AH1

P3

V14

P1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

SERIRQ

SATA_COMP

SATA3_COMP

RBIAS_SATA3

SATA_LED#

HDDHALT_LED#

BBS_BIT0_R

3

LPC_AD0 31,36
LPC_AD1 31,36
LPC_AD2 31,36
LPC_AD3 31,36

LPC_FRAME# 31,36

SERIRQ 36

1 2

RH130 37.4_0402_1%RH130 37.4_0402_1%

1 2

RH132 49.9_0402_1%RH132 49.9_0402_1%

1 2

RH137 750_0402_1%RH137 750_0402_1%

SATA_LED# 35

HDDHALT_LED# 35

R60 10K_0402_5%R60 10K_0402_5%

1 2

Reserve for EMI please close t o U48

+1.05VS_VCC_SATA

+1.05VS_SATA3

@

@

CH1

CH1

12

22P_0402_50V8J

22P_0402_50V8J

+3VS

RH151

RH151

1 2

33_0402_5%

33_0402_5%

@

@

SATA_PRX_DTX_N0 33
SATA_PRX_DTX_P0 33
SATA_PTX_DRX_N0 33
SATA_PTX_DRX_P0 33

SATA_PRX_DTX_N1 33
SATA_PRX_DTX_P1 33
SATA_PTX_DRX_N1 33
SATA_PTX_DRX_P1 33

SATA_PRX_DTX_N2 33
SATA_PRX_DTX_P2 33
SATA_PTX_DRX_N2 33
SATA_PTX_DRX_P2 33

Place CH95 clos e to PCH.

PCH_SPI_CLK

2

SATA HDD

m-SATA SSD

SATA ODD

HDA_SDO

ME debug mode , this signal has a weak internal PD

L=>security measures defined in the Flash
Descriptor will be in effect (default)

H=>Flash Descriptor Security will be overridden

RTC Battery

+RTCVCC

W=20mils

1

CH7

CH7
1U_0603_10V4Z

1U_0603_10V4Z

2

1

BAV70W 3P C/C_SOT-323

BAV70W 3P C/C_SOT-323

1K_0402_5%

1K_0402_5%

RH148

DH1

DH1

RH148

2

3

+3VLP

W=20mils

Should be ACES_50273-0020N-001_2P,need check

1

HDA_SYNC

This signal has a weak interna l pull-down
On Die PLL VR i s supplied by

1.5V when smapl ed high

1.8V when sampl ed low
Needs to be pul led High for Ch ief River platf rom

HDA_SYNC

RH149 1K_0402_5%RH149 1K_0402_5%

PCH_INTVRMEN

RH124 330K_0402_5%RH124 330K_0402_5%

PCH_INTVRMEN

RH126 330K_0402_5%@RH126 330K_0402_5%@

INTVRMEN

H：Integrated VRM enable

*

L：Integrated VRM disable

SERIRQ

HDDHALT_LED#

RH131 10K_0402_5%RH131 10K_0402_5%

RH136 10K_0402_5%RH136 10K_0402_5%

SATA_LED#

RH138 10K_0402_5%RH138 10K_0402_5%

HDA_SPKR

RH139 1K_0402_5%@RH139 1K_0402_5%@

*

HDA_SDOUT

RH140 1K_0402_5%@RH140 1K_0402_5%@

Low = Disabled

*

High = Enabled

LOW=Default
HIGH=No Reboot

+3V_PCH

12

+RTCVCC

12

12

+3VS

12

12

12

+3VS

12

+3V_PCH

12

11/24 according RTC spec swap RTC to pin1

+RTCBATT

20mils

10mils20mils

12

ACES_50273-0020N-001

ACES_50273-0020N-001

1

1

2

2

3

G1

4

G2

JRTC1

CONN@JRTC1

CONN@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

PCH (1/8) SATA,HDA,SPI, LPC

LA-8711

LA-8711

LA-8711

1

13 57Sunday, November 27, 2011

13 57Sunday, November 27, 2011

13 57Sunday, November 27, 2011

0.1

0.1

0.1

5

PCIE_PRX_DTX_N134

PCIE LAN

MiniWLAN --->

D D

PCIE_PRX_DTX_P134
PCIE_PTX_C_DRX_N134
PCIE_PTX_C_DRX_P134

PCIE_PRX_DTX_N331

PCIE_PRX_DTX_P331
PCIE_PTX_C_DRX_N331
PCIE_PTX_C_DRX_P331

Card Reader+ Giga LAn--->

C C

B B

3

YH2

OSC1OSC

GND2GND

YH2

4

27P_0402_50V8J

27P_0402_50V8J

1

CH12

CH12

2

25MHZ_20PF_FSX3M-25.M20FDO

25MHZ_20PF_FSX3M-25.M20FDO

WLAN--->

XTAL25_IN

XTAL25_OUT

12

RH1871M_0402_5% RH1871M_0402_5%

27P_0402_50V8J

27P_0402_50V8J

1

CH13

CH13

2

CLK_PCIE_MINI1#31
CLK_PCIE_MINI131

CLK_RES_ITP#7

CLK_RES_ITP7

CH10 0.1U_0402_10V7KCH10 0.1U_0402_10V7K
CH11 0.1U_0402_10V7KCH11 0.1U_0402_10V7K

CLK_PCIE_CD#34
CLK_PCIE_CD34

+3V_PCH

LAN_CLKREQ#34

+3VS

MINI1_CLKREQ#31

+3VS

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

+3V_PCH

CLK_PCH_14M

CH37 0.1U_0402_10V7KCH37 0.1U_0402_10V7K

1 2

CH9 0.1U_0402_10V7KCH9 0.1U_0402_10V7K

1 2

1 2
1 2

RH182 10K_0402_5%RH182 10K_0402_5%

RH180 10K_0402_5%RH180 10K_0402_5%

RH177 10K_0402_5%RH177 10K_0402_5%

RH320 10K_0402_5%RH320 10K_0402_5%

RH183 10K_0402_5%RH183 10K_0402_5%

RH185 10K_0402_5%RH185 10K_0402_5%

RH189 10K_0402_5%RH189 10K_0402_5%

RH190 0_0402_5%@RH190 0_0402_5%@
RH191 0_0402_5%@RH191 0_0402_5%@

4

RH4 0_0402_5%RH4 0_0402_5%
RH5 0_0402_5%RH5 0_0402_5%

RH171

RH171

10K_0402_5%

10K_0402_5%

1 2

RH175 10K_0402_5%RH175 10K_0402_5%

12

MINI1CLK_REQ#

1 2

12

12

1 2

1 2

1 2

1 2

12
12

@

@

RH193

RH193

12

33_0402_5%

33_0402_5%

1 2

22P_0402_50V8J

22P_0402_50V8J

PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

12
12

CLK_PCIE_MINI1#
CLK_PCIE_MINI1

CLK_BCLK_ITP#
CLK_BCLK_ITP

@

@

CH14

CH14

PCIE_CD#
PCIE_CD

UH1B

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_ B_N

AB40

CLKOUT_PEG_ B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

SMBUSController

SMBUSController

SML1ALERT# / PCH HOT# / GPIO74

PCI-E*

PCI-E*

CLOCKS

CLOCKS

3

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_ A_N
CLKOUT_PEG_ A_P

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKOUT_DP_ N

CLKOUT_DP_ P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N

CLKIN_GND1_P

CLKIN_DOT_96 N
CLKIN_DOT_96 P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

SMBALERT#

E12

SMBCLK

H14

SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

SML0CLK

C8

SML0DATA

G12

GPIO74

C13

SML1CLK

E14

SML1DATA

M16

M7

T11

P10

PEG_CLKREQ#_R

M10

CLK_VGA#

AB37

CLK_VGA

AB38

AV22

CLK_CPU_DMI_PCH

AU22

AM12
AM13

CLKIN_DMI#

BF18

CLKIN_DMI

BE18

CLKIN_DMI2#

BJ30

CLKIN_DMI2

BG30

CLKIN_DOT96#

G24

CLKIN_DOT96

E24

CLKIN_SATA#

AK7

CLKIN_SATA

AK5

CLK_PCH_14M

K45

CLK_PCI_LPBACK

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

K43

F47

H47

DGPU_PRSNT#

K49

T1616 PAD~D@ T1616 PAD~D@
T1628 PAD~D@ T1628 PAD~D@

T1615 PAD~D@ T1615 PAD~D@

T1627 PAD~D@ T1627 PAD~D@

T1629 PAD~D@ T1629 PAD~D@

RH155 10K_0402_5%RH155 10K_0402_5%

1 2

DRAMRST_CNTRL_PCH 6,9

+3V_PCH

12

RH8

RH8
10K_0402_5%

10K_0402_5%

12

12
12

RH172 0_0402_5%RH172 0_0402_5%

1 2

RH173 0_0402_5%RH173 0_0402_5%

1 2

CLK_PCI_LPBACK 16

1 2

RH184 90.9_0402_1%RH184 90.9_0402_1%

R2860_0402_5% R2860_0402_5%

R2750_0402_5% R2750_0402_5%
R2760_0402_5% R2760_0402_5%

2

+3V_PCH

VGA_CLKREQ# 22

CLK_PCIE_VGA# 21
CLK_PCIE_VGA 21

CLK_CPU_DMI#CLK_CPU_DMI#_PCH
CLK_CPU_DMI

+1.05VS_VCCDIFFCLKN

+3VS

1 2

1 2

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

SMBCLK

SMBDATA

RH316

RH316
10K_0402_5%UMA@

10K_0402_5%UMA@

RH318

RH318
10K_0402_5%PX@

10K_0402_5%PX@

DB# 10/14 check to intel

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

2

6 1

QH2A

QH2A

RH192

@RH192

@

1 2

0_0402_5%

0_0402_5%

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

1

SMBDATA

SMBCLK

SML0CLK

SML0DATA

SML1CLK

SML1DATA

GPIO74

DRAMRST_CNTRL_PCH

CLKIN_DMI2#
CLKIN_DMI2
CLKIN_DMI#
CLKIN_DMI
CLKIN_DOT96#
CLKIN_DOT96
CLKIN_SATA#
CLKIN_SATA
CLK_PCH_14M

If use extenal CLK gen, please place close to CLK gen
else, please place close to PCH

+3VS

2.2K_0402_5%

2.2K_0402_5%

5

3 4

QH2B

QH2B

RH194

RH194

1 2

0_0402_5%

0_0402_5%

@

@

+3VS

1 2

RH152 2.2K_0402_5%RH152 2.2K_0402_5%

1 2

RH153 2.2K_0402_5%RH153 2.2K_0402_5%

1 2

RH156 2.2K_0402_5%RH156 2.2K_0402_5%

1 2

RH157 2.2K_0402_5%RH157 2.2K_0402_5%

1 2

RH159 2.2K_0402_5%RH159 2.2K_0402_5%

1 2

RH160 2.2K_0402_5%RH160 2.2K_0402_5%

RH263 10K_0402_5%RH263 10K_0402_5%

1 2

1 2

RH161 1K_0402_5%RH161 1K_0402_5%

RH176

RH176

1 2

1M_0402_5%@

1M_0402_5%@

RH162 10K_0402_5%RH162 10K_0402_5%

1 2

RH163 10K_0402_5%RH163 10K_0402_5%

1 2

RH164 10K_0402_5%RH164 10K_0402_5%

1 2

RH165 10K_0402_5%RH165 10K_0402_5%

1 2

RH166 10K_0402_5%RH166 10K_0402_5%

1 2

RH167 10K_0402_5%RH167 10K_0402_5%

1 2

RH168 10K_0402_5%RH168 10K_0402_5%

1 2

RH169 10K_0402_5%RH169 10K_0402_5%

1 2

RH170 10K_0402_5%RH170 10K_0402_5%

1 2

+3VS

RH186

RH186

+3VS

1 2

RH188

RH188

2.2K_0402_5%

2.2K_0402_5%

1 2

PCH_SMBCLK 11,12,37,40

PCH_SMBDATA 11,12,37,40

+3V_PCH

Reserve for EMI please close t o UH1

RH291

@

@

@

12

1 2

22P_0402_50V8J

22P_0402_50V8J

@

CH15

CH15

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

SML1CLK

6 1

SML1DATA

2

QH6A

QH6A

2N7002DWH_SOT363-6

2N7002DWH_SOT363-6

RH195

CLK_PCI_LPBACK

Reserve for EMI please close t o
UH1

A A

RH195

33_0402_5%

33_0402_5%

2.2K_0402_5%

2.2K_0402_5%

5

3 4

QH6B

QH6B

RH291

1 2

RH311

RH311

2.2K_0402_5%

2.2K_0402_5%

1 2

EC_SMB_CK2 22,36

EC_SMB_DA2 22,36

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DR AWING IS THE PR OPRIETARY PROPERT Y OF COMPAL ELECT RONICS, INC. AND CONTAINS CON FIDENTIAL
AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D

AND TRAD E SECRET INFOR MATION. THIS SHEET M AY NOT BE TRANSF ERED FROM T HE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS

DEPARTMEN T EXCEPT AS AUT HORIZED BY COMPA L ELECTRONICS, INC . NEITHER THIS SHE ET NOR THE INF ORMATION IT CONT AINS
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WRI TTEN CONSENT OF COMPAL ELECTRONICS, IN C.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

PCH (2/8) PCIE, SMBUS, CLK

LA-8711

LA-8711

LA-8711

1

14 57Sunday, November 27, 2011

14 57Sunday, November 27, 2011

14 57Sunday, November 27, 2011

0.1

0.1

0.1

5

UH1C

DMI_CTX_PRX_N04
DMI_CTX_PRX_N14
DMI_CTX_PRX_N24
DMI_CTX_PRX_N34

DMI_CTX_PRX_P04
DMI_CTX_PRX_P14
DMI_CTX_PRX_P24
DMI_CTX_PRX_P34

D D

XDP_DBRESET#5

SYS_PWROK5

C C

PCH_RSMRST#36

PCH_GPIO29

B B

GPIO72

RI#

WAKE#

ACIN_R

SUSWARN#

PCH_RSMRST#

PCH_PWROK

A A

DMI_CRX_PTX_N04
DMI_CRX_PTX_N14
DMI_CRX_PTX_N24
DMI_CRX_PTX_N34

DMI_CRX_PTX_P04
DMI_CRX_PTX_P14
DMI_CRX_PTX_P24
DMI_CRX_PTX_P34

+1.05VS

RH196 49.9_0402_1%RH196 49.9_0402_1%

RH197 750_0402_1%RH197 750_04 02_1%

4mil width and place
within 500mil of the PCH

SUSWARN# SUSACK#_R

SUSACK#36

SYS_PWROK

PCH_PWROK36

PM_DRAM_PWRGD5

SUSWARN#36

PBTN_OUT#36

C268

PCH_PWROK

PCH_RSMRST# PCH_RSMRST#_R

ACIN22,36,48

RH228 10 K_0402_5%RH228 10 K_0402_5%

1 2

RH210 10 K_0402_5%RH210 10 K_0402_5%

1 2

RH211 10 K_0402_5%RH211 10 K_0402_5%

1 2

RH212 10 K_0402_5%RH212 10 K_0402_5%

1 2

RH214 100K_0402_5%RH214 100K_0402_5%

1 2

RH216 10 K_0402_5%RH216 10 K_0402_5%

1 2

RH217 10 K_0402_5%RH217 10 K_0402_5%

1 2

@C268

@

1 2

100P_0402_50V8J

100P_0402_50V8J

PCH_PWROK

VGATE55

RH223 10K_0402_5%RH223 10K_0402_5%

5

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3

DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3

1 2

1 2

RH198 0_0402_ 5%

RH198 0_0402_ 5%

RH200 0_0402_ 5%RH200 0_0402_ 5%

RH202 0_0402_5%RH202 0_0402_5%

RH203 0_0402_5%RH203 0_0402_5%

RH206 0_0402_5%RH206 0_0402_5%

RH208 0_0402_5%RH208 0_0402_5%

RH209 0_0402_5%RH209 0_0402_5%

DH2 CH751H-40PT_SOD323-2DH2 CH75 1H-40PT_SOD323-2

GPIO72

1

2

DMI_IRCOMP

RBIAS_CPY

@

@

1 2

SUSACK#_R

1 2

XDP_DBRESET#

1 2

PM_PWROK_R

1 2

1 2

RH204 0_0402_5%RH204 0_0402_5%

PM_DRAM_PWRGD

1 2

SUSWARN#_R

1 2

PBTN_OUT#_R

1 2

ACIN_R

21

RI#

+3V_PCH

+3VS

5

UH3

UH3

IN1

VCC

SYS_PWROK

4

OUT

IN2

GND

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

3

12

SYS_PWROK

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

RH213 330K_0402_5%RH213 330K_0402_5%

DSWODVREN

DSWODVREN

RH215 330K_0402_5%

RH215 330K_0402_5%

DSWODVREN - On Die DSW VR Enable

H：Enable

*

L：Disable

4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5

DMI

DMI

System Power Management

System Power Management

@

@

FDI_RXP6

FDI

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Check EC for S3 S4 LED

12

12

+3VS

RH218 8.2K_0402_5%RH218 8.2K_0402_5%

1 2

RH219 2.2K_0402_5%RH219 2.2K_0402_5%

1 2

RH221 2.2K_0402_5%RH221 2.2K_0402_5%

1 2

1 2

RH222 2.37K_0402_1 %RH222 2.37K_0402_1%

1 2

RH224 100K_0402_5%RH224 100K_0402_5%

1 2

RH225 100K_0 402_5%RH225 100K_0402_5%

4

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

+RTCVCC

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK

WAKE#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#

H_PM_SYNC

PCH_GPIO29

LVDS_IBG

PCH_ENVDD

ENBKL

RH199 0_0402_5%RH199 0_0402_5%

1 2

1 2

RH201 0_0402_5%RH201 0_0402_5%

PM_CLKRUN#

12

RH205 0_0402_5%RH205 0_0402_5%

SLP_A# 36

SPOK47,49

PM_CLKRUN#

CTRL_CLK

CTRL_DATA

FDI_CTX_PRX_N0 4
FDI_CTX_PRX_N1 4
FDI_CTX_PRX_N2 4
FDI_CTX_PRX_N3 4
FDI_CTX_PRX_N4 4
FDI_CTX_PRX_N5 4
FDI_CTX_PRX_N6 4
FDI_CTX_PRX_N7 4

FDI_CTX_PRX_P0 4
FDI_CTX_PRX_P1 4
FDI_CTX_PRX_P2 4
FDI_CTX_PRX_P3 4
FDI_CTX_PRX_P4 4
FDI_CTX_PRX_P5 4
FDI_CTX_PRX_P6 4
FDI_CTX_PRX_P7 4

FDI_INT 4

FDI_FSYNC0 4

FDI_FSYNC1 4

FDI_LSYNC0 4

FDI_LSYNC1 4

PCH_DPWROK 36

T38 PAD~DT38 PAD~D

PM_SLP_S5# 36

PM_SLP_S4# 36

PM_SLP_S3# 36

PM_SLP_SUS# 36

H_PM_SYNC 5

3

PCH_RSMRST#

PCH_PCIE_WAKE# 34

SUSCLK_R 36

2 1

D30 CH751 H-40PT_SOD323-2D30 CH751H-40PT_SOD323-2

21

D29 CH751 H-40PT_SOD323-2D29 CH751H-40PT_SOD323-2

PCH_CRT_CLK30

PCH_CRT_DATA30

PCH_CRT_HSYNC30
PCH_CRT_VSYNC30

PM_CLKRUN#

EC Request
on 20110309

12

RH308

RH308
10K_0402_5%

10K_0402_5%

@

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

ENBKL36

PCH_ENVDD32

DPST_PWM32

PCH_LCD_CLK32

PCH_LCD_DATA32

1 2

RH207 0_0402_ 5%RH207 0_0402_ 5%

PCH_TXCLK-32
PCH_TXCLK+32

PCH_TXOUT0-32
PCH_TXOUT1-32
PCH_TXOUT2-32

PCH_TXOUT0+32
PCH_TXOUT1+32
PCH_TXOUT2+32

PCH_RSMRST#PCH_PWROK

PCH_CRT_B30
PCH_CRT_G30
PCH_CRT_R30

1K_0402_0.5%

1K_0402_0.5%

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

ENBKL

PCH_LCD_CLK
PCH_LCD_DATA

T37PAD~D T37PAD~D

LVD_VREF

PCH_TXCLK­PCH_TXCLK+

PCH_TXOUT0­PCH_TXOUT1­PCH_TXOUT2-

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

PCH_CRT_CLK
PCH_CRT_DATA

PCH_CRT_HSYNC
PCH_CRT_VSYNC

RH220

RH220

Compal Secret Data

Compal Secret Data

Compal Secret Data

CTRL_CLK

CTRL_DATA

LVDS_IBG

CRT_IREF

12

J47

M45

P45

T40
K47

T45
P39

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47
AK47

AJ48

AN47
AM49
AK49

AJ47

AF40
AF39

AH45
AH47
AF49
AF45

AH43
AH49
AF47
AF43

N48
P49
T49

T39

M40

M47
M49

T43
T42

Deciphered Date

Deciphered Date

Deciphered Date

UH1D

UH1D

L_BKLTEN
L_VDD_EN

L_BKLTCTL

L_DDC_CLK
L_DDC_DATA

L_CTRL_CLK
L_CTRL_DATA

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

mDP

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

CRT

DMC

2

AP43
AP45

AM42
AM40

AP39

SDVO_INTN

AP40

SDVO_INTP

P38
M39

AT49

DDPB_AUXN

AT47

DDPB_AUXP

AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46
P42

AP47

DDPC_AUXN

AP49

DDPC_AUXP

AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

M43
M36

AT45

DDPD_AUXN

AT43

DDPD_AUXP

BH41

DDPD_HPD

BB43

DDPD_0N

BB45

DDPD_0P

BF44

DDPD_1N

BE44

DDPD_1P

BF42

DDPD_2N

BE42

DDPD_2P

BJ42

DDPD_3N

BG42

DDPD_3P

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

PCH (3/8) DMI,FDI,PM,GFX,DP

LA-8711

LA-8711

LA-8711

1

PCH_DDPB_CLK 29
PCH_DDPB_DAT 29

PCH_DDPB_HPD 29

PCH_DPB_N2 29
PCH_DPB_P2 2 9
PCH_DPB_N1 29
PCH_DPB_P1 2 9
PCH_DPB_N0 29
PCH_DPB_P0 2 9
PCH_DPB_N3 29
PCH_DPB_P3 2 9

1

HDMI

0.1

0.1

15 57Sunday, November 27, 2011

15 57Sunday, November 27, 2011

15 57Sunday, November 27, 2011

0.1

5

D D

USB3_RX1_N35
USB3_RX2_N35
USB3_RX3_N35

USB3_RX1_P35
USB3_RX2_P35

USB3.0 x3

C C

WL_OFF#31

DB# 10/20 move ACCEL_INT# to P CH_GPIO_02.
PCH_GPIO_03 is reserved for O DD_DA#

AOAC_PME#36

B B

A A

CLK_PCI_LPBACK14

CLK_PCI_LPC36

CLK_PCI_DEBUG31

CLK_PCI_LPC
CLK_PCI_DEBUG

DP_CBL_DET
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQC#

PIRQH#
GPIO53
ODD_DA#
GPIO51

PCI_PIRQA#

ACCEL_INT#

DGPU_HOLD_RST#

DGPU_SELECT#

PXS_PWREN

WL_OFF#

5

USB3_RX3_P35

USB3_TX1_N35
USB3_TX2_N35
USB3_TX3_N35

USB3_TX1_P35
USB3_TX2_P35
USB3_TX3_P35

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

DGPU_HOLD_RST#21

PXS_PWREN23,53,54,56

WL_OFF#

ACCEL_INT#42

ODD_DA#33

AOAC_PME# PCH_AOAC_PME#

RPH3

RPH3

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RPH4

RPH4

1 8
2 7
3 6
4 5

8.2K_0804_8P4R_5%

8.2K_0804_8P4R_5%

RH7

RH7

1 2

1 2

RH235 10K_0402_5%@ RH235 10K_0402_5%@

1 2

RH236 10K_0402_5%RH236 10K_0402_5%

1 2

RH237 10K_0402_5%RH237 10K_0402_5%

1 2

RH302 10K_0402_5%RH302 10K_0402_5%

1 2

1 2

RH274 0_0402_5%RH274 0_0402_5%

PLT_RST#5,21,31,34,36

RH230 22_0402_5%RH230 22_0402_5%
RH231 22_0402_5%RH231 22_0402_5%

1 2

RH242 22_0402_5%RH242 22_0402_5%

1 2

8.2K_0402_5%

8.2K_0402_5%

RH6 8.2K_0402_5%RH6 8.2K_0402_5%

DGPU_HOLD_RST#
DGPU_SELECT#
PXS_PWREN

GPIO51
GPIO53

ACCEL_INT#

ODD_DA#
DP_CBL_DET
PIRQH#

PLT_RST#

+3VS

CLK_PCI0CLK_PCI_LPBACK
CLK_PCI1
CLK_PCI2

12

DB# 11/1 Reserve 10pF by RF re quest

CLK_PCI1

4

UH1E

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

@

@

CH83

CH83

1 2

10P_0402_50V8J

10P_0402_50V8J

10K_0402_5%

10K_0402_5%

PLT_RST_BUF#31

4

@

@

RH233

RH233

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

RSVD

RSVD

PCI

PCI

USB

USB

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC6# / GPIO10
OC7# / GPIO14

+3VS

1 2

12

RH234

@RH234

@

100K_0402_5%

100K_0402_5%

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

C33

USBRBIAS#

B33

USBRBIAS

A14
K20
B17
C16
L16
A16

OC5# / GPIO9

D14
C14

1 2

RH232 0_0402_5%RH232 0_0402_5%

+3VS

5

UH4

@UH4

@

P

IN1

4

O

IN2

G

SN74AHC1G08DCKR_SC70-5

SN74AHC1G08DCKR_SC70-5

3

1

2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3

USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10

USBRBIAS

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

Within 500 mils

RH229 22.6_0402_1%RH229 22.6_0402_1%

PLT_RST#

USB20_N0 35
USB20_P0 35
USB20_N1 35
USB20_P1 35
USB20_N2 35
USB20_P2 35
USB20_N3 42
USB20_P3 42

USB20_N8 32
USB20_P8 32
USB20_N9 35
USB20_P9 35
USB20_N10 31
USB20_P10 31

1 2

To USB3.0 connector
(Port 0 & 1 & 2)

USB2.0 Finger Print (Port 3)

Camera

USB2.0 and sleep charger(Port 9)

mPCIE-WLAN/BT

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

2

Deciphered Date

Deciphered Date

Deciphered Date

2

1

+3V_PCH

RPH1

USB_OC3#
USB_OC2#

USB_OC0#35

USB_OC0#
USB_OC1#

USB_OC4#
USB_OC6#
USB_OC7#
USB_OC5#

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

PCH (4/8) PCI, USB, NVRAM

LA-8711

LA-8711

LA-8711

RPH1

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

10K_1206_8P4R_5%

RPH2

RPH2

4 5
3 6
2 7
1 8

10K_1206_8P4R_5%

10K_1206_8P4R_5%

1

0.1

0.1

16 57Sunday, November 27, 2011

16 57Sunday, November 27, 2011

16 57Sunday, November 27, 2011

0.1

5

D D

GPIO28

On-Die PLL Voltage Regulator

This signal has a weak internal pull up

H：On-Die voltage regulator enabl e

*

L：On-Die PLL Voltage Regulator d isable

+3V_PCH

RH267 10K_0402_5%RH267 10K_0402_5%

RH241 1K_0402_5%

RH241 1K_0402_5%

PCH_GPIO37

C C

FDI TERMINATION VOLTAGE OVERRIDE

LOW - Tx, Rx terminated

*

to same voltage
(DC Coupling Mode)

+3VS

RH245 1K_0402_5%@RH245 1K_0402_5%@

RH246

RH246

1 2

1 2

@

@

12

12

100K_0402_5%

100K_0402_5%

SLP_ME_CSW_DEV#

SLP_ME_CSW_DEV#

PCH_GPIO37

PCH_GPIO37

DB# 10/20 Common BT_ON is GPIO 34
(Rout to GPIO 38 currently), G PIO 38 pull
high 10K to 3VS only

GPIO27

PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable

*

Low: VCCVRM VR Disable

RH250 10K_0402_5%@ RH250 10K_0402_5%@

B B

A A

DB# 10/20 Reserve GPIO 36 pull up resistor
and add pull down resistor

DB# 11/23 pull up +3VS for ODD _detect#

+3VS

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

1 2

@ RH255

@

RH301

RH301

RH255

PCH_GPIO27

12

12

ODD_DETECT#

ODD_DETECT#

EC_LID_OUT#36

SLP_ME_CSW_DEV#36

BT_ON#31

ODD_DETECT#33

HDD_DETECT#33

4

GPIO036

EC_SCI#36

EC_SMI#36

RH154 0_0402_5%RH154 0_0402_5%

VGA_PWRGD56

DDR3L_EN51

12

VGA_PWRGD

BT_ON#

ODD_DETECT#

GPIO49

HDD_DETECT#

GPIO0

GPIO1

GPIO6

EC_SCI#

EC_SMI#

DMC_DET#

EC_LID_OUT#_R

PCH_GPIO16

PCH_GPIO22

DDR3L_EN

PCH_GPIO27

SLP_ME_CSW_DEV#

PCH_GPIO35

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

UH1F

UH1F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

3

ODD_EN#

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

C40

B41

C41

A40

P4

AU16

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

PCH_PECI_R

EC_KBRST#

H_THERMTRIP#_C

NV_CLE

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

GPIO

GPIO

CPU/MISC

CPU/MISC

NCTF

NCTF

@

1 2

RH2390_0402_5%@RH2390_0402_5%

1 2

ODD_EN# 33

RH240390_0402_5% RH240390_0402_5%

H_PECI 5,36

EC_KBRST# 36

H_CPUPWRGD 5

H_THEMTRIP#

2

+3VS

11/24 Kirk review need pu +3VS; but not in check list.

RH280

RH280
10K_0402_5%

10K_0402_5%

1 2

+3VS

RH238

RH238
10K_0402_5%

10K_0402_5%

1 2

GATEA20 36

+1.8VS

H_THEMTRIP# 5

RH227 1K_0402_5%RH227 1K_0402_5%

12

Layout note: CLOSE TO THE BRANCHING POINT

GPIO0

PCH_GPIO38

PCH_GPIO48

PCH_GPIO22

BT_ON#

PCH_GPIO39

VGA_PWRGD

GPIO49

ODD_EN#

GPIO6

GPIO1

EC_KBRST#

PCH_GPIO35

PCH_GPIO16

DDR3L_EN

HDD_DETECT#

DMC_DET#

EC_LID_OUT#_R

EC_SMI#

12

RH254 10K_0402_5%RH254 10K_0402_5%

RH226

RH226

2.2K_0402_5%

2.2K_0402_5%

RH310 10K_0402_5%RH310 10K_0402_5%

1 2

RH243 10K_0402_5%RH243 10K_0402_5%

1 2

RH244 10K_0402_5%RH244 10K_0402_5%

1 2

RH295 10K_0402_5%RH295 10K_0402_5%

1 2

RH273 10K_0402_5%RH273 10K_0402_5%

1 2

RH247 10K_0402_5%RH247 10K_0402_5%

1 2

1 2

RH248

@RH248

@

1 2

RH249

RH249

1 2

RH251

RH251

1 2

RH252

RH252

1 2

RH253

@RH253

@

1 2

1 2

RH256

RH256

1 2

RH257

RH257

1 2

RH258

RH258

1 2

RH259

RH259

1 2

RH260

RH260

1 2

RH261

RH261

1 2

RH262

RH262

H_SNB_IVB# 5

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

1K_0402_5%

1K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

1

+3VS

+3V_PCH

+3VS

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

PCH (5/8) GPIO, CPU, MISC

LA-8711

LA-8711

LA-8711

1

17 57Sunday, November 27, 2011

17 57Sunday, November 27, 2011

17 57Sunday, November 27, 2011

of

0.1

0.1

0.1

5

4

3

2

1

+1.05VS

1

CH17

CH17

10U_0603_6.3V6M

D D

+1.05VS

+1.05VS

C C

+1.05VS

B B

10U_0603_6.3V6M

12

RH264 0_0603_5%

RH264 0_0603_5%

@

@

RH297

RH297

1 2

0_0805_5%

0_0805_5%

+3VS

12

RH268

RH268
0_0805_5%

0_0805_5%

1

0.1U_0402_10V7K

0.1U_0402_10V7K

2

Place CH53 Near AP13,AP15 pin

RH270 0_0603_5%

RH270 0_0603_5%

Place CH35 Near AP19 pin

1

CH28

CH28

2

10U_0603_6.3V6M

10U_0603_6.3V6M

+3VS_VCCA3GBG

CH35

CH35

12

@

@

1

CH18

2

1

2

CH18

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

CH29

CH29

CH30

CH30

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS_VCCAPLL_FDI

+1.05VS

1

CH19

CH19

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.05VS

1

CH32

CH32

CH31

CH31

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCAFDI_VRM

RH271

RH271

1 2

0_0805_5%

0_0805_5%

+VCCP_VCCDMI

1

CH16

CH16

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCAPLLEXP

1

CH27

CH27

2

@

@

10U_0805_4VAM

10U_0805_4VAM

+1.05VS_VCCDPLL_FDI

UH1G

UH1G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

PANTHER-POINT_FCBGA989

1300mA

POWER

POWER

VCC CORE

VCC CORE

2925mA

VCCIO

VCCIO

FDI

FDI

CRTLVDS

CRTLVDS

DMI

DMI

DFT / SPI HVCMOS

DFT / SPI HVCMOS

60mA

20mA

190mA

1mA

VCCADAC

VSSADAC

1mA

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

VCCSPI

20mA

U48

U47

AK36

AK37

AM37

AM38

AP36

AP37

+3VS_VCC3_3_6

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

+3V_VCCPSPI

V1

CH38

CH38

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCADAC

+VCCP_VCCDMI

+1.05VS_VCC_DMI_CCI

+3VS

+VCCTX_LVDS

0.01U_0402_16V7K

0.01U_0402_16V7K

+VCCAFDI_VRM+1.05VS_VCC_EXP

1

2

1

2

CH23

CH23

1

2

1

2

1

CH21

CH21

CH20

CH20

2

0.01U_0402_16V7K

0.01U_0402_16V7K

Near AP43

1

2

RH265

RH265

1 2

0_0805_5%

0_0805_5%

CH26

CH26

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

1

CH34

CH34
1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCCPNAND

CH36

CH36

0.1U_0402_10V7K

0.1U_0402_10V7K

RH272

RH272

1 2

0_0805_5%

0_0805_5%

1

CH22

CH22
10U_0603_6.3V6M

10U_0603_6.3V6M

2

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CH24

CH24

0.01U_0402_16V7K

0.01U_0402_16V7K

2

+VCCP_VCCDMI

RH314

RH314

0_0805_5%

0_0805_5%

1 2

RH269 0_0805_5%RH269 0_0805_5%

+3V_PCH

LH1

LH1

BLM18PG181SN1D_2P

BLM18PG181SN1D_2P

1

CH25

CH25

2

+3VS

+1.05VS

+1.8VS

+3VS

12

0.1UH_MLF1608DR10KT_10%_1608

0.1UH_MLF1608DR10KT_10%_1608
LH2

LH2

0.1uH inductor, 200mA

22U_0805_6.3V6M

22U_0805_6.3V6M

RH266

RH266

1 2

1

0_0805_5%

0_0805_5%

CH33

CH33

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.8VS

12

+1.05VS

PCH Power Rail Table

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

3.3

1.05

1.05

1.05

1.05

S0 Iccmax
Current (A)

0.001

5

5

0.001

0.001

0.266

0.001

0.08

0.08

1.3

0.042

1.05V ccIO 2.925

1.05V ccASW 1.01

3.3VccSPI 0.02

3.3VccDSW 0.003

1.8 0.19VccpNAND

3.3VccRTC 6 uA

3.3VccSus3_3

3.3 / 1.5VccSusHDA

0.119

0.01

VccVRM 1.8 / 1. 5 0 .16

1.05V ccCLKDMI

0.02

VccSSC 1.05 0. 095

VccDIFFCLKN 1.05 0.0 55

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0 .06

11/24 change +1.5VS to 1.5VPCIEV

+VCCAFDI_VRM

RH275

RH275

1.5VPCIEV

A A

5

4

12

0_0603_5%

0_0603_5%

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS

DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VCCAFDI_VRM

Compal Secret Data

Compal Secret Data

2011/11/02 2011/11/02

2011/11/02 2011/11/02

2011/11/02 2011/11/02

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

PCH (6/8) PWR

PCH (6/8) PWR

PCH (6/8) PWR

LA-8711

LA-8711

LA-8711

1

18 57Sunday, November 27, 2011

18 57Sunday, November 27, 2011

18 57Sunday, November 27, 2011

0.1

0.1

0.1