COMPAL LA-8692P Schematics

A

1 1

B

C

D

E

QIQY6

2 2

Brandy3.0 (Y500)

LA-8692P Rev0.2 Schematic

3 3

Intel IVY Bridge Processor with DDRIII + Panther Point PCH

nVIDIA N13P GT-1 + 2nd VGA N13P GT-1

2012-02-05 Rev0.2

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

2012/07/01

LC Future Center Secret Data

Deciphered Date

D

2014/07/01

Title

Cover Page

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

E

1 66

0.2

A

B

C

D

E

Chief River

PCI-Express 16X Gen3

PEG 0~7PEG 8~15

1 1

2nd VGA N13P-GT1

VRAM 64*32

GDDR5*8

Sub/B (SLI)

Page 32 Page 23,24,25,26,27,28,29,30,31

N13P-GT1

VRAM 64*32

GDDR5*8

FDI *8

2.7GT/s

HDMI Conn. CRT Conn. LVDS Conn.

HDMI1.4b

2 2

Atheros

RJ45 Conn.

Page 40

AR8161 1G AR8151 1G

PCIe port 1

CardReader JMB389 SD/MMC/MS/XD

PCIe port 4

3 3

SPI ROM (4MB+2MB)

Page 39

Page 44

Page 14

Page 34Page 36Page 37

PCIe Gen1 1x

1.5V 5GT/s

PCIe Gen1 1x

1.5V 5GT/s

SPI BUS

3.3V 33MHz

Intel

IVY Bridge

Processor

Socket-rPGA989

37.5mm*37.5mm

Intel Panther Point

PCH

FCBGA 989 Balls

25mm*25mm

LPC BUS

3.3V 33MHz

Memory BUS (DDRIII) Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

DMI *4 5GT/s

USB 2.0 1x 5V 480MHz

USB 2.0 3x 5V 480MHz

USB 3.0 3x

5V 5GT/s

USB 2.0 2x 5V 480MHz

PCIe Gen1 2x 5V 480MHz

SATA Gen3 Port 0 5V 6GHz(600MB/s)

SATA Gen3 Port 1 SATA HDD 5V 6GHz(600MB/s)

SATA Gen1 Port2 5V 3GHz(300MB/s)

HD Audio

3.3V 24MHz

USB Left

USB 3.0 Port 2 USB 3.0 Port 3

Int. Camera

USB 3.0 Port 0 USB 2.0 Port 0

PCIeMini Card WLAN

SATA ODD

Page 48

Page 50

PCIe Port 2

page 38

USB Port 10

page 38

SATA Port 1

page 41

SATA Port 1

page 41

DDR3-SO-DIMM X2

BANK 0, 1, 2, 3

TV

USB 2.0 Port 12

USB 2.0 Port 13

mSATA SSD

PCIeMini Card TV

Page 38

BT

Page 47

SATA Port 0

PCIe Port 3

USB Port 12

UP TO 16G

page 38

USB Charger

PS8710BT

Page 50

USB Right

USB 2.0 Port 9, Cha

Sub/B

Page 50

EC ITE IT8580E

Page 45

Codec ALC269Q-VC3

Page 43

SPK Conn.

Page 43

Power Circuit DC/DC

Page 54,55,56,57,58,59, 60,61,62,63,64

4 4

DC/DC Interface CKT.

POWER/B Conn. AUDIO, USB/B Conn.

ODD/B Conn.

Page 53

Page 51 Page 49

page 42

A

RTC CKT.

NOVO/B Conn.

Page 54

Page 51

B

Touch Pad

Page 46

Int.KBD

Page 46

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

Thermal Sensor EMC 1403

LC Future Center Secret Data

2012/07/01

LC Future Center Secret Data

Page 41

Deciphered Date

Int. MIC Conn. (JCMOS Conn.)

Page 50 Page 49

2014/07/01

D

Ext. MIC Conn.

Sub/B

Title

MB Block Diagram

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

Sub/B

HP Conn.

Page 49

LA-8692P

LA-8692PLA-8692P

E

2 66

0.2

A

B

C

D

E

Voltage Rails

+5VS

+3VS

+1.5VS

plane

1 1

+B

State

+5VALW

+3VALW

+1.5V

+VCCSApower

+V1.5S_VCCP

+CPU_CORE

+VGA_CORE

+GFX_CORE

+1.8VS

+1.05VS

+0.75VS

+3.3VS_VGA

+1.5VS_VGA

+1.05VS_VGA

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

HIGH HIGH HIGH HIGH

LOW

LOW LOW LOW LOW

HIGH

LOWLOWLOW

HIGHHIGHHIGH

HIGH

ON

OFF

ON

OFF

ON ON

ON

OFF

LOW

OFF

S0

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O

X

SMBUS Control Table

2nd

Main

SOURCE

VGA

BATT

SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA

3 3

SML0CLK SML0DATA SML1CLK SML1DATA

IT8580E

+3VALW

IT8580E

+3VALW

PCH

+3VALW

PCH

+3VALW

PCH

+3VALW

Address

X V

X

+3VALW

X

V

+3VS

EC SM Bus1 address

Device

Smart Battery

0001 011X b

PCH SM Bus address

Device Address

DDR DIMM0

4 4

DDR DIMM2

1001 000Xb

1001 010Xb

O

X

O

X X

X

X X X

IT8580E SODIMM

X

V

X

+3VS

Thermal Sen sor EMC1403-2

X X

V

+3VS

X X

EC SM Bus2 address

Device

Master VGA

Slave VGA

WLAN WWAN

X XX

V

+3VS

X

Thermal Sensor

Address

1001_101xb

0x9E

0x9C

X X X XX

V

+3VS

OO

X

USB Port Table

X

USB 3.0USB 2.0 Port

0

1

PCH

X

V

+3VS

X X X

XHCI

EHCI1

EHCI2

1

2

3

4

4 5 6 7

8

9 10 11 12 13

4 External USB Port

Camera

USB Port (Left Side) USB Port (Left Side)

USB Port (Left Side)

USB Port (Right Side)

Mini Card(WLAN)

Mini Card(TV)

Blue Tooth

PCIE PORT LIST

Port Device

1

LAN

2

WLAN

3

TV

4

Card Reader

5 6 7 8

BOM Structure Table

BTO ItemBOM Structure

HDMI@

TV@ CMOS@ 8161@ 8151@ 8161S@ 8151S@ SURGE@

X76@ GC6@ NOGC6@

AOAC@ KBL@ ME@

OPT@ SLI@

DS3@

GT@

@

HDMI part

TV module part

CMOS Camera part

AR8161 LAN part

AR8151 LAN part

AR8161 LAN surge part

AR8151 LAN surge part

AR8151&8161 LAN surge part

X76 Level part for VRAM

NV CG6 support part

NV no CG6 support part AOAC support part

K/B Light part

ME part

For optimus function part

For SLI function part

Deep S3 support part

NV chip part

Unpop

ZZZ

DA80000T20J

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

C

2012/07/01

LC Future Center Secret Data

Deciphered Date

D

2014/07/01

Title

Notes List

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

E

3 66

0.2

5

4

3

2

1

Hot plug detect for IFP link E

VGA and GDDR5 Voltage Rails (N13Px GPIO)

GPIO I/O ACTIVE Function Description

GPIO0

D D

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

C C

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16

GPIO17

GPIO18

GPIO19

B B

+3VS_VGA

+VGA_CORE

+1.5VS_VGA

+1.05VS_VGA

OUT GPU VID4-

-

GPU VID3OUT

OUT

I/O

OUT

VGA_BL_PWM

-

VGA_ENVDD

- VGA_ENBKL

GPU VID1

-

GPU VID2

-

DPRSLPVR_VGA

-

Thermal Catastrophic Over Temperature

-

GPIO9

-

Memory VREF Control

-

GPU VID0-OUT

IN

OUT

IN

OUT

IN

1. all power ra il ramp up tim e should be la rger than 40us

AC Power Detect Input

GPU VID5-

FB_CLAMP_TOGGLE_REQ#

-

N/A (100K pull low)

GPIO16

-

N/A

GPIO17

-

dGPU_HDMI_HPD

GPIO19

-

tNVVDD >0

tFBVDDQ >0

tPEX_VDD >0

(10K pull High)

Performance Mode P0 TDP at Tj = 102 C* (GDDR5)

GPU Mem NVCLK (4) (1,5) (6)

Products

(W) (W) (MHz)

N13X 128bit 1GB GDDR5

Physical Strapping pin

ROM_SCLK

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

N13P-GT (28nm)

/MCLK NVVDD

(V) (A) (W) (A) (W)

TBD TBDTBD TBD TBD T BD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

Power Rail

+3VS_VGA

Device ID

0x0FDB

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

3GIO_PAD_CFG_AD R[2] 3GIO_PAD_CFG_AD R[1]3GIO_PAD_CFG_AD R[3]

setting

SMB_ALT_ADDR

(ROM_SO Bit 1)

0

1

ROM_SO ROM_SCLK

GPU

N13P-GT1 28nm

FB Memory (GDDR5)

Samsung 2500MHz

Hynix 2500MHz

Samsung 2500MHz

2500MHz

GPU

PU 25K

GC6@

PU 5K

OPT@,SLI@

PU 45KPU 10K PD 10K PD 45K

N13P-GT

ROM_SI

K4G10325FD-FC04

32Mx32

PD 45K

H5GQ1H24BFR-T2C

32Mx32 PD 35K

K4G20325FD-FC04

64Mx32

PD 30K

H5GQ2H24AFR-T2CHynix

64Mx32

PD 25K

PD 5K

FBVDDQ PCI Express I/O and

FBVDD

(GPU+Mem) (1.35V)(1.35V)

(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)

Logical Strapping Bit2

SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

SOR2_EXPOSED SOR1_EXPOSED

CHANGE_GEN3

I2C Slave addrees ID

0x9E

0x9C

STRAP2STRAP1STRAP0 STRAP3 STRAP4

(1.05V)

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

PCIE_MAX_SPEED DP_PL L_VDD33V

PU 5K

SLI@

PD 5K

OPT@

PLLVDD

I/O and PLLVDD

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_AD R[0]

SOR0_EXPOSED

Other

(3.3V)(1.05V)(1.8V)

Other Power rail

A A

+3VS_VGA

Tpower-off <10m s

1.all GPU power rails should be turned off within 10ms

2. Optimus syst em VDD33 avoid s drop down ea rlier than NVDD and FBVDDQ

5

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

VGA Notes List

Size Document Number Rev

Custom

Thursday, June 07, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

4 66

0.2

5

4

3

2

1

D D

+1.05VS

12

R1

24.9_0402_1%

JCPU1A

EDP_COMP

eDP_HPD

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD#

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE

ME@

DMI

Intel(R) FDI

eDP

DMI_CRX_PTX_N0<16> DMI_CRX_PTX_N1<16> DMI_CRX_PTX_N2<16> DMI_CRX_PTX_N3<16>

DMI_CRX_PTX_P0<16> DMI_CRX_PTX_P1<16> DMI_CRX_PTX_P2<16> DMI_CRX_PTX_P3<16>

DMI_CTX_PRX_N0<16> DMI_CTX_PRX_N1<16> DMI_CTX_PRX_N2<16> DMI_CTX_PRX_N3<16>

DMI_CTX_PRX_P0<16>

C C

+1.05VS

12

R7

B B

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

24.9_0402_1%

R7

FDI_FSYNC0<16> FDI_FSYNC1<16>

FDI_INT<16>

FDI_LSYNC0<16> FDI_LSYNC1<16>

DMI_CTX_PRX_P1<16> DMI_CTX_PRX_P2<16> DMI_CTX_PRX_P3<16>

FDI_CTX_PRX_N0<16> FDI_CTX_PRX_N1<16> FDI_CTX_PRX_N2<16> FDI_CTX_PRX_N3<16> FDI_CTX_PRX_N4<16> FDI_CTX_PRX_N5<16> FDI_CTX_PRX_N6<16> FDI_CTX_PRX_N7<16>

FDI_CTX_PRX_P0<16> FDI_CTX_PRX_P1<16> FDI_CTX_PRX_P2<16> FDI_CTX_PRX_P3<16> FDI_CTX_PRX_P4<16> FDI_CTX_PRX_P5<16> FDI_CTX_PRX_P6<16> FDI_CTX_PRX_P7<16>

FDI_FSYNC0 FDI_FSYNC1

FDI_INT

FDI_LSYNC0 FDI_LSYNC1

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

K33

PCIE_CRX_GTX_N0

M35

PCIE_CRX_GTX_N1

L34

PCIE_CRX_GTX_N2

J35

PCIE_CRX_GTX_N3

J32

PCIE_CRX_GTX_N4

H34

PCIE_CRX_GTX_N5

H31

PCIE_CRX_GTX_N6

G33

PCIE_CRX_GTX_N7

G30

PCIE_CRX_GTX_N8

F35

PCIE_CRX_GTX_N9

E34

PCIE_CRX_GTX_N10

E32

PCIE_CRX_GTX_N11

D33

PCIE_CRX_GTX_N12

D31

PCIE_CRX_GTX_N13

B33

PCIE_CRX_GTX_N14

C32

PCIE_CRX_GTX_N15

J33

PCIE_CRX_GTX_P0

L35

PCIE_CRX_GTX_P1

K34

PCIE_CRX_GTX_P2

H35

PCIE_CRX_GTX_P3

H32

PCIE_CRX_GTX_P4

G34

PCIE_CRX_GTX_P5

G31

PCIE_CRX_GTX_P6

F33

PCIE_CRX_GTX_P7

F30

PCIE_CRX_GTX_P8

E35

PCIE_CRX_GTX_P9

E33

PCIE_CRX_GTX_P10

F32

PCIE_CRX_GTX_P11

D34

PCIE_CRX_GTX_P12

E31

PCIE_CRX_GTX_P13

C33

PCIE_CRX_GTX_P14

B32

PCIE_CRX_GTX_P15

M29

PCIE_CTX_GRX_C_N0

M32

PCIE_CTX_GRX_C_N1

M31

PCIE_CTX_GRX_C_N2

L32

PCIE_CTX_GRX_C_N3

L29

PCIE_CTX_GRX_C_N4

K31

PCIE_CTX_GRX_C_N5

K28

PCIE_CTX_GRX_C_N6

J30

PCIE_CTX_GRX_C_N7

J28

PCIE_CTX_GRX_C_N8

H29

PCIE_CTX_GRX_C_N9

G27

PCIE_CTX_GRX_C_N10

E29

PCIE_CTX_GRX_C_N11

F27

PCIE_CTX_GRX_C_N12

D28

PCIE_CTX_GRX_C_N13

F26

PCIE_CTX_GRX_C_N14

E25

PCIE_CTX_GRX_C_N15

M28

PCIE_CTX_GRX_C_P0

M33

PCIE_CTX_GRX_C_P1

M30

PCIE_CTX_GRX_C_P2

L31

PCIE_CTX_GRX_C_P3

L28

PCIE_CTX_GRX_C_P4

K30

PCIE_CTX_GRX_C_P5

K27

PCIE_CTX_GRX_C_P6

J29

PCIE_CTX_GRX_C_P7

J27

PCIE_CTX_GRX_C_P8

H28

PCIE_CTX_GRX_C_P9

G28

PCIE_CTX_GRX_C_P10

E28

PCIE_CTX_GRX_C_P11

F28

PCIE_CTX_GRX_C_P12

D27

PCIE_CTX_GRX_C_P13

E26

PCIE_CTX_GRX_C_P14

D25

PCIE_CTX_GRX_C_P15

PEG_COMP

24.9_0402_1%

PCIE_CRX_GTX_N[0..15] <2 3,32>

PEG Static Lane Reversal - CFG2 is for the 16x

CFG2

PCIE_CRX_GTX_P[0..15] <23,32>

1 2

C1 0.22U _0402_10V6KC1 0.22U_0402_10V6K

1 2

C2 0.22U _0402_10V6KC2 0.22U_0402_10V6K

1 2

C3 0.22U _0402_10V6KC3 0.22U_0402_10V6K

1 2

C4 0.22U _0402_10V6KC4 0.22U_0402_10V6K

1 2

C5 0.22U _0402_10V6KC5 0.22U_0402_10V6K

1 2

C6 0.22U _0402_10V6KC6 0.22U_0402_10V6K

1 2

C7 0.22U _0402_10V6KC7 0.22U_0402_10V6K

1 2

C8 0.22U _0402_10V6KC8 0.22U_0402_10V6K

SLI@

1 2

C9 0.22U _0402_10V6K

SLI@

SLI@ 1 2

C10 0.22U_0402_10V6K

SLI@

1 2

C11 0.22U_0402_10V6K

SLI@

1 2

C12 0.22U_0402_10V6K

SLI@

1 2

C13 0.22U_0402_10V6K

SLI@

1 2

C14 0.22U_0402_10V6K

SLI@

SLI@ 1 2

C15 0.22U_0402_10V6K

SLI@

SLI@ 1 2

C16 0.22U_0402_10V6K

1 2

C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K

1 2

C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K

1 2

C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K

1 2

C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K

1 2

C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K

1 2

C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K

1 2

C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K

1 2

C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K

SLI@

SLI@ 1 2

C19 0.22U_0402_10V6K

1 2

C24 0.22U_0402_10V6KSLI@C24 0.22U_0402_10V6KSLI@

SLI@

1 2

C29 0.22U_0402_10V6K

SLI@

1 2

C17 0.22U_0402_10V6K

SLI@

SLI@ 1 2

C21 0.22U_0402_10V6K

SLI@

SLI@ 1 2

C27 0.22U_0402_10V6K

SLI@

1 2

C26 0.22U_0402_10V6K

SLI@

1 2

C31 0.22U_0402_10V6K

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 mohms

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

*

PCIE_CTX_GRX_N0 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N15

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P15

PCIE_CTX_GRX_N[0..15] <2 3,32>

PCIE_CTX_GRX_P[0..15] <23,32>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(1/7) DMI,FDI,PEG

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

5 66

0.2

5

D D

+1.05VS

12

R9

62_0402_5%

H_PROCHOT#<45,54>

H_PROCHOT#

Reserve 43 Ohm resistor closs to EC(250~750mils)

H_PECI<45>

H_THRMTRIP#<19>

4

H_SNB_IVB#<19>

T14 PADT14 PAD

56_0402_5%

R15

1 2

H_THRMTRIP#

H_CATERR#

H_PECI

H_PROCHOT#_R

C26

AN34

AL33

AN33

AL32

AN32

JCPU1B

PROC_SELECT#

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

3

A28

BCLK

A27

BCLK#

A16 A15

R8

AK1 A5 A4

CLOCKS

DDR3

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

MISC

MISCTHERMALPWR MANAGEMENT

CLK_CPU_DMI

CLK_CPU_DMI#

R12 1K_0402_5%R12 1K_0402_5% R13 1K_0402_5%R13 1K_0402_5%

H_DRAMRST#

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

2

12 12

H_DRAMRST# <7>

R16 140_0402_1%R16 140_0402_1% R17 25.5_0402_1%R 17 25.5_0402_1% R18 200_0402_1%R18 200_0402_1%

+1.05VS

12 12 12

CLK_CPU_DMI <15> CLK_CPU_DMI# <15>

DDR3 Compensation Signals

1

12 12 12

12 12

JXDP1

+1.05VS

@JXDP1

@

27 28

R1499 0_0402_5%R1499 0_0402_5%

AP29

TDI

PLT_RST#

AP27

AR26 AR27 AP30

AR28 AP26

AL35

XDP_DBRESET#

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

3V

XDP_PRDY# XDP_PREQ#

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7

PRDY#

PREQ#

C C

R26

H_CPUPWRGD<19,6>

100P_0402_50V8J

C550

1

2

R27

10K_0402_5%

1 2

R_short 0_0402_5%

H_PM_SYNC<16>

9/23 ESD Request

1 2

+3VALW

1

C33

0.1U_0402_16V4Z

2

5

1

B

2

A

3

P

G

U1

4

PM_SYS_PWRGD_BUF

O

74AHC1G09GW_TSSOP5

+1.5V_CPU_VDDQ

12

R30

R30 200_0402_5%

200_0402_5%

R338

10K_0402_5%

+3VS

SYS_PWROK<16>

B B

PM_DRAM_PWR GD<16>

0_0402_5% @

12

R65

R22

1 2

R_short 0_0402_5%

R29

1 2

PM_DRAM_PWR GD_R

130_0402_5%

H_PM_SYNC_R

H_CPUPWRGD_R

BUF_CPU_RST#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

V8

SM_DRAMPWR OK

AR33

RESET#

TYCO_2013620-2_IVY BRIDGE

ME@

1.05V

12

R35

@R35

@

0_0402_5%

+1.05VS

R32

75_0402_5%

R34

43_0402_1%

1 2

SN74LVC1G07DCKR_SC70-5

Buffered reset to CPU

0.1U_0402_16V4Z

12

BUFO_CPU_RST#

JTAG & BPM

1

C34

2

U2

4

Y

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

+3VS

This is NC pin

5

1

P

NC

2

A

G

3

TCK TMS

TDO

1 2

R1500 0_0402_5%R1500 0_0402_5%

1 2

R1501 0_0402_5%R1501 0_0402_5%1 2 R1502 0_0402_5%R1502 0_0402_5%1 2 R1503 0_0402_5%R1503 0_0402_5%

1 2

R1504 0_0402_5%R1504 0_0402_5%

1 2

R1505 0_0402_5%R1505 0_0402_5%1 2

R28 1K_0402_5%R28 1K_0402_5%

R1506 0_0402_5%R1506 0_0402_5%

1 2

R1507 0_0402_5%R1507 0_0402_5%

1 2

R1508 0_0402_5%R1508 0_0402_5%

1 2

R1509 0_0402_5%R1509 0_0402_5%1 2

PLT_RST# <18,23,32,38,39,44,45,6>

T31PAD T31PAD T30PAD T30PAD T33PAD T33PAD T32PAD T32PAD

XDP_PRDY#_R XDP_PREQ#_R

XDP_TCK_R XDP_TMS_R

XDP_TRST#_R

XDP_TDI_R XDP_TDO_R

12

XDP_BPM#0_R XDP_BPM#1_R XDP_BPM#2_R XDP_BPM#3_R

+1.05VS

PU/PD for JTAG signals

XDP_TMS

R20 51_0402_5%R20 51_0402_5%

XDP_TDI

R21 51_0402_5%R21 51_0402_5%

XDP_TDO

R23 51_0402_5%

+3VS

R23 51_0402_5%

XDP_TCK

R24 51_0402_5%R24 51_0402_5%

XDP_TRST#

R25 51_0402_5%R25 51_0402_5%

@

XDP Connector

XDP_PREQ#_R XDP_PRDY#_R

XDP_BPM#0_R XDP_BPM#1_R

XDP_BPM#2_R XDP_BPM#3_R

1K_0402_5%

12

PBTN_OUT#

VGATE

CLK_BCLK_ITP

H_CPUPWRGD_R

12

CFG0_R

1K_0402_5%

CLK_BCLK_ITP#

PLT_RST#

XDP_DBRESET#

XDP_TDO_R XDP_TRST#_R XDP_TDI_R XDP_TMS_R

XDP_TCK_R

R1510

H_CPUPWRGD<19,6>

PBTN_OUT#<16,45>

CFG0<8>

R1510

R1511

VGATE<16,60>

CLK_BCLK_ITP<15>

CLK_BCLK_ITP#<15>

PLT_RST#<18,23,32,38,39,44,45,6>

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MOLEX 52435-2671

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(2/7) PM,XDP,CLK

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

6 66

0.2

5

JCPU1C

4

3

JCPU1D

2

1

DDR_A_D[0..63]<12>

D D

C C

B B

DDR_A_BS0<12> DDR_A_BS1<12> DDR_A_BS2<12>

DDR_A_CAS#<12> DDR_A_RAS#<12> DDR_A_WE#<12>

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6

AK8

AK9 AH8 AH9 AL9 AL8

AP11

AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10

AF10

AE8 AD9 AF9

F10

AJ5 AJ6 AJ8

AJ9

C5 D5 D3 D2 D6 C6 C2 C3

F8

G9

F9

F7 G8 G7

K4

K5

K1

K2 M8

N8

N7

M9

N9 M7

V6

J1 J5 J4 J2

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0]

SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

M_CLK_DDR0 <12> M_CLK_DDR#0 <12> DDR_CKE0_DIMMA < 12>

M_CLK_DDR1 <12> M_CLK_DDR#1 <12> DDR_CKE1_DIMMA < 12>

DDR_CS0_DIMMA# <12 > DDR_CS1_DIMMA# <12 >

M_ODT0 <12> M_ODT1 <12>

DDR_A_DQS#[0..7] <12>

DDR_A_DQS[0..7] <1 2>

DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>

DDR_B_D[0..63]<13>

DDR_B_BS0<13> DDR_B_BS1<13> DDR_B_BS2<13>

DDR_B_CAS#<13> DDR_B_RAS#<13> DDR_B_WE#<13>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

AM5 AM6

AJ11

AH11

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA10

AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9

AT8 AT9

AR8

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

DDR SYSTEM MEMORY B

SB_CK[0]

SB_CLK#[0]

SB_CKE[0]

SB_CK[1]

SB_CLK#[1]

SB_CKE[1]

SB_CK[2]

SB_CLK#[2]

SB_CKE[2]

SB_CK[3]

SB_CLK#[3]

SB_CKE[3]

SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3]

SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

AE2 AD2 R9

AE1 AD1 R10

AB2 AA2 T9

AA1 AB1 T10

AD3 AE3 AD6 AE6

AE4 AD4 AD5 AE5

D7 F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

M_CLK_DDR2 <13> M_CLK_DDR#2 <13> DDR_CKE2_DIMMB < 13>

M_CLK_DDR3 <13> M_CLK_DDR#3 <13> DDR_CKE3_DIMMB < 13>

DDR_CS2_DIMMB# <13 > DDR_CS3_DIMMB# <13 >

M_ODT2 <13> M_ODT3 <13>

DDR_B_DQS#[0..7] <13>

DDR_B_DQS[0..7] <1 3>

TYCO_2013620-2_IVY BRIDGE

Deciphered Date

TYCO_2013620-2_IVY BRIDGE

ME@

2014/07/01

2

Title

PROCESSOR(3/7) DDRIII

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

7 66

0.2

TYCO_2013620-2_IVY BRIDGE

ME@

D

S

D

S

13

H_DRAMRST#<6>

R39

4.99K_0402_1%

A A

DRAMRST_CNTRL_PC H<15>

DRAMRST_CNTRL<10>

DRAMRST_CNTRL_EC<45>

No DS3 to stuff R40

@

1 2

R40 0_0402_5%

1 2

R64 0_0402_5%

DS3@

5

1 2

DRAMRST_CNTRL

DDR3_DRAMRST#_RH_DRAMRST#

Q2

G

BSS138_NL_SOT23-3

2

1

C35

0.047U_0402_16V4Z

2

Module design used 0.047u

+1.5V

R37

1K_0402_5%

12

R38

R38 1K_0402_5%

1K_0402_5%

1 2

4

DDR3_DRAMRST# <12,13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

5

4

3

2

1

CFG Straps for Processor

CFG2

12

R41

@

1K_0402_1%

D D

PEG Static Lane Reversal - CFG2 is for the 16x

*

CFG2

JCPU1E

1K_0402_1%

1: Normal Operation; Lane # definition matches socket pin map definition

0:Lane Reversed

VSS

RSVD28 RSVD29 RSVD30 RSVD31

RSVD32

RSVD33 RSVD34 RSVD35

RSVD37 RSVD38 RSVD39 RSVD40

RSVD51 RSVD52

BCLK_ITP

BCLK_ITP#

KEY

AH27 AH26

L7 AG7 AE7 AK2

W8

AT26 AM33 AJ27

T8 J16 H16 G16

AR35 AT34 AT33 AP35 AR34

B34 A33 A34 B35 C35

AJ32 AK32

AN35 AM35

AT2 AT1 AR1

B1

RESERVED

VCC_DIE_SENSE

RSVD_NCTF1 RSVD_NCTF2 RSVD_NCTF3 RSVD_NCTF4 RSVD_NCTF5

RSVD_NCTF6 RSVD_NCTF7 RSVD_NCTF8 RSVD_NCTF9

RSVD_NCTF10

RSVD_NCTF11 RSVD_NCTF12 RSVD_NCTF13

CFG0<6>

C C

11/24 Intel recommend to reserve test point

B B

A A

CFG0

CFG2

CFG5 CFG6 CFG7

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

PAD

T56

AJ31

PAD

T57

PAD

T58

PAD

T59

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

J15

RSVD27

TYCO_2013620-2_IVY BRIDGE

ME@

CFG

T13PAD T13PAD

Display Port Presence Strap

CFG4

*

1K_0402_1%

PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled

CFG[6:5]

10: x8, x8 - Device 1 function 1 enabled ; function 2

*

disabled 01: Reserved - (Device 1 function 1 disabled ; function

2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7

de assertion

0: PEG Wait for BIOS for training

1 : Disabled; No Physical Display Port attached to Embedded Display Port

0 : Enabled; An external Display Port device is connected to the Embedded Display Port

CFG6

CFG5

CFG7

12

R44

@R44

12

@R45

@

1K_0402_1%

R45 1K_0402_1%

1K_0402_1%

R43

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(4/7) RSVD,CFG

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

8 66

0.2

5

D D

C C

B B

A A

4

+VCC_CORE

QC=94A DC=53A

AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26

JCPU1F

3

POWER

+1.05VS

2

1

8.5A

VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

CORE SUPPLY

PEG AND DDR

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID

VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8

VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24

VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK VIDSOUT

AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12

E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

AJ35 AJ34

B10 A10

VCCSENSE_R VSSSENSE_R

Reserve 0.1u to avoid noise

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R47 43_0402_5%R47 43_0402_5% R48 R_short 0_0402_5%R48 R_short 0_0402_5% R49

R49

R50 130_0402_5%R50 130_0402_5%

Place the PU resistor close to CPU

VCC_SENCE 100ohm +-1% pull-up to VCC near processor

R52 R_short 0_0402_5%R52 R_short 0_0402_5%

1 2

R53 R_short 0_0402_5%R53 R_short 0_0402_5%

1 2

R1294 10_0402_1%R1294 10_0402_1%

VCCIO_SENSE VSSIO_SENSE

R1297

R1297 10_0402_1%

10_0402_1%

1 2

VSS_SENCE 100ohm +-1% pull-down to GND near processor

0.1U_0402_10V7K

1 2 1 2 1 2

12

VCCIO_SENSE <58>

1

@

C36

2

R_short 0_0402_5%

12

+1.05VS

Place the PU resistor close to CPU

12

R46

R46 75_0402_5%

75_0402_5%

VR_SVID_ALRT# <60> VR_SVID_CLK < 60> VR_SVID_DAT <60>

+1.05VS

+VCC_CORE

12

R51

R51 100_0402_1%

100_0402_1%

12

R54

100_0402_1%

VCCSENSE <60> VSSSENSE <60>

TYCO_2013620-2_IVY BRIDGE

ME@

5

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(5/7) PWR,BYPASS

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

9 66

0.2

5

AO4714 Vgs=10V,Id=20A, Rds=6.7m ohm

R1537

100K_0402_5%

@

Q156

Q156 2N7002_SOT23

2N7002_SOT23

@

2

G

1K_0402_1%

R56 check EVT

+3VALW

12

13

D

S

12

R132

R139

1K_0402_1%

@

2

G

+V_DDR_REFA_R +V_DDR_REFB_R

D D

CPU1.5V_S3_GATE<45>

R1538 R_short 0_0402_5%R1538 R_short 0_0402_5%

2

G

1 3

D

@

@ 1 2 1 2

@

1 3

D

G

2

S

1 2

SUSP<38,52,56,58>

C C

DRAMRST_CNTRL<7>

+VREF_DQ_DIMMA

+VREF_DQ_DIMMB

B B

DRAMRST_CNTRL

Q8 BSS1 38_SOT23

R74 0_0402_5%

R74 0_0402_5% R75 0_0402_5%

R75 0_0402_5%

Q7 BSS138_S OT23

6/8 Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)

+1.8VS

R67

1 2

R_short 0_0805_5%

A A

+VSB

@

+

330U_B2_2.5VM_R15M

4

12

R56

R56 100K_0402_5%

100K_0402_5%

RUN_ON_CPU1.5VS3

61

D

Q4A

S

2N7002KDWH_SOT363-6

1

C279

2

+1.5V

1

2

0_0402_5%

C130

10U_0805_6.3V6M

C130

10U_0805_6.3V6M

C287

1 2

0.1U_0402_10V6K

C286

1 2

0.1U_0402_10V6K

C96

1 2

0.1U_0402_10V6K

C95

1 2

0.1U_0402_10V6K

U3

U3 AO4304L 1N SOIC-8

AO4304L 1N SOIC-8

8 7 6 5

4

R1349

1 2

470K_0402_5%

12

R57

R57 470K_0402_5%

470K_0402_5%

+VCC_GFXCORE_AXG

12

R1514

SLI@

C131

1U_0402_6.3V6K

C131

1U_0402_6.3V6K

1

2

1 2 3

46A

+1.8VS_VCCPLL

C132

1U_0402_6.3V6K

C132

1U_0402_6.3V6K

1

2

+1.5V_CPU_VDDQ

1

C97

2

0.01U 50V K X7R 0402

JCPU1G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

B6

VCCPLL1

A6

VCCPLL2

A2

VCCPLL3

TYCO_2013620-2_IVY BRIDGE

ME@

Q4B

2N7002KDWH_SOT363-6

3

12

R1487

R1487 470_0603_5%

470_0603_5%

@

34

D

5

G

S

POWER

GRAPHICS

1.8V RAIL

SUSP

SENSE

VAXG_SENSE

VSSAXG_SENSE

LINES

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VCCSA_VID[0] VCCSA_VID[1]

VCCIO_SEL

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

AK35

VCC_AXG_SENSE_R

AK34

VSS_AXG_SENSE_R

+V_SM_VREF_CNT

AL1

B4 D1

5A

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

6A

M27 M26 L26 J26 J25 J24 H26 H25

H23

C22 C24

A19

R1488

OPT@R1488

OPT@

0_0402_5%

1 2 1 2

0_0402_5%

R1489

OPT@

0.1U_0402_16V4Z

+V_DDR_REFA_R +V_DDR_REFB_R

C117

10U_0603_6.3V6M

C117

10U_0603_6.3V6M

1

2

+VCCSA

C124

10U_0805_6.3V6M

C124

10U_0805_6.3V6M

1

2

H_VCCSA_VID0 <57> H_VCCSA_VID1 <57>

2

Place the PU/PD resistor close to CPU within 2 inch (Reserve power side)

+VCC_GFXCORE_AXG

R66

R66 100_0402_1%

100_0402_1%

OPT@

1 2

1

C114

2

C118

10U_0603_6.3V6M

C118

10U_0603_6.3V6M

1

2

C125

10U_0805_6.3V6M

C125

10U_0805_6.3V6M

1

2

R68 0_0402_5%

C119

10U_0603_6.3V6M

C119

10U_0603_6.3V6M

1

2

C126

10U_0805_6.3V6M

C126

10U_0805_6.3V6M

1

2

@

1 2

C120

10U_0603_6.3V6M

C120

10U_0603_6.3V6M

1

2

10U_0805_6.3V6M@C127

10U_0805_6.3V6M

1

2

R89 100_0402_1%

12

OPT@

+1.5V_CPU_VDDQ

12

R77

R77 1K_0402_1%

1K_0402_1%

12

R88

R88 1K_0402_1%

1K_0402_1%

+1.5V_CPU_VDDQ

C122

10U_0603_6.3V6M

C122

10U_0603_6.3V6M

C121

10U_0603_6.3V6M

C121

10U_0603_6.3V6M

1

2

+VCCSA

330U_D2_2.5VY_R9M

C128

C127

1

+

@

2

+VCCSA_SENSE <57>

330U_D2_2.5VY_R9M

C123

1

+

@

2

VCC_AXG_SENSE <60>

VSS_AXG_SENSE <60>

6/3 modify for VCCSA 4-Level voltage

1

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(6/7) PWR

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

of

10 66

0.2

5

D D

C C

B B

4

JCPU1H

AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10

AT7 AT4

AT3 AR25 AR22 AR19 AR16 AR13 AR10

AR7

AR4

AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AP7

AP4

AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AN7

AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AL7 AL4

AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AK7

AK4

AJ25

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

3

JCPU1I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

2

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

1

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

TYCO_2013620-2_IVY BRIDGE

ME@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

TYCO_2013620-2_IVY BRIDGE

ME@

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PROCESSOR(7/7) VSS

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

11 66

0.2

5

4

3

2

1

+1.5V

+VREF_DQ_DIMMA

12

R78

1K_0402_1%

+VREF_DQ_DIMMA

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C140

1

2

DDR_CKE0_DIMMA<7>

DDR_A_BS2<7>

M_CLK_DDR0<7> M_CLK_DDR#0<7>

DDR_A_BS0<7>

DDR_A_WE#<7> DDR_A_CAS#<7>

DDR_CS1_DIMMA#<7>

+3VS

D D

C C

B B

A A

1K_0402_1%

12

R79

5

DDR_A_D0

C141

DDR_A_D1

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS2

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

M_CLK_DDR0 M_CLK_DDR#0

DDR_A_MA10 DDR_A_BS0

DDR_A_WE# DDR_A_CAS# M_ODT0

DDR_A_MA13 DDR_CS1_DIMMA#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

1 2

R82

10K_0402_5%

0.1U_0402_10V6K

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K C162

C162

C290

1

2

3A@1.5V

3A@1.5V3A@1.5V

DDR3 SO-DIMM A

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2 DQS247VSS17

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

R83

10K_0402_5%

R83

10K_0402_5%

12

VTT1

205

G1

LCN_DAN06-K4806-0103

ME@

4

DQS#0

VSS10

VSS19

VSS21

VDD12

VDD14

VDD16

VDD18

VREF_CA

VSS28

VSS30

VSS31

VSS33

VSS35 DQS#5

VSS38

VSS40

VSS42

VSS43

VSS45

VSS47 DQS#7

VSS50

VSS52

EVENT#

VSS3

DQS0

VSS6

VSS8 DQ12 DQ13

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

CK1#

RAS#

ODT0

ODT1

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5

DQ46 DQ47

DQ52 DQ53

DQ54 DQ55

DQ60 DQ61

DQS7

DQ62 DQ63

VTT2

+1.5V+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR3_DRAMRST#

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDR_CKE1_DIMMA

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

M_CLK_DDR1 M_CLK_DDR#1

DDR_A_BS1 DDR_A_RAS#

DDR_CS0_DIMMA#

M_ODT1

DDR_A_D36 DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

SMB_DATA_S3 SMB_CLK_S3

+0.75VS

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA

SCL

G2

1

@

C1064

2

0.047U_0402_16V4Z

DDR3_DRAMRST# <13,7>

DDR_CKE1_DIMMA <7>

M_CLK_DDR1 <7> M_CLK_DDR#1 <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDR_CS0_DIMMA# <7> M_ODT0 <7>

M_ODT1 <7>

SMB_DATA_S3 <13,15,38,46> SMB_CLK_S3 <13,15,38,46>

1

@

2

C1066

C1065

2

0.047U_0402_16V4Z

For RF request

+1.5V

12

R80

1K_0402_1%

+VREF_CA

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C149

C150

1

2

C150

1

2

3

12

R81

1K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_DQS#[0..7]<7>

DDR_A_MA[0..15]<7>

Layout Note: Place near DIMM

10U_0603_6.3V6M

C151

C142

1

@

2

Layout Note: Place near DIMM

+0.75VS

C288

1U_0402_6.3V6K

C288

1U_0402_6.3V6K

C158

1

2

2012/07/01

+1.5V

10U_0603_6.3V6M

C143

C152

1

2

C159

1U_0402_6.3V6K

C159

1U_0402_6.3V6K

C160

1U_0402_6.3V6K

C160

1U_0402_6.3V6K

1

2

LC Future Center Secret Data

OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

10U_0603_6.3V6M

1

2

Deciphered Date

10U_0603_6.3V6M

C145

C144

1

2

C153

10U_0603_6.3V6M

1

2

2014/07/01

10U_0603_6.3V6M

0.1U_0402_10V6K

C154

C146

C154

C155

1

2

C155

1

2

Title

DDRIII-SODIMM SLOT1

Size Document Number Rev

Custom

Date: Sheet of

0.1U_0402_10V6K

0.1U_0402_10V6K C147

C147

1

2

Tuesday, June 05, 2012

0.1U_0402_10V6K

0.1U_0402_10V6K C156

C156

1

2

1

+

C148

C148 220U_6.3V_M

220U_6.3V_M

2

LA-8692P

LA-8692PLA-8692P

1

12 66

0.2

5

+1.5V

12

+VREF_DQ_DIMMB

R84

1K_0402_1%

2.2U_0603_6.3V6K

0.1U_0402_10V6K

+3VS

0.1U_0402_10V6K

C289

1

2

DDR_CKE2_DIMMB<7>

DDR_B_BS2<7>

M_CLK_DDR2<7> M_CLK_DDR#2<7>

DDR_B_BS0<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDR_CS3_DIMMB#<7>

2.2U_0603_6.3V6K

1

2

D D

C C

B B

A A

1K_0402_1%

12

R85

5

+VREF_DQ_DIMMB

DDR_B_D0 DDR_B_D1

1

C157

2

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDR_CKE2_DIMMB

DDR_B_BS2

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

M_CLK_DDR2 M_CLK_DDR#2

DDR_B_MA10 DDR_B_BS0

DDR_B_WE# DDR_B_CAS#

DDR_B_MA13 DDR_CS3_DIMMB#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

R95

10K_0402_5%

1 2

0.1U_0402_10V6K

0.1U_0402_10V6K R97 10K_0402_5%R97 10K_0402_5%

C178

C177

1

2

+1.5V

3A@1.5V

3A@1.5V3A@1.5V

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013287-1

ME@

4

VSS3

DQS#0

DQS0 VSS6

VSS8 DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

VTT2

4

3

DDR_B_D[0..63]<7>

+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR3_DRAMRST#

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3 DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDR_CKE3_DIMMB

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

M_CLK_DDR3 M_CLK_DDR#3

DDR_B_BS1 DDR_B_RAS#

DDR_CS2_DIMMB# M_ODT2

M_ODT3

DDR_B_D36 DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5 DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

SMB_DATA_S3 SMB_CLK_S3

0.65A@0.75V

0.65A@0.75V0.65A@0.75V

DQ4 DQ5

DQ6 DQ7

DM1

DM2

A15 A14

A11

A7

A6 A4

A2 A0

CK1

BA1

S0#

NC2

DM4

DM6

SDA SCL

G2

1

@

C1069

2

0.047U_0402_16V4Z

DDR3_DRAMRST# <12,7>

DDR_CKE3_DIMMB <7>

M_CLK_DDR3 <7> M_CLK_DDR#3 <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>

DDR_CS2_DIMMB# <7> M_ODT2 <7>

M_ODT3 <7>

SMB_DATA_S3 <12,15,38,46> SMB_CLK_S3 <12,15,38,46>

+0.75VS

1

@

C1068

C1067

2

0.047U_0402_16V4Z

For RF request

+1.5V

12

R86

1K_0402_1%

+VREF_CB

0.1U_0402_10V6K

2.2U_0603_6.3V6K

C280

C281

1

2

1K_0402_1%

12

R87

3

DDR_B_DQS[0..7]<7>

DDR_B_DQS#[0..7]<7>

DDR_B_MA[0..15]<7>

Layout Note: Place near DIMM

10U_0603_6.3V6M

C161

C282

C163

1

@

2

Layout Note: Place near DIMM

+0.75VS

C173

1

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C163

1

@

2

C174

1U_0402_6.3V6K

C174

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

C175

1U_0402_6.3V6K

1

2

(10uF_0603_6.3V)*8

(0.1uF_402_10V)*4

+1.5V

10U_0603_6.3V6M

C176

2012/07/01

C165

C164

1

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

LC Future Center Secret Data

10U_0603_6.3V6M

C167

C166

1

2

Deciphered Date

2

10U_0603_6.3V6M

0.1U_0402_10V6K

C168

1

2

C169

1

2

2014/07/01

0.1U_0402_10V6K C170

C170

1

2

0.1U_0402_10V6K

0.1U_0402_10V6K C172

C172

C171

1

2

Title

DDRIII-SODIMM SLOT2

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

1

13 66

0.2

5

W=20milsW=20mils

+RTCBATT+RTCVCC

R99

1K_0402_5%

1 2

1

C179

C179 1U_0603_10V6K

1U_0603_10V6K

2

D D

18P_0402_50V8J

4

1 2

R98 10M_0402_5%R98 10M_0402_5%

Y1

1 2

32.768KHZ_12.5PF_CM31532768DZFT

1

C180

2

1

C181

C181 18P_0402_50V8J

18P_0402_50V8J

2

PCH_RTCX1

PCH_RTCX2

3

2

1

+RTCVCC

1 2

R101 1M_0402 _5%R101 1M_0402_5%

1 2

R102 330K_0402_ 5%R102 330K_0402_5%

INTVRMEN

H

：：：：

Integrated VRM enable

*

L

：：：：

Integrated VRM disable

(INTVRMEN should always be pull high.)

+3VS

1 2

R105 1K_0402_5%@R105 1K_0402_ 5%@

HIGH= Enable ( No Reboot ) LOW= Disable (Default)

*

C C

+3V_PCH

R106 1K_0402_5%@R106 1K_0402_5%@

Low = Disabled (Default)

*

High = Enabled [Flash Descriptor Security Overide]

+3V_PCH

R108 1K_0402_5%R108 1K_0402_5%

12

This signal has a weak internal pull-down

On Die PLL VR Select is supplied by

1.5V when smapled high

*

1.8V when sampled low Needs to be pulled High for Chief River platfrom

HDA_BITCLK_AUDIO

HDA_SYNC_AUDIO<43>

B B

HDA_RST_AUDIO#<43>

HDA_SDOUT_AUDIO

+3V_PCH +3V _PCH +3V_PCH

12

R121

@

200_0402_5%

PCH_JTAG_TDO PC H_JTAG_TDIPCH_JTAG_TMS

12

R125

100_0402_1%

@

A A

@

12

R122

200_0402_5%

12

R126

R126 100_0402_1%

100_0402_1%

@

R112

33_0402_5%

1 2

R114

33_0402_5%

1 2

R116

33_0402_5%

1 2

R118

33_0402_5%

1 2

SM_INTRUDER#

PCH_INTVRMEN

HDA_SDOUT

HDA_SYNC

HDA_BIT_CLK

HDA_SYNC_R

HDA_RST#

HDA_SDOUT

12

@

200_0402_5%

12

100_0402_1%

@

HDA_SPKR

R123

R128

+RTCVCC

R103 20K_0402_5%R103 20K_0402_5%

R100 20K_0402_5%R100 20K_0402_5%

ME_FLASH<45>

+3V_PCH

12

1M_0402_5%

R1353

C183

1U_0603_10V6K

1 2

C182

1U_0603_10V6K

ME_FLASH

R107 1K_0402_1%@R107 1K_0402_ 1%@

R317 10K_0402_5 %

+5VS

G

2

S

CMOS

1

12

SHORT PADS

2

1

12

SHORT PADS

2

HDA_SPKR<43>

HDA_SDIN0<43>

1 2

R_short 0_0402_5%

1 2

12

@

51_0402_5%

R110

Q10

Q10 BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

13

HDA_SYNC

D

JCMOS

JME

R109

PCH_RTCX1

PCH_RTCX2

PCH_RTCRST#

PCH_SRTCRST#

SM_INTRUDER#

PCH_INTVRMEN

HDA_BIT_CLK

HDA_SYNC

HDA_SPKR

HDA_RST#

HDA_SDIN0

12

PCH_JTAG_TCK

PCH_JTAG_TMS

PCH_JTAG_TDI

PCH_JTAG_TDO

SPI_CLK_PCH

SPI_SB_CS0#

SPI_CS1#

SPI_SI

SPI_SO_R

HDA_SDOUT

PCH_GPIO33

PCH_GPIO13

U4A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989

RTCIHDA

JTAG

SPI

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA4RXN SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

SATA0GP / GPIO21

SATA1GP / GPIO19

C38

LPC_AD0

A38

LPC_AD1

B37

LPC_AD2

C37

LPC_AD3

D36

LPC_FRAME#

E36 K36

V5

SERIRQ

AM3 AM1 AP7

SATA_ITX_C_DRX_N0

AP5

SATA_ITX_C_DRX_P0

AM10 AM8 AP11

SATA_ITX_C_DRX_N1

AP10

SATA_ITX_C_DRX_P1

AD7 AD5 AH5

SATA_ITX_C_DRX_N2

AH4

SATA_ITX_C_DRX_P2

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11

Y10

AB12

AB13

AH1

RBIAS_SATA3

P3

V14

PCH_GPIO21

P1

SATA_DET#

LPC_AD0 <38,45> LPC_AD1 <38,45> LPC_AD2 <38,45> LPC_AD3 <38,45>

LPC_FRAME# <38,45>

R104 10K_0402_5%R104 10K_0402_5%

R111

37.4_0402_1%

SATA_COMP

SATA3_COMP

1 2

R113

49.9_0402_1%

1 2

R115 750 _0402_1%R115 750_0402_1%

HDD_LED#

R120

10K_0402_5%

R119

10K_0402_5%

R316 10K_0402_5 %R316 10K_0402_5%

EC and Mini card debug port

12

SERIRQ <45>

+1.05VS_VCC_SATA

+1.05VS_SATA3

HDD_LED# < 47>

12

+3VS

SATA_DET# <38>

+3VS

SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0

+3VS

12 12

SATA_ITX_DRX_N0

C1840.01U_0402_16V7K C1840.01U_0402_16V7K

SATA_ITX_DRX_P0

C1850.01U_0402_16V7K C1850.01U_0402_16V7K

SATA_DTX_C_IRX_N1 SATA_DTX_C_IRX_P1

SATA_ITX_DRX_N1

C2730.01U_0402_16V7K C2730.01U_0402_16V7K

SATA_ITX_DRX_P1

C2720.01U_0402_16V7K C2720.01U_0402_16V7K

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2

SATA_ITX_DRX_N2_CONN

C1860.01U_0402_16V7K C1860.01U_0402_16V7K

SATA_ITX_DRX_P2_CONN

C1870.01U_0402_16V7K C1870.01U_0402_16V7K

+3VS

R292

R246

R_short 0_0402_5%

1 2

SPI_CS1#

1 2

SPI_SO_R SPI_SO_L1

33_0402_5%

R130

R_short 0_0402_5%

1 2

SPI_SB_CS0# SPI_SO_R SPI_SO_L

1 2

33_0402_5%

R131

SATA_DTX_C_IRX_N0 <38>

SATA_DTX_C_IRX_P0 <38> SATA_ITX_DRX_N0 <38> SATA_ITX_DRX_P0 <38>

SATA_DTX_C_IRX_N1 <42>

SATA_DTX_C_IRX_P1 <42> SATA_ITX_DRX_N1 <42>

SATA_ITX_DRX_P1 <42>

SATA_DTX_C_IRX_N2 <42>

SATA_DTX_C_IRX_P2 <42> SATA_ITX_DRX_N2_CONN <42>

SATA_ITX_DRX_P2_CONN <42>

2MB P/N : SA00003FO10

1 2

SPI_WP#_1

3.3K_0402_5%

1 2

SPI_HOLD#_1

3.3K_0402_5%

R303

SPI_CS1#_R

R294

4MB P/N : SA00003K800

+3VS

1 2

R127

1 2

R129

SPI_SB_CS0#_R

SPI_WP#

U9

1

CS#

2

DO(IO1)

3

WP#(IO2)

4

GND

W25Q16BVSSIG_SO8

SPI_WP#

3.3K_0402_5%

SPI_HOLD#

3.3K_0402_5%

U5

1

CS#

2

DO

HOLD#

3

WP#

4

GND

W25Q32BVSSIG_SO8

HOLD#(IO3)

VCC

CLK

DI

SSD

HDD

ODD

VCC

CLK

DI(IO0)

+3VS

8 7

SPI_HOLD#

6

SPI_CLK_PCH_0

5

SPI_SI_R

+3VS

0.1U_0402_16V4Z

8 7

SPI_HOLD#_1

6

SPI_CLK_PCH_1

5

SPI_SI_R1

C191

1 2

0.1U_0402_16V4Z

1 2 1 2

C275

1 2

R298

33_0402_5%

R133

R299

33_0402_5%

1 2 1 2

33_0402_5%

R204

SPI_CLK_PCH

33_0402_5%

22P_0402_50V8J

SPI_CLK_PCH

SPI_SI

SPI_CLK_PCHSPI_WP#_1

SPI_SI

R124

@

C190

12

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (1/9) SATA,HDA,SPI, LPC, XDP

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

14 66

0.2

5

4

3

2

1

2N7002KDWH

U4B

LAN

D D

WLAN

TV

Card Reader

C C

LAN

WLAN

TV

Card Reader

B B

2nd VGA

PCIE_PRX_DTX_N1<39>

PCIE_PRX_DTX_P1<39> PCIE_PTX_C_DRX_N1<39> PCIE_PTX_C_DRX_P1<39>

PCIE_PRX_DTX_N2<38>

PCIE_PRX_DTX_P2<38> PCIE_PTX_C_DRX_N2<38> PCIE_PTX_C_DRX_P2<38>

PCIE_PRX_DTX_N3<38>

PCIE_PRX_DTX_P3<38> PCIE_PTX_C_DRX_N3<38> PCIE_PTX_C_DRX_P3<38>

PCIE_PRX_DTX_N4<44>

PCIE_PRX_DTX_P4<44> PCIE_PTX_C_DRX_N4<44> PCIE_PTX_C_DRX_P4<44>

CLK_PCIE_LAN#<39> CLK_PCIE_LAN<39>

+3V_PCH

CLK_PCIE_WLAN1#<38> CLK_PCIE_WLAN1<38>

WLAN_CLKREQ1#<38>

CLKREQ_TV#<38>

CLK_PCIE_CARD_PCH#<44> CLK_PCIE_CARD_PCH<44>

CLK_PCIE_2VGA#<32> CLK_PCIE_2VGA<32>

+3VS

CLK_PCIE_TV#<38> CLK_PCIE_TV<38>

CLKREQ_TV#

+3VS

+3V_PCH

CLK2_REQ_GPU#_R<32>

+3V_PCH

1 2

C192 0.1U_0402_10V7KC 192 0.1U_0402_10V7K

1 2

C193 0.1U_0402_10V7KC 193 0.1U_0402_10V7K

1 2

C194 0.1U_0402_10V7KC 194 0.1U_0402_10V7K

1 2

C195 0.1U_0402_10V7KC 195 0.1U_0402_10V7K

TV@

C292 0.1U_0402_10V7K

1 2 1 2

0.1U_0402_10V7K

TV@

1 2 1 2

CLK_PCIE_TV# CLK_PCIE_TV

CLK_PCIE_2VGA#

CLK_PCIE_2VGA

CLK_BCLK_ITP#<6> CLK_BCLK_ITP<6>

0.1U_0402_10V7K

12

WLAN_CLKREQ1#

12

C285

C277 0.1U_0402_10V7KC 277 0.1U_0402_10V7K C276 0.1U_0402_10V7KC 276 0.1U_0402_10V7K

R152 10K_0402_5%R152 10K_0402_5%

R158 10K_0402_5%R158 10K_0402_5%

R308 10K_0402_5%R308 10K_0402_5%

R168 10K_0402_5%R168 10K_0402_5%

R165 10K_0402_5%R165 10K_0402_5%

R147 10K_0402_5%R147 10K_0402_5%

R170 10K_0402_5%R170 10K_0402_5%

R172 10K_0402_5%R172 10K_0402_5%

R174 10K_0402_5%R174 10K_0402_5%

PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1

PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

CLK_PCIE_LAN# CLK_PCIE_LAN

CLKREQ_LAN#

CLK_PCIE_WLAN1# CLK_PCIE_WLAN1

CLK_PCIE_CARD_PCH# CLK_PCIE_CARD_PCH

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44

CLK2_REQ_GPU#_R

PCH_GPIO45

PCH_GPIO46

CLK_BCLK_ITP#

CLK_BCLK_ITP

for XDP

A A

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N

CLKIN_DOT_96P

CLKIN_SATA_N

CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

SMBCLK

SMBDATA

SML0CLK

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

E12

PCH_GPIO11

H14

PCH_SMBCLK

C9

PCH_SMBDATA

A12

DRAMRST_CNTRL_PC H

C8

SML0CLK

G12

SML0DATA

C13

PCH_HOT#

E14

SML1CLK

M16

SML1DATA

M7

T11

P10

M10

CLK_REQ_GPU#_R

AB37

CLK_PCIE_VGA#

AB38

CLK_PCIE_VGA

AV22

CLK_CPU_DMI#

AU22

CLK_CPU_DMI

AM12 AM13

BF18

CLK_BUF_CPU_DMI#

BE18

CLK_BUF_CPU_DMI

BJ30

CLKIN_DMI2#

BG30

CLKIN_DMI2

G24

CLK_BUF_DREF_96M#

E24

CLK_BUF_DREF_96M

AK7

CLK_BUF_PCIE_SATA#

AK5

CLK_BUF_PCIE_SATA

K45

CLK_BUF_ICH_14M

H45

CLK_PCI_LPBACK

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

F47

H47

S_DGPU_RST_R

K49

PCH_GPIO67

10K_0402_5%

12

R134

1 2

R335 2.2K_0402_5%R335 2.2K_0402_5%

1 2

R336 2.2K_0402_5%R336 2.2K_0402_5%

R140 10K_0402_5%R 140 10K_0402_5%

90.9_0402_1%

1 2

S_DGPU_GC6_EN

R1592 10K_0402_5%R1592 10K_0402_5%

R1593 R_short 0_0402_5%R1593 R_short 0_0402_5%

+3V_PCH

12

1 2

CLK_CPU_DMI# <6> CLK_CPU_DMI <6>

1 2

R155 10K_0402_5%R155 10K_0402_5%

1 2

R157 10K_0402_5%R157 10K_0402_5%

1 2

R159 10K_0402_5%R159 10K_0402_5%

1 2

R160 10K_0402_5%R160 10K_0402_5%

1 2

R162 10K_0402_5%R162 10K_0402_5%

1 2

R163 10K_0402_5%R163 10K_0402_5%

1 2

R164 10K_0402_5%R164 10K_0402_5%

1 2

R166 10K_0402_5%R166 10K_0402_5%

1 2

R167 10K_0402_5%R167 10K_0402_5%

CLK_PCI_LPBACK <18 >

R171

+1.05VS_VCCDIFFCLKN

1 2

PCH_GPIO67 <19>

BIOS Request SKU ID

Vth= min 1V, max 2.5V ESD 2KV

+3V_PCH

12

R329

R329 1K_0402_5%

1K_0402_5%

+3V_PCH

CLK_REQ_GPU#_R < 23>

R20210K _0402_5% R20210K_0402_5%

S_DGPU_GC6_EN <3 2>

2.2K_0402_5%

1 2

R136

1 2

R135

2.2K_0402_5%

DRAMRST_CNTRL_PC H <7>

+3V_PCH

2.2K_0402_5%

1 2

R141

1 2

R142

2.2K_0402_5%

+3V_PCH

CLK_PCIE_VGA# <23>

CLK_PCIE_VGA <23>CLKREQ_LAN#<39>

Change C196, C197 value of Cap from 10pF to 27pF

XTAL25_IN

XTAL25_OUT

27P_0402_50V8J

+3VS

S_DGPU_RST <18,32>

Q60A

Q60A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

6 1

D

G

2

5

G

3 4

D

2N7002KDWH_SOT363-6

Q61A

Q61A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

6 1

D

G

2

5

G

3 4

D

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6 Q61B

Q61B

R169 1M_0402_5%R169 1M_0402_5%

4

1

C196

25MHZ_12PF_X3G025000DC1H~D

2

CLK_BUF_ICH_14M

CLK_PCI_LPBACK

S

SMB_CLK_S3

2.2K_0402_5%

1 2

+3VS

1 2

2.2K_0402_5%

SMB_DATA_S3

S

Q60B

S

EC_SMB_CK2

+3VS

R137

R138

DIMM1 DIMM2 MINI CARD

VGA EC

SMB_CLK_S3 <12,13,38,46>

SMB_DATA_S3 <12,13,38,46>

EC_SMB_CK2 <23,32,41,45>

thermal sensor

EC_SMB_DA2

S

1 2

Y2

NC

OSC

NC

Reserve for EMI please close to PCH

EC_SMB_DA2 <23,32,41,45>

3

2

1

C197

C197 27P_0402_50V8J

27P_0402_50V8J

2

R175

@R175

@

33_0402_5%

12

R176

@R176

@

33_0402_5%

12

22P_0402_50V8J

C198

@C198

@

1 2

C199

@C199

@

1 2

Reserve for EMI please close to PCH

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (2/9) PCIE, SMBUS, CLK

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

15 66

0.2

5

D D

+3VS

1

C1060

0.1U_0402_16V4Z

VGATE

PCH_PWROK

C C

VGATE

2

5

MC74VHC1G08DFT2G SC70 5P

2

P

B

Y

1

A

G

3

U6

4

12

R180

R180 100K_0402_1%

100K_0402_1%

@

SYS_PWROK <6>

For Deep S3

1 2

PCH_PWROK<45>

+3V_PCH

B B

R192 200_0402_5%R192 200_0402_5%

R194 10K_0402_5%R194 10K_0402_5%

R197 10K_0402_5%R197 10K_0402_5%

12

PM_DRAM_PWR GD

SUSWARN#

PCH_RSMRST#_R

R190 0_0402_5%R 190 0_0402_5%

PM_DRAM_PWR GD<6>

For Deep S3

AC_PRESENT<45>

4

U4C

PWROK

APWROK

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPW RDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989

DS3@

12

1 2

DS3@

1 2

8.2K_0402_5%

10K_0402_5%

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3

DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3

DMI_IRCOMP

RBIAS_CPY

12

SUSACK#_R

12

SYS_RST#

SYS_PWROK

PM_DRAM_PWR GD

PCH_RSMRST#_R

12

SUSWARN#_R

PBTN_OUT#_R

AC_PRESENT_R

PCH_GPIO72

R200

R201

12

RI#

DMI_CTX_PRX_N0<5> DMI_CTX_PRX_N1<5> DMI_CTX_PRX_N2<5> DMI_CTX_PRX_N3<5>

DMI_CTX_PRX_P0<5> DMI_CTX_PRX_P1<5> DMI_CTX_PRX_P2<5> DMI_CTX_PRX_P3<5>

DMI_CRX_PTX_N0<5> DMI_CRX_PTX_N1<5> DMI_CRX_PTX_N2<5> DMI_CRX_PTX_N3<5>

DMI_CRX_PTX_P0<5> DMI_CRX_PTX_P1<5> DMI_CRX_PTX_P2<5> DMI_CRX_PTX_P3<5>

+1.05VS

SUSACK#<45 > DPWROK_EC <45>

SUSWARN#<45>

PBTN_OUT#<45,6>

+3V_PCH

1 2

R177 49.9_0402_1%R177 49.9_0402_1%

1 2

R178 750_0402_1%R178 750_0402_1%

4mil width and place within 500mil of the PCH

R1457 0_0402_5%

+3VS

R184 10K_0402_5 %R184 10K_0402_5%

R191 0_0402_5%R191 0_0402_5%

R193 0_0402_5%R 193 0_0402_5%

R1455 0_0402_5%

R198 0_0402_5%R198 0_0402_5%

1 2

R208

0_0402_5%

3

DMI

System Power Management

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

BJ14

FDI_CTX_PRX_N0

AY14

FDI_CTX_PRX_N1

BE14

FDI_CTX_PRX_N2

BH13

FDI_CTX_PRX_N3

BC12

FDI_CTX_PRX_N4

BJ12

FDI_CTX_PRX_N5

BG10

FDI_CTX_PRX_N6

BG9

FDI_CTX_PRX_N7

BG14

FDI_CTX_PRX_P0

BB14

FDI_CTX_PRX_P1

BF14

FDI_CTX_PRX_P2

BG13

FDI_CTX_PRX_P3

BE12

FDI_CTX_PRX_P4

BG12

FDI_CTX_PRX_P5

BJ10

FDI_CTX_PRX_P6

BH9

FDI_CTX_PRX_P7

AW16

AV12

BC10

AV14

BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

FDI_INT

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWODVREN

PCH_DPWROK_R

WAKE#

PM_CLKRUN#

SUS_STAT#

SUSCLK

PM_SLP_S5#

PM_SLP_S4#

PM_SLP_S3#

PM_SLP_SUS#_R

H_PM_SYNC

PCH_GPIO29

1 2

R185

R185 0_0402_5%

0_0402_5%

1 2 1 2

10K_0402_5%

R186

R1447 0_0402 _5%

12

DS3@

For Deep S3

0_0402_5%

R181

1 2

R253 10K_0402_5%R253 10K_0402_5%

10/06 Test point request

2

FDI_CTX_PRX_N0 <5> FDI_CTX_PRX_N1 <5> FDI_CTX_PRX_N2 <5> FDI_CTX_PRX_N3 <5> FDI_CTX_PRX_N4 <5> FDI_CTX_PRX_N5 <5> FDI_CTX_PRX_N6 <5> FDI_CTX_PRX_N7 <5>

FDI_CTX_PRX_P0 <5> FDI_CTX_PRX_P1 <5> FDI_CTX_PRX_P2 <5> FDI_CTX_PRX_P3 <5> FDI_CTX_PRX_P4 <5> FDI_CTX_PRX_P5 <5> FDI_CTX_PRX_P6 <5> FDI_CTX_PRX_P7 <5>

FDI_INT <5>

FDI_FSYNC0 <5>

FDI_FSYNC1 <5>

FDI_LSYNC0 <5>

FDI_LSYNC1 <5>

DPWROK_EC

PCIE_WAKE# <19,38,39>

+3V_PCH

T76PAD T 76PAD

T77PAD T 77PAD

T78PAD T 78PAD

PM_SLP_S4# <45>EC_RSMRST#<45>

PM_SLP_S3# <45>

PM_SLP_SUS# <45,52>

H_PM_SYNC <6>

T74PAD T 74PAD

Can be left NC when IAMT is no t support on the platfrom

For Deep S3

Can be left NC if no use integrated LAN.

+RTCVCC

12

R179

R179 330K_0402_5%

330K_0402_5%

R183

R183 330K_0402_5%

330K_0402_5%

@

1

DSWODVREN - On Die DSW VR Ena ble

*

H：Enable L：Disable

+3VALW

R195 200K_0402_5 %R195 200K_0402_5 %

+3VS

A A

R1290 200_0402_5%

12

@

12

AC_PRESENT_R

PM_DRAM_PWR GD

7/28 Modify follow Module Design.

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (3/9) DMI,FDI,PM,

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

16 66

0.2

5

D D

+3VS

R836

2.2K_0402_5%

OPT@

C C

B B

R848

2.2K_0402_5%

OPT@

+3VS

R835

2.2K_0402_5%

OPT@

EDID_DATA

EDID_CLK

DAC_BLU<36>

DAC_GRN<36>

DAC_RED<36>

12

R849

2.2K_0402_5%

OPT@

CRT_DDC_DATA

CRT_DDC_CLK

R266 150 _0402_1%

R264 150 _0402_1%

R262 150 _0402_1%

OPT@

12

4

R205 2.2K_0402_5%OPT@R205 2.2K_0402_5%OPT@

+3VS

R261 2.2K_0402_5%

Remove netname LVD_REF

DAC_BLU

DAC_GRN

DAC_RED

PCH_ENBKL<34> PCH_ENVDD<34>

1 2 1 2

OPT@

EDID_CLK<34> EDID_DATA<34>

R257

PCH_PWM<34>

LVDS_ACLK#<34> LVDS_ACLK<34>

LVDS_A0#<34> LVDS_A1#<34> LVDS_A2#<34>

LVDS_A0<34> LVDS_A1<34> LVDS_A2<34>

LVDS_BCLK#<34> LVDS_BCLK<34>

LVDS_B0#<34> LVDS_B1#<34> LVDS_B2#<34>

LVDS_B0<34> LVDS_B1<34> LVDS_B2<34>

CRT_DDC_CLK<36> CRT_DDC_DATA<36>

CRT_HSYNC<36> CRT_VSYNC<36>

2.37K_0402_1%

12

OPT@

R211

1K_0402_1%

PCH_ENBKL PCH_ENVDD

EDID_CLK EDID_DATA

CRT_DDC_CLK CRT_DDC_DATA

12

CTRL_CLK CTRL_DATA

LVDS_IBG

CRT_IREF

3

U4D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989

2

SDVO_INTN SDVO_INTP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

2.2K_0402_5%

OPT@

P38

HDMICLK

M39

HDMIDAT

AT49 AT47 AT40

AV42

TMDS_B_DATA2#_PCH

AV40

TMDS_B_DATA2_PCH

AV45

TMDS_B_DATA1#_PCH

AV46

TMDS_B_DATA1_PCH

AU48

TMDS_B_DATA0#_PCH

AU47

TMDS_B_DATA0_PCH

AV47

TMDS_B_CLK#_PCH

AV49

TMDS_B_CLK_PCH

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

R267

+3VS

12

R203

2.2K_0402_5%

OPT@

HDMICLK <37> HDMIDAT <37>

TMDS_B_HPD <37>

TMDS_B_DATA2#_PCH <37> TMDS_B_DATA2_PCH <37> TMDS_B_DATA1#_PCH <37> TMDS_B_DATA1_PCH <37> TMDS_B_DATA0#_PCH <37> TMDS_B_DATA0_PCH <37> TMDS_B_CLK#_PCH <37> TMDS_B_CLK_PCH <37>

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN SDVO_STALLP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN DDPC_AUXP

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN

CRT

DDPD_AUXP

1

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (4/9) LVDS,CRT,DP,HDMI

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

17 66

0.2

5

+3VS

D D

PCH_WL_OFF#

A16 swap overide Strap/Top-Block Swap Override jumper

C C

PCI_GNT3#

GPIO53=This Signal has a weak internal pull-up. NOTE: The internal pull-up is disabled after PLTRST# deasserts.

B B

PCH_GPIO51

RP2

18

PCI_PIRQA#

27

PCI_PIRQD#

36

PCI_PIRQC#

45

8.2K_0804_8P4R_5%

1 2

R305 8.2K_0402_5%

1 2

R297 8.2K_0402_5%

1 2

R213 8.2K_0402_5%

1 2

R225 8.2K_0402_5%R225 8.2K_0402_5%

1 2

R212 8.2K_0402_5%R212 8.2K_0402_5%

1 2

R252 8.2K_0402_5%R252 8.2K_0402_5%

1 2

R306 8.2K_0402_5%

1 2

R214 8.2K_0402_5%

R215 1K_0402_5%@R215 1K_0402_ 5%@

R221 1K_0402_5%@R221 1K_0402_ 5%@

PCI_PIRQB#

RP1

18

PCH_GPIO2

27

DGPU_PWR_EN

36

PCH_GPIO4

45

ODD_DA#_R

@

OPT@

@

1 2

Low=A16 swap override/Top-Block Swap Override enabled High=Default

1 2

PPT EDS DOC#474146

PCH_GPIO51

DGPU_GC6_EN

HDMI_HPD

PCH_WL_OFF#

NVDD_PWR_EN

DGPU_HOLD_RST#

DGPU_GC6_EN

DGPU_HOLD_RST#

*

DGPU_HOLD_RST#<23>

S_DGPU_RST<15,32>

NVDD_PWR_EN<59>

DGPU_GC6_EN<27> PCH_WL_OFF#<38>

CLK_PCI_LPBACK<15>

CLK_PCI_EC<45>

CLK_PCI_DB<38>

USB30

PORT1

PORT2

PORT3

PORT4

R1591 0_0402_5%@R1591 0 _0402_5%@

Camera USB

LEFT USB

1 2

Boot BIOS Strap bit1 BBS1

Boot BIOS

Bit10

0

1

0

Destination

Reserved

SPI

*

LPC

(Default)

GNT1#/ GPIO51

Bit11

0 1

1

0

ODD_DA#_R<42>

PLT_RST#<23,32,38,39,44,45,6>

USB30_RX_N1<50>

USB30_RX_N3<48> USB30_RX_N4<48> USB30_RX_P1<50>

USB30_RX_P3<48> USB30_RX_P4<48> USB30_TX_N1<50>

USB30_TX_N3<48> USB30_TX_N4<48> USB30_TX_P1<50>

USB30_TX_P3<48> USB30_TX_P4<48>

HDMI_HPD<37>

1 2 1 2

4

@

R21922_0402_5% R21922_0402_5% R22022_0402_5% R22022_0402_5%

12

R17322_0402_5%

12

R223

R223 100K_0402_5%

100K_0402_5%

USB30_RX_N1

USB30_RX_N3 USB30_RX_N4 USB30_RX_P1

USB30_RX_P3 USB30_RX_P4 USB30_TX_N1

USB30_TX_N3 USB30_TX_N4 USB30_TX_P1

USB30_TX_P3 USB30_TX_P4

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_HOLD_RST#

NVDD_PWR_EN

DGPU_PWR_EN

DGPU_GC6_EN PCH_WL_OFF#

PCH_GPIO2 ODD_DA#_R PCH_GPIO4 HDMI_HPD

PLT_RST#

CLK_PCI_LPBACK_R CLK_PCI_EC_R CLK_PCI_DB_R

PLT_RST#

U4E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989

3

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

RSVD

PCI

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RSVD23 RSVD24

RSVD25

RSVD26 RSVD27

RSVD28 RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

AV5 AV10

AT8

AY5 BA2

AT12 BF3

C24

USB20_N0

A24

USB20_P0

C25 B25 C26

USB20_N2

A26

USB20_P2

K28

USB20_N3

H28

USB20_P3

E28 D28 C28 A28 C29 B29 N28

Some PCH config not support USB port 6 & 7.

M28 L30 K30 G30

USB20_N9

E30

USB20_P9

C30

USB20_N10

A30

USB20_P10

L32 K32 G32

USB20_N12

E32

USB20_P12

C32

USB20_N13

A32

USB20_P13

C33

USBRBIAS

B33

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

USB_OC3#

L16

USB_OC4#

A16

USB_OC5#

D14

USB_OC6#

C14

USB_OC7#

USB DEBUG=PORT1 AND PORT9

USB20_N0 <50> USB20_P0 <50>

USB20_N2 <48> USB20_P2 <48> USB20_N3 <48> USB20_P3 <48>

USB20_N9 <49> USB20_P9 <49> USB20_N10 <38> USB20_P10 <38>DGPU_PWR_EN<23,52>

USB20_N12 <38> USB20_P12 <38> USB20_N13 <47> USB20_P13 <47>

Within 500 mils

1 2

R218 22.6_0402_1%R218 22.6_0402 _1%

USB_OC1# <48>

USB_OC4# <49>

2

Camera

LEFT USB

RIGHT USB 1 (SUB/B)

WLAN

TV

BT

USB_OC5# USB_OC2#PCH_GPIO51 USB_OC7# USB_OC0#

USB_OC6# USB_OC1# USB_OC4# USB_OC3#

1

RP3

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

RP4

4 5 3 6 2 7 1 8

10K_1206_8P4R_5%

+3V_PCH

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (5/9) PCI, USB

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

18 66

0.2

5

D D

+3VS

10K_0402_5%

+3V_PCH

R235 10K_0402_5%R235 10K_0402_5%

GPIO28

On-Die PLL Voltage Regulator This signal has a weak internal pull up

H：On-Die voltage regulator enab le

*

L：On-Die PLL Volt age Regulator disable

C C

PCH_GPIO27 (Have internal Pull-High)

*

High: VCCVRM VR Enable Low: VCCVRM VR Disable

+3VALW

+3VS

B B

+3V_PCH

1 2

R240 1K_0402_5%@R240 1K_0402_ 5%@

AOAC@

R207 10K_0402_5%

1 2

R245 10K_0402_5%@R245 10K_0402_5%@

200K_0402_5%

1 2

R251 10K_0402_5%R251 10K_0402_5%

1 2

R259 10K_0402_5%R259 10K_0402_5%

12

1 2

12

R250

R1493

EC_SCI#

EC_SMI#

PCH_GPIO28

DS3_WAKE#_R

ODD_DETECT#

SLAVE_PRESENT#

PCH_GPIO37

+3VS

+3V_PCH

EC_LID_OUT#<45>

S_Toggle_REQ#<32>

PCH_BT_DISABLE#<38>

PCH_BT_ON#<38,47>

+3VS

DGPU_PWROK<27,56,59>

+3VS

PCIE_WAKE#<16,38,39>

+3VS

4

GC6_EVENT#<23>

R233 10K_0402_5%R233 10K_0402_5%

R227 10K_0402_5%R227 10K_0402_5%

R228 10K_0402_5%R228 10K_0402_5%

R229 10K_0402_5%@R229 10K_0402_5%@

R230 10K_0402_5%R230 10K_0402_5%

R231 10K_0402_5%R231 10K_0402_5% R232 10K_0402_1%

R232 10K_0402_1%

R238 10K_0402_5%R238 10K_0402_5%

@

R241 10K _0402_5%R241 10K_0402_5%

+3V_PCH

+3VS

R243

R247 10K_0402_5%R247 10K_0402_5%

R248 10K_0402_5%R248 10K_0402_5%

R249 10K_0402_5%R249 10K_0402_5%

SLAVE_PRESENT#<32>

1 2

1 2 1 2

@

1 2

R242

1 2

ODD_DETECT#<42>

1 2

EC_SCI#<45>

EC_SMI#<45>

ODD_EN<42>

12

R2240_0402_5%

10K_0402_5%

GC6_EVENT#

SLAVE_PRESENT#

PCH_GPIO1

PCH_GPIO6

EC_SCI#

EC_SMI#

PCH_GPIO12

EC_LID_OUT#

DGPU_PWROK

PCH_BT_DISABLE#

ODD_EN

DS3_WAKE#_R

PCH_GPIO28

PCH_BT_ON#

PCH_GPIO35

ODD_DETECT#

PCH_GPIO37

PCH_GPIO38

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

3

Optimus

Reserve

DIS (SLI)

Reserve

14"

15"

U4F

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989

PCH_GPIO38Function

0 0

0 1

1 0

1 1

X X

GPIO

NCTF

PCH_GPIO67

TACH4 / GPIO68

TACH5 / GPIO69

TACH6 / GPIO70

TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

NC_1

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

PCH_GPIO70

C40

B41

S_DGPU_PWR_EN

C41

PCH_GPIO70

A40

S_NVDD_PWR_EN

P4

AU16

P5

KBRST#

AY11

AY10

PCH_THRMTRIP#_R

T14

AY1

NV_CLE

AH8

AK11

AH10

AK10

P37

BG2

BG48

BH3

BH47

BJ4

BJ44

BJ45

BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

F1

F49

X

0

1

S_DGPU_PWROK

2

S_DGPU_PWROK <32>

S_DGPU_PWR_EN <32,52>

9/18 Reseve for SKU ID

S_NVDD_PWR_EN <32>

R236 10K _0402_5%R236 10K_0402_5%

KBRST# <45>

1 2

R239 390_0402_5%R239 390_0402_5%

H_CPUPWRGD <6>

H_THRMTRIP#

INIT3_3V

This signal has weak internal PU, can't pull low

Intel schematic reviwe recommand.

SKU ID

PCH_GPIO67<15>

S_DGPU_PWR_EN

S_NVDD_PWR_EN

12

NV_CLE

1

R711

SLI@

PCH_GPIO38

PCH_GPIO67

PCH_GPIO70

R712

OPT@

1 2

R1589 10K_0402_5%R1589 10K_0402_5%

1 2

R1590 10K_0402_5%R1590 10K_0402_5%

+3VS

GATEA20 <45>

H_THRMTRIP# <6>

PCH_THRMTRIP#_R <2 3,32>

R255

S_DGPU_PWROK

KBRST#

PCH_THRMTRIP#_R

PROC_SEL

H : Sandy Bridge

L : Ivy Bridge

1 2

R217 1K_0402_5%R217 1K _0402_5%

1 2

R226

1 2

R244 10K_0402_5%R244 10K_0402_5%

CLOSE TO THE BRANCHING POINT

R708

1 2

R709

1 2

+1.8VS

+3VS

R704

@

1 2

10K_0402_5%

R706

1 2

10K_0402_5%

R216

2.2K_0402_5%

H_SNB_IVB# <6>

+3VS

1 2

10K_0402_5%

@

1 2

10K_0402_5%

+3VS

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (6/9) GPIO, CPU, MISC

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

19 66

0.2

5

+1.05VS

J17

@J17

@

2

112

JUMP_43X118

D D

+1.05VS

R254 0_0603_5%R254 0_0603_5%

This pin can be left as no connect in On-Die VR enabled mode (default).

C C

B B

+1.05VS

+3VS

C221

10U_0603_6.3V6M

C221

10U_0603_6.3V6M

1

2

1 2

R260

0_0603_5%

10U_0603_6.3V6M

1

2

1

2

+1.05VS

C209

12

C222

1U_0402_6.3V6K

C222

1U_0402_6.3V6K

+1.05VS_PCH

C210

1U_0402_6.3V6K

C210

1U_0402_6.3V6K

1

2

T47PAD @T47PAD @

C223

1U_0402_6.3V6K

C223

1U_0402_6.3V6K

1

2

1

C227

0.1U_0402_10V7K

2

T48PAD @T48PAD @

1 2

0_0603_5%

C211

1U_0402_6.3V6K

C211

1U_0402_6.3V6K

1

2

+1.05VS_VCCDPLLEXP

+VCCAPLLEXP

C224

1U_0402_6.3V6K

C224

1U_0402_6.3V6K

1

2

+3VS_VCCA3GBG

+1.05VS_VCCAPLL_FDI

+1.05VS_VCCDPLL_FDI

R263

+VCCP_VCCDMI

C212

1U_0402_6.3V6K

C212

1U_0402_6.3V6K

1

2

C225

1U_0402_6.3V6K

C225

1U_0402_6.3V6K

1

2

+VCCAFDI_VRM

4

U4G

1700mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989

3711mA

POWER

VCC CORE

VCCIO

190mA

FDI

CRTLVDS

40mA

DMI

70mA

DFT / SPI HVCMOS

63mA

1mA

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[2]

VCCDFTERM[3]

VCCDFTERM[4]

10mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCSPI

U48

+VCCADAC

U47

AK36

+VCCA_LVDS

AK37

AM37

AM38

AP36

AP37

V33

+3VS_VCC3_3_6

V34

AT16

+VCCAFDI_VRM

AT20

+VCCP_VCCDMI

AB36

+1.05VS_VCC_DMI_CCI

AG16

AG17

AJ16

AJ17

V1

+3V_VCCPSPI

3

1

C213

0.01U_0402_16V7K

2

+VCCTX_LVDS

1

C216

0.01U_0402_16V7K

2

1

C219

0.1U_0402_10V7K

2

C226

1U_0402_6.3V6K

1

C228

0.1U_0402_10V7K

2

1

C230

C230 1U_0402_6.3V6K

1U_0402_6.3V6K

2

R256

0_0603_5%

1

2

1

C214

0.1U_0402_10V7K

2

1

C217

0.01U_0402_16V7K

2

+3VS

12

+VCCP_VCCDMI

R293

0_0603_5%

R399

0_0603_5%

L1 change to 1 ohm P/N S RES 1/10W 1 +-1% 0603

L1

10U_0603_6.3V6M

C215

1

2

R295

12

0_0603_5%

0.1UH_MLF1608DR10KT_10%_1608

0.1uH inductor, 200mA

1

C218

C218 22U_0805_6.3V6M

22U_0805_6.3V6M

2

+1.05VS

12

R300

0_0603_5%

+1.8VS+VCC PNAND

12

+3VS

12

1_0603_1%

12

+3VS

L2

+3VS

12

2

+1.8VS

1

C220

C220 1U_0402_6.3V6K

1U_0402_6.3V6K

2

R258

0_0603_5%

12

+1.05VS

1

PCH Power Rail Table Refer to CPU EDS R1.5

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

3.3

1.05

S0 Iccmax Current (A)

0.001

5

0.001

0.228

0.063

0.08

1.7

0.047

1.05VccIO 3.711

1.05VccASW 0.903

3.3VccSPI 0.01

3.3VccDSW 0.001

1.8 0.0 02VccDFTERM

3.3VccRTC 6 uA

3.3VccSus 3_3

3.3 / 1.5VccSusHDA

0.095

0.01

VccVRM 1.8 / 1.5 0.167

1.05VccCLKDMI

0.07

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_ LVDS 0.04

+1.5VS

R265 0_0603_5%R265 0_0603_5%

Intel recommand stuff R265 and unstuff R266

12

+VCCAFDI_VRM

VCCVRM==>1.5V FOR MOBILE VCCVRM==>1.8V FOR DESKTOP

VCCVRM = 160mA detal waiting for newest spec

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (7/9) PWR

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

20 66

0.2

5

+3VS

4

Have internal VRM

3

2

1

VCC3_3 = 266mA detal waiting for newest spec

VCCDMI = 42mA detal waiting for newest spec

R280

0_0603_5%

12

D D

On-Die PLL Voltage Regulator

H：On-Die PLL volt age regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

+1.05VS

C C

L5

1 2

BLM18PG181SN1D_0603

L6

1 2

BLM18PG181SN1D_0603

C250

22U_0805_6.3V6M

C250

22U_0805_6.3V6M

1

2

+3VS_VCC_CLKF33

C231

10U_0805_10V4Z

C231

10U_0805_10V4Z

1

2

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

C251

1U_0402_6.3V6K

C251

1U_0402_6.3V6K

1

2

1

2

+1.05VS

1

2

C232

1U_0402_6.3V6K

C232

1U_0402_6.3V6K

+1.05VS

C252

22U_0805_6.3V6M

C252

22U_0805_6.3V6M

Before gerber out change to 22u_0805

B B

+1.05VS

A A

R274

R274 0_0603_5%

0_0603_5%

R304

R304 0_0603_5%

0_0603_5%

R284

R284 0_0603_5%

0_0603_5%

12

1

C256

C256 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C259

C259 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1

C262

C262 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

1

2

C253

1U_0402_6.3V6K

C253

1U_0402_6.3V6K

+3VALW

1 2

R277

0_0805_5%

0.1U_0402_10V7K

+1.05VS

R286

R286 0_0603_5%

0_0603_5%

R269

0_0603_5%

R271

R271 0_0603_5%

0_0603_5%

1

2

C258

C263

12

1

2

12

C244

1U_0402_6.3V6K

C244

1U_0402_6.3V6K

1

2

1

2

C265

4.7U_0603_6.3V6K

C265

4.7U_0603_6.3V6K

12

1

C234

0.1U_0402_10V7K

2

1

C239

@C239

@

1U_0402_6.3V6K

2

+1.05VM_VCCASW

C241

22U_0805_6.3V6M

C241

22U_0805_6.3V6M

1

2

C245

1U_0402_6.3V6K

C245

1U_0402_6.3V6K

1

2

+VCCRTCEXT

+VCCAFDI_VRM

+1.05VS_VCCA_A_DPL

+1.05VS_VCCA_B_DPL

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+1.05VS_SSCVCC

+VCCSST

C266

0.1U_0402_10V7K

C266

0.1U_0402_10V7K

0.1U_0402_10V7K@C267

0.1U_0402_10V7K

1

2

+VCCPDSW

+3VS_VCC_CLKF33

+VCCDPLL_CPY

+VCCSUS1

C242

22U_0805_6.3V6M

C242

22U_0805_6.3V6M

1

2

C246

1U_0402_6.3V6K

C246

1U_0402_6.3V6K

1

2

+V_CPU_IO

C267

+RTCVCC

@

C268

1U_0402_6.3V6K

C268

1U_0402_6.3V6K

1

2

POWER

903mA

55mA

95mA

1mA

POWER

1mA

Clock and Miscellaneous

80mA

CPURTC

228mA

PCI/GPIO/LPCMISC

SATA USB

HDA

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

1mA

VCCSUS3_3[1]

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCCAPLLSATA

10mA

VCCSUSHDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

V5REF

1mA

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

N26

P26

P28

T27

T29

T23

T24

V23

V24

P24

T26

M26

AN23

AN24

P34

N20

N22

P20

P22

AA16

W16

T34

AJ2

AF13

AH13

AH14

AF14

AK1

AF11

AC16

AC17

AD17

+1.05VS

T21

V21

T19

P32

+1.05VS_VCCUSBCORE

1

2

1

2

+1.05VS_VCCAUPLL

+PCH_V5REF_SUS

+VCCA_USBSUS

+3V_VCCPSUS

+PCH_V5REF_RUN

+3V_VCCPSUS

+3VS_VCCPCORE

+3VS_VCCPPCI

+VCC3_3_2

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCSUSHDA

1

C271

0.1U_0402_16V4Z

2

C233

C233 1U_0402_6.3V6K

1U_0402_6.3V6K

+3V_VCCPUSB

C236

0.1U_0402_10V7K

C236

0.1U_0402_10V7K

+3V_VCCAUBG

1

C255

2

0.1U_0402_10V7K

+1.05VS_VCC_SATA

0_0603_5%

1

C238

0.1U_0402_10V7K

2

C243 1U_0402_6.3V6K@C243 1U_0402_6.3V6K@

R283

R283 0_0603_5%

0_0603_5%

+1.05VS_SATA3

R287

R287 0_0603_5%

0_0603_5%

U4J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

C269

0.1U_0402_10V7K

C269

0.1U_0402_10V7K

C270

0.1U_0402_10V7K@C270

0.1U_0402_10V7K

1

PANTHER-POINT_FCBGA989

@

2

R270

R272

R272 0_0603_5%

0_0603_5%

1 2

12

+3VS

1

2

+1.05VS

12

+3V_PCH

12

R273

R273 0_0603_5%

0_0603_5%

12

R276

R276 0_0603_5%

0_0603_5%

+1.05VS_SATA3

R288

R288 0_0603_5%

0_0603_5%

C261

C261 1U_0402_6.3V6K

1U_0402_6.3V6K

12

+3V_PCH

+1.05VS

1

C247

C247 1U_0402_6.3V

1U_0402_6.3V

2

1

C249

0.1U_0402_10V7K

2

1

C254

0.1U_0402_10V7K

2

1

C257

C257 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS

12

+3V_PCH

12

R278

R278 0_0603_5%

0_0603_5%

+3VS

12

R281

R281 0_0603_5%

0_0603_5%

+3VS

12

R282

R282 0_0603_5%

0_0603_5%

+1.05VS

12

R285

R285 0_0603_5%

0_0603_5%

On-Die PLL Voltage Regulator

H：On-Die PLL volt age regulator enable

VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2 ,VCCAPLLSATA

R275

10_0402_5%

R279

10_0402_5%

+5V_PCH

+5VS

12

+3V_PCH

21

D1

D1 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_SUS

1

C240

0.1U_0603_25V7K

2

+3VS

21

D2

D2 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_RUN

1

C248

C248 1U_0603_10V6K

1U_0603_10V6K

2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (8/9) PWR

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

21 66

0.2

5

D D

C C

B B

A A

U4H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER-POINT_FCBGA989

4

AK38

VSS[80]

AK4

VSS[81]

AK42

VSS[82]

AK46

VSS[83]

AK8

VSS[84]

AL16

VSS[85]

AL17

VSS[86]

AL19

VSS[87]

AL2

VSS[88]

AL21

VSS[89]

AL23

VSS[90]

AL26

VSS[91]

AL27

VSS[92]

AL31

VSS[93]

AL33

VSS[94]

AL34

VSS[95]

AL48

VSS[96]

AM11

VSS[97]

AM14

VSS[98]

AM36

VSS[99]

AM39

VSS[100]

AM43

VSS[101]

AM45

VSS[102]

AM46

VSS[103]

AM7

VSS[104]

AN2

VSS[105]

AN29

VSS[106]

AN3

VSS[107]

AN31

VSS[108]

AP12

VSS[109]

AP19

VSS[110]

AP28

VSS[111]

AP30

VSS[112]

AP32

VSS[113]

AP38

VSS[114]

AP4

VSS[115]

AP42

VSS[116]

AP46

VSS[117]

AP8

VSS[118]

AR2

VSS[119]

AR48

VSS[120]

AT11

VSS[121]

AT13

VSS[122]

AT18

VSS[123]

AT22

VSS[124]

AT26

VSS[125]

AT28

VSS[126]

AT30

VSS[127]

AT32

VSS[128]

AT34

VSS[129]

AT39

VSS[130]

AT42

VSS[131]

AT46

VSS[132]

AT7

VSS[133]

AU24

VSS[134]

AU30

VSS[135]

AV16

VSS[136]

AV20

VSS[137]

AV24

VSS[138]

AV30

VSS[139]

AV38

VSS[140]

AV4

VSS[141]

AV43

VSS[142]

AV8

VSS[143]

AW14

VSS[144]

AW18

VSS[145]

AW2

VSS[146]

AW22

VSS[147]

AW26

VSS[148]

AW28

VSS[149]

AW32

VSS[150]

AW34

VSS[151]

AW36

VSS[152]

AW40

VSS[153]

AW48

VSS[154]

AV11

VSS[155]

AY12

VSS[156]

AY22

VSS[157]

AY28

VSS[158]

3

U4I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER-POINT_FCBGA989

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

2

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

1

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

PCH (9/9) VSS

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

22 66

0.2

5

PCIE_CTX_GRX_N[0..15]<32,5>

PCIE_CTX_GRX_P[0..15]<32,5>

PCIE_CRX_GTX_N[0..15]<32,5>

PCIE_CRX_GTX_P[0..15]<32,5>

D D

+VDD33MISC +3VS

12

RV237

0_0402_5%

@

RV24

RV25

@

DGPU_HOLD_RST#<18>

RV25

2.2K_0402_5%

@

1 2

2N7002DW-T/R7_SOT363-6

RV137

PLT_RST#<18,32,38,39,44,45,6>

2.2K_0402_5%

VGA_SMB_CK2

C C

VGA_SMB_DA2

B B

A A

QV1A

1 2

RV126

2

12

RV238

0_0402_5%

@

5

@

QV1B

4

2N7002DW-T/R7_SOT363-6

1 2

@

61

R_short 0_0402_5%

0.1U_0402_16V4Z

PLT_RST#

DGPU_HOLD_RST#

3

R_short 0_0402_5%

1

C1061

2

1

NC7SZ08P5X_NL_SC70-5

DGPU_PWR_EN<18,52>

+1.05VS_VGA

180ohms (ESR=0.2) Bead

EC_SMB_CK2 <15,32,41,45>

EC_SMB_DA2 <15,32,41,45>

+3VS

5

B

A

3

R1495

CLK_REQ_GPU#_R< 15>

UV2

P

4

Y

G

@

1 2

LV1 BLM18PG181SN1D_2PLV1 BLM18PG181SN1D_2P

1 2

PLT_RST_VGA#

1 2

0_0402_5%

RV231

10K_0402_5%

RV111

RV111 10K_0402_5%

10K_0402_5%

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

Under GPU(below 150mils)

1

CV112

2

22U_0805_6.3V6M

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

Differential signal

+3VS_VGA

RV230

RV230 10K_0402_5%

10K_0402_5%

@

1 2

12

2

G

QV16

1 3

D

S

D

S

2N7002H 1N_SOT23-3

@

1 2

RV233 0_0402_5%

4

1

CV4

CV113

2

0.1U_0402_10V7K

4.7U_0402_6.3V6M

CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K CV41 0.22U_0402_10V6KCV41 0.22U_0402_10V6K CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K

+3VS_VGA

RV30

RV30 10K_0402_5%

10K_0402_5%

1 2

CLK_REQ_GPU#

RV232

@RV232

@

10K_0402_5%

1 2

1

2

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

CV5

CLK_PCIE_VGA<15>

CLK_PCIE_VGA#<15>

150mA

+SP_PLLVDD

1 2

@

RV20 200_0402_1%

1 2

RV22 2.49K_0402_1%RV22 2.49K_0402_1%

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

PCIE_CRX_C_GTX_P7 PCIE_CRX_C_GTX_N7 PCIE_CRX_C_GTX_P6 PCIE_CRX_C_GTX_N6 PCIE_CRX_C_GTX_P5 PCIE_CRX_C_GTX_N5 PCIE_CRX_C_GTX_P4 PCIE_CRX_C_GTX_N4 PCIE_CRX_C_GTX_P3 PCIE_CRX_C_GTX_N3 PCIE_CRX_C_GTX_P2 PCIE_CRX_C_GTX_N2

PCIE_CRX_C_GTX_N1 PCIE_CRX_C_GTX_P0 PCIE_CRX_C_GTX_N0

CLK_PCIE_VGA CLK_PCIE_VGA#

CLK_REQ_GPU#

PEX_TSTCLK_OUT PEX_TSTCLK_OUT#

PLT_RST_VGA#

PEX_TERMP

UV1A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

PEX_WAKE_N

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

PEX_TSTCLK_OUT

AK26

PEX_TSTCLK_OUT_N

AJ12

PEX_RST_N

AP29

PEX_TERMP

N13P-GT1-A2_FCBGA908

GT@

3

Part 1 of 7

GPIO

PCI EXPRESS

15P_0402_50V8J

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

M7

GPIO6

N8

GPIO7

M1

GPIO8

M2

GPIO9

L1

GPIO10

M5

GPIO11

N3

GPIO12

M4

GPIO13

N4

GPIO14

P2

GPIO15

R8

GPIO16

M6

GPIO17

R1

GPIO18

P3

GPIO19

P4

GPIO20

P1

GPIO21

AK9

DACA_RED

AL10

DACA_GREEN

AL9

DACA_BLUE

AM9

DACA_HSYNC

AN9

DACA_VSYNC

DACs

CLK

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL

I2CA_SDA

I2CB_SCL

I2CB_SDA

I2CC_SCL

I2C

I2CC_SDA

I2CS_SCL

I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

AG10 AP9 AP8

R4 R5

R7 R6

R2 R3

T4 T3

AD8

AE8

AD7

H3 H2

J4 H1

Internal Thermal Sensor

1 2

RV23 10M_0402_5%RV23 10M_0402_5%

YV1

4

NC

1

XTAL_IN

OSC

27MHZ 16PF +-30PPM X3G027000FG1H-HX

1

CV37

2

DPRSLPVR_VGA GPIO16

GPU_VID4 GPU_VID3 VGA_BL_PWM VGA_ENVDD VGA_ENBKL GPU_VID1 GPU_VID2

DPRSLPVR_VGA_R

OVERT# GPIO9

GPU_VID0

GPU_VID5 FB_CLAMP_TOGGLE_REQ#

GPIO15 GPIO16

DGPU_HDMI_HPD

VGA_CRT_R VGA_CRT_G VGA_CRT_B

VGA_CRT_HSYNC VGA_CRT_VSYNC

+DACA_VDD +DACA_VREF DACA_RSET

VGA_CRT_CLK VGA_CRT_DATA

I2CB_SCL I2CB_SDA

VGA_EDID_CLK VGA_EDID_DATA

VGA_SMB_CK2 VGA_SMB_DA2

60mA

+PLLVDD

1 2

RV112 0_0402_5%@RV112 0_0402_5%@

45mA

XTAL_IN

XTAL_OUT

XTALOUT

1 2

XTALSSIN

3

XTAL_OUT

OSC

2

NC

CV38

15P_0402_50V8J

1 2

RV234 0_0402_5%@RV234 0_0402_5%@

GPU_VID4 <59> GPU_VID3 <59> VGA_BL_PWM <34> VGA_ENVDD <34> VGA_ENBKL <34> GPU_VID1 <59> GPU_VID2 <59>

1 2

RV235

0_0402_5%

@

GPU_VID0 <59>

DGPU_HDMI_HPD <37>

VGA_CRT_R <36> VGA_CRT_G <36> VGA_CRT_B <36>

VGA_CRT_HSYNC <36> VGA_CRT_VSYNC <36>

124_0402_1%

VGA_CRT_CLK <36>

VGA_CRT_DATA <36>

VGA_EDID_CLK <34>

VGA_EDID_DATA <34>

RV2610K_0402_5% RV2610K_0402_5%

RV27

10K_0402_5%

1

2

VGA_AC_DET

GPU_VID5 <59>

12

RV107

SLI@

CRT

LVDS

+SP_PLLVDD

12

2

+VDD33MISC

DPRSLPVR_VGA <59>

VGA_AC_DET <32,45,59>

GPIO15 <27>

Vendor recommand reserve PU/PD resistor

1

CV130

SLI@

2

0.1U_0402_10V7K

VGA_BL_PWM

VGA_ENBKL

VGA_CRT_R

VGA_CRT_G

VGA_CRT_B

120mA

+DACA_VDD

1

CV126

10K_0402_5%

OPT@

+PLLVDD

2

0.1U_0402_10V7K

Under GPU Near GPU

+VDD33MISC

12

RV65

@

10K_0402_5%

1 2

MEM_VREF <28,29,30,31>

12

RV223

10K_0402_5%

Close to GPU

1 2

RV106 150_0402_1%

1 2

RV108 150_0402_1%

1 2

RV109 150_0402_1%

OVERT#

PLT_RST_VGA#

SLI@

RV16 10K_0402_5%

1 2

RV17 100K_0402_5%

SLI@

61

2

13

2

G

GC6_EVENT#<19>

12

Under GPU Near GPU

1

CV139

2

0.1U_0402_10V7K

22U_0805_6.3V6M

CV126

@C V126

@

2

0.1U_0402_10V7K

SLI@

LV7 0_0402_5%LV7 0_0402_5%

1

CV40

2

CV139

0.1U_0402_10V7K

SLI@

1 2

CV125

@C V125

@

1

CV131

2

1

CV122

2

1U_0402_6.3V4Z

SLI@

RV208

RV208 10K_0402_5%

10K_0402_5%

5

QV7A

QV7A DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

D

S

+1.05VS_VGA

Add QV17, C38 has abnormal shutdown issue

QV17

QV17 2N7002KW_SOT323-3

2N7002KW_SOT323-3

RV170

GC6@RV170

GC6@

0_0402_5%

FB_CLAMP_TOGGLE_REQ#

OVERT#

VGA_EDID_CLK

VGA_EDID_DATA

VGA_CRT_DATA

VGA_CRT_CLK

I2CB_SCL

I2CB_SDA

1

CV127

CV128

2

SLI@

4.7U_0603_6.3V6K

1

PCH_THRMTRIP#_R

3

QV7B

QV7B DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

4

12

GPIO9

VGA_AC_DET

220 ohms @100MHz (ESR=0.05)

BLM18PG181SN1D_0603

SLI@

RV52

@RV52

@

1 2

10K_0402_5%

1 2

RV1 10K_0402_5%RV1 10K_0402_5%

R_short 0_0402_5%

1 2

RV15 2.2K_0402_5%RV15 2.2K_0402_5%

1 2

RV4 2.2K_0402_5%RV4 2.2K_0402_5%

1 2

RV7 2.2K_0402_5%RV7 2.2K_0402_5%

1 2

RV10 2.2K_0402_5%RV10 2.2K_0402_5%

1 2

RV11 2.2K_0402_5%RV11 2.2K_0402_5%

1 2

RV12 2.2K_0402_5%RV12 2.2K_0402_5%

1 2

RV13 2.2K_0402_5%RV13 2.2K_0402_5%

1 2

RV2 10K_0402_5%RV2 10K_0402_5%

LV5

12

PCH_THRMTRIP#_R <19,32>

+VDD33MISC

RV240

+3VS_VGA

+3VS

12

RV239

0_0402_5%

@

0_0402_5%

@

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N13P-PCIE/DAC/GPIO

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

23 66

0.2

5

VGA_TXCLK+<34>

VGA_TXCLK-<34>

VGA_TXOUT0+<34>

VGA_TXOUT0-<34>

VGA_TXOUT1+<34>

VGA_TXOUT1-<34>

VGA_TXOUT2+<34>

VGA_TXOUT2-<34>

D D

VGA_TZCLK+<34>

VGA_TZCLK-<34>

VGA_TZOUT0+<34>

VGA_HDMI_TX2+<37>

VGA_HDMI_TX2-<37>

VGA_HDMI_TX1+<37>

VGA_HDMI_TX1-<37>

VGA_HDMI_TX0+<37>

VGA_HDMI_TX0-<37>

VGA_HDMI_CLK+<37>

VGA_HDMI_CLK-<37>

HDMI

VGA_TZOUT0-<34>

VGA_TZOUT1+<34>

VGA_TZOUT1-<34>

VGA_TZOUT2+<34>

VGA_TZOUT2-<34>

VGA_HDMI_CLK<37> VGA_HDMI_DATA<37>

for 15" dual channel

C C

B B

+VDD33MISC

SLI@

1 2

RV113 4.7K_0402_5%

1 2

RV114 4.7K_0402_5%

SLI@

VGA_HDMI_DATA

4

VGA_TXCLK+ VGA_TXCLKVGA_TXOUT0+ VGA_TXOUT0VGA_TXOUT1+ VGA_TXOUT1VGA_TXOUT2+ VGA_TXOUT2-

VGA_TZCLK+ VGA_TZCLKVGA_TZOUT0+ VGA_TZOUT0VGA_TZOUT1+ VGA_TZOUT1VGA_TZOUT2+ VGA_TZOUT2-

VGA_HDMI_TX2+

VGA_HDMI_TX2-

VGA_HDMI_TX1+

VGA_HDMI_TX1-

VGA_HDMI_TX0+

VGA_HDMI_TX0-

VGA_HDMI_CLK+

VGA_HDMI_CLK-

VGA_HDMI_CLKVGA_HDMI_CLK VGA_HDMI_DATA

UV1D

AM6

IFPA_TXC

AN6

IFPA_TXC_ N

AP3

IFPA_TXD0

AN3

IFPA_TXD0 _N

AN5

IFPA_TXD1

AM5

IFPA_TXD1 _N

AL6

IFPA_TXD2

AK6

IFPA_TXD2 _N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3 _N

AJ9

IFPB_TXC

AH9

IFPB_TXC_ N

AP6

IFPB_TXD4

AP5

IFPB_TXD4 _N

AM7

IFPB_TXD5

AL7

IFPB_TXD5 _N

AN8

IFPB_TXD6

AM8

IFPB_TXD6 _N

AK8

IFPB_TXD7

AL8

IFPB_TXD7 _N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_ I2CW _SCL

AG2

IFPC_AUX_ I2CW _SDA_N

AK3

IFPD_AUX_ I2CX_SCL

AK2

IFPD_AUX_ I2CX_SDA _N

AB3

IFPE_AUX_ I2CY_SCL

AB4

IFPE_AUX_ I2CY_SDA_N

AF3

IFPF_AUX_ I2CZ_SCL

AF2

IFPF_AUX_ I2CZ_SDA _N

Part 4 of 7

VDD_SEN SE

GND_SEN SE

TEST

TESTMOD E

JTAG_TR ST_N

SERIAL

ROM_CS_ N ROM_SCL K

LVDS/TMDS

GENERAL

MULTI_STR AP_REF0_GND

3

NC

JTAG_TC K

JTAG_TD I JTAG_TD O JTAG_TM S

ROM_SI

ROM_SO

BUFRST_ N

CEC

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP THERMDN

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

VCCSENSE_VGA

L5

VSSSENSE_VGA

AK11

AM10 AM11 AP12 AP11 AN11

H6 H4 H5 H7

RV35 10K_0402_5%RV35 10K_0402_5%

L2

L3

J1

J2 J7 J6 J5 J3

K3 K4

VCCSENSE_VGA <59>

VSSSENSE_VGA <59>

trace width: 16mils differential voltage sensing. differential signal routing.

TESTMODE

TV2TV2 TV3TV3 TV4TV4

1 2

RV34 10K_0402_5%RV34 10K_0402_5%

ROM_CS# ROM_SCLK ROM_SI ROM_SO

1 2

RV38 40.2K_0402_1%RV38 40.2K_0402_1%

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

TV5TV5

ROM_SCLK <33> ROM_SI <33> ROM_SO <33>

12

STRAP0 <33> STRAP1 <33> STRAP2 <33> STRAP3 <33> STRAP4 <33>

12

10K_0402_5%

10K_0402_5% RV33

RV33

2

1

N13P-GT1-A2_FCBGA908

CV295

GC6@

12

0.1U_0402_16V4Z

GC6@

RV224 0_0402_5%

1 2

ROM_CS#

1 2

ROM_SO

RV226 0_0402_5%

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

3

LC Future Center Secret Data

RV226 0_0402_5%

GC6@

Deciphered Date

1MB SPI ROM FOR VBIOS ROM (SLI)

+3VS_VGA

20mils

12

GC6@

RV229

10K_0402_5%

ROM_CS#_R

2014/07/01

2

UV15

GC6@UV15

GC6@

1

CS#

2

HOLD#

DO

3

WP#

4

GND

MX25L1005AMC-12G SOP

12

RV225

RV225 10K_0402_5%

10K_0402_5%

GC6@

8

VCC

7

ROM_HOLD#ROM_SO_R

6

CLK

5

DIO

ROM_SCLK_R ROM_SI_R

Title

N13P-LVDS/HDMI/DP/THM

Size Document Number Rev

Custom

Date: Sheet of

GC6@

RV228 0_0402_5%

GC6@

1 2 1 2

RV227 0_0402_5%

GC6@

Tuesday, June 05, 2012

ROM_SCLK

ROM_SI

LA-8692P

LA-8692PLA-8692P

1

24 66

0.2

5

+1.5VS_VGA

D D

+1.5VS_VGA

1

CV277

2

1U_0402_6.3V6K

C C

B B

+3VS_VGA

A A

300ohms @100MHz (ESR=0.25) P/N: SM01003168 0

CV147

10K_0402_5%

OPT@

220ohms @100MHz (ESR=0.05)

+1.05VS_VGA

CV172

10K_0402_5%

OPT@

For GDDR5 setti ng. Near GPU

1

CV263

2

4.7U_0603_6.3V6K

1

CV264

CV265

2

4.7U_0603_6.3V6K

1

CV267

CV266

2

4.7U_0603_6.3V6K

Under GPU(below 150mils)

1

CV282

CV281

2

1U_0402_6.3V6K

1

CV278

2

1U_0402_6.3V6K

1

CV279

CV280

2

1U_0402_6.3V6K

VDDQ_SENSE<56>

CALIBRATION PIN

FB_CAL_x_PD_VDDQ

FB_CAL_x_PU_GND

FB_CAL_xTERM_GND

LV9

BLM18PG181SN1D_0603

12

SLI@

LV10

12

BLM18PG181SN1D_0603

SLI@

1

2

SLI@

4.7U_0603_6.3V6K

CV147

CV149

2

0.1U_0402_10V7K

1U_0402_6.3V6K

SLI@

1

Place near ball s

1

CV152

CV172

2

SLI@

4.7U_0603_6.3V6K

CV172

2

0.1U_0402_10V7K

1U_0402_6.3V6K

SLI@

Place near ball s

2

CV268

1

10U_0603_6.3V6M

0.1U_0402_10V7K

2

CV270

CV269

1

10U_0603_6.3V6M

1

CV287

CV292

2

0.1U_0402_10V7K

GDDR5

40.2Ohm

60.4Ohm

220mA

+IFPEF_PLLVDD

1

CV150

CV173

CV171

2

0.1U_0402_10V7K

SLI@

570mA

+IFPE_IOVDD +IFPAB_IOVDD

1

CV158

CV153

2

0.1U_0402_10V7K

SLI@

4

UV1E

3.5A

AA27

FBVDDQ_0

AA30

FBVDDQ_1

2

CV271

1

10U_0603_6.3V6M

1

CV294

2

0.1U_0402_10V7K

1

CV272

2

22U_0805_6.3V6M

1

2

0.1U_0402_10V7K

1 2

R_short 0_0402_5%

1 2

R_short 0_0402_5%

+1.5VS_VGA

CV273

CV284

22U_0805_6.3V6M

RV141

RV142

1

2

0.1U_0402_10V7K

1

CV276

2

22U_0805_6.3V6M

CV285

0.1U_0402_10V7K

FB_VSS_SENSE

1 2

CV276

CV275

2

22U_0805_6.3V6M

1

CV286

2

FB_VDDQ_SENSE

CV274

1

2

RV6 40.2_0402_1%RV6 40.2_0402_1%

RV8 40.2_0402_1%RV8 40.2_0402_1%

RV9 60.4_0402_1%RV9 60.4_0402_1%

AB27 AB33 AC27 AD27 AE27 AF27 AG27

H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24

M27 N27

R27

W27 W30 W33

H27

H25

B13 B16 B19 E13 E16 E19

H8 H9

L27

P27

T27 T30 T33 V27

Y27

F1

F2

J27

FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

Place near ball s

N13P-GT1-A2_FCBGA908

120ohms @100MHz (ESR=0.18)

+1.05VS_VGA

P/N:SM01000BZ00

CV140

10K_0402_5%

OPT@

180ohms @100MHz (ESR=0.2) P/N: SM01003071 0

+3VS_VGA

LV4

12

BLM18PG181SN1D_0603

SLI@

CV176

10K_0402_5%

OPT@

LV6

12

BLM18PG181SN1D_0603

SLI@

1

CV156

2

SLI@

1U_0402_6.3V6K

SLI@

4.7U_0603_6.3V6K

1

CV146

2

SLI@

1U_0402_6.3V6K

SLI@

4.7U_0603_6.3V6K

1

CV176

2

0.1U_0402_10V7K

SLI@

Place near ball s

200mA

1

CV140

2

Place near ball s

1

CV216

2

0.1U_0402_10V7K

SLI@

3

Part 5 of 7

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13

PEX_PLL_HVDD

PEX_SVDD_3V3

POWER

PEX_PLLVDD

VDD33_0 VDD33_1 VDD33_2 VDD33_3

IFPAB_PLLVDD

IFPAB_RSET

IFPA_IOVDD IFPB_IOVDD

IFPC_PLLVDD

IFPC_RSET

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD IFPF_IOVDD

+IFPAB_PLLVDD

1

CV141

2

0.1U_0402_10V7K

SLI@

IFPA_IOVDD and IFPB_IOVDD comb ined

CV197

2000mA

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

AG26

J8 K8 L8 M8

AH8

+IFPAB_PLLVDD

AJ8

AG8

+IFPAB_IOVDD

AG9

AF7

+IFPC_PLLVDD

AF8

AF6

+IFPC_IOVDD

AG7

+IFPD_PLLVDD

AN2

AG6

+IFPD_IOVDD

AB8

+IFPEF_PLLVDD

AD6

AC7

+IFPE_IOVDD

AC8

1

CV43

2

1U_0402_6.3V6K

Under GPU(below 150mils)

1

CV54

2

22U_0805_6.3V6M

+PEX_PLLVDD

+VDD33MISC

+VDD33

1 2

RV4210K_0402_5% RV4210K_0402_5%

1 2

RV4410K_0402_5% RV4410K_0402_5%

1 2

RV4510K_0402_5% RV4510K_0402_5%

1 2

RV4710K_0402_5% RV4710K_0402_5%

2

Near GPU

1

CV44

CV45

2

1U_0402_6.3V6K

1

CV53

CV56

2

22U_0805_6.3V6M

1

CV47

CV46

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

+1.05VS_VGA

1

CV55

2

22U_0805_6.3V6M

2

1

CV49

CV48

1

2

10U_0603_6.3V6M

4.7U_0603_6.3V6K

1

CV70

CV74

2

0.1U_0402_10V7K

4.7U_0603_6.3V6K

10U_0603_6.3V6M

+3VS_VGA

4.7U_0603_6.3V6K

2

CV50

1

CV73

2

10U_0603_6.3V6M

CV51

1

+VDD33MISC

10U_0603_6.3V6M

DGPU_PWR_EN#<52>

2

CV52

1

+VDD33MISC

For N13P-GT

0.1U_0402_10V7K

+1.05VS_VGA

1

CV72

2

0.1U_0402_10V7K

1

G

2

S

1

CV105

2

+3VS_VGA

QV8AO3413_SOT23

13

D

Under GPU(below 150mils)

RV5

12

LV2

0_0603_5%

+3VS_VGA

+3VS

+3VS_VGA

+VDD33MISC

+1.05VS_VGA

12

S3 GC6

Off On

Off

SLI@

Place near ball s Place ne ar GPU

1

CV111

CV109

12

RV401K_0402_1%@RV401K_0402_1%

@

12

RV431K_0402_1%@RV431K_0402_1%

@

CV109

2

0.1U_0402_10V7K

1

CV75

CV293

2

4.7U_0603_6.3V6K

1U_0402_6.3V6K

R_short 0_0603_5%

1

IFPAB & IFPEF have to use

12

RV461K_0402_1%@RV461K_0402_1%

@

12

RV501K_0402_1%

+PEX_PLLVDD

120mA

1

CV3

CV66

CV65

2

1U_0603_10V6K

0.1U_0402_10V7K

CV66

2

4.7U_0805_25V6-K

Place near ball s

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N13P-POWER

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

25 66

0.2

5

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

+VGA_CORE

UV1G

+VGA_CORE

D D

C C

B B

A A

UV1G

AA12

VDD_0

AA14

VDD_1

AA16

VDD_2

AA19

VDD_3

AA21

VDD_4

AA23

VDD_5

AB13

VDD_6

AB15

VDD_7

AB17

VDD_8

AB18

VDD_9

AB20

VDD_10

AB22

VDD_11

AC12

VDD_12

AC14

VDD_13

AC16

VDD_14

AC19

VDD_15

AC21

VDD_16

AC23

VDD_17

M12

VDD_18

M14

VDD_19

M16

VDD_20

M19

VDD_21

M21

VDD_22

M23

VDD_23

N13

VDD_24

N15

VDD_25

N17

VDD_26

N18

VDD_27

N20

VDD_28

N22

VDD_29

P12

VDD_30

P14

VDD_31

P16

VDD_32

P19

VDD_33

P21

VDD_34

P23

VDD_35

R13

VDD_36

R15

VDD_37

R17

VDD_38

R18

VDD_39

R20

VDD_40

R22

VDD_41

T12

VDD_42

T14

VDD_43

T16

VDD_44

T19

VDD_45

T21

VDD_46

T23

VDD_47

U13

VDD_48

U15

VDD_49

U17

VDD_50

U18

VDD_51

U20

VDD_52

U22

VDD_53

V13

VDD_54

V15

VDD_55

N13P-GT1-A2_FCBGA908

5

Part 7 of 7

POWER

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30

XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38

4

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19

AB2

AB21

A33 AB23 AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AA15 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AJ7

AK10

AK7

AL12 AL14 AL15 AL17 AL18

AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AL5

AM13 AM16 AM19 AM22 AM25

AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34

AN4

AN7

AP2 AP33

B1 B10 B22 B25 B28 B31 B34

B4

B7 C10 C13 C19 C22 C25 C28

C7

2014/07/01

2

GND_100 GND_101 GND_102 GND_103 GND_104 GND_105 GND_106 GND_107 GND_108 GND_109 GND_110 GND_111 GND_112 GND_113 GND_114 GND_115 GND_116 GND_117 GND_118 GND_119 GND_120 GND_121 GND_122 GND_123 GND_124 GND_125 GND_126 GND_127 GND_128 GND_129 GND_130 GND_131 GND_132 GND_133 GND_134 GND_135 GND_136 GND_137 GND_138 GND_139 GND_140 GND_141 GND_142 GND_143 GND_144 GND_145 GND_146 GND_147 GND_148 GND_149 GND_150 GND_151 GND_152 GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_199 GND_OPT GND_OPT

1

D2 D31 D33 E10 E22 E25 E5 E7 F28 F7 G10 G13 G16 G19 G2 G22 G25 G28 G3 G30 G32 G33 G5 G7 K2 K28 K30 K32 K33 K5 K7 M13 M15 M17 M18 M20 M22 N12 N14 N16 N19 N2 N21 N23 N28 N30 N32 N33 N5 N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32

LA-8692P

LA-8692PLA-8692P

1

26 66

UV1F

N13P-GT1-A2_FCBGA908

Part 6 of 7

GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99

Title

N13P-VGA CORE, GND

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

GND

Tuesday, June 05, 2012

0.2

of

5

FBA_D[0..63]<28,29>

30ohms (ESR=0.01) Bead P/N;SM010007W00

+1.05VS_VGA +FB_PLLAVDD

FBMA-L11-160808300LMA25T_2P

D D

C C

B B

1 2

LV3

Place close to BGA

200mA

+FB_PLLAVDD

FBA_EDC[3..0]< 28>

FBA_EDC[7..4]< 29>

For N13P-GT GC6 support

+3VS

13

D

@GD

@

2

QV4

DGPU_GC6_EN<18>

GC6@

0_0402_5%

RV169

A A

RV169

10K_0402_5%

12

GC6@

RV68

QV4

G

2N7002_SOT23

S

GC6_EN

12

5

FBA_D[0..63]

FBA_DBI0#<28> FBA_DBI1#<28> FBA_DBI2#<28> FBA_DBI3#<28> FBA_DBI4#<29> FBA_DBI5#<29> FBA_DBI6#<29> FBA_DBI7#<29>

For GC6 test

@

1 2

GPIO15

RV241 0_0402_5%

12

FB_CLAMP

RV18 1K_0402_1%

GC6@

DGPU_PWROK<19,56,59>

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DBI0# FBA_DBI1# FBA_DBI2# FBA_DBI3# FBA_DBI4# FBA_DBI5# FBA_DBI6# FBA_DBI7#

FBA_EDC0

FBA_EDC1

FBA_EDC2

FBA_EDC3

FBA_EDC4

FBA_EDC5

FBA_EDC6

FBA_EDC7

GPIO15 <23>

DV3

DAN202UT106_SC70-3

2

1

3

GC6@

1 2

RV156 0_0402_5%

NOGC6@

UV1B

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N13P-GT1-A2_FCBGA908

12

RV29

RV29 200K_0402_5%

200K_0402_5%

GC6@

4

Part 2 of 7

FBA_CMD_RFU0 FBA_CMD_RFU1

MEMORY INTERFACE

A

MEMORY INTERFACE

A

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0_N

FBA_CLK1_N

FBA_WCK01_N

FBA_WCK23_N

FBA_WCK45_N

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

FB_DLL_AVDD

FBA_PLL_AVDD

FBVDDQ_PWR_EN <56>

4

U30

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CLK0

FBA_CLK1

FBA_WCK01

FBA_WCK23

FBA_WCK45

FBA_WCK67

FB_CLAMP

FB_VREF

FBA_CS#_L

T31

FBA_MA3_BA3_L

U29

FBA_MA2_BA0_L

R34

FBA_MA4_BA2_L

R33

FBA_MA5_BA1_L

U32

FBA_WE#_L

U33

FBA_MA7_MA8_L

U28

FBA_MA6_MA11_L

V28

FBA_ABI#_L

V29

FBA_MA12_RFU_L

V30

FBA_MA0_MA10_L

U34

FBA_MA1_MA9_L

U31

FBA_RAS#_L

V34

FBA_RST#_L

V33

FBA_CKE_L

Y32

FBA_CAS#_L

AA31

FBA_CS#_H

AA29

FBA_MA3_BA3_H

AA28

FBA_MA2_BA0_H

AC34

FBA_MA4_BA2_H

AC33

FBA_MA5_BA1_H

AA32

FBA_WE#_H

AA33

FBA_MA7_MA8_H

Y28

FBA_MA6_MA11_H

Y29

FBA_ABI#_H

W31

FBA_MA12_RFU_H

Y30

FBA_MA0_MA10_H

AA34

FBA_MA1_MA9_H

Y31

FBA_RAS#_H

Y34

FBA_RST#_H

Y33

FBA_CKE_H

V31

FBA_CAS#_H

R32 AC32

@

1 2

R28 AC28

1 2

@

R30

FBA_CLK0

R31

FBA_CLK0#

AB31

FBA_CLK1

AC31

FBA_CLK1#

K31

FBA_WCK0

L30

FBA_WCK0_N

H34

FBA_WCK1

J34

FBA_WCK1_N

AG30

FBA_WCK2

AG31

FBA_WCK2_N

AJ34

FBA_WCK3

AK34

FBA_WCK3_N

J30 J31 J32 J33

GC6 support on 15"

AH31 AJ31

FB_CLAMP

AJ32 AJ33

RV66 10K_0402_5%NOGC6@RV66 10K_0402_5%NOGC6@

E1

K27

U27

H26

Place close to ball Place close to BGA

12

CV106 0.1U_0402_10V7KCV106 0.1U_0402_10V7K

1 2

Place close to ball

1

2

0.1U_0402_10V7K

FBA_RST#_L FBA_RST#_H

12

FBA_CS#_L <28> FBA_MA3_BA3_L <28> FBA_MA2_BA0_L <28> FBA_MA4_BA2_L <28> FBA_MA5_BA1_L <28> FBA_WE#_L <28> FBA_MA7_MA8_L <28> FBA_MA6_MA11_L <28> FBA_ABI#_L <28> FBA_MA12_RFU_L <28> FBA_MA0_MA10_L <28> FBA_MA1_MA9_L <28> FBA_RAS#_L <28> FBA_RST#_L <28>

FBA_CAS#_L <28> FBA_CS#_H <29> FBA_MA3_BA3_H <29> FBA_MA2_BA0_H <29> FBA_MA4_BA2_H <29> FBA_MA5_BA1_H <29> FBA_WE#_H <29> FBA_MA7_MA8_H <29> FBA_MA6_MA11_H <29> FBA_ABI#_H <29> FBA_MA12_RFU_H <29> FBA_MA0_MA10_H <29> FBA_MA1_MA9_H <29> FBA_RAS#_H <29> FBA_RST#_H <29>

FBA_CAS#_H <29>

RV5860.4_0402_1%@RV5860.4_0402_1% RV5960.4_0402_1%@RV5960.4_0402_1%

FBA_CLK0 <28> FBA_CLK0# <28> FBA_CLK1 <29> FBA_CLK1# <29>

FBA_WCK0 <28> FBA_WCK0_N <28> FBA_WCK1 <28> FBA_WCK1_N <28> FBA_WCK2 <29> FBA_WCK2_N <29> FBA_WCK3 <29> FBA_WCK3_N <29>

+FB_PLLAVDD

1

CV107

2

1U_0402_6.3V6K

12

RV71

RV71 10K_0402_5%

10K_0402_5%

+1.5VS_VGA

CV110

22U_0805_6.3V6M

RV72

RV72 10K_0402_5%

10K_0402_5%

1

2

+FB_PLLAVDD

CV39

FBC_D[0..63]<30,31>

+1.5VS_VGA

12

+1.5VS_VGA

12

RV209

RV209 10K_0402_5%

10K_0402_5%

RV221

RV221 10K_0402_5%

10K_0402_5%

FBC_EDC[3..0]<30>

FBC_EDC[7..4]<31>

3

FBC_D[0..63]

FBA_CKE_L <28>

FBA_CKE_H <29>

FBC_DBI0#<30> FBC_DBI1#<30> FBC_DBI2#<30> FBC_DBI3#<30> FBC_DBI4#<31> FBC_DBI5#<31> FBC_DBI6#<31> FBC_DBI7#<31>

3

2

UV1C

Part 3 of 7

FBC_D0 FBC_D1 FBC_D2 FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7 FBC_D8 FBC_D9

FBC_D10 FBC_D11 FBC_D12 FBC_D13 FBC_D14 FBC_D15 FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23 FBC_D24 FBC_D25 FBC_D26 FBC_D27 FBC_D28 FBC_D29 FBC_D30 FBC_D31 FBC_D32 FBC_D33 FBC_D34 FBC_D35 FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63

FBC_DBI0# FBC_DBI1# FBC_DBI2# FBC_DBI3# FBC_DBI4# FBC_DBI5# FBC_DBI6# FBC_DBI7#

FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

G9

E9

G8

F9

F11

G11

F12

G12

G6

F5 E6 F6 F4

G4

E2

F3 C2 D4 D3 C1

B3 C4

B5 C5

A11 C11 D11

B11

D8

A8

C8

B8

F24 G23

E24 G24 D21

E21 G21

F21 G27 D27 G26

E27

E29

F29

E30 D30

A32 C31 C32

B32 D29

A29 C29

B29

B21 C23

A21 C21

B24 C24

B26 C26

E11

E3 A3

C9 F23 F27

C30

A24

D10

D5

C3

B9 E23 E28 B30 A23

D9

E4

B2

A9

D22 D28

A30 B23

Part 3 of 7

FBB_D0 FBB_D1 FBB_D2 FBB_D3 FBB_D4 FBB_D5 FBB_D6 FBB_D7 FBB_D8 FBB_D9 FBB_D10 FBB_D11 FBB_D12 FBB_D13 FBB_D14 FBB_D15 FBB_D16 FBB_D17 FBB_D18 FBB_D19 FBB_D20 FBB_D21 FBB_D22 FBB_D23 FBB_D24 FBB_D25 FBB_D26 FBB_D27 FBB_D28 FBB_D29 FBB_D30 FBB_D31 FBB_D32 FBB_D33 FBB_D34 FBB_D35 FBB_D36 FBB_D37 FBB_D38 FBB_D39 FBB_D40 FBB_D41 FBB_D42 FBB_D43 FBB_D44 FBB_D45 FBB_D46 FBB_D47 FBB_D48 FBB_D49 FBB_D50 FBB_D51 FBB_D52 FBB_D53 FBB_D54 FBB_D55 FBB_D56 FBB_D57 FBB_D58 FBB_D59 FBB_D60 FBB_D61 FBB_D62 FBB_D63

FBB_DQM0 FBB_DQM1 FBB_DQM2 FBB_DQM3 FBB_DQM4 FBB_DQM5 FBB_DQM6 FBB_DQM7

FBB_DQS_WP0 FBB_DQS_WP1 FBB_DQS_WP2 FBB_DQS_WP3 FBB_DQS_WP4 FBB_DQS_WP5 FBB_DQS_WP6 FBB_DQS_WP7

FBB_DQS_RN0 FBB_DQS_RN1 FBB_DQS_RN2 FBB_DQS_RN3 FBB_DQS_RN4 FBB_DQS_RN5 FBB_DQS_RN6 FBB_DQS_RN7

N13P-GT1-A2_FCBGA908

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

FBB_CMD_RFU0 FBB_CMD_RFU1

MEMORY INTERFACE B

FBB_WCKB01_N

FBB_WCKB23_N

FBB_WCKB45_N

FBB_WCKB67_N

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_DEBUG0

FBB_DEBUG1

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB23

FBB_WCKB45

FBB_WCKB67

FBB_PLL_AVDD

2012/07/01

D13

FBC_CS#_L

E14

FBC_MA3_BA3_L

F14

FBC_MA2_BA0_L

A12

FBC_MA4_BA2_L

B12

FBC_MA5_BA1_L

C14

FBC_WE#_L

B14

FBC_MA7_MA8_L

G15

FBC_MA6_MA11_L

F15

FBC_ABI#_L

E15

FBC_MA12_RFU_L

D15

FBC_MA0_MA10_L

A14

FBC_MA1_MA9_L

D14

FBC_RAS#_L

A15

FBC_RST#_L

B15

FBC_CKE_L

C17

FBC_CAS#_L

D18

FBC_CS#_H

E18

FBC_MA3_BA3_H

F18

FBC_MA2_BA0_H

A20

FBC_MA4_BA2_H

B20

FBC_MA5_BA1_H

C18

FBC_WE#_H

B18

FBC_MA7_MA8_H

G18

FBC_MA6_MA11_H

G17

FBC_ABI#_H

F17

FBC_MA12_RFU_H

D16

FBC_MA0_MA10_H

A18

FBC_MA1_MA9_H

D17

FBC_RAS#_H

A17

FBC_RST#_H

B17

FBC_CKE_H

E17

FBC_CAS#_H

C12 C20

@

1 2

G14

1 2

G20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

@

FBC_CLK0 FBC_CLK0# FBC_CLK1 FBC_CLK1#

FBC_WCK0 FBC_WCK0_N FBC_WCK1 FBC_WCK1_N FBC_WCK2 FBC_WCK2_N FBC_WCK3 FBC_WCK3_N

1

CV108

2

0.1U_0402_10V7K

Place close to ball

LC Future Center Secret Data

Deciphered Date

2

FBC_CS#_L <30> FBC_MA3_BA3_L <30> FBC_MA2_BA0_L <30> FBC_MA4_BA2_L <30> FBC_MA5_BA1_L <30> FBC_WE#_L <30> FBC_MA7_MA8_L <30> FBC_MA6_MA11_L <30> FBC_ABI#_L <30> FBC_MA12_RFU_L <30> FBC_MA0_MA10_L <30> FBC_MA1_MA9_L <30> FBC_RAS#_L <30> FBC_RST#_L <30>

FBC_CAS#_L <30> FBC_CS#_H <31> FBC_MA3_BA3_H <31> FBC_MA2_BA0_H <31> FBC_MA4_BA2_H <31> FBC_MA5_BA1_H <31> FBC_WE#_H <31> FBC_MA7_MA8_H <31> FBC_MA6_MA11_H <31> FBC_ABI#_H <31> FBC_MA12_RFU_H <31> FBC_MA0_MA10_H <31> FBC_MA1_MA9_H <31> FBC_RAS#_H <31> FBC_RST#_H <31>

FBC_CAS#_H <31>

RV6060.4_0402_1%@RV6060.4_0402_1% RV6160.4_0402_1%@RV6160.4_0402_1%

FBC_CLK0 <30> FBC_CLK0# <30> FBC_CLK1 <31> FBC_CLK1# <31>

FBC_WCK0 <30> FBC_WCK0_N <30> FBC_WCK1 <30> FBC_WCK1_N <30> FBC_WCK2 <31> FBC_WCK2_N <31> FBC_WCK3 <31> FBC_WCK3_N <31>

+FB_PLLAVDD

+1.5VS_VGA

FBC_RST#_L FBC_RST#_H

2014/07/01

PU for X16 modePU for X16 mode

+1.5VS_VGA

12

+1.5VS_VGA

12

1

GDDR5 Mode H - Mirror Mode Mapping

RV210

RV210 10K_0402_5%

10K_0402_5%

FBC_CKE_L <30>

RV222

RV222 10K_0402_5%

10K_0402_5%

FBC_CKE_H <31>

12

RV74

RV74 10K_0402_5%

10K_0402_5%

Title

N13P-MEM Interface

Size Document Number Rev

Custom

Date: Sheet of

RV73

RV73 10K_0402_5%

10K_0402_5%

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

Tuesday, June 05, 2012

1

A3_BA3

A2_BA0

A4_BA2

A5_BA1

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

LA-8692P

LA-8692PLA-8692P

CS#

WE#

RAS#

RST#

CKE#

CAS#

DATA Bus

27 66

32..630..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

0.2

5

Memory - Lower 32 bits

FBA_EDC0

FBA_D[0..31]<27>

FBA_EDC[3..0]<27>

D D

Follow DG

1 2

FBA_CLK0

RV21 40.2_0402_1%RV21 40.2_0402_1%

RV123

RV123 160_0402_1%

160_0402_1%

@

FBA_CLK0#

MEM_VREF<23,29,30,31>

@

1 2

RV28 40.2_0402_1%RV28 40.2_0402_1%

2

G

1

CV155

2

0.01U_0402_25V7K

RV212

1 2

931_0402_1%

1.33K_0402_1%

13

D

QV9

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

549_0402_1%

10U_0603_6.3V6M

C C

B B

A A

FBA_DBI0#<27>

FBA_DBI2#<27> FBA_DBI1#<27>

FBA_CLK0< 27>

FBA_CLK0#<27>

FBA_CKE_L< 27>

FBA_MA2_BA0_L<27> FBA_MA5_BA1_L<27> FBA_MA4_BA2_L<27> FBA_MA3_BA3_L<27>

FBA_MA7_MA8_L<27>

FBA_MA1_MA9_L<27> FBA_MA0_MA10_L<27> FBA_MA6_MA11_L<27>

FBA_MA12_RFU_L<27>

RV119

121_0402_1%

FBA_ABI#_L<27>

FBA_RAS#_L<27>

FBA_CS#_L<27>

FBA_CAS#_L<27>

FBA_WE#_L<27>

FBA_WCK0_N<27> FBA_WCK0<27>

FBA_WCK1_N<27> FBA_WCK1<27>

FBA_RST#_L<27>

+1.5VS_VGA

12

RV127

12

1

RV128

2

820P_0402_25V7

+1.5VS_VGA

RV129

549_0402_1%

RV213

1 2

931_0402_1%

RV130

1.33K_0402_1%

UV3 SIDE

2

1

CV68

CV166

1

2

1U_0603_10V6K

FBA_EDC2

FBA_DBI0#

FBA_DBI2#

FBA_CLK0 FBA_CLK0# FBA_CKE_L

FBA_MA2_BA0_L FBA_MA5_BA1_L FBA_MA4_BA2_L FBA_MA3_BA3_L

FBA_MA7_MA8_L

FBA_MA1_MA9_L FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA12_RFU_L

12

RV115

1K_0402_1%

12

RV117

12

1K_0402_1%

FBA_ABI#_L

FBA_RAS#_L

FBA_CS#_L

FBA_CAS#_L

FBA_WE#_L

FBA_WCK0_N FBA_WCK0

FBA_WCK1_N FBA_WCK1

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

+FBA_VREFC0

16 mil

CV42

+1.5VS_VGA +1.5VS_VGA

12

+FBA_VREFD_L

12

820P_0402_25V7

1

CV69

CV77

2

1U_0603_10V6K

UV3

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

1

CV58

2

1

2

170-BALL

SGRAM GDDR5

X76@

1

CV78

2

0.1U_0402_10V7K

1

CV129

CV132

2

0.1U_0402_10V7K

CV133

4

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV4

MF=0 MF=1 MF=0MF=1

A4

FBA_D0

A2

FBA_D1

B4

FBA_D2

B2

FBA_D3

E4

FBA_D4

E2

FBA_D5

F4

FBA_D6

F2

FBA_D7

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBA_D16

U13

FBA_D17

T11

FBA_D18

T13

FBA_D19

N11

FBA_D20

N13

FBA_D21

M11

FBA_D22

M13

FBA_D23

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

10U_0603_6.3V6M

2

1

CV174

BYTE0

BYTE2

UV4 SIDE

1

CV71

2

1U_0603_10V6K

FBA_DBI3#<27>

+1.5VS_VGA

RV120

121_0402_1%

1

CV76

2

1U_0603_10V6K

1

CV79

CV80

CV134

2

1U_0603_10V6K

0.1U_0402_10V7K

12

1

CV135

2

FBA_CLK0 FBA_CLK0#

FBA_CKE_L

FBA_MA4_BA2_L FBA_MA3_BA3_L FBA_MA2_BA0_L FBA_MA5_BA1_L

FBA_MA0_MA10_L FBA_MA6_MA11_L

FBA_MA7_MA8_L FBA_MA1_MA9_L

FBA_MA12_RFU_L

12

RV116

1K_0402_1%

12

RV118

1K_0402_1%

FBA_ABI#_L

FBA_CAS#_L

FBA_WE#_L

FBA_RAS#_L

FBA_CS#_L

FBA_WCK1_N FBA_WCK1

FBA_WCK0_N FBA_WCK0

+FBA_VREFD_L

+FBA_VREFC0

FBA_RST#_L

1

CV136

2

0.1U_0402_10V7K

FBA_EDC3

FBA_EDC1

FBA_DBI3#

FBA_DBI1#

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

2

A4

FBA_D24

A2

FBA_D25

B4

FBA_D26

B2

FBA_D27

E4

FBA_D28

E2

FBA_D29

F4

FBA_D30

F2

FBA_D31

A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11

FBA_D10

T13

FBA_D11

N11

FBA_D12

N13

FBA_D13

M11

FBA_D14

M13

FBA_D15

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBA_D8 FBA_D9

BYTE3

GDDR5

BYTE1

+1.5VS_VGA+1.5VS_VGA

Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

1

DATA Bus

0..31 32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N13P-VRAM A Lower

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

28 66

0.2

5

Memory - Upper 32 bits

C2

FBA_EDC4

C13 R13

FBA_CLK1

FBA_CLK1#

FBA_MA2_BA0_H FBA_MA5_BA1_H FBA_MA4_BA2_H FBA_MA3_BA3_H

FBA_MA7_MA8_H

FBA_MA1_MA9_H FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA12_RFU_H

12

+FBA_VREFC1

16 mil

CV59

+FBA_VREFD_H

820P_0402_25V7

1

CV138

2

FBA_CKE_H

RV131

1K_0402_1%

RV133

1K_0402_1%

FBA_ABI#_H

FBA_RAS#_H

FBA_CS#_H

FBA_CAS#_H

FBA_WE#_H

FBA_WCK2_N FBA_WCK2

FBA_WCK3_N FBA_WCK3

+FBA_VREFD_H

+FBA_VREFC1

FBA_RST#_H

+1.5VS_VGA

1

CV60

2

1

CV142

2

0.1U_0402_10V7K

FBA_EDC6

FBA_DBI4#

FBA_DBI6#

12

0.1U_0402_10V7K

R2

D2

D13

P13

P2

J12 J11

J3

H11

K10 K11

H10

K4 H5 H4

K5

J5

A5 U5

J1

J10 J13

J4 G3

G12

L3

L12

D5 D4

P5

P4

A10

U10

J14

J2

H1

K1

B5 G5

L5

T5

B10 D10 G10

L10

P10

T10 H14

K14

G1

L1

G4

L4 C5 R5

C10 R10 D11 G11

L11 P11

G14

L14

1

CV137

2

FBA_D[63..32]<27>

D D

FBA_EDC[7..4]<27>

Follow DG

1 2

FBA_CLK1

RV31 40.2_0402_1%RV31 40.2_0402_1%

RV139

RV139 160_0402_1%

C C

B B

MEM_VREF<23,28,30,31>

A A

FBA_CLK1#

160_0402_1%

@

1 2

RV36 40.2_0402_1%RV36 40.2_0402_1%

13

D

2

G

QV11

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

UV5 SIDE

2

1

CV179

1

2

1U_0603_25V6

10U_0603_6.3V6M

1

2

0.01U_0402_25V7K

1 2

931_0402_1%

CV84

CV175

RV214

RV215

1 2

931_0402_1%

1

2

1U_0603_25V6

549_0402_1%

1.33K_0402_1%

549_0402_1%

1.33K_0402_1%

CV81

1U_0603_25V6

FBA_MA2_BA0_H<27> FBA_MA5_BA1_H<27> FBA_MA4_BA2_H<27> FBA_MA3_BA3_H<27>

FBA_MA7_MA8_H<27>

FBA_MA1_MA9_H<27> FBA_MA0_MA10_H<27> FBA_MA6_MA11_H<27>

FBA_MA12_RFU_H<27>

RV143

RV144

RV145

RV146

1

2

FBA_CLK1< 27>

FBA_CLK1#<27>

FBA_CKE_H<27>

FBA_ABI#_H<27>

FBA_RAS#_H<27>

FBA_CS#_H<27>

FBA_CAS#_H<27>

FBA_WE#_H<27>

FBA_WCK2_N<27> FBA_WCK2<27>

FBA_WCK3_N<27> FBA_WCK3<27>

FBA_RST#_H<27>

+1.5VS_VGA

CV82

1U_0603_25V6

12

1

2

RV135

CV83

FBA_DBI4#<27>

FBA_DBI6#<27>

121_0402_1%

1

2

820P_0402_25V7

0.1U_0402_10V7K

4

UV5

MF=0 MF=1 MF=0MF=1

EDC0 EDC3 EDC1 EDC2 EDC2 EDC1 EDC3 EDC0

DBI0# DBI3# DBI1# DBI2# DBI2# DBI1# DBI3# DBI0#

CK CK# CKE#

BA0/A2 BA2/A4 BA1/A5 BA3/A3 BA2/A4 BA0/A2 BA3/A3 BA1/A5

A8/A7 A10/A0 A9/A1 A11/A6 A10/A0 A8/A7 A11/A6 A9/A1 A12/RFU/NC

VPP/NC VPP/NC

MF SEN ZQ

ABI# RAS# CAS# CS# WE# CAS# RAS# WE# CS#

WCK01# WC K23# WCK01 WCK23

WCK23# WC K01# WCK23 WCK01

VREFD VREFD VREFC

RESET#

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14

DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

3

UV6

MF=0 MF=1 MF=0MF=1

A4

FBA_D32

A2

FBA_D33

B4

FBA_D34

B2

FBA_D35

E4

FBA_D36

E2

FBA_D37

F4

FBA_D38

F2

FBA_D39

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBA_D48

U13

FBA_D49

T11

FBA_D50

T13

FBA_D51

N11

FBA_D52

N13

FBA_D53

M11

FBA_D54

M13

FBA_D55

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

10U_0603_6.3V6M

2

1

CV187

BYTE4

BYTE6

UV6 SIDE

1

CV87

2

1U_0603_25V6

FBA_DBI7#<27>

FBA_DBI5#<27>

FBA_CLK1

FBA_CLK1#

FBA_CKE_H

FBA_MA4_BA2_H FBA_MA3_BA3_H FBA_MA2_BA0_H FBA_MA5_BA1_H

FBA_MA0_MA10_H FBA_MA6_MA11_H

FBA_MA7_MA8_H FBA_MA1_MA9_H

FBA_MA12_RFU_H

+1.5VS_VGA

RV132

1K_0402_1%

RV134

12

RV136

1

2

1U_0603_25V6

1

CV85

CV88

CV86

2

1U_0603_25V6

2

1U_0603_25V6

0.1U_0402_10V7K

121_0402_1%

CV145

0.1U_0402_10V7K

+FBA_VREFD_H

+FBA_VREFC1

+1.5VS_VGA

1

CV143

2

1K_0402_1%

FBA_ABI#_H

FBA_CAS#_H

FBA_WE#_H

FBA_RAS#_H

FBA_CS#_H

FBA_WCK3_N FBA_WCK3

FBA_WCK2_N FBA_WCK2

FBA_RST#_H

0.1U_0402_10V7K

FBA_EDC7

FBA_EDC5

FBA_DBI7#

FBA_DBI5#

12

1

2

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WC K23#

D4

WCK01 WCK23

P5

WCK23# WC K01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

CV144

H5GQ1H24AFR-T2L_BGA170

2

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

A4

FBA_D56

A2

FBA_D57

B4

FBA_D58

B2

FBA_D59

E4

FBA_D60

E2

FBA_D61

F4

FBA_D62

F2

FBA_D63

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBA_D40

U13

FBA_D41

T11

FBA_D42

T13

FBA_D43

N11

FBA_D44

N13

FBA_D45

M11

FBA_D46

M13

FBA_D47

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

BYTE7

BYTE5

GDDR5 Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. A ND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHE R THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N13P-VRAM A Upper

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

29 66

0.2

5

4

3

2

1

Memory Partition C - Lower 32 bits

UV8

UV7

MF=0 MF=1 MF=0MF=1

C2

FBC_EDC0

FBC_CLK0 FBC_CLK0#

FBC_CKE_L

FBC_MA2_BA0_L FBC_MA5_BA1_L FBC_MA4_BA2_L FBC_MA3_BA3_L

FBC_MA7_MA8_L

FBC_MA1_MA9_L FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA12_RFU_L

RV147

RV149

FBC_ABI#_L

FBC_RAS#_L

FBC_CS#_L

FBC_CAS#_L

FBC_WE#_L

FBC_WCK0_N FBC_WCK0

FBC_WCK1_N FBC_WCK1

+FBC_VREFD_L

+FBC_VREFC0

1

CV61

2

+1.5VS_VGA

+FBC_VREFD_L

1

2

820P_0402_25V7

1

CV157

2

0.1U_0402_10V7K

FBC_EDC2

FBC_DBI0#

FBC_DBI2#

12

1K_0402_1%

12

1K_0402_1%

FBC_RST#_L

CV62

1

2

0.1U_0402_10V7K

FBC_D[0..31]<27>

D D

C C

B B

A A

FBC_EDC[3..0]<27>

Follow DG

FBC_CLK0

FBC_CLK0#

MEM_VREF<23,28,29,31>

+1.5VS_VGA

1 2

RV37 40.2_0402_1%RV37 40.2_0402_1%

RV155

RV155 160_0402_1%

160_0402_1%

@

1 2

RV39 40.2_0402_1%RV39 40.2_0402_1%

13

D

2

G

S

UV7 SIDE

1

2

CV91

CV199

2

1

1U_0603_25V6

10U_0603_6.3V6M

1

CV195

2

0.01U_0402_25V7K

RV216

1 2

931_0402_1%

1.33K_0402_1%

549_0402_1%

RV217

1 2

931_0402_1%

1.33K_0402_1%

QV13

2N7002W-T/R7_SOT323-3

1

CV92

CV89

2

1U_0603_25V6

FBC_CLK0<27>

FBC_CLK0#<27>

FBC_CKE_L<27>

FBC_MA2_BA0_L<27> FBC_MA5_BA1_L<27> FBC_MA4_BA2_L<27> FBC_MA3_BA3_L<27>

FBC_MA7_MA8_L<27>

FBC_MA1_MA9_L<27> FBC_MA0_MA10_L<27> FBC_MA6_MA11_L<27>

FBC_MA12_RFU_L<27>

FBC_ABI#_L<27>

FBC_RAS#_L<27>

FBC_CS#_L<27>

FBC_CAS#_L<27>

FBC_WE#_L<27>

FBC_WCK0_N<27> FBC_WCK0<27>

FBC_WCK1_N<27> FBC_WCK1<27>

FBC_RST#_L<27>

RV159

549_0402_1%

RV160

+1.5VS_VGA

RV161

RV162

1

2

1U_0603_25V6

RV151

+1.5VS_VGA

12

CV90

0.1U_0402_10V7K

FBC_DBI0#<27>

FBC_DBI2#<27>

12

121_0402_1%

820P_0402_25V7

1

CV160

2

CV159

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4

FBC_D0

A2

FBC_D1

B4

FBC_D2

B2

FBC_D3 FBC_D4 FBC_D5 FBC_D6 FBC_D7

FBC_D16 FBC_D17 FBC_D18 FBC_D19 FBC_D20 FBC_D21 FBC_D22 FBC_D23

+1.5VS_VGA

BYTE0

BYTE2

+1.5VS_VGA

10U_0603_6.3V6M

2

1

CV207

UV8 SIDE

1

CV95

2

1U_0603_25V6

FBC_DBI3#<27>

FBC_DBI1#<27>

+1.5VS_VGA

12

RV152

121_0402_1%

1

CV96

2

1U_0603_25V6

CV94

CV93

2

1U_0603_25V6

0.1U_0402_10V7K

E4 E2 F4 F2 A11 A13 B11 B13 E11 E13 F11 F13 U11 U13 T11 T13 N11 N13 M11 M13 U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

FBC_MA0_MA10_L FBC_MA6_MA11_L

FBC_MA12_RFU_L

1

CV163

2

FBC_EDC3

FBC_EDC1

FBC_DBI3#

FBC_DBI1#

FBC_CLK0 FBC_CLK0# FBC_CKE_L

FBC_MA4_BA2_L FBC_MA3_BA3_L FBC_MA2_BA0_L FBC_MA5_BA1_L

FBC_MA7_MA8_L FBC_MA1_MA9_L

12

RV148

1K_0402_1%

12

RV150

1K_0402_1%

FBC_ABI#_L

FBC_CAS#_L

FBC_WE#_L

FBC_RAS#_L

FBC_CS#_L

FBC_WCK1_N FBC_WCK1

FBC_WCK0_N FBC_WCK0

+FBC_VREFD_L

+FBC_VREFC0

FBC_RST#_L

+1.5VS_VGA

1

CV161

2

0.1U_0402_10V7K

UV8

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

1

CV162

2

0.1U_0402_10V7K

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4

FBC_D24

A2

FBC_D25

B4

FBC_D26

B2

FBC_D27

E4

FBC_D28

E2

FBC_D29

F4

FBC_D30

F2

FBC_D31

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBC_D8

U13

FBC_D9

T11

FBC_D10

T13

FBC_D11

N11

FBC_D12

N13

FBC_D13

M11

FBC_D14

M13

FBC_D15

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

BYTE3

GDDR5 Mode H - Mirror Mode Mapping

BYTE1

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N12P-VRAM C Lower

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

30 66

0.2

5

4

3

2

1

Memory Partition C - Upper 32 bits

UV9

MF=0 MF=1 MF=0MF=1

C2

FBC_EDC4

FBC_CLK1

FBC_CLK1#

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA12_RFU_H

1

CV64

2

820P_0402_25V7

1

CV167

2

0.1U_0402_10V7K

FBC_EDC6

FBC_DBI4#

FBC_DBI6#

FBC_CKE_H

FBC_MA2_BA0_H FBC_MA5_BA1_H FBC_MA4_BA2_H FBC_MA3_BA3_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

12

RV163

1K_0402_1%

12

RV165

1K_0402_1%

FBC_ABI#_H

FBC_RAS#_H

FBC_CS#_H

FBC_CAS#_H

FBC_WE#_H

FBC_WCK2_N FBC_WCK2

FBC_WCK3_N FBC_WCK3

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#_H

+1.5VS_VGA

1

CV164

2

0.1U_0402_10V7K

FBC_D[63..32]<27>

D D

FBC_EDC[7..4]<27>

Follow DG

1 2

FBC_CLK1

RV41 40.2_0402_1%RV41 40.2_0402_1%

RV171

FBC_CLK1#

RV171 160_0402_1%

160_0402_1%

@

1 2

RV48 40.2_0402_1%RV48 40.2_0402_1%

1 2

931_0402_1%

1 2

931_0402_1%

13

D

2

G

QV15

S

2N7002W-T/R7_SOT323-3

+1.5VS_VGA

UV9 SIDE

1

2

CV245

2

1

1U_0603_25V6

10U_0603_6.3V6M

CV99

RV218

RV219

0.01U_0402_25V7K

1

CV215

2

1.33K_0402_1%

1

2

1U_0603_25V6

RV175

549_0402_1%

RV176

RV177

549_0402_1%

RV178

1

CV100

2

1U_0603_25V6

+1.5VS_VGA

CV97

C C

B B

MEM_VREF<23,28,29,30>

A A

FBC_DBI4#<27>

FBC_DBI6#<27>

FBC_CLK1<27>

FBC_CLK1#<27>

FBC_CKE_H<27>

FBC_MA2_BA0_H<27> FBC_MA5_BA1_H<27> FBC_MA4_BA2_H<27> FBC_MA3_BA3_H<27>

FBC_MA7_MA8_H<27>

FBC_MA1_MA9_H<27> FBC_MA0_MA10_H<27> FBC_MA6_MA11_H<27>

FBC_MA12_RFU_H<27>

12

RV167

121_0402_1%

FBC_ABI#_H<27>

FBC_RAS#_H<27>

FBC_CS#_H<27>

FBC_CAS#_H<27>

FBC_WE#_H<27>

FBC_WCK2_N<27> FBC_WCK2<27>

FBC_WCK3_N<27> FBC_WCK3<27>

FBC_RST#_H<27>

12

+FBC_VREFC1

12

1

CV63

2

820P_0402_25V7

12

+FBC_VREFD_H

12

1

CV98

2

1U_0603_25V6

0.1U_0402_10V7K

CV165

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14 DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

H5GQ1H24AFR-T2L_BGA170

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

A4

FBC_D32

A2

FBC_D33

B4

FBC_D34

B2

FBC_D35

E4

FBC_D36

E2

FBC_D37

F4

FBC_D38

F2

FBC_D39

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBC_D48

U13

FBC_D49

T11

FBC_D50

T13

FBC_D51

N11

FBC_D52

N13

FBC_D53

M11

FBC_D54

M13

FBC_D55

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

10U_0603_6.3V6M

2

1

BYTE4

BYTE6

UV10 SIDE

CV227

1U_0603_25V6

FBC_DBI7#<27>

FBC_DBI5#<27>

+1.5VS_VGA

12

RV168

121_0402_1%

1

2

1

CV103

2

1U_0603_25V6

1

CV101

CV102

CV104

CV102

2

1U_0603_25V6

FBC_CLK1#

FBC_MA0_MA10_H FBC_MA6_MA11_H

FBC_MA12_RFU_H

1

CV170

2

0.1U_0402_10V7K

FBC_EDC7

FBC_EDC5

FBC_DBI7#

FBC_DBI5#

FBC_CLK1

FBC_CKE_H

FBC_MA4_BA2_H FBC_MA3_BA3_H FBC_MA2_BA0_H FBC_MA5_BA1_H

FBC_MA7_MA8_H FBC_MA1_MA9_H

12

RV164

1K_0402_1%

12

RV166

1K_0402_1%

FBC_ABI#_H

FBC_CAS#_H

FBC_WE#_H

FBC_RAS#_H

FBC_CS#_H

FBC_WCK3_N FBC_WCK3

FBC_WCK2_N FBC_WCK2

+FBC_VREFD_H

+FBC_VREFC1

FBC_RST#_H

+1.5VS_VGA

1

CV168

2

0.1U_0402_10V7K

1

CV169

2

UV10

MF=0 MF=1 MF=0MF=1

C2

EDC0 EDC3

C13

EDC1 EDC2

R13

EDC2 EDC1

R2

EDC3 EDC0

D2

DBI0# DBI3#

D13

DBI1# DBI2#

P13

DBI2# DBI1#

P2

DBI3# DBI0#

J12

CK

J11

CK#

J3

CKE#

H11

BA0/A2 BA2/A4

K10

BA1/A5 BA3/A3

K11

BA2/A4 BA0/A2

H10

BA3/A3 BA1/A5

K4

A8/A7 A10/A0

H5

A9/A1 A11/A6

H4

A10/A0 A8/A7

K5

A11/A6 A9/A1

J5

A12/RFU/NC

A5

VPP/NC

U5

VPP/NC

J1

MF

J10

SEN

J13

ZQ

J4

ABI#

G3

RAS# CAS#

G12

CS# WE#

L3

CAS# RAS#

L12

WE# CS#

D5

WCK01# WCK23#

D4

WCK01 WCK23

P5

WCK23# WCK01#

P4

WCK23 WCK01

A10

VREFD

U10

VREFD

J14

VREFC

J2

RESET#

H1

VSS

K1

VSS

B5

VSS

G5

VSS

L5

VSS

T5

VSS

B10

VSS

D10

VSS

G10

VSS

L10

VSS

P10

VSS

T10

VSS

H14

VSS

K14

VSS

G1

VDD

L1

VDD

G4

VDD

L4

VDD

C5

VDD

R5

VDD

C10

VDD

R10

VDD

D11

VDD

G11

VDD

L11

VDD

P11

VDD

G14

VDD

L14

VDD

170-BALL

SGRAM GDDR5

X76@

DQ24 DQ0 DQ25 DQ1 DQ26 DQ2 DQ27 DQ3 DQ28 DQ4 DQ29 DQ5 DQ30 DQ6 DQ31 DQ7 DQ16 DQ8 DQ17 DQ9

DQ18 DQ10 DQ19 DQ11 DQ20 DQ12 DQ21 DQ13 DQ22 DQ14

DQ23 DQ15 DQ8 DQ16 DQ9 DQ17 DQ10 DQ18 DQ11 DQ19 DQ12 DQ20 DQ13 DQ21 DQ14 DQ22 DQ15 DQ23 DQ0 DQ24 DQ1 DQ25 DQ2 DQ26 DQ3 DQ27 DQ4 DQ28 DQ5 DQ29 DQ6 DQ30 DQ7 DQ31

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

H5GQ1H24AFR-T2L_BGA170

A4

FBC_D56

A2

FBC_D57

B4

FBC_D58

B2

FBC_D59

E4

FBC_D60

E2

FBC_D61

F4

FBC_D62

F2

FBC_D63

A11 A13 B11 B13 E11 E13 F11 F13 U11

FBC_D40

U13

FBC_D41

T11

FBC_D42

T13

FBC_D43

N11

FBC_D44

N13

FBC_D45

M11

FBC_D46

M13

FBC_D47

U4 U2 T4 T2 N4 N2 M4 M2

B1 D1 F1 M1 P1 T1 G2 L2 B3 D3 F3 H3 K3 M3 P3 T3 E5 N5 E10 N10 B12 D12 F12 H12 K12 M12 P12 T12 G13 L13 B14 D14 F14 M14 P14 T14

A1 C1 E1 N1 R1 U1 H2 K2 A3 C3 E3 N3 R3 U3 C4 R4 F5 M5 F10 M10 C11 R11 A12 C12 E12 N12 R12 U12 H13 K13 A14 C14 E14 N14 R14 U14

+1.5VS_VGA

BYTE7

BYTE5

GDDR5 Mode H - Mirror Mode Mapping

Address

FBx_CMD0

FBx_CMD1

FBx_CMD2

FBx_CMD3

FBx_CMD4

FBx_CMD5

FBx_CMD6

FBx_CMD7

FBx_CMD8

FBx_CMD9

FBx_CMD10

FBx_CMD11

FBx_CMD12

FBx_CMD13

FBx_CMD14

FBx_CMD15

FBx_CMD16

FBx_CMD17

FBx_CMD18

FBx_CMD19

FBx_CMD20

FBx_CMD21

FBx_CMD22

FBx_CMD23

FBx_CMD24

FBx_CMD25

FBx_CMD26

FBx_CMD27

FBx_CMD28

FBx_CMD29

FBx_CMD30

FBx_CMD31

0..31

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

DATA Bus

32..63

CS#

A3_BA3

A2_BA0

A4_BA2

A5_BA1

WE#

A7_A8

A6_A11

ABI#

A12_RFU

A0_A10

A1_A9

RAS#

RST#

CKE#

CAS#

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL

THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF LC FU TURE CENTER. AND CONTAINS CONF IDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF LC FUTURE CENT ER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

N12P-VRAM C Upper

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

1

LA-8692P

LA-8692PLA-8692P

31 66

0.2

5

4

3

2

1

SLI

D D

PCIE_CTX_GRX_N15 PCIE_CTX_GRX_P15

PCIE_CTX_GRX_N14 PCIE_CTX_GRX_P14

PCIE_CTX_GRX_N13 PCIE_CTX_GRX_P13

PCIE_CTX_GRX_N12 PCIE_CTX_GRX_P12

PCIE_CTX_GRX_N11 PCIE_CTX_GRX_P11

C C

SLI@

PCIE_CRX_GTX_N15

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

B B

PCIE_CTX_GRX_N[0..15]

PCIE_CTX_GRX_P[0..15]

PCIE_CRX_GTX_N[0..15]

PCIE_CRX_GTX_P[0..15]

PCIE_CRX_GTX_P15

PCIE_CRX_GTX_N14 PCIE_CRX_GTX_P14

PCIE_CRX_GTX_N13 PCIE_CRX_GTX_P13

PCIE_CRX_GTX_N12 PCIE_CRX_GTX_P12

PCIE_CRX_GTX_N11 PCIE_CRX_GTX_P11

PCIE_CRX_GTX_N10 PCIE_CRX_GTX_P10

PCIE_CRX_GTX_N9 PCIE_CRX_GTX_P9

PCIE_CRX_GTX_N8 PCIE_CRX_GTX_P8

12

CV200.22U_0402_10V6K

SLI@

12

CV220.22U_0402_10V6K

SLI@

12

CV160.22U_0402_10V6K

SLI@

12

CV180.22U_0402_10V6K

SLI@

12

CV190.22U_0402_10V6K

SLI@

12

CV140.22U_0402_10V6K

SLI@

12

CV150.22U_0402_10V6K

SLI@

12

CV170.22U_0402_10V6K

SLI@

12

CV120.22U_0402_10V6K

12

CV130.22U_0402_10V6K SLI@ CV130.22U_0402_10V6K SLI@

SLI@

12

CV100.22U_0402_10V6K

12

CV110.22U_0402_10V6K SLI@ CV110.22U_0402_10V6K SLI@

12

CV80.22U_0402_10V6K S LI@ CV80.22U_0402_10V6K SLI@

12

CV90.22U_0402_10V6K

SLI@

12

CV60.22U_0402_10V6K

SLI@

12

CV70.22U_0402_10V6K

PCIE_CTX_GRX_N10 PCIE_CTX_GRX_P10

PCIE_CTX_GRX_N9 PCIE_CTX_GRX_P9

PCIE_CTX_GRX_N8 PCIE_CTX_GRX_P8

PCIE_CRX_C_GTX_N15 PCIE_CRX_C_GTX_P15

PCIE_CRX_C_GTX_N14 PCIE_CRX_C_GTX_P14

PCIE_CRX_C_GTX_N13

PCIE_CRX_C_GTX_P13

PCIE_CRX_C_GTX_N12 PCIE_CRX_C_GTX_P12

PCIE_CRX_C_GTX_N11 PCIE_CRX_C_GTX_P11

PCIE_CRX_C_GTX_N10 PCIE_CRX_C_GTX_P10

PCIE_CRX_C_GTX_N9

PCIE_CRX_C_GTX_P9

PCIE_CRX_C_GTX_N8

PCIE_CRX_C_GTX_P8

JSLI1

1

GND

3

NC

5

NC

7

NC

9

NC

11

NC

13

NC

15

NC

17

GND

19

PEG_RX_N7

21

PEG_RX_P7

23

GND

25

PEG_RX_N6

27

PEG_RX_P6

29

GND

31

GND

33

PEG_RX_N5

35

PEG_RX_P5

37

GND

39

PEG_RX_N4

41

PEG_RX_P4

43

GND

45

PEG_RX_N3

47

PEG_RX_P3

49

GND

51

PEG_RX_N2

53

PEG_RX_P2

55

GND

57

PEG_RX_N1

59

PEG_RX_P1

61

GND

63

PEG_RX_N0

65

PEG_RX_P0

67

GND

69

GND

71

PEG_TX_N7

73

PEG_TX_P7

75

GND

77

PEG_TX_N6

79

PEG_TX_P6

81

GND PEG_TX_N583PWR_GOOD

85

PEG_TX_P5

87

GND

89

PEG_TX_N4

91

PEG_TX_P4

93

GND PEG_TX_N395TH_OVERT#

97

PEG_TX_P3

99

GND

101

PEG_TX_N2

103

PEG_TX_P2

105

GND

107

PEG_TX_N1

109

PEG_TX_P1

111

GND

113

PEG_TX_N0

115

PEG_TX_P0

117

GND

119

GND

121

GND

TE_2199022-1

ME@

GND GND GND

GND +19V +19V +19V +19V +19V +19V +19V +19V

GND

TH_TACH

TH_PWN

PEX_STD_SW#

AC_DC

PWR_EN

CLK_REQ#

RSVD RSVD

RSVD SMB_DAT SMB_CLK

WAKE#

RSVD

GND CLK_PCIE_N CLK_PCIE_P

GND

+5V +5V +5V +5V +5V

NC +3V +3V

NC

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118

120 122

SLI_B+

+5V_SLI

+3VS_SLI

SLI_FAN_SPEED

SLI_FAN_PWM

S_DGPU_PWROK S_DGPU_PWR_EN#

CLK2_REQ_GPU#_R

S_NVDD_PWR_EN

S_DGPU_RST

PLT_RST# GC6_EVENT_SLI#

S_DGPU_PWR_EN

CLK_PCIE_2VGA#

CLK_PCIE_2VGA

1 2

RV158 0_0402_5%GC6@RV 158 0_0402_5%GC6@

S_DGPU_GC6_EN

SLI_B+_ON# <53> SLI_5V_ON# <53>

SUSP# <45,52,56,58,59>

SLI_FAN_SPEED <42,45>

SLI_FAN_PWM <42,45>

VGA_AC_DET <23,45,59>

S_DGPU_PWROK <19>

S_DGPU_PWR_EN# <52>

CLK2_REQ_GPU#_R <15>

S_NVDD_PWR_EN <19>

S_DGPU_RST <15,18>

PCH_THRMTRIP#_R <19,23>

PLT_RST# <18,23,38,39,44,45,6>

EC_SMB_DA2 <15,23,41,45>

EC_SMB_CK2 <15,23,41,45>

S_DGPU_GC6_EN <15>

S_DGPU_PWR_EN <19,52>

CLK_PCIE_2VGA# <15> CLK_PCIE_2VGA <15>

S_Toggle_REQ# <19>

1

CV296

2

0.01U_0402_25V7K

SLAVE_PRESENT# <19>

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

DDRIII-SODIMM SLOT1

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

32 66

0.2

5

@

RV94

RV92

45.3K_0402_ 1%

D D

STRAP0<2 4> STRAP1<2 4> STRAP2<2 4> STRAP3<2 4> STRAP4<2 4>

C C

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

1 2

RV95

@RV9 5

@

45.3K_0402_ 1%

1 2

Change STRAP1 to "0000" for N13P-GT

RV93

4.99K_0402_ 1%

@

1 2

RV96

4.99K_0402_ 1%

1 2

RV94 10K_0402_1 %

10K_0402_1 %

1 2

RV97

RV97 10K_0402_1 %

10K_0402_1 %

1 2

+3VS_VGA

4

1 2

RV121

4.99K_0402_ 1%

SLI@

OPT@

RV124

4.99K_0402_ 1%

+3VS_VGA

1 2

RV100

RV122

RV122 20K_0402_1 %

20K_0402_1 %

@

RV125

45.3K_0402_ 1%

3

Physical Strapping pin

ROM_SCLK

ROM_SI

ROM_SO FB[0]

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

Resistor Values

Power Rail

+3VS_VGA

Pull-up to +3VS_VGA

5K

10K

15K

20K

25K

30K

35K

45K

Logical Strapping Bit3

PCI_DEVID[4]

FB[1]

PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]

SOR3_EXPOSED

RESERVED PCIE_SPEED_

1000

1001

1010

1011

1100

1101

1110

1111

2

3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]

Pull-down to Gnd

0000

0001

0010

0011

0100

0101

0110

0111

Logical Strapping Bit2

SUB_VENDOR

USER[2] USER[1] USER[0]USER[3]

SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

CHANGE_GEN3

1

Logical Strapping Bit1

SLOT_CLK_CFG

RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]

Logical Strapping Bit0

PEX_PLL_EN_TERM

RAM_CFG[0]

VGA_DEVICESMB_ALT_ADDR

3GIO_PAD_CFG_ADR[0]

PCIE_MAX_SPEED DP_PLL_VDD33V

4.99K_0402_1%

SLI@

RV100

RV98

4.99K_0402_ 1%

@

1 2

ROM_SI<24>

ROM_SO<24 >

ROM_SCLK<24>

B B

ROM_SI ROM_SO ROM_SCLK

X76

RV101

RV101 30K_0402_1 %

30K_0402_1 %

X76@

1 2

RV99

RV99 10K_0402_1 %

10K_0402_1 %

1 2

RV102

RV102 30K_0402_1 %

30K_0402_1 %

@

1 2

RV100

24.9K_0402_ 1%

GC6@

1 2

RV103

RV103 15K_0402_1 %

15K_0402_1 %

@

1 2

SLI@

RV100

4.99K_0402_1%

OPT@

3GIO_PADCFG

3GIO_PADCFG[3:0]

0000

Notebook Default

SLOT_CLK_CFG

0

GPU and MCH don't share a common reference clock

1

GPU and MCH share a common reference clock (Default)

SMBUS_ALT_ADDR

0

0x9E (Default)

1

0x9C (Multi-GPU usage)

X76

FB Memory (GDDR5)

N13P-GT1 28nm

Hynix

A A

Samsung

K4G10325FG-HC041G1G

H5GQ2H24AFR-T2C

H5GQ1H24BFR-T2C

5

K4G20325FD-FC04

2G

PD 30K

PD 45K

PD 25K

PD 35K

ROM_SO ROM_SCLKROM_SIGPU STRAP2STRAP1STRAP0

PU 25K

GC6@

PU 10K

PU 45K

PU 5K

OPT@,SLI@

Security Classification

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L

THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIA L AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY LC FUTURE CENTER NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF LC FUTURE CENTER.

PD 5K

Issued Date

PD 10K

STRAP3

PU 5K

PD 5K

2012/07/01

3

SLI@

OPT@

STRAP4

64Mx32

PD 45K

32Mx32

64Mx32

32Mx32

LC Future Center Secret Data

Deciphered Date

SUB_VENDOR

0

No VBIOS ROM

1

BIOS ROM is present (Default)

FB_0_BAR_SIZE

0

Reserved

1

Reserved

2

256MB (Default)

3

Reserved

2014/07/01

2

Title

N13P_MISC

Size Doc ument Number Rev

Custom

Thursday, June 07, 2012

Date: Sheet of

Thursday, June 07, 2012

XCLK_417

0

277MHz (Default)

1

Reserved

VGA_DEVICE

0

3D Device (Class Code 302h)

1

VGA Device (Default)

USER Straps

User[3:0]

1000-1100

Customer defined

PEX_PLL_EN_TERM

0

Disable (Default)

1

Enable

PCIE_MAX_SPEED

0

Limit to PCIE Gen1

1

PCIE Gen 2/3 Capable

LA-8692P

LA-8692PLA-8692P

1

33 66

0.2

5

2A 80mil

1

C523

470P_0603_50V8J

D D

470P_0603_50V8J

9/23 EMI Reques t

INVPWM

C525

@

1

2

470P_0402_50V7K

2

DISPOFF#

@

1

C527

2

1

C524

4.7U_0805_25V6-K

2

1 2

R_short 0_0805_5%

R813

B++LEDVDD

For EMI

+LCDVDD_CONN

C C

2N7002DW-T/R7_SOT363-6

VGA_ENVDD<23>

PCH_ENVDD<17>

B B

Q67A

R816

R816 150_0603_1%

150_0603_1%

61

1 2

R1195

0_0402_5%

PCH

2

SLI@

R189

0_0402_5%

1 2

OPT@R1195

OPT@

100K_0402_5%

R821

100K_0402_5%

LVDS_ACLK#<17> LVDS_ACLK<17>

LVDS_BCLK#<17> LVDS_BCLK<17>

+5VALW

R1467

@

LCD_ENVDD#

12

LVDS_A0#<17> LVDS_A0<17> LVDS_A1#<17> LVDS_A1<17> LVDS_A2#<17> LVDS_A2<17>

LVDS_B0#<17> LVDS_B0<17> LVDS_B1#<17> LVDS_B1<17> LVDS_B2#<17> LVDS_B2<17>

+3VS

12

R817

R817 100K_0402_5%

100K_0402_5%

R820

1 2

100K_0402_5%

1

C1050

3

5

Q67B

Q67B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

LVDS_ACLK# LVDS_ACLK LVDS_ACLK_CONN

LVDS_A0#

LVDS_A0

LVDS_A1#

LVDS_A1

LVDS_A2#

LVDS_A2

LVDS_BCLK# LVDS_BCLK

LVDS_B0#

LVDS_B0

LVDS_B1#

LVDS_B1

LVDS_B2#

LVDS_B2

C1050

C1046

@

2

0.1U_0402_16V4Z

OPT@

1 2

R1255 0_0402_5%

OPT@

1 2

R1257 0_0402_5%

1 2

R1259 0_0402_5%OPT@ R1259 0_0402_5%OPT@

OPT@

1 2

R1261 0_0402_5%

1 2

R1262 0_0402_5%OPT@ R1262 0_0402_5%OPT@

OPT@

1 2

R1265 0_0402_5%

OPT@

1 2

R1267 0_0402_5%

OPT@

1 2

R1269 0_0402_5%

1 2

R1279 0_0402_5%

1 2

R1278 0_0402_5%

1 2

R1277 0_0402_5%OPT@R1277 0_0402_5%OPT@

1 2

R1281 0_0402_5%OPT@R1281 0_0402_5%OPT@

1 2

R1280 0_0402_5%OPT@R1280 0_0402_5%OPT@

1 2

R1282 0_0402_5%OPT@R1282 0_0402_5%OPT@

1 2

R1283 0_0402_5%OPT@R1283 0_0402_5%OPT@

1 2

R1284 0_0402_5%OPT@R1284 0_0402_5%OPT@

+3VS

1

C530

0.1U_0402_16V4Z

2

G

2

1 3

1

2

0.01U_0402_16V7K

OPT@

OPT@ OPT@

OPT@

4

S

D

AO3413_SOT23-3

AO3413_SOT23-3 Q68

Q68

W=60mils

+LCDVDD_CONN

C531

4.7U_0603_6.3V6K

C531

4.7U_0603_6.3V6K

W=60mils

1

2

LVDS_ACLK#_CONN

LVDS_BCLK#_CONN LVDS_BCLK_CONN

LVDS_B0#_CONN

LVDS_B1#_CONN

LVDS_B2#_CONN

1

C532

0.1U_0402_16V4Z

2

LVDS_A0#_CONN

LVDS_A0_CONN

LVDS_A1#_CONN

LVDS_A1_CONN

LVDS_A2#_CONN

LVDS_A2_CONN

LVDS_B0_CONN

LVDS_B1_CONN

LVDS_B2_CONN

3

LVDS_BCLK#_CONN

OPT@

1 2

R1212 0_0402_5%

PCH_ENBKL<17>

VGA_ENBKL<23>

R1212 0_0402_5%

SLI@

R1600

12

0_0402_5%

100K_0402_1%

EDID_CLK<17>

EDID_DATA<17>

VGA_EDID_CLK<23>

VGA_EDID_DATA<23>

R827

1 2

EDID_CLK

EDID_DATA

VGA_EDID_DATA

ENBKL <45>

1 2

R1210 0_0402_5%

OPT@

1 2

R1211 0_0402_5%

OPT@

1 2

R1199 0_0402_5%

SLI@

1 2

R1200 0_0402_5%

SLI@

EDID_CLK_CONNVGA_EDID_CLK

EDID_DATA_CONN

LVDS_ACLK#_CONN

LVDS_ACLK_CONN

LVDS_A1_CONN

LVDS_A1#_CONN

LVDS_A2_CONN

LVDS_A2#_CONN

LVDS_A0_CONN

LVDS_A0#_CONN

LVDS_B0_CONN LVDS_B0#_CONN LVDS_B1#_CONN

LVDS_B1_CONN

LVDS_B2_CONN

LVDS_B2#_CONN

LVDS_BCLK_CONN

2

EDID_CLK_CONN EDID_DATA_CONN

INVPWM LVDS_ACLK#_CONN LVDS_ACLK_CONN

LVDS_A1_CONN

LVDS_A1#_CONN

LVDS_A2_CONN

LVDS_A2#_CONN

LVDS_A0_CONN

LVDS_A0#_CONN

LVDS_B0_CONN LVDS_B0#_CONN LVDS_B1#_CONN

LVDS_B1_CONN

LVDS_B2_CONN LVDS_B2#_CONN

LVDS_BCLK_CONN

LVDS_BCLK#_CONN

BKOFF#<45>

JLVDS1

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

39 GND141GND2

ACES_87142-4041-BS

ME@

R_short 0_0402_5%

INVPWM

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

R891

1 2

W=60mils

+3VS

12

@

R822

4.7K_0402_5%

R1515

R_short 0_0402_5%

@

1

ECR_EN <45>

DISPOFF#

DISPOFF#BKOFF#

12

R824

0_0402_5%

12

R847

0_0402_5%

+LCDVDD_CONN

(60 MIL)

+LEDVDD

+3VS

1

C528

@

2

680P_0402_50V7K

EC_INVT_PWM <45>

VGA_BL_PWM <23>

PCH_PWM <17>

VGA_TXOUT0+<24>

VGA_TXOUT0-<24>

VGA_TXOUT1+<24>

VGA_TXOUT1-<24>

VGA_TXOUT2+<24>

A A

VGA

5

VGA_TXOUT2-<24>

VGA_TXCLK+<24>

VGA_TXCLK-<24>

VGA_TZOUT0+<24>

VGA_TZOUT0-<24>

VGA_TZOUT1+<24>

VGA_TZOUT1-<24>

VGA_TZOUT2+<24>

VGA_TZOUT2-<24>

VGA_TZCLK+<24>

VGA_TZCLK-<24>

VGA_TXOUT0+ VGA_TXOUT0-

VGA_TXOUT1+ VGA_TXOUT1-

VGA_TXOUT2+ VGA_TXOUT2-

VGA_TXCLK+ VGA_TXCLK-

VGA_TZOUT0+ VGA_TZOUT0-

VGA_TZOUT1+ VGA_TZOUT1-

VGA_TZOUT2+ VGA_TZOUT2-

VGA_TZCLK+ VGA_TZCLK-

1 2

R1296 0_0402_5%SLI@R1296 0_0402_5%SLI@

1 2

R1292 0_0402_5%SLI@R1292 0_0402_5%SLI@

1 2

R1299 0_0402_5%SLI@R1299 0_0402_5%SLI@

1 2

R1298 0_0402_5%SLI@R1298 0_0402_5%SLI@

1 2

R1301 0_0402_5%SLI@R1301 0_0402_5%SLI@

1 2

R1300 0_0402_5%SLI@R1300 0_0402_5%SLI@

SLI@

1 2

R1295 0_0402_5%

SLI@

1 2

R1293 0_0402_5%

SLI@

1 2

R1303 0_0402_5%

SLI@

1 2

R1304 0_0402_5%

SLI@

1 2

R1305 0_0402_5%

SLI@

1 2

R1310 0_0402_5%

SLI@

1 2

R1309 0_0402_5%

SLI@

1 2

R1307 0_0402_5%

SLI@

1 2

R1306 0_0402_5%

SLI@

1 2

R1308 0_0402_5%

LVDS_A0_CONN

LVDS_A0#_CONN

LVDS_A1_CONN

LVDS_A1#_CONN

LVDS_A2_CONN

LVDS_A2#_CONN

LVDS_ACLK_CONN LVDS_ACLK#_CONN

LVDS_B0_CONN LVDS_B0#_CONN

LVDS_B1_CONN LVDS_B1#_CONN

LVDS_B2_CONN LVDS_B2#_CONN

LVDS_BCLK_CONN

LVDS_BCLK#_CONN

4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

LVDS

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

34 66

0.2

5

D D

4

3

2

1

C C

B B

No use NVSR chip for DVT

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

NO NVSR

Size Document Number Rev

C

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

35 66

0.2

A

VGA_CRT _R<23 >

1 1

2 2

3 3

VGA_CRT _G<23>

VGA_CRT _B< 23>

DAC_RED<17>

DAC_GRN<17>

DAC_BLU<17>

VGA_CRT _R

VGA_CRT _G

VGA_CRT _B

DAC_RED

DAC_GRN

DAC_BLU

CRT_HSYNC<17 >

VGA_CRT _HSYNC< 23>

CRT_VSYNC<17>

VGA_CRT _VSYNC<23>

1 2

R1276 0_0 402_5%

SLI@

1 2

R1273 0_0 402_5%

SLI@

1 2

R1275 0_0 402_5%

SLI@

1 2

R1274 0_0 402_5%

OPT@

1 2

R1181 0_0 402_5%

OPT@

1 2

R1182 0_0 402_5%

OPT@

CRT_HSYNC HSYNC_G

VGA_CRT _HSYNC

CRT_VSYNC

VGA_CRT _VSYNC VSYNC_G

1 2

R1183 0_0 402_5%

R1184 0_0 402_5%

1 2

R1185 0_0 402_5%

OPT@

1 2

R1186 0_0 402_5%

SLI@

OPT@

1 2

SLI@

B

+5VS + 5VS +5VS

3

1

2

@

D31

D31 BAT54S-7 -F_SOT23-3

BAT54S-7 -F_SOT23-3

DAC_RED _1

DAC_GRN _1

12

R830

R830 150_040 2_1%

150_040 2_1%

CLOSE TO CONN

0.1U_040 2_16V4Z

12

R831

R831 150_040 2_1%

150_040 2_1%

+3VS

C544

C546

DAC_BLU _1

12

R832

R832 150_040 2_1%

150_040 2_1%

1

2

1

2

10P_040 2_50V8J

+CRT_VC C

R833

1 2

1K_0402 _5%

OE#

1

5

P

OE#

A2Y

G

U24

U24 SN74AHC T1G125DCKR_S C70-5

SN74AHC T1G125DCKR_S C70-5

3

+CRT_VC C

OE#

1

5

P

OE#

A2Y

G

U25

U25 SN74AHC T1G125DCKR_S C70-5

SN74AHC T1G125DCKR_S C70-5

3

+CRT_VC C

3

2

1

C537

2

4

CRT_HSYNC _1

4

CRT_VSYNC _1

C

3

1

@

D32

D32 BAT54S-7 -F_SOT23-3

BAT54S-7 -F_SOT23-3

1 2

L16 N BQ100505T-800 Y_0402L16 N BQ100505T-800 Y_0402

1 2

L17 N BQ100505T-800 Y_0402L17 N BQ100505T-800 Y_0402

1 2

L18 N BQ100505T-800 Y_0402L18 N BQ100505T-800 Y_0402

1

C538

C539

C539 10P_040 2_50V8J

10P_040 2_50V8J

2

10P_040 2_50V8J

R840

1 2

33_0603 _5%

R839

1 2

33_0603 _5%

2

10P_040 2_50V8J

CRT_HSYNC _2

CRT_VSYNC _2

1

BAT54S-7 -F_SOT23-3

@

D33

1

C540

2

NBQ1005 05T-800Y_0402

1 2

NBQ1005 05T-800Y_0402

1 2

REDGREE NBLUE

1

C541

C542

10P_040 2_50V8J

2

10P_040 2_50V8J

L19

L20

D

+5VS

T75 PADT75 PAD

1

@

C545

C545 10P_040 2_50V8J

10P_040 2_50V8J

2

1

C547

@C 547

@

10P_040 2_50V8J

2

+CRT_VC C

D36

2 1

RB491D_ SC59-3

RED

CRT_DDC _DAT_CONN GREEN

JVGA_HS BLUE

JVGA_VS

CRT_DDC _CLK_CONN

JVGA_HS

JVGA_VS

CRT Connector

F1

21

0.5A_8V_ KMC3S050RY

W=40mils

CRT_TES T

1

C543

100P_04 02_50V8J

2

JVGA_VS

CRT_DDC _CLK_CONN

1

2

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

D8

3

2

1

AZC099-0 4S.R7G_SOT23-6

E

+CRT_VC C_CONN

C536

0.1U_040 2_16V4Z

JCRT1

16

G

17

G

SUYIN_070546 HR015M22BZR

ME@

@

I/O2

GND

I/O1

I/O4

VDD

I/O3

6

5

4

JVGA_HS

+5VS

CRT_DDC _DAT_CONN

12

C548

@

12

R838

2.2K_040 2_5%

CRT_DDC _DAT_CONN

CRT_DDC _CLK_CONN

1

@

C549

C549 68P_040 2_50V8K

68P_040 2_50V8K

2

2012/07/ 01

C

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

D

Title

CRT Connector

Size Do cument Number Rev

Custom

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

E

36 66

0.2

G

5

R837

2.2K_040 2_5%

CRT_DDC _DATA<17 >

CRT_DDC _CLK<17>

VGA_CRT _DATA< 23>

VGA_CRT _CLK<23>

4 4

CRT_DDC _DATA

CRT_DDC _CLK

VGA_CRT _DATA

VGA_CRT _CLK

A

1 2

R1189 0_0402_5 %

OPT@

1 2

R1190 0_0402_5 %

OPT@

1 2

R1191 0_0402_5 %

SLI@

1 2

R1192 0_0402_5 %

SLI@

CRT_DDC _DATA_R

CRT_DDC _CLK_R

B

G

2

S

Q73A

2N7002K DWH_SOT36 3-6

2.2K_040 2_5%

34

D

S

Q73B

2N7002K DWH_SOT36 3-6

61

D

100P_04 02_50V8J

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

L23

HDMI_CLK+ _CK

HDMI_CLK-_ CK HDMI_CLK -_CONN

D D

C C

B B

HDMI_TX0+ _CK

HDMI_TX0-_ CK

HDMI_TX1+ _CK

HDMI_TX1-_ CK

HDMI_TX2+ _CK

HDMI_TX2-_ CK

HDMI_CLK+ _CONN

HDMI_CLK-_ CONN

HDMI_TX0+ _CONN

HDMI_TX0-_ CONN

HDMI_TX1+ _CONN

HDMI_TX1-_ CONN

HDMI_TX2+ _CONN

HDMI_TX2-_ CONN

R327

680_040 2_1%

OPT@

R324

680_040 2_1%

OPT@

R321

4

1

WCM-2 012-900T_4P

L24

1

4

WCM-2 012-900T_4P

L26

4

1

WCM-2 012-900T_4P

L27

1

4

WCM-2 012-900T_4P

+3VS

R326

680_040 2_1%

OPT@

R323

680_040 2_1%

OPT@

R320

3

2

3

2

3

SLI@

1 2

SLI@

1 2

R321 49 9_0402_1%

SLI@

1 2

R322 4 99_0402_1%

SLI@

1 2

R323 4 99_0402_1%

SLI@

1 2

R324 49 9_0402_1%

SLI@

1 2

R325 499_0402_1%

SLI@

1 2

R326 4 99_0402_1%

SLI@

1 2

R327 4 99_0402_1%

1 2

R328 100K_ 0402_5%

HDMI_CLK+ _CONN

HDMI_TX0+ _CONN

HDMI_TX0-_ CONN

HDMI_TX1+ _CONN

HDMI_TX1-_ CONN

HDMI_TX2+ _CONN

HDMI_TX2-_ CONN

R320

499_040 2_1%

@

1 2

C1016 3.3P_0 402_50V8C

@

1 2

C1015 3.3P_0 402_50V8C

@

1 2

C1018 3.3P_0 402_50V8C

@

1 2

C1017 3.3P_0 402_50V8C

@

1 2

C1020 3.3P_0 402_50V8C

@

1 2

C1019 3.3P_0 402_50V8C

@

1 2

C1022 3.3P_0 402_50V8C

@

1 2

C1021 3.3P_0 402_50V8C

@

13

D

2

G

2N7002H 1N_SOT23-3

S

46@

HDMI+HDCP

Q114

HDMI@

4

for NVSR

HDMIDAT_R HDMICLK_R

TMDS_B_ HPD<17>

HDMI_HPD<18>

3

2

3

D57

D57 PJSOT24 C 3P C/A SOT-23

PJSOT24 C 3P C/A SOT-23

@

1

+3VS

R862

1M_0402 _5%

OPT@

1 2

R1486

0_0402_ 5%

1 2

R1587

0_0402_ 5%

GC6@

DGPU_HD MI_HPD<23>

VGA_HDM I_CLK-<24>

VGA_HDM I_CLK+<24 > VGA_HDM I_TX0-< 24>

VGA_HDM I_TX0+<24> VGA_HDM I_TX1-< 24>

VGA_HDM I_TX1+<24> VGA_HDM I_TX2-< 24>

VGA_HDM I_TX2+<24>

TMDS_B_ CLK#_PCH<17 > TMDS_B_ CLK_PCH<17> TMDS_B_ DATA0#_PCH<17> TMDS_B_ DATA0_PCH<1 7> TMDS_B_ DATA1#_PCH<17> TMDS_B_ DATA1_PCH<1 7> TMDS_B_ DATA2#_PCH<17>

TMDS_B_ DATA2_PCH<1 7>

R1598

R1598 0_0402_ 5%

0_0402_ 5%

SLI@

1 2

R859

12

1K_0402 _5%

@

R864

100K_0402_5%

VGA_HDM I_CLK- HDMI_CLK-_ CK

VGA_HDM I_CLK+ HDMI_CLK+ _CK VGA_HDM I_TX0-

VGA_HDM I_TX0+ VGA_HDM I_TX1-

VGA_HDM I_TX1+ VGA_HDM I_TX2-

VGA_HDM I_TX2+

TMDS_B_ CLK#_PCH TMDS_B_ CLK_PCH TMDS_B_ DATA0#_PCH TMDS_B_ DATA0_PCH TMDS_B_ DATA1#_PCH TMDS_B_ DATA1_PCH TMDS_B_ DATA2#_PCH TMDS_B_ DATA2_PCH

G

1 2

S

for NV recommend

12

@

VGA_HDM I_CLK<24>

HDMICLK<17>

VGA_HDM I_DATA<24>

HDMIDAT<1 7>

2

Q85

13

D

2N7002_ SOT23

HDMI_DET_ R HDMI_DET

CV254 0.1 U_0402_10V6KSLI@ CV25 4 0.1U_0 402_10V6KSLI@

CV253 0.1 U_0402_10V6KSLI@ CV25 3 0.1U_0 402_10V6KSLI@ CV256 0.1 U_0402_10V6KSLI@ CV25 6 0.1U_0 402_10V6KSLI@

CV255 0.1 U_0402_10V6KSLI@ CV25 5 0.1U_0 402_10V6KSLI@ CV258 0.1 U_0402_10V6KSLI@ CV25 8 0.1U_0 402_10V6KSLI@

CV257 0.1 U_0402_10V6KSLI@ CV25 7 0.1U_0 402_10V6KSLI@ CV260 0.1 U_0402_10V6KSLI@ CV26 0 0.1U_0 402_10V6KSLI@

CV259 0.1 U_0402_10V6KSLI@ CV25 9 0.1U_0 402_10V6KSLI@

R885

R885 20K_040 2_5%

20K_040 2_5%

1 2

L67

BLM18PG 181SN1D_0603

@

1 2

1 2 1 2

1 2

C208 0 .1U_0402_10V6 KOPT@ C20 8 0.1 U_0402_10V6KOPT@

1 2

C207 0 .1U_0402_10V6 KOPT@ C20 7 0.1 U_0402_10V6KOPT@

1 2

C204 0 .1U_0402_10V6 KOPT@ C20 4 0.1 U_0402_10V6KOPT@

1 2

C205 0 .1U_0402_10V6 KOPT@ C20 5 0.1 U_0402_10V6KOPT@

1 2

C203 0 .1U_0402_10V6 KOPT@ C20 3 0.1 U_0402_10V6KOPT@

1 2

C206 0 .1U_0402_10V6 KOPT@ C20 6 0.1 U_0402_10V6KOPT@

1 2

C200 0 .1U_0402_10V6 KOPT@ C20 0 0.1 U_0402_10V6KOPT@

1 2

C201 0 .1U_0402_10V6 KOPT@ C20 1 0.1 U_0402_10V6KOPT@

12

VGA_HDM I_CLK

HDMICLK

VGA_HDM I_DATA

HDMIDAT

1

C59

C59 220P_04 02_25V8J@

220P_04 02_25V8J@

2

HDMI_TX0-_ CK

HDMI_TX0+ _CK HDMI_TX1-_ CK

HDMI_TX1+ _CK HDMI_TX2-_ CK

HDMI_TX2+ _CK

2

R1473 0_0 402_5%OPT@R1 473 0_04 02_5%OPT@

+5VS

R866 0_040 2_5%@R866 0_0402 _5%@

R865 0_040 2_5%@R865 0_0402 _5%@ R868 0_040 2_5%@R868 0_0402 _5%@

R867 0_040 2_5%@R867 0_0402 _5%@ R870 0_040 2_5%@R870 0_0402 _5%@

R869 0_040 2_5%@R869 0_0402 _5%@ R872 0_040 2_5%@R872 0_0402 _5%@

R871 0_040 2_5%@R871 0_0402 _5%@

1 2

R1470 0_0 402_5%SLI@R1470 0_0 402_5%SLI@

1 2

R1471 0_0 402_5%OPT@R1 471 0_04 02_5%OPT@

1 2

R1472 0_0 402_5%SLI@R1472 0_0 402_5%SLI@

1 2

2

3

@

1

D38

D38 BAT54S-7 -F_SOT23-3

BAT54S-7 -F_SOT23-3

1 2

1 2 1 2

1 2

HDMI_CLK-_ CK HDMI_CLK+ _CK HDMI_TX0-_ CK HDMI_TX0+ _CK

HDMI_TX1-_ CK HDMI_TX1+ _CK HDMI_TX2-_ CK HDMI_TX2+ _CK

+3VS

R1468

0_0402_ 5%

OPT@

1 2

2

3 1

SGD

BSH111_ SOT23-3

HDMI@

PMEG2010AEH IF=0.1A, 0.29V IF=1A, 0.43V

R860

2.2K_040 2_5%

HDMI@

1 2

HDMIDAT_R

HDMICLK_R

HDMI_CLK-_ CONN

HDMI_CLK+ _CONN HDMI_TX0-_ CONN

HDMI_TX0+ _CONN HDMI_TX1-_ CONN

HDMI_TX1+ _CONN HDMI_TX2-_ CONN

HDMI_TX2+ _CONN

+3VS_VG A

R1469

R1469 0_0402_ 5%

0_0402_ 5%

SLI@

1 2

BSH111_ SOT23-3

2

3 1

SGD

Q80

+5VS

R861

2.2K_040 2_5%

HDMI@

1 2

1

Q152

HDMI@

HDMICLK_R

HDMIDAT_R

21

HDMI@

D37

D37 PMEG201 0AEH_SOD123

PMEG201 0AEH_SOD123

21

HDMI@

F2

0.5A_8V_ KMC3S050RY

+5VS_HD MI

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

TAITW_ PDVBR0-19FLBS 4NN4N0

ME@

C561

1

0.1U_040 2_16V4Z

HDMI@

2

GND GND GND GND

20 21 22 23

680_040 2_1%

5

680_040 2_1%

OPT@

R322

680_040 2_1%

OPT@

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/ 01

3

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

2

Title

HDMI CONN

Size Do cument Number Rev

Custom

Date: Sheet

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

of

37 66

0.2

680_040 2_1%

OPT@

R325

A A

R325

680_040 2_1%

OPT@

A

B

C

D

E

Mini-Express Card for WLAN/WiMAX(Half) Mini-Express Card for SSD(Full)

9/18 JP1 Pin2,24,52 contact t o +3VS_WLAN for AOAC function

+3VS_WLAN

1 1

COMBT@

BT_CTRL

For isolate Intel Rainbow Peak and Compal debug card.

1 2

R897 0_0402_5%

1 2

R1556

1K_0402_5%

COMBT@

BT_DISABLE#

LAN_WAKE#<39,45>

PCIE_WAKE#<16,19, 39>

WLAN_CLKREQ1#<15>

WLAN&BT Combo m odule circuits

BT on module Enable

BT_CRTL

2 2

PCH_BT_ON#

PCH_BT_DISABLE#<19>

H

L

PCH_BT_ON#<19,47> SUSP <10,52,56,58>

BT on module Disable

R1557

0_0402_5%

1 2

COMBT@

AOAC@

L

H

BT_CTRL

61

D

2

G

Q157A

S

2N7002KDWH_SOT363-6

Mini-Express Card(WLAN/WiMAX)

CLK_PCIE_WLAN1#<15>

CLK_PCIE_WLAN1<15>

PCIE_PRX_DTX_N2<15> PCIE_PRX_DTX_P2<15>

PCIE_PTX_C_DRX_N2<15> PCIE_PTX_C_DRX_P2<15>

EC_TX<45> EC_RX<45>

34

D

5

G

Q157B

S

AOAC@

Q157 is AOAC+COMBT need to stuff only AOAC or only COMBT is un-stuff

2N7002KDWH_SOT363-6

R1620

@R1620

@

1 2

0_0402_5%

PCI_RST#_R CLK_PCI_DB

100_0402_1%

R887

1 2 1 2

R888

100_0402_1%

0_0402_5%

+3VS_WLAN

PCIE_WAKE#

BT_CTRL_R

WLAN_CLKREQ1#

EC_TX EC_RX BT_DISABLE#

For EC to detect debug card insert.

R889

R889 100K_0402_5%

100K_0402_5%

1 2

JWLN1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

LED_WWAN#

43

NC

LED_WLAN#

45

NC

LED_WPAN#

47

NC

49

NC

51

NC

53

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

ME@

PERST#

+3.3Vaux

+1.5V

SMB_CLK

SMB_DATA

USB_D-

USB_D+

+1.5V

+3.3V

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22 24 26

GND

28 30

SMB_CLK_S3_R

32

SMB_DATA_S3_R

34

GND

36 38 40

GND

42 44 46 48 50

GND

52

54

GND

+1.5VS

12

1

@

2

+1.5VS_WLAN

LPC_FRAME#_R

LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R

WL_OFF#

R881 0_0402_5%@R881 0_0402_5%@ R882 R_short 0_0402_5%R882 R_short 0_0402_5%

R883 0_0402_5%@R883 0_0402_5%@ R884 0_0402_5%@R884 0_0402_5%@

C1071

0.047U_0402_16V4Z

1 2 1 2

For RF request

R1518

R1518 0_0603_5%

0_0603_5%

USB20_N10 <18> USB20_P10 <18>

R1541 0_0402_5%@R1541 0_0402_5%@ R880 0_0402_5%R880 0_0402_5%

12

1 2

PLT_RST#

SMB_CLK_S3 <12,13,15,46> SMB_DATA_S3 <12,13,15,46>

+3VALW +3VS_WLAN

+1.5VS

1

C564

0.1U_0402_16V4Z

2

will check on EVT PCB

EC_WL_OFF#_R <45>

PCH_WL_OFF# <18>

PLT_RST# <18,23,32,38,39,44,45,6>

AOAC_ON#<52>

softstart (RC) will check on EVT PCB

Reserve for SW mini-pcie debug card. Series resistors closed to KBC side.

LPC_FRAME#_R LPC_AD3_R LPC_AD2_R LPC_AD1_R LPC_AD0_R PCI_RST#_R CLK_PCI_DB

1

C565

0.1U_0402_16V4Z

2

+3VS

+3VALW

C526

0.1U_0402_16V4Z AOAC@

R436

1 2

100K_0402_5%

AOAC@

R873 0_0402_5%@R873 0_0402_5%@ R874 0_0402_5%@R874 0_0402_5%@ R875 0_0402_5%@R875 0_0402_5%@ R876 0_0402_5%@R876 0_0402_5%@ R878 0_0402_5%@R878 0_0402_5%@ R879 0_0402_5%@R879 0_0402_5%@

J8

JUMP_43X79

Q104 AO3413_SOT23-3

AOAC@

S

1

2

1

@

C1055

0.1U_0402_16V4Z

2

1 2 1 2 1 2 1 2 1 2 1 2

112

G

2

D

C1048

@

2

13

9/18 Increase for Intel AOAC f unction

+3VS_WLAN

1

2

0.01U_0402_25V7K

2

AOAC@

LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 PLT_RST#

AOAC@

C533

0.1U_0402_16V4Z

LPC_FRAME# <14,45> LPC_AD3 <14,45> LPC_AD2 <14,45> LPC_AD1 <14,45> LPC_AD0 <14,45>

CLK_PCI_DB <18>

3 3

0.1U_0402_16V4Z

1

C566

2

0.01U_0402_25V7K

SATA_DTX_C_IRX_P0<14> SATA_DTX_C_IRX_N0<14>

4 4

For SSD use:

A

SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0

SATA_ITX_DRX_N0<14> SATA_ITX_DRX_P0<14>

SATA_DET#<14>

1

2

C567

SATA_DET#

+3VS_SSD

1

C568

2

10U_0805_10V4Z

0.01U_0402_16V7K

SATA_ITX_DRX_N0 SATA_ITX_DRX_P0

1 2

R896 0_0402_5%

@

12

C572

12

C573

+3VS_SSD

10U_0805_10V4Z

1

@

C569

2

SATA_DTX_IRX_N0SATA_DTX_C_IRX_N0

Mini-Express Card(SSD)

JSSD1

1

WAKE#

3

NC

5

NC

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

ME@

B

SSD Active:4.5W(1.5A)

+3VS

J5

2

112

JUMP_43X79

@

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22

PERST#

24

+3.3Vaux

26

GND

28

+1.5V

30

SMB_CLK

32

SMB_DATA

34

GND

36

USB_D-

38

USB_D+

40

GND

42

LED_WWAN#

44

LED_WLAN#

46

LED_WPAN#

48

+1.5V

50

GND

52

+3.3V

54

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

+3VS_SSD

Mini-Express Card(TV)

JTV1

1

WAKE#

3

NC

5

NC

CLKREQ_TV#<15>

C

CLK_PCIE_TV#<15> CLK_PCIE_TV<15>

PCIE_PRX_DTX_N3<15> PCIE_PRX_DTX_P3<15>

PCIE_PTX_C_DRX_N3<15>

PCIE_PTX_C_DRX_P3<15>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

CLK_PCIE_TV#

CLK_PCIE_TV

PCIE_PTX_C_DRX_N3

PCIE_PTX_C_DRX_P3

+3VS_TV

2012/07/01

CLKREQ_TV#

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

NC

19

NC

21

GND

23

PERn0

25

PERp0

27

GND

29

GND

31

PETn0

33

PETp0

35

GND

37

NC

39

NC

41

NC

43

NC

45

NC

47

NC

49

NC

51

NC

53

GND

ME@

LC Future Center Secret Data

Deciphered Date

D

2

3.3V

4

GND

6

1.5V

8

NC

10

NC

12

NC

14

NC

16

NC

18

GND

20

NC

22

PERST#

24

+3.3Vaux

26

GND

28

+1.5V

30

SMB_CLK

32

SMB_DATA

34

GND

36

USB_D-

38

USB_D+

40

GND

42

LED_WWAN#

44

LED_WLAN#

46

LED_WPAN#

48

+1.5V

50

GND

52

+3.3V

54

GND

TAITW_PFPET0-AFGLBG1ZZ4N0

2014/07/01

+3VS_TV

+1.5VS_TV

PLT_RST#

USB20_N12 <18> USB20_P12 <18>

Size Document Number Rev

Date: Sheet of

Title

Mini-Card

C

Tuesday, June 05, 2012

PLT_RST# <18,23,32,38,39,44,45,6>

+3VS_TV +3VS

4.7U_0603_6.3V6K

+1.5VS_TV

4.7U_0603_6.3V6K

LA-8692P

LA-8692PLA-8692P

E

1

C902

TV@

2

1

C901

TV@

2

R1204

1 2

R_short 0_0805_5%

R1206

1 2

R_short 0_0603_5%

38 66

+1.5VS

0.2

5

Atheros request can't disable LAN power

Layout Notice : Place as close chip as possible.

D D

1 2 1 2

1

2

0.1U_0402_16V4Z

@

1 2

@

Near Pin31

LAN_PWR_ON#

1

C958

2

0.1U_0402_16V4Z

LAN_PWR_ON#<45>

Vendor recommand reseve the PU resistor close LAN chip

1 2

R345 4.7K_0402_5%

+3V_LAN

PLT_RST#<18,23,32,38,44,45,6>

C C

B B

A A

PCIE_PRX_DTX_N1<15>

PCIE_PRX_DTX_P1<15>

PCIE_PTX_C_DRX_N1<15>

PCIE_PTX_C_DRX_P1<15>

CLK_PCIE_LAN#<15 >

CLK_PCIE_LAN<15>

PCIE_WAKE#<16,19,38> LAN_WAKE#<38,45>

CLKREQ_LAN#<15>

R345 4.7K_0402_5%

Place Close to Chip

C946 0.1U_0402_16V7KC946 0.1U_040 2_16V7K

C947 0.1U_0402_16V7KC947 0.1U_040 2_16V7K

R1369 0_0 402_5%

R1369 0_0 402_5% R1370

R1370

R_short 0_0402_5%

1

C957

C956

2

0.1U_0402_16V4Z

Near

Pin13

Pin19

5

+3VALW +3V_LAN

C552

0.1U_0402_16V4Z

R59

12

100K_0402_5%

PLT_RST#

PCIE_PRX_C_DTX_N1

PCIE_PRX_C_DTX_P1

PLT_RST#

PCIE_WAKE#_R

LAN_XTALO LAN_XTALI

+1.1_AVDDL +1.1_AVDDL +1.1_AVDDL +1.1_AVDDL_L +1.1_AVDDL

1

C960

C959

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near Pin6

Change C968, C969 value of Cap from 33pF to 15pF for TXC recommend

J10

112

JUMP_43X79

Q70

S

1

G

2

@

29

30

36

35

32 33

2

3

25 26

28 27

7 8

4

13 19 31 34

6

41

15P_0402_50V8J

U63

8161@

4

2

@

D

13

1

LP2301ALT1G_SOT-23

C1047

0.01U_0402_25V7K

2

1

C1056

0.1U_0402_16V4Z

2

TX_N

Atheros

TX_P

AR8151/AR8161

RX_N

RX_P

REFCLK_N REFCLK_P

PERST#

WAKE#

SMCLK SMDATA

NC TESTMODE

XTLO XTLI

CLKREQ#

AVDDL AVDDL AVDDL AVDDL AVDDL_REG/AVDDL

GND

AR8161-BL3A-R_QFN40_5X5

U63

SA00003LE2J

25MHZ_12PF_X3G025000DC1H~D

1

C968

2

4

VDDCT/ISOLAN

DVDDL/PPS

DVDDL_REG/DVDD L

AVDDH/AVDD33

AVDDH_REG

8151@

Y6

4

NC

OSC

1

OSC

NC

LED_0 LED_1 LED_2

TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3

RBIAS

VDD33

AVDDH

3

2

LX

38

ACTIVITY#

39

LAN_LINK#

23

LAN_CLK_SEL

12

MDI0-

11

MDI0+

15

MDI1-

14

MDI1+

18

MDI2-

17

MDI2+

21

MDI3-

20

MDI3+

10

LAN_RBIAS

1

+3V_LAN

40

+LX

5

+1.7_VDDCT

24 37

+1.1_DVDDL

16

+AVDDH_AVDD3.3

22

+2.7_AVDDH

9

+2.7_AVDDH

Near Pin9

LAN_XTALI

LAN_XTALO

1

C969

C969 15P_0402_50V8J

15P_0402_50V8J

2

3

1

2

0.1U_0402_16V4Z

+LX

1

2

C952

C951

1U_0402_6.3V4Z

10U_0805_10V4Z

Deciphered Date

+1.7_VDDCT

R1356 0_0402_5%8151@R1356 0_0402_5%8151@

1 2

R1357 0_0402_5%8161@R1357 0_0402_5%8161@

1 2

+1.1_DVDDL

H --> Overclocking mode L --> Not overclocking mode

R58

1 2

R1371 2 .37K_0402_1%R1371 2.37K_0402_1%

Place Close to PIN10

R1372 30K_0402_5%8161@R1372 30K_0402_5%8161@

+LX

R1366 0_0402_5%

1

C962

C961

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near Pin22

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

12

10K_0402_5%@

MDI0- <40> MDI0+ <40> MDI1- <40> MDI1+ <40> MDI2- <40> MDI2+ <40> MDI3- <40> MDI3+ <40>

1 2

8151@

1 2

C955 0.1U_0402_16V4Z

1 2

8151@

1

C963

2

0.1U_0402_16V4Z

Issued Date

3

C964

Near Pin37

Close together

L74

+LX_R +LX

1

C935

C936

@ C935

@

2

1000P_0402_50V7K

Close to Pin40

ACTIVITY# <40>

LAN_LINK# <40>

1 2

4.7UH_SIA4012-4R7M_20%

1

C937

Note: Place Close to LAN chip L39 DCR< 0.15 ohm

2

Rate current > 1A

10U_0805_10V4Z

0.1U_0402_16V4Z

2011103 for ven dor comment

Place Close to PIN1

@

+3VS

+1.1_DVDDL+1.1_DVDDL_R

1

C965

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Near Pin24

2012/07/01

1 2

C950

1000P_0402_50V7K

2

C966

8151@

1

0.1U_0402_16V4Z

For AR8151: Stuff C966,R1366 For AR8161: NC

LC Future Center Secret Data

1

2

+3V_LAN

C953

10U_0805_10V4Z

2

1

@C954

@

2

C954

2014/07/01

2

1

AR8151

AR8161

LX Voltage <Pin 40>

+1.7V <VDDCT>

+1.1V <DVDDL,AVDDL>

FBMA-L11160808601LMA10T_2P

1

C980

C967

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

1 2

1

C278

2

4.7U_0603_6.3V6K

L75

R1356,C955

R1357,R1372,L76

Configure

L76

FBMA-L11160808601LMA10T_2P

L76

1 2

8161@

Place close to Pin34

Place Close to LAN chip

49.9_0402_1%8151@

R1358

R1359

R1360

R1361

R1362

R1363

R1364

R1365

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

49.9_0402_1%8151@

1 2

MDI0+

MDI0-

MDI1+

MDI1-

MDI2+

MDI2-

MDI3+

MDI3-

Note : C938, C940, C942, 944, reserved for EMI.

For AR8151: Stuff 49.9K and 0.1u For AR8161: NC

+AVDDH_AVDD3.3 +2.7_AVDDH

1

C948

2

Place close to Pin16

For AR8151: Stuff R1368 for +AVDD3.3 For AR8161: Stuff R1367,C949 for +AVDDH

Title

LAN-AR8151/8161

Size Document Number Rev

Custom

Date: Sheet of

1 2

R1367 0_0 402_5%

R1368 0_0 402_5%

1

C949

8161@

2

1U_0402_6.3V4Z

0.1U_0402_16V4Z

Tuesday, June 05, 2012

C938 1000P_0402_50V7K@ C938 1000P_0402_50V7K@

8151@

C939 0.1U_0402_16V4Z

C940 1000P_0402_50V7K@ C940 1000P_0402_50V7K@

8151@

C941 0.1U_0402_16V4Z

C942 1000P_0402_50V7K@ C942 1000P_0402_50V7K@

8151@

C943 0.1U_0402_16V4Z

C944 1000P_0402_50V7K@ C944 1000P_0402_50V7K@

8151@

C945 0.1U_0402_16V4Z

8161@

1 2

8151@

1 2

LA-8692P

LA-8692PLA-8692P

1

+1.1_DVDDL+1.1_AVDDL+1.1_AVDDL_L

+3V_LAN

+2.7_AVDDH

39 66

0.2

5

+1.7_VDDCT

D D

C972

C970

0.1U_0402_16V4Z

8161S@

C972

0.1U_0402_16V4Z

8161S@

C974

0.1U_0402_16V4Z

8161S@

C975

0.1U_0402_16V4Z

8161S@

Place Close to T49

MDI3-

C C

TCLAMP3302N.TCT_SLP26 26P10-10

B B

TCLAMP3302N.TCT_SLP26 26P10-10

A A

D68

D67

11

6677889

GND

5

8151S@

6677889

GND

5

8151S@

Reserve D67,D68 for EMI go rural solution

5

91010

112233445

MDI2-

MDI2+

MDI0-

MDI0+

MDI3+

MDI1-

MDI1+

R02

ACTIVITY#<39>

4

8151@

R1373

12

0_0603_5%

C976

@C97 6

@

1U_0402_6.3V4Z

6/23 update

LAN_LINK#<39>

470P_0402_50V7K

4

1

2

LAN_LINK#

C978

ACTIVITY#

@

C979

3

+1.7_VDDCT_R

1

@

2

1

2

+3V_LAN

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2

C970

0.1U_0402_16V4Z

1

8151@

2

C972

0.1U_0402_16V4Z

1

8151@

2

C974

0.1U_0402_16V4Z

1

8151@

2

C975

0.1U_0402_16V4Z

1

8151@

220_0402_5%

R1442

220_0402_5%

12

R1378

2012/07/01

MDO0+

MDO0-

MDO1+

MDO2+

MDO2-

MDO1-

MDO3+

MDO3-

MDI3+<39>

MDI3-<39>

MDI2+<39>

MDI2-<39>

MDI1+<39>

MDI1-<39>

MDI0+<39>

MDI0-<39>

12

3

MDI3+

MDI3-

MDI2+

MDI2-

MDI1+

MDI1-

MDI0+

MDI0-

JRJ1

9

Green LED-

10

Green LED+

1

PR1+

2

PR1-

3

PR2+

4

PR3+

5

PR3-

6

PR2-

7

PR4+

8

PR4-

11

Yellow LED-

12

Yellow LED+

SANTA_130456-111

ME@

LC Future Center Secret Data

Place close to TCT pin

T49

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

NS892402 1G

G2

G1

Deciphered Date

1:1

14

13

2

BOM option: for GDTx4 R1374/R1375/R1376/R1377=75 ohm R1194=0 ohm MCT0~3=Mount

2014/07/01

2

MCT1

MX1+

MX1-

MCT2

MX2+

MX2-

MCT3

MX3+

MX3-

MCT4

MX4+

MX4-

24

MCT3

23

MDO3+

22

MDO3-

21

MCT2

20

MDO2+

19

MDO2-

18

MCT1

17

MDO1+

16

MDO1-

15

MCT0

14

MDO0+

13

MDO0-

Place Close to T49

MCT3

MCT2

MCT1

MCT0

F6

SURGE@

1 2

Reserve for EMI go rural solution

Title

LAN_Transformer

Size D ocument Number Rev

B

Date: Sheet of

LSE-200NX3216TRLF_1206-2

R1374

0_0402_5%

R1375

0_0402_5%

R1377

0_0402_5%

R1376

0_0402_5%

F3

@

12

F4

@

1 2

LSE-200NX3216TRLF_1206-2

for GDTx1 R1374/R1375/R1376/R1377=0 ohm R1194=75 ohm MCT0=Mount MCT1~3=Un mount

Tuesday, June 05, 2012

R1194

R1194 75_0402_5%

75_0402_5%

1 2

1

C973

C973 10P_1206_2KV7K

10P_1206_2KV7K

2

F5

@

LSE-200NX3216TRLF_1206-2

LA-8692P

LA-8692PLA-8692P

1

1 2

LSE-200NX3216TRLF_1206-2

0.2

40 66

1

5

4

3

2

1

D D

C C

B B

Close U29

C449

2200P_0 402_50V7K

C658

2200P_0 402_50V7K

1

2

1

2

REMOTE1 +

REMOTE1 -

REMOTE2 +

REMOTE2 -

+3VS

2

C443

0.1U_040 2_16V4Z

1

+VDD

REMOTE1 +

REMOTE1 -

REMOTE2 +

REMOTE2 -

FAN_PWM & TACH for PWM FAN

SMSC thermal sensor placed near by VRAM

U29

1

VDD

2

DP1

3

DN1

4

DP2

5

DN2

EMC1403 -2-AIZL-TR_MSOP10

Address 1001_101xb

internal pull up 1.2K to 1.5V R for initial thermal shutdown temp

SMCLK

SMDATA

ALERT#

THERM#

GND

10

9

8

7

6

EC_SMB_ CK2

EC_SMB_ DA2

R624

12

10K_040 2_5%

@

EC_SMB_ CK2 <15,23 ,32,45>

EC_SMB_ DA2 <15,23 ,32,45>

+3VS

REMOTE1 +

C982

100P_04 02_50V8J

REMOTE1 -

REMOTE2 +

C984

100P_04 02_50V8J

REMOTE2 -

1

@

2

Close to SSD side

1

@

2

C

2

Q137

B

MMST390 4-7-F_SOT323-3

E

3 1

C

2

Q138

B

MMST390 4-7-F_SOT323-3

E

3 1

Under VRAM

REMOTE2+/-: Trace width/space:10/10 mil Trace length:<8"

FAN1 Conn

+5VS

2

C1109

C986

10U_080 5_10V4Z

A A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/ 01

3

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

C1109

@

1

2

EC_FAN_ SPEED<45>

EC_FAN_ PWM<45>

0.1U_0402_16V4Z

ACES_85 205-04001

Title

EMC1403/2103_Thermal sensor/FAN

Size Do cument Number Rev

Custom

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

2

3

4

5

G5

6

G6

ME@

JFAN1

41 66

0.2

A

1 1

B

C

D

E

F

G

H

SATA HDD Conn.

JHDD1

2 2

SATA_DTX_C_IRX_N1<14>

SATA_DTX_C_IRX_P1<14>

+5VS

1

C631

C631 1000P_0402_50V7K

1000P_0402_50V7K

3 3

2

SATA_DTX_C_IRX_P1

1

C632

0.1U_0402_16V4Z

2

1

C633

C633 1U_0603_10V4Z

1U_0603_10V4Z

2

SATA_ITX_DRX_P1<14> SATA_ITX_DRX_N1<14>

1 2

C627 0.01U_0402_16V7KC627 0.01U_0402_16V7 K

1 2

C628 0.01U_0402_16V7KC628 0.01U_0402_16V7 K

@ J12

+5VS

1

C634

10U_0603_6.3V6M

2

@

112

JUMP_43X79

J12

2

+5VS_HDD

1

C635

10U_0603_6.3V6M

2

SATA_ITX_DRX_P1 SATA_ITX_DRX_N1

SATA_DTX_IRX_N1SATA_DTX_C_IRX _N1 SATA_DTX_IRX_P1

JHDD1

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V33

9

V33

10

V33

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

Reserved

19

GND

20

V12

21

V12 V1222GND

SANTA_191201-1

ME@

GND

SATA ODD Conn.

JODD1

1

GND

SATA_ITX_DRX_P2_CONN<14> SATA_ITX_DRX_N2_CONN<1 4>

SATA_DTX_C_IRX_N2<14> SATA_DTX_C_IRX_P2<14>

24 23

SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 SATA_DTX_IRX_P2

SLI_FAN_SPEED<32,45>

ODD_DETECT#<19>

ODD_DA#_R<18>

1 2

C629 0.01U_0402_16V7KC629 0.01U_0 402_16V7K

1 2

C630 0.01U_0402_16V7KC630 0.01U_0 402_16V7K

ODD_DA#_R

SLI_FAN_PWM<32,45>

R1516 R_short 0_0402_5%R1516 R_short 0_0402_5%

@

R1476 0_0402_5%

+3VS

R922 0_0402_5%

R1517 R_short 0_0402_5%R1 517 R_short 0_0402_5%

SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_N2_CONN

SATA_DTX_IRX_N2

1 2 1 2

@

1 2

R710 0_0402_5%

+5VS_ODD

1 2

10K_0402_5%

R921

1 2

@

1 2

ODD_DA#

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

DP

9

+5V

10

+5V

11

MD

12

GND

GND13GND

SANTA_202404-1

ME@

GND

15 14

ODD Power Control

AO3413 VGS= -4.5V, Id=-3A, Rds<97m ohm

2

C638

0.01U_0402_16V7K

1

+5VS_ODD

1

C639

C639 10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

C637

0.1U_0402_16V4Z

2

Q89B

2N7002KDWH_SOT363-6

Q89B

12

R1477

R1477 470_0603_5%

470_0603_5%

@

34

D

S

5

G

ODD_EN#

ODD_EN<19>

R1478

100K_0402_5%

R923

100K_0402_5%

2

G

12

@

+5VALW

12

61

D

S

+5VS

12

R1496

100K_0402_5%

C1049

0.1U_0402_16V4Z

R1110

12

100K_0402_5%

Q89A

Q89A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

@ J6

@

112

JUMP_43X79

AO3413_SOT23-3

Q88

S

G

1

2

1

J6

D

13

ODD_EN#

C1057

0.01U_0402_16V7K@

4 4

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

D

2012/07/01

E

LC Future Center Secret Data

Deciphered Date

F

2014/07/01

Title

HDD/ODD Connector

Size Document Number Rev

B

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

G

LA-8692P

LA-8692PLA-8692P

42 66

H

0.2

A

B

C

D

E

F

G

H

L10

+5VS

+MIC1_VREFO_L

1 1

MIC2_R

RA1634 1K_0402_5%RA1634 1K_0402_5%

MIC1_R

RA1633 1K_0402_5%RA1633 1K_0402_5%

2 2

+3VS

1 2

@ CA1368

@

3 3

RA1622

2.2K_0402_5%

12

+3VALW

EC_MUTE#

RA475

4.7K_0402_5%@

HDA_RST_AUDIO#

CA1368 100P_0402_50V8J~N

100P_0402_50V8J~N

1 2

RA1623

2.2K_0402_5%

1 2

EXT_MIC_R

EXT_MIC_L

R1407

R1407 10K_0402_5%

10K_0402_5%

@

EC_MUTE#<45>

HDA_SDOUT_AUDIO<14>

HDA_BITCLK_AUDIO<14>

HDA_SDIN0<14>

HDA_SYNC_AUDIO<14>

HDA_RST_AUDIO#<14>

MIC Sense --> RA1639 place near pin13 Capless HP Sense --> RA1638 place near pin34

MIC_JD<49>

PLUG_IN<49>

EXT_MIC_R <49>

EXT_MIC_L <49>

PLUG_IN

600ohms @100MHz 1A P/N: SM01000BU00

+5VS

600ohms @100MHz 2A P/N: SM01000EE00

RA1639 20K_0402_1%RA1639 20K_0402_1 %

RA1638 39.2K_0402_1%RA1638 39.2K_0402_1%

CA1288 2.2U_0603_6.3V6KCA1288 2.2U_0603_6.3V6K

C673 2.2U_0603_6.3V6KC673 2.2U_0603_6.3V6K

C291 4.7U_0603_6.3V6KC291 4.7U_0603_6.3V6K

For EMI

HDA_SDOUT_AUDIOHDA_SYNC_AUDIO

2

CA1278

CA1278 10P_0402_50V8J

10P_0402_50V8J

1

2

CA1285

@ CA1285

@

10P_0402_50V8J

1

CA1282

@ CA1282

@

22P_0402_50V8J~N

2

@

RA1635

0_0402_5%

12

HDA_BITCLK_AUDIO

1 2

FBMA-L11160808601LMA10T_2P

CA13

Place near UA8. Pin25

RA5

1 2

0_0805_5%

2

1

CA6

1

4.7U_0603_6.3V6K

CA8

CA7

2

0.1U_0402_16V4Z

Place near UA8. Pin39, Pin46

EC_MUTE#

HDA_SDOUT_AUDIO

HDA_BITCLK_AUDIO

HDA_SDIN0 HDA_SDIN0_R

HDA_SYNC_AUDIO

HDA_RST_AUDIO#

12

1 2

12

RA1637

22_0402_5%

RA1640

20K_0402_1%

+MIC1_VREFO_L

12

PC_BEEP

JDREF

SENSEAMIC_JD

CBN

CBP

CPVEE

LDO_CAP

10 mils

1

CA14

2

4.7U_0805_10V4Z

+5VS_PVDD

1

2

0.1U_0402_16V4Z

UA8

47

DAPD/COMB_JACK

4

PD#

5

SDATA-OUT

6

BIT-CLK

8

SDATA-IN

10

SYNC

11

RESET#

12

PCBEEP

19

JDREF

20

MONO-OUT(PORT-H)

13

Sense A

18

Sense-B

35

CBN

36

CBP

34

CPVEE

28

LDO-CAP

29

MIC2-VREFO

30

MIC1-VREFO-R

31

MIC1-VREFO-L

42

PVSS1

43

PVSS2

7

DVSS

ALC269Q-VC2-GR_QFN48_6X6

0.1U_0402_16V4Z

+5VS_AVDD

39

PVDD1

+5VS_AVDD

46

PVDD2

25

AVDD1

+5VS_AVDD

38

AVDD2

R1355

1 2

+3VS_DVDD +3VS_DVDDIO

0_0603_5%

+3VS_DVDD

+3VS_DVDDIO

1

9

DVDD1

DVDD-IO

LINE1-R(PORT-C-R)

LINE1-L(PORT-C-L)

MIC1-R(PORT-B-R)

MIC1-L(PORT-B-L)

MIC2-R(PORT-F-R)

MIC2-L(PORT-F-L)

LINE2-R(PORT-E-R)

LINE2-L(PORT-E-L)

SPK-OUT-L+

SPK-OUT-L-

SPK-OUT-R-

SPK-OUT-R+

HPOUT-R(PORT-A-R)

HPOUT-L(PORT-A-L)

SPDIF-OUT

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

VREF

AVSS1

AVSS2

Thermal PAD

1

CA15

2

0.1U_0402_16V4Z

Place near UA8. Pin1

+5VS_AVDD

2

1

C648

C293

1

2

0.1U_0402_16V4Z

4.7U_0603_6.3V6K

Place near UA8. Pin38

24

23

22

C_MIC2

21

17

16

15

14

CA1277 2.2U_0603_6.3V6KCA1277 2.2U_0603_6.3V6K

C_MIC1

CA1276 2.2U_0603_6.3V6KCA1276 2.2U_0603_6.3V6K

10 mils

30 mils

40

SPKOUT_L1+

41

SPKOUT_L2-

44

SPKOUT_R2-

45

SPKOUT_R1+

10 mils

33

HPOUTR_R

32

HPOUTL_R

48

SPDIF SPDIF_OUT

3

DMIC_CLK_R

2

DMIC_DATA_R DMIC_DATA

10 mils

27

AC97_VREF

26

37

49

AGND

+3VS_DVDD+3VS +3VS_DVDD +3VS_DVDDIO

1

CA16

2

1U_0603_10V4Z

12

MIC2_R

MIC1_R

RA6

1 2

0_0402_5%

P/N: SM01000DI0 J

SPKOUT_R2-

Ext. MIC

Place near UA8. Pin1

RA56

1 2

RA58

1 2

RA60

1 2

RA61

1 2

SPK_R1

SPK_R2

SPK_L1

SPK_L2

D62

@D62

@

1

CA17

2

@

10U_0603_6.3V6M

11/07 --> Change CA17 typ e to 0603

30 mils

0_0603_5%

SPK_L1SPKOUT_L1+

0_0603_5%

SPK_L2SPKOUT_L2-

0_0603_5%

SPK_R1SPKOUT_R1+

0_0603_5%

SPK_R2

CA9 1000P_0402_50V7K~N@CA9 1000P_0402_50V7K~N@

CA10 1000P_0402_50V7K~N@ CA10 1000P_0402_50V7K~N@

CA11 1000P_0402_50V7K~N@ CA11 1000P_0402_50V7K~N@

CA12 1000P_0402_50V7K~N@ CA12 1000P_0402_50V7K~N@

2

3

2

3

1

AZ5125-02S.R7G_SOT23-3

Reserve for ESD request.

R3 75_0402_5%R3 7 5_0402_5%

R4 75_0402_5%R4 7 5_0402_5%

R945

R945 FBMA-10-100505-301T_2P

FBMA-10-100505-301T_2P

R955

R955 FBMA-10-100505-301T_2P

FBMA-10-100505-301T_2P R954 0_0402_5%R 954 0_0402_5%

12

1 2

12

EMI Request

HP_OUTR

HP_OUTL

DMIC_CLK

HP_OUTR <49>

HP_OUTL <49>

SPDIF_OUT <49>

DMIC_CLK <50>

DMIC_DATA <50>

10 mils

2

CA1290

1

CA1291

2

1U_0603_10V4Z

Close to UA8.Pin27

0.1U_0402_16V4Z

CA18

@

1 2

D61

AZ5125-02S.R7G_SOT23-3

1

2

@

0.1U_0402_16V4Z

JSPK1

1

2

3

4

5

G5

6

G6

ACES_85205-04001

ME@

HeadPhone

SPDIF

Int. MIC

Pin Assignment Location Function

PC Beep

4 4

EC Beep

PCH Beep

BEEP#<45>

HDA_SPKR<14>

A

1 2

CA4 0.1U_0402_16V4ZCA4 0.1U_0402_16V4Z

1 2

CA5 0.1U_0402_16V4ZCA5 0.1U_0402_16V4Z

B

12

RA2

@ RA2

@

10K_0402_5%

RA1

1 2

33_0402_5%

PC_BEEPPC_BEEP1

C

RA1647

@ RA1647

@

1 2

0_0402_5%

DGND AGND

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

D

2012/07/01

E

LC Future Center Secret Data

Deciphered Date

SPK-OUT (Pin40/41/44/45)

Capless HP-OUT (Pin32/33)

MIC1(Pin21/22) External Mic in

Title

HD Audio ALC269/Audio Jack

2014/07/01

F

HD Audio ALC269/Audio Jack

Size Document Number Rev

Custom

Date: Sheet of

G

Internal

External

Tuesday, June 05, 2012

Int Speaker

Headphone out

LA-8692P

LA-8692PLA-8692P

43 66

H

0.2

5

R1458

12

0_0603_5%

U71

D D

+1.8VS_CARD

+3VS_CARD

+1.8VS_CARD

PLT_RST#

+CRD_POWER

C C

B B

1 2

C1027 2.2U_0603_6.3V6KC1027 2.2U_0603_6.3V6K

Please close to pin43

SD_CD# MS_CD# XD_CD#

U71

5

APVDD

10

APV18

36

TAV33

19

DV33

20

DV33

44

DV33

18

DV18

37

DV18

43

SDDV33_18

1

XRSTN

2

XTEST

13

CPPE_N

21

CR1_LEDN

17

CR1_PCTLN

16

CR1_CD0N/WAKEN

15

CR1_CD1N

14

CR2_CD2N

33

SPI_CSN

34

SPI_SO

35

SPI_SI

30

SPI_SCK

39

TXIN

6

APGND

31

GND

32

GND

38

GND

JMB389-LGAZ0C_LQFP48_7X7

+3VS_CARD+3VS

JMB389

Power

System

GND

PCIECard Reader

1

2

C1034

0.1U_0402_16V4Z

Close to pin10

XD_CD#

A A

SD_CD#

C1044

0.1U_0402_16V4Z

@

1

C1045

0.1U_0402_16V4Z

2

@

5

1

2

MDIO6

MDIO13

1 2

R1465

R1465 1K_0402_5%

1K_0402_5%

1 2

R1466

R1466 1K_0402_5%

1K_0402_5%

4

3

APCLKN

4

APCLKP APREXT

APRXN APRXP APTXN APTXP

MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MIDO6 MDIO7 MDIO8

MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14

7 9 8 11 12

48 47 46 45 41 42 24 40 29 28 27 26 25 23 22

APREXT

PCIE_PRX_C_DTX_N4 PCIE_PRX_C_DTX_P4

MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 MDIO5 MDIO6 MDIO7 MDIO8 MDIO9 MDIO10 MDIO11 MDIO12 MDIO13 MDIO14

C1036

0.1U_0402_16V4Z

R_short 0_0402_5%

+1.8VS_CARD

1

2

C1037

Close to pin5->1000P->0.1u->10u

+CRD_POWER

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

CLK_PCIE_CARD_PCH# CLK_PCIE_CARD_PCH

1 2

R1461

12K_0402_1%

1 2

C1026 .1U_0402_16V7KC 1026 .1U_0402_16V7K

1 2

C1028 .1U_0402_16V7KC 1028 .1U_0402_16V7K

R1463

1 2

@

1

2

10U_0805_10V4Z

Issued Date

3

CLK_PCIE_CARD_PCH# <15> CLK_PCIE_CARD_PCH <15>

PCIE_PTX_C_DRX_N4 PCIE_PTX_C_DRX_P4 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4

R1464

1 2

MDIO5_R MDIO5_RR

R_short 0_0402_5%

1

2

R_short 0_0402_5%

C1031

C1031 22P_0402_50V8J

22P_0402_50V8J

@

1

2

C1038

0.1U_0402_16V4Z

Close to CONN.

+3VS_CARD

C1039

Close to pin 44

2012/07/01

3

close to JREAD1 pin 9

close to JREAD1 pin 17

close to JREAD1 pin 36

PCIE_PTX_C_DRX_N4 <15> PCIE_PTX_C_DRX_P4 <15> PCIE_PRX_DTX_N4 <15> PCIE_PRX_DTX_P4 <15>

+CRD_POWER

1

C1029

10U_0805_10V4Z~D

1

2

0.1U_0402_16V4Z

LC Future Center Secret Data

1

2

C1041

C1040

@

0.1U_0402_16V4Z

Close to pin 36

Deciphered Date

2

1

2

C1030

0.1U_0402_16V4Z

1

2

0.1U_0402_16V4Z

(40mil)

800mA

MDIO0 MDIO1 MDIO2 MDIO3 MDIO8 MDIO9 MDIO10

MDIO4 MDIO6 MDIO14 XD_CD# MDIO13 MDIO12 MDIO5_RR MDIO7

2014/07/01

2

MDIO5_R

MDIO5_RR

R1459

R1460

R1462

100_0402_5%

Close to connector for EMI request.

JREAD1

22

XD-VCC

30

XD10-D0

29

XD11-D1

28

XD12-D2

27

XD13-D3

26

XD14-D4

25

XD15-D5

24

XD16-D6

23

XD17-D7

33

XD07-WE

32

XD08-WP

34

XD06-ALE

39

XD01-CD

38

XD02-R/B

37

XD03-RE

36

XD04-CE

35

XD05-CLE

31

XD GND

40

XD GND

41

SD CD/WP GND

42

SD CD/WP GND

T-SOL_144-131300 2600_40P_NR-T

ME@

1

C1042

0.1U_0402_16V4Z

2

Close to pin 37Close to pin 19,20

Title

Card reader JMB389

Size D ocument Number Rev

B

Date: Sheet of

2

Date: Sheet of

12

@R1459

@

12

@R1460

@

12

@R1462

@

+1.8VS_CARD

@

1 2

C1023

100P_0402_50V8J

@

1 2

C1024

100P_0402_50V8J

@

1 2

C1025

100P_0402_50V8J

11

SD4-VDD

18

MS9-VCC

9

SD5-CLK

SD2-CMD

SD-CD

SD-WP

SD6-VSS SD3-VSS

MS6-INS

MS2-BS

MS1-VSS

C1043

4 3 21 19 16 1 2

6 13

17 10 8 12 15 14 7 5 20

SD7-DAT0 SD8-DAT1 SD9-DAT2 SD1-DAT3

MS8-SCLK MS4-DATA0 MS3-DATA1 MS5-DATA2 MS7-DATA3

MS10-VSS

1

10U_0805_10V4Z

2

Close to pin 18

Tuesday, June 05, 2012

1

MDIO5_R MDIO0 MDIO1 MDIO2 MDIO3 MDIO4 SD_CD#MDIO11 MDIO6

MDIO5_R MDIO0 MDIO1 MDIO2 MDIO3 MS_CD# MDIO4

LA-8692P

LA-8692PLA-8692P

1

+CRD_POWER

(40mil)

C1032

0.1U_0402_16V4Z

44 66

(40mil)

1

2

1

2

C1033

0.1U_0402_16V4Z

0.2

EC_SCI#/ EC_SMI# pull up to PCH

D70

EC_SMI#<19>

EC_SCI#<19>

pull up to PCH

R1404

1 2

+3VALW

100K_0402_5%

+3VL

1 2

@

R1545 100K_0402_5%

For S3.5

KSO[0..17]<46>

KSI[0..7]< 46>

Reserved SMBus channel 0 for debugging

EC_SMB_CK1<49,54,63> EC_SMB_DA1<49,54,63>

Please place R1435 close to EC with in 790mil

EC_SMB_DA1

H_PECI<6>

D70

D71

SERIRQ< 14>

C999

1U_0402_6.3V6K

C999

1U_0402_6.3V6K

1

2

KSO[0..17]

KSI[0..7]

EC_SMB_CK2< 15,23,32,41> EC_SMB_DA2< 15,23,32,41>

H_PECI PECI_EC

For Deep S3

12

LPC_FRAME#<14,38>

CLK_PCI_EC<18>

EC_SMB_CK2 EC_SMB_DA2

EC_LID_OUT#<19>

CPU1.5V_S3_GATE<10>

EC_SMI#_R

RB751V-40_SOD323-2

EC_SCI#_R

RB751V-40_SOD323-2

LPC_AD3<14,38> LPC_AD2<14,38> LPC_AD1<14,38> LPC_AD0<14,38>

BATT_LEN#<54>

PLT_RST#<18,23,32,38,39,44,6>

GATEA20<19>

LAN_PWR_ON#<39>

PM_SLP_S3#<16>

PM_SLP_S4#<16>

EC_RSMRST#<16>

USB_ON#< 48>

DPWROK_EC<16>

NUM_LED#<47>

ECR_EN<34>

KBRST#<19>

LPC_FRAME#

12

R143543_0402_1% R143543_0402_1%

ON/OFF<51>

NOVO#<51>

LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

R1539

GATEA20

1 2

R_short 0_0402_5%

R1540

1 2

0_0402_5%

@

EC_SMI#_R

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16EC_SMB_CK1 KSO17

EC_SMB_CK1 EC_SMB_DA1

LAN_PWR_ON#

USB_ON#

EC_LID_OUT#

+RTCBATT

KBRST#

SERIRQ

WRST#

BATT_LEN#

EC_SCI#_R

NOVO#

NUM_LED#

ECR_EN_R

12

close EC

C1082

1 2

.1U_0402_16V7K

@

R1519

0_0402_5%

R1520

R_short 0_0402_5%

U70

4

KBRST#/GPB6

5

SERIRQ/GPM6

6

LFRAME#/GPM5

7

LAD3/GPM3

8

LAD2/GPM2

9

LAD1/GPM1

10

LAD0/GPM0

13

LPCCLK/GPM4

14

WRST#

15

ECSMI#/GPD4

16

PWUREQ#/BBO/SMCLK2ALT/GPC7

17

NC

22

LPCRST#/WUI4/GPD2

23

ECSCI#/GPD3

126

GA20/GPB5

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

56

KSO16/SMOSI/GPC3

57

KSO17/SMISO/GPC5

110

SMCLK0/GPB3

111

SMDAT0/GPB4

115

SMCLK1/GPC1

116

SMDAT1/GPC2

117

SMCLK2/PECI/WUI22/GPF6

118

SMDAT2/PECIRQT#/WUI23/GPF7

94

WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1

95

WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2

112

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7

125

PWRSW/GPE4

19

BAO/WUI24/GPE0

33

GINT/CTS0#/GPD5

35

RTS1#/WUI5/GPE5

93

CLKRUN#/WUI16/GPH0/ID0

2

CK32KE/GPJ7

128

CK32K/GPJ6

100K_0402_5%

100K_0402_5% R1102

R1102

VCOREVCC

12

Int. K/B

Int. K/B Matrix

Matrix

All capacitors close to EC

R1543

R1417

R1424

R1423

R1422

10K_0402_5%

C1004

C1004 47P_0402_50V8J

47P_0402_50V8J

+3VS

C1075

0.1U_0402_16V4Z

C1075

0.1U_0402_16V4Z

1

2

+3VALW

+3VL

12

R1544

0_0603_5%@

12

+3VS

12

+3VS

R1431

12

10K_0402_5%

R1485

12

+3VS

@

R1402

12

10K_0402_5%

+3VS

H_PROCHOT# <54,6>

LAN_WAKE# <38,39>

L80

BLM18PG181SN1D_0603

R1524

12

+3VALW

0_0603_5%

12

+3VS

12

11

12

3

VBAT/VCC

VCORE/VCC

LPC

SM Bus

WAKE UP

Clock

VSS/GND

VSS/GND20VSS/GND

1

21

VCC/VCC

R1535

GPIO

27

0_0603_5%

VSS/GND

18

VSTBY/VCC

VSS/GND49VSS/GND

R1542

For S3.5

50

92

114

121

127

VSTBY/VCC

VSTBY/VCC26VSTBY/VCC

ADC

ADC5/DCD1#/WUI29/GPI5 ADC6/DSR1#/WUI30/GPI6 ADC7/CTS1#/WUI31/GPI7

DAC

PS2

PS2CLK1/DTR0#/GPF2 PS2DAT1/RTS0#/GPF3

PS2DAT2/WUI21/GPF5

SPI Flash ROM

EXTERNAL SERIAL FLASH

UART

GPIO

DTR1#/SBUSY/GPG1/ID7

AVSS/AGND

VSS/GND

75

91

113

122

ECAGND

+3VALW_EC

VSTBY/VCC

PWM

DAC2/TACH0B/GPJ2 DAC3/TACH1B/GPJ3

PS2CLK0/TMB0/GPF0 PS2DAT0/TMB1/GPF1

PS2CLK2/WUI20/GPF4

EGCS#/WUI26/GPE2 EGCLK/WUI27/GPE3

TACH1A/TMA1/GPD7

+3VL

0_0603_5%

@

minimum trace width 12 mil

+3VALW_R

C1081

0.1U_0402_16V4Z

C1081

0.1U_0402_16V4Z

1

2

74

AVCC

24

PWM0/GPA0

25

GPH4/ID4 GPH5/ID5 GPH6/ID6

GPG3 GPG4 GPG5 GPG7

GPJ1

BATT_CHG_LED#

28 29 30 31 32 34 120

ACIN

124

66 67 68 69 70 71 72 73

78 79 80 81

85 86 87 88 89 90

96 97 98 99

101 102 103 105

108 109

82

SYSON

83

SUSP#

84

77 100 106

H_PROCHOT#_EC

104 107 119 123

76 48 47

BATT_LOW_LED#

LED_KB_PWM

SLI_FAN_PWM EC_FAN_PWM BEEP#

EC_INVT_PWM

BATT_TEMP

LAN_WAKE#

AD_ID LID_SW#

TP_CLK TP_DATA

ACOFF

GPG3 GPG4 GPG5

CMOS_ON#

EC_ON

BKOFF#

PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

PWM6/SSCK/GPA6

PWM7/RIG1#/GPA7

TMRI0/WUI2/GPC4 TMRI1/WUI3/GPC6

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2 ADC3/GPI3

ADC4/WUI28/GPI4

DAC4/DCD0#/GPJ4

DAC5/RIG0#/GPJ5

WUI19/GPH3/ID3

RXD/SIN0/GPB0

TXD/SOUT0/GPB1

EGAD/WUI25/GPE1

SSCE0#/GPG2 SSCE1#/GPG0

DSR0#/GPG6

CRX0/GPC0

CTX0/TMA0/GPB2

TACH2/GPJ0

TACH0A/GPD6

IT8580E-HX_LQFP128

C1080

0.1U_0402_16V4Z

C1080

0.1U_0402_16V4Z

1

2

VGA_AC_DET

VGA_IMON

EC_WL_OFF#_R

USB_CH#

SUSACK#

PCH_PWR_EN

PCH_PWROK

ENBKL

AOAC_ON

A_DET#

SLI_FAN_SPEED

EC_FAN_SPEED

C1078

C1079

0.1U_0402_16V4Z

C1079

0.1U_0402_16V4Z

1

2

CAPS_LED#

EC_RX

EC_TX

R1429 0_0402_5%@R1429 0_0402_5%@

1 2

C1077

0.1U_0402_16V4Z

C1077

0.1U_0402_16V4Z

C1076

1

2

BATT_TEMP <54>

IMVP_IMON <60>

ADP_I <54,63>

LID_SW# <46>

SUSWARN# <16> AC_PRESENT <16>

DRAMRST_CNTRL_EC <7>

EC_WL_OFF#_R <38>

USB_CH# <49>

PM_SLP_SUS# <16,52>

SUSACK# <16>

PCH_PWR_EN < 52>

ACOFF <63>

CMOS_ON# <50>

EC_RX <38> EC_TX <38>

12

AOAC_ON <52>

R1619

@R1619

@

0_0402_5%

SLI_FAN_SPEED <32,42>

EC_FAN_SPEED <41>

EMC Request

0.1U_0402_10V6K

0.1U_0402_16V4Z

PWR_LED# <47> BATT_CHG_LED# <47> BATT_LOW_LED# <47>

LED_KB_PWM <51>

SLI_FAN_PWM <32,42>

EC_FAN_PWM <41> BEEP# <43>

EC_INVT_PWM <34>

ACIN <63>

VGA_AC_DET <23,32,59>

VGA_IMON <59> SA_PGOOD <57>

AD_ID <54>

PBTN_OUT# <16,6>

TP_CLK <46> TP_DATA <46>

CAPS_LED# <47>

R1433

SYSON <56>

SUSP# <32,52,56,58,59>

VR_ON <60>

ENBKL <34>

PROCHOT <54>

ME_FLASH <14>

EC_ON <51,55>

BKOFF# <34>

A_DET# <47>

A_DET#_R <49>

BATT_TEMP

ACINSYSON

C1007

1

@

2

for 2nd fan

for fan

for EC beep

10K_0402_5%

1 2

@

1 2

C1000 100P_0402_50V8JC1000 100P_0402_50V8J

1 2

C1001 100P_0402_50V8JC1001 100P_0402_50V8J

EC_MUTE# <43>

+3VALW_R

TP_CLK

TP_DATA

PCH_PWROK <16>

1 2

0.1U_0402_16V4Z

1 2

L81

BLM18PG181SN1D_0603

+5VALW

R1482

1 2

USB_CH#

10K_0402_5%

R1409

1 2

USB_ON#

10K_0402_5%

1 2

R1410 4.7K_0402_5%R1410 4.7K_0402_5%

1 2

R1412 4.7K_0402_5%R1412 4.7K_0402_5%

VR_HOT#<60>

SUSP#

12

100K_0402_5%

100K_0402_5% R1101

R1101

C1072

ECAGND

+3VS

H_PROCHOT#_EC

WRST#

VR_HOT#

H_PROCHOT#_EC

SYSON

1

2

LPC_FRAME#

R_short 0_0402_5%

2N7002H_SOT23-3

+3VALW_EC

1

C1073

1000P_0402_50V7K

2

R_short 0_0603_5%

EC_SMB_CK1

2.2K_0402_5%

EC_SMB_DA1

2.2K_0402_5%

EC_SMB_CK2

2.2K_0402_5%

EC_SMB_DA2

2.2K_0402_5%

EC_FAN_SPEED

SLI_FAN_SPEED

EC_FAN_PWM

1 2

R1521 10K_0402_5%R1521 10K_0402_5%

GPG5

CMOS_ON#

GPG3

GPG4

For factory EC flash

R1427

1 2

13

D

2

G

Q141

S

+3VALW

1 2

LAN_WAKE#

12

100K_0402_5%

100K_0402_5% R1522

R1522

IT0PAD IT0PAD

IT1PAD IT1PAD

IT2PAD IT2PAD

IT3PAD IT3PAD IT4PAD IT4PAD IT5PAD IT5PAD IT6PAD IT6PAD IT7PAD IT7PAD

IT8PAD IT8PAD

1

2

R1434

10K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

Title

BIOS & EC I/O Port

Size Document Number Rev

C

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

45 66

0.2

5

4

3

2

1

15" INT_KBD Conn.

KSI[0..7]

KSO[0..17]

D D

C C

KSO16

KSO17

KSO2

KSO15

KSO6

KSO8

KSO13

KSO12

KSO11

KSO10

KSO3

KSO4

KSI0

KSO0

CONN PIN define need double check

1 2

C794 100P_04 02_50V8J@C794 100P _0402_50V8J@

1 2

C795 100P_04 02_50V8J@C795 100P _0402_50V8J@

1 2

C734 100P_04 02_50V8J@C734 100P _0402_50V8J@

1 2

C736 100P_04 02_50V8J@C736 100P _0402_50V8J@

1 2

C738 100P_04 02_50V8J@C738 100P _0402_50V8J@

1 2

C740 100P_04 02_50V8J@C740 100P _0402_50V8J@

1 2

C742 100P_04 02_50V8J@C742 100P _0402_50V8J@

1 2

C744 100P_04 02_50V8J@C744 100P _0402_50V8J@

1 2

C746 100P_04 02_50V8J@C746 100P _0402_50V8J@

1 2

C748 100P_04 02_50V8J@C748 100P _0402_50V8J@

1 2

C750 100P_04 02_50V8J@C750 100P _0402_50V8J@

1 2

C752 100P_04 02_50V8J@C752 100P _0402_50V8J@

1 2

C754 100P_04 02_50V8J@C754 100P _0402_50V8J@

1 2

C756 100P_04 02_50V8J@C756 100P _0402_50V8J@

To TP/B Conn.

SMB_DAT A_S3<12,13,15 ,38> SMB_CLK _S3<12,13 ,15,38>

TP_DATA<45> TP_CLK<45 >

B B

SMB_DAT A_S3 SMB_CLK _S3

TP_DATA TP_CLK

1

@

C761

C761 100P_04 02_50V8J

100P_04 02_50V8J

2

KSI[0..7] <45>

KSO[0..17] <45>

1

@

C762

C762 100P_04 02_50V8J

100P_04 02_50V8J

2

+3VALW

KSO1

KSO7

KSI2

KSO5

KSI3

KSO14

KSI7

KSI6

KSI5

KSI4

KSO9

KSI1

+3VS

0.1U_040 2_16V4Z

D58

4

I/O3

5

VDD

1 2

C735 100P_04 02_50V8J@C735 100P _0402_50V8J@

1 2

C737 100P_04 02_50V8J@C737 100P _0402_50V8J@

1 2

C739 100P_04 02_50V8J@C739 100P _0402_50V8J@

1 2

C741 100P_04 02_50V8J@C741 100P _0402_50V8J@

1 2

C743 100P_04 02_50V8J@C743 100P _0402_50V8J@

1 2

C745 100P_04 02_50V8J@C745 100P _0402_50V8J@

1 2

C747 100P_04 02_50V8J@C747 100P _0402_50V8J@

1 2

C749 100P_04 02_50V8J@C749 100P _0402_50V8J@

1 2

C751 100P_04 02_50V8J@C751 100P _0402_50V8J@

1 2

C753 100P_04 02_50V8J@C753 100P _0402_50V8J@

1 2

C755 100P_04 02_50V8J@C755 100P _0402_50V8J@

1 2

C757 100P_04 02_50V8J@C757 100P _0402_50V8J@

C760

1

I/O1

2

GND

JTP1

1

2

3

4

5

6

7

GND

8

GND

ACES_88 514-00601-071

ME@

KSO17 KSO16 KSO15 KSO10 KSO11 KSO14 KSO13 KSO12 KSO3 KSO6 KSO8 KSO7 KSO4 KSO2 KSI0 KSO1 KSO5 KSI3 KSI2 KSO0 KSI5 KSI4 KSO9 KSI6 KSI7 KSI1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

ACES_85 202-3005N

ME@

JKB1

G1 G2

Lid Switch

31 32

+3VALW

R1002

1 2

R_short 0_0 402_5%

C758

0.1U_040 2_16V4Z

+VCC_LID

1

2

1 2

R1003 100K_040 2_5%R10 03 100K_0402 _5%

2

5711ACD L-M3T1S SOT-23

VDD

3

OUTPUT

GND

U37

1

2

C759

10P_040 2_50V8J

1

LID_SW # <45>

6

I/O4

AZC099-0 4S.R7G_SOT23-6

@

A A

5

I/O2

3

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/ 01

3

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

2

Title

KB /SW /LPC Debug Conn.

Size Do cument Number Rev

B

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

46 66

0.2

R1559

100K_0402_5%

5

G

1 2

+3VALW

R1621

0_0402_5%

R1622

0_0402_5%

@

12

34

D

S

2

1

C1099

2

0.1U_0402_16V4Z

2N7002KDWH_SOT363-6

1 2

@

5

G

0.1U_0402_16V4Z

+5VS

12

34

R1490

R1490 10K_0402_1%

10K_0402_1%

@

D

S

@

Q159B

R1560 0_0402_5%

PWR_LED#_R

61

D

G

R1492 0_0402_5%R1492 0_0402_ 5%

Q151B

2N7002KDWH_SOT363-6

1 2

Q159A

S

2N7002KDWH_SOT363-6

2

G

+5VS

12

61

R1491

R1491 10K_0402_1%

10K_0402_1%

@

D

Q151A

S

@

HDD_LED#_R

2N7002KDWH_SOT363-6

PWR_LED#_R<51>

CAPS_LED#<45>

NUM_LED#<45>

Amber

BATT_LOW_LED#_R

BATT_CHG_LED#_R

White

PWR_LED#_R

12

R1012470_0402_5% R1012470_0 402_5%

12

R1014470_0402_5% R1014470_0 402_5%

HDD_LED#_R

CPU:H_3P8X 3

H10

H10 HOLEA

HOLEA

1

12-21SYGCS530-E1S155TR8_W

LED3

power

H12

H11

HOLEA

1

LED

LED2

3

2

12-22-S2ST3D-C30-2C_WHI-ORG

12-21SYGCS530-E1S155TR8_W

LED4

12-21SYGCS530-E1S155TR8_W

LED2

battery

LED1

LED4

CAPS

HDD

GPU:H_3P8 X 3

H14

H13

HOLEA

1

White

LED3

White

LED1

LED5

1

H15

H15 HOLEA

HOLEA

1

21

LED5

NUM

FD1FD1

1

FD3FD3

FD2FD2

1

+5VALW

12

+5VALW

R1013300_0402_5% R1013300_0402_5%

12

+5VS

R1322300_0402_5% R1322300_0402_5%

12

+5VS

R1323300_0402_5% R132330 0_0402_5%

12

+5VS

R1563300_0402_5% R1563300_0402_5%

FD4FD4

1

+3VALW

2

G

C1098

BATT_LOW_LED#_R

61

D

S

BATT_CHG_LED#_R

61

D

Q158A

S

2N7002KDWH_SOT363-6

Q160A

2N7002KDWH_SOT363-6

PWR_LED#<45>

A_DET#<45>

HDD_LED#<14>

12

R1558

100K_0402_5%

1

34

D

R1562

100K_0402_5%

5

G

5

G

S

+3VALW

12

34

D

Q160B

S

2N7002KDWH_SOT363-6

R1564 0_0402_5%

BATT_CHG_LED#<45>

BATT_LOW_LED#<45>

2

0.1U_0402_16V4Z

2N7002KDWH_SOT363-6

1 2

@

1

2

0.1U_0402_16V4Z

2

G

C1100

Q158B

R1561 0_0402_5%

1 2

@

MIN PCIE:H_3P3 X 3

H17

H16

H22

H22 HOLEA

HOLEA

1

+3VS +3VS_BT

BT@

Q154 AO3413_SOT23-3

D

S

D

S

BT@

C1085

0.1U_0402_16V4Z

100K_0402_5%

C1084

@

0.1U_0402_16V4Z

1

2

USB20_P13<18> USB20_N13<18>

1 2

R1526

PCH_BT_ON#<19,38>

R1526

BT@

0.1U_0402_16V4Z

13

1

G

2

C1086

1

2

BT@

0.01U_0402_16V7K

USB20_P13 USB20_N13

30mils

1

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z C1083

C1083

BT@

JBT1

1

2

3

4

5

GND

6

GND

ACES_50209-0040N-001

ME@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

H16

HOLEA

1

H_4P0X2P8N X 2

H20

H20 HOLEA

HOLEA

1

Keyboad:H_2P8X3

H31

H31 HOLEA

HOLEA

1

H_3P0 X 9

H18

H23

H24

H25

H26

HOLEA

1

H21

H21 HOLEA

HOLEA

1

H33

H32

HOLEA

1

Title

LED/EC SPI ROM/BT

Size Document Number Rev

B

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

HOLEA

1

H26 HOLEA

HOLEA

1

H34

H34 HOLEA

HOLEA

1

LA-8692P

LA-8692PLA-8692P

H27

H27 HOLEA

HOLEA

1

H28

H28 HOLEA

HOLEA

1

47 66

H29

H29 HOLEA

HOLEA

1

H35

H35 HOLEA

HOLEA

1

0.2

A

B

C

D

E

LEFT SIDE USB3.0 PORT X1

+USB_VCCA+5VALW

U39

1

C767 0.1U_0402_16V4ZC767 0.1U_0402_16V4Z

1 1

12

USB_ON#<45 >

2

4

USB_ON# USB_OC1#

G547I2P81U_MSOP8

Low Active 2A

For EMI request

USB2.0 choke --> SM070000I00

USB3.0 Choke --> SM070001U00

USB20_N2<18>

L68

USB30_RX_N3

USB30_RX_P3

USB30_TX_C_N3

2 2

USB30_TX_C_P3

USB20_N2

USB20_P2 USB30_TX_R_P3

2

3

WCM-2012-900T_4P

L70

2

3

WCM-2012-900T_4P

L72

2

3

WCM-2012-900T_4P

1

4

1

4

1

4

USB30_RX_R_N3

USB30_RX_R_P3

USB30_TX_R_N3

USB30_TX_R_P3

USB20_N2_R

USB20_P2_R

USB30_RX_R_N3

USB30_RX_R_P3

USB30_TX_R_N3

USB20_P2<18>

USB30_RX_N3<18> USB30_RX_P3<18>

USB30_TX_N3<18> USB30_TX_P3<18>

For ESD request

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

8

GND

VOUT

7

VOUT

VIN

6

VIN3VOUT

5

FLG

EN

USB30_RX_P3 USB30_RX_R_P3

USB30_TX_N3 USB30_TX_C_N3 USB30_TX_R_N3

D27

@

1

2

4

3

8

1

C904

1000P_0402_50V7K@

2

C300 0.1U_0402_10V6KC300 0.1U_0402_10V6K C299 0.1U_0402_10V6KC299 0.1U_0402_10V6K

1

USB30_RX_R_N3

2

USB30_RX_R_P3

4

USB30_TX_R_N3

5

USB30_TX_R_P3

3

1 2 1 2

USB_OC1# <18>

USB20_N2_R

USB30_TX_C_P3 USB30_TX_R_P3USB30_TX_P3

D24

@

3

2

1

AZC099-04S.R7G_SOT23-6

I/O2

GND

I/O1

I/O4

VDD

I/O3

1 2

R1162 0_0402_5%

1 2

R1163 0_0402_5%

@

1 2

R1154 0_0402_5%

@

1 2

R1155 0_0402_5%

@

1 2

R1156 0_0402_5%

@

1 2

R1157 0_0402_5%

@

@ @

@

6

5

+5VALW

4

USB20_P2_R

+USB_VCCA

C814 220 U_6.3V_M

1 2

+

1 2

C816 470 P_0402_50V7KC816 470P_0402_50V7K

JUSB1

1

VBUS

USB20_N2_RUSB20_N2 USB20_P2_RUSB20_P2

USB30_RX_R_N3USB30_RX_N3

2

D-

3

D+

4

GND_1

5

SSRX-

6

SSRX+

7

GND_2

8

SSTX-

9

SSTX+

SANTA_370300-1

ME@

GND_6 GND_5 GND_4 GND_3

13 12 11 10

+USB_VCCA

3 3

1 2

R1165 0_0402_5%

USB20_N3<18>

USB20_P3<18>

USB30_RX_N4<18> USB30_RX_P4<18>

USB30_TX_N4<18> USB30_TX_P4<18>

USB30_RX_P4 USB30_RX_R_P4

USB30_TX_N4 USB30_TX_C_N4 USB30_TX_R_N4

1 2

C301 0.1U_0402_10V6KC301 0.1U_0402_10V6K

1 2

C302 0.1U_0402_10V6KC302 0.1U_0402_10V6K

USB30_TX_C_P4 USB30_TX_R_P4U SB30_TX_P4

R1165 0_0402_5%

1 2

R1164 0_0402_5%

@

1 2

R1158 0_0402_5%

@

1 2

R1159 0_0402_5%

@

1 2

R1161 0_0402_5%

@

1 2

R1160 0_0402_5%

@

@ @

@

USB20_N3_RUSB20_N3 USB20_P3_RUSB20_P3

USB30_RX_R_N4USB30_RX_N4

For ESD request

D25

Issued Date

D25

@

3

2

1

AZC099-04S.R7G_SOT23-6

I/O2

GND

I/O1

I/O4

VDD

I/O3

6

5

4

2012/07/01

+5VALW

USB20_P3_R

LC Future Center Secret Data

Deciphered Date

C

D28

@

USB30_RX_R_N4

USB30_RX_R_P4

USB30_TX_R_N4

USB30_TX_R_P4

4 4

A

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

1

USB30_RX_R_N4

1

2

USB30_RX_R_P4

2

4

USB30_TX_R_N4

4

5

USB30_TX_R_P4

3

8

USB20_N3_R

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

@

C815 220 U_6.3V_M

1 2

+

1 2

C817 470 P_0402_50V7KC817 470P_0402_50V7K

JUSB2

1

VBUS

2

D-

3

D+

4

GND_1

5

SSRX-

6

GND_6

SSRX+

7

GND_5

GND_2

8

SSTX-

GND_4

9

SSTX+

GND_3

SANTA_370300-1

ME@

2014/07/01

D

For EMI request

USB2.0 choke --> SM070000I00

USB3.0 Choke --> SM070001U00

L69

USB30_RX_N4

USB30_RX_P4

13 12 11 10

USB30_TX_C_N4

USB30_TX_C_P4

USB20_N3

USB20_P3

Title

USB3.0 ports

Size Document Number Rev

Custom

Date: Sheet of

2

3

WCM-2012-900T_4P

L71

2

3

WCM-2012-900T_4P

L79

2

3

WCM-2012-900T_4P

Tuesday, June 05, 2012

1

4

1

4

1

4

LA-8692P

LA-8692PLA-8692P

1

USB30_RX_R_N4

4

USB30_RX_R_P4

1

USB30_TX_R_N4

4

USB30_TX_R_P4

USB20_N3_R

USB20_P3_R

48 66

E

0.2

5

D D

4

3

+5V_CHGUSB

EXT_MIC_L<43> EXT_MIC_R<43> MIC_JD<43> HP_OUTR<43> HP_OUTL<43> SPDIF_OUT<43> PLUG_IN<43>

+5VS

USB20_P9_C

USB20_N9_C

EXT_MIC_L

EXT_MIC_R

MIC_JD

HP_OUTR

HP_OUTL

SPDIF_OUT

PLUG_IN

2

JSB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17 18

19

17

G1

20

18

G2

ACES_50505-0184N-001

ME@

1

A_DET#_R

+3VALW

1 2

R1599

R1599 10K_0402_5%

10K_0402_5%

@

R1583

R1583 10K_0402_5%

10K_0402_5%

+5VALW

SEL

+5V_CHGUSB

3 4

17 16

18 13 11 12 6 5

Del C1095

USB20_N9_C

A_DET#_R

EC_SMB_DA1 EC_SMB_CK1 CH_SEL

1 2

R1555

33K_0402_5%

ILIM SETTING

*

1 2

R1553

10K_0402_5%

Pull Low Pull Low OR-500mA 10K-900mA 12K-1000mA 15K-1200mA 18K-1500mA 22K-1800mA 27K-2000mA 33K-2500mA

A_DET#_R<45>

USB_OC4# <18> EC_SMB_DA1 <45,54,63> EC_SMB_CK1 <45,54,63>

SEL Pin Decode

0R-1010_1110 10K-1010_1100

*

12K-1010_1010 15K-1010_1000 18K-0110_0000 22K-0110_0010 27K-0110_0100 33K-0110_0110

C C

+5VALW

B B

@

R1584

1 2

10K_0402_5%

@

R1552

1 2

10K_0402_5%

R1554

@

1 2

10K_0402_5%

A A

EM_EN

CH_M1

CH_M2

10U_0603_6.3V6M

1

C1096

2

R1551

10K_0402_5%

R1585

10K_0402_5%

R1586

10K_0402_5%

0.01U_0402_16V7K

1

C1097

2

12

+5VALW

USB20_P9<18> USB20_N9<18>

USB_CH#<45>

Active Mode Selection:

M1 M2 EM_EN ACTIVE MODE

0 0 1 Dedicated Charger Emulation Cycle 0 1 0 Date Pass-through 0 1 1 BC1.2 DCP 1 0 0 BC1.2 SDP 1 0 1 Dedicated Charger Emulation Cycle 1 1 0 Date Pass-through 1 1 1 BC1.2 CDP

*

1U_0402_6.3V6K

USB20_P9 USB20_P9_C USB20_N9

USB_CH#

0.1U_0402_16V4Z

C1093

EM_EN

CH_M1 CH_M2 CH_ILIM

2

1

C1094

1

2

9

VDD

VBUS1 VBUS2

DPOUT

DMOUT

A_DET# ALERT#

SMDATA/LATCH

SMCLK/S0

COMM_SEL/ILIM

GND FLAG21GND

UCS1002-1-BP-TR_QFN20_4X4

20

14 15

10

19

7

8

1 2

U8

VS1

VS2

DPIN DMIN

PWR_E N

EM_EN

M1 M2

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIET ARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIET ARY PROPERTY OF LC FUTURE CENTER. AND CON TAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

2012/07/01

4

LC Future Center Secret Data

Deciphered Date

3

2014/07/01

Title

USB charger

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

2

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

49 66

1

0.2

5

D D

+3VS

1

C1101

0.1U_0402_16V7K

C C

12

R1569

2.49K_0402_1%

@

R1570 4.7K_0402_5%@R1570 4.7K_0402_5%@

R1572 4.7K_0402_5%@R1572 4.7K_0402_5%@

R1574 4.7K_0402_5%@R1574 4.7K_0402_5%@

R1576 4.7K_0402_5%@R1576 4.7K_0402_5%@

R1578 4.7K_0402_5%@R1578 4.7K_0402_5%@

1 2

R1571 4.7K_0402_5%@R1571 4.7K_0402_5%@

1 2

R1573 4.7K_0402_5%@R1573 4.7K_0402_5%@

1 2

R1575 4.7K_0402_5%@R1575 4.7K_0402_5%@

1 2

R1577 4.7K_0402_5%@R1577 4.7K_0402_5%@

1 2

A_EQ0

B B

A_EQ1

A_DE0

A_DE1

TEST

B_EQ0

B_EQ1

A A

B_DE0

B_DE1

B_INn B_INp

A_OUTn A_OUTp A_OUTp_C

5

R1581

R1581 R1582

R1582

C1107

C1107 C1108

C1108

@

+3VS

1

C1102

@

2

@

2

B_EQ0

0.01U_0402_16V7K

1 2 1 2

0_0402_5%@

0_0402_5%@ 0_0402_5%@

0_0402_5%@

0.1U_0402_10V6K@

Equalizer control and program for channel A

3.3V tolerant. Internally pulled down at ~150KΩ [A_EQ1, A_EQ0] == LL: adaptive EQ enable LH: program EQ for channel loss up to 7dB HL: program EQ for channel loss up to 14.5dB HH: program EQ for channel loss up to 11.5dB

*

Programmable output pre-emphasis level setting for channel A

3.3V tolerant. Internally pulled down at ~150KΩ [A_DE1, A_DE0] == LL: 3.5dB de-emphasis

*

LH: No de-emphasis HL: 7dB de-emphasis HH: 5dB with boost output swing

Chip test mode enable.

3.3V tolerant. Internally pulled down at ~150KΩ. TEST == L: Normal operation (default)

*

H: Test mode enable

Equalizer control and program for channel B

3.3V tolerant. Internally pulled down at ~150KΩ [B_EQ1, B_EQ0] == LL: adaptive EQ enable LH: program EQ for channel loss up to 7dB HL: program EQ for channel loss up to 14.5dB HH: program EQ for channel loss up to 11.5dB

*

Programmable output pre-emphasis level setting for channel B

3.3V tolerant. Internally pulled down at ~150KΩ [B_DE1, B_DE0] == LL: 3.5dB de-emphasis

*

LH: No de-emphasis HL: 7dB de-emphasis HH: 5dB with boost output swing

B_DE0 B_EQ1

B_DE1

B_INn_C B_INp_C

A_OUTn_C

4

@

EPAD

12C_EN B_OUTn B_OUTp

A_INn A_INp

A_DE1

A_EQ0

SDA_CTL

TEST

USB30_RX_N1 USB30_RX_P1

USB30_TX_N1 USB30_TX_P1

25 24 23 22 21

GND

20 19 18 17 16 15 14 13

VDD

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

USB30_RX_N1<18> USB30_RX_P1<18>

USB30_TX_N1<18> USB30_TX_P1<18>

U75

1

VDD

2

B_EQ0

3

I2C_R0

4

I2C_R1

5

PD#

6

B_DE1

7

REXT

8

B_INn B_INp9SCL_CTL

10

GND

11

A_OUTn

12

A_OUTp

PS8710BTQFN24GTR2-A0_TQFN24_4X4

4

R1565

R1565 R1566

R1566

R1567

R1567 R1568

R1568

B_OUTn B_OUTp

A_INn A_INp A_DE1 A_EQ0 A_DE0 A_EQ1 TEST

Issued Date

1 2 1 2

close to IC

3

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

0_0402_5% 0_0402_5%

0_0402_5%

@

12

C11040.1U_0402_16V7K

12

C11030.1U_0402_16V7K @C11030.1U_0402_16V7K @

12

C11050.1U_0402_16V7K

12

C11060.1U_0402_16V7K

@

2012/07/01

3

USB30_RX_N1_R USB30_RX_P1_R

USB30_TX_N1_C USB30_TX_P1_C

USB30_RX_N1 USB30_RX_P1

@

USB30_TX_N1 USB30_TX_P1

CMOS_ON#<45>

LC Future Center Secret Data

R1579 0_0402_5%R1579 0_0402_5% R1580 0_0402_5%R1580 0_0402_5%

C304

C304 C303

C303

R435

1 2

100K_0402_5%

CMOS@

Deciphered Date

1 2 1 2

B_INn

B_INp

A_OUTn

A_OUTp

(40 MIL)

+3VS

C1051

0.1U_0402_16V4Z

2

+CMOS_PW

CMOS

W=40mils

0.1U_0402_10V6K

DMIC_CLK<43>

DMIC_DATA<43>

For ESD request

D69

@

9

10

8

9

7

6

6 5

YSCLAMP0524P_SLP2510P8-10-9

1

2

4

5

3

8

CMOS Camera

Q94 AO3413_SOT23-3

D

S

D

S

13

+CMOS_PW_R

CMOS@

G

2

1

CMOS@

2

1

@

C520

0.1U_0402_16V4Z

2

2014/07/01

2

C1052

CMOS@

1

C1070

For RF request

@

12

0.047U_0402_16V4Z

+3VS

B_INn

B_INp

A_OUTn

A_OUTp

0.047U_0402_16V4Z

USB20_N0<18> USB20_P0<18>

USB20_N0 USB20_P0

USB20_P0

+3VS

USB20_N0

B_INn B_INp

A_OUTn A_OUTp

D55

4

I/O3

5

VDD

6

I/O4

AZC099-04S.R7G_SOT23-6

@

DMIC_CLK

JCMOS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

I-PEX_20374-014E-31

ME@

1 2

R1498

0_0402_5%

For EMI

I/O1

GND

I/O2

@

ESD request

(40 MIL)

+CMOS_PW

R432

1 2

1

R_short 0_0603_5%

C518

1

2

0.01U_0402_16V7K

C518

0.1U_0402_16V4Z

2

CMOS@

Title

USB3.0 Redriver and Camera

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

C519

10U_0603_6.3V6M@C519

10U_0603_6.3V6M

1

@

2

LA-8692P

LA-8692PLA-8692P

1

GND1 GND2

1

2

1

DMIC_DATA

2

3

DMIC_CLK

50 66

15 16

@

C934

100P_0402_50V8J

0.2

ON/OFF switch

Power Button

TOP Side

Bottom Side

ON/OFFBTN#

EC_ON<45,55>

10K_0402_5 %

NOVO#<45 >

SW2

1

2

EC_ON

R1523

51_ON#

ON/OFF

5

6

J7

1 2

SHORT PADS

@

1 2

NOVO#

R19

R1549 0_0 402_5%

@

3

4

SMT1-05_4P

1

DAN202UT106 _SC70-3

2N7002_SOT2 3-3

+3VALW

R1118

R1118 100K_0402_ 5%

100K_0402_ 5%

1 2

R_short 0_0402_5 %

1 2

100K_0402_ 5%

R1116

1 2

@

R1547 0_0603_5%

For S3.5

D72

3

2

13

2

G

Q153

+3VL

R1548

R1548 100K_0402_ 5%

100K_0402_ 5%

@

1 2

D56

2

3

DAN202UT106 _SC70-3

For S3.5

+3VALW

1 2

51_ON#

D

S

For S3.5

1

+3VL

ON/OFF

100K_0402_ 5%

R1546

@

1 2

For S3.5

NOVO_BTN#

ON/OFF <45>

51_ON# <53>

Power Button/B link to Function/B Conn. 10pin KB Lighting CONN.4pin

JKBL1

12

13

D

Q122

Q122 2N7002_SOT2 3

2N7002_SOT2 3

S

KBL@

1

2

3

4

5

G1

6

G2

ACES_85201-0 4051

ME@

+5VS

Q121

PWR_LE D#_R<47 >

ON/OFFBTN#

C551

@

100P_0402_ 50V8J

+5VALW

NOVO_BTN#

1

2

JPWR1

8

GND

7

GND

6

5

4

3

2

1

ACES_88514-0 0601-071

ME@

LED_KB_PW M<45>

+VCC_KB_LED

R1480

100K_0402_ 5%

KBL@

2

C905

@

1

0.1U_0402_10V6K

R1229

10K_0402_5 %

KBL@

2

G

12

AO3413 VGS= -4.5V, Id=-3A, Rds<97m ohm

AO3413_SOT2 3-3

D

S

D

S

KBL@

13

G

2

+VCC_KB_LED

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/ 01

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

Title

other IO connector

Size Document Num ber Rev

Custom

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

51 66

0.2

A

+5VALW TO +5VS

+5VALW +1.5V +1.5VS

1

C836

C836 10U_0805_10V4Z

10U_0805_10V4Z

2

SUSP

+VSB

R1085

R1085 150K_0402_5%

150K_0402_5%

5VS_GATE

61

D

2

PCH_PWR_EN<4 5>

PM_SLP_SUS#<16, 45>

Q99A

G

S

2N7002KDWH_SOT363-6

PCH_PWR_EN

1 1

2 2

12/13 add for Deep S3

AOAC_ON#<38>

AOAC_ON<45>

3 3

AOAC_ON

U46

U46 AP4800BGM-HF

AP4800BGM-HF

8 7 6 5

R1088

82K_0402_5%

12

R1484

R1484 820K_0402_5%

820K_0402_5%

@

PM_SLP_SUS#

R1530

1 2

0_0402_5%

R117

AP4800BGM VGS=10V, ID=9A, Rds=18m ohm VGS=+-25V

R_short 0_0402_5%

R1448 0_ 0402_5%

AOAC@

4

12

5VS_GATE_R

R60

100K_0402_5%

DS3@

1 2

@

AOAC_ON#

AOAC@

+5VS

1 2

1

3

2

2N7002KDWH_SOT363-6

1

C842

0.01U_0402_25V7K

2

PCH_PWR_EN#PCH_PWR_EN#_R

12

+5VALW

2

G

12

100K_0402_5%

100K_0402_5% R1531

R1531

10U_0603_6.3V6M

C837

12

100K_0402_5%

100K_0402_5% R1121

R1121

DS3@

12

13

D

S

1

C838

C838 1U_0603_10V4Z

1U_0603_10V4Z

2

+5VALW

12

13

2

G

100K_0402_5%

100K_0402_5% R1529

R1529

AOAC@

Q155

Q155 2N7002_SOT23

2N7002_SOT23

AOAC@

Q99B

100K_0402_5%

100K_0402_5% R1120

R1120

DS3@

D

Q118

Q118 2N7002_SOT23

2N7002_SOT23

S

DS3@

12

R1475

R1475 470_0603_5%

470_0603_5%

@

34

D

S

B

5

SUSP

G

SUSP

0.1U_0402_16V4Z

+V1.05S_VCCP_PWRGOOD<57,58>

For S3 CPU Power Saving

+3VALW TO +3VS

U47

U47 AP4800BGM-HF

AP4800BGM-HF

8

R_short 0_0402_5%

12

R1483

R1483 820K_0402_5%

820K_0402_5%

2N7002KDWH_SOT363-6

JUMP_43X79

J11

112

@

Q148

AO3413_SOT23

D

S

D

S

G

2

C1088

12

0.75VR_EN

2

G

@

7 6 5

R1089

12

@

2

13

1

C38

0.1U_0402_16V4Z

2

DS3@

0.01U_0402_16V7K

+3VALW

@

5

G

61

D

S

1

C839

C839 10U_0805_10V4Z

10U_0805_10V4Z

2

+VSB

12

R1086

R1086 470K_0402_5%

470K_0402_5%

3VS_GATE

61

D

2

Q100A

G

S

+3V_DSW to +3V_PCH

+3VALW +3V_PCH

DS3@

1

C1087

DS3@

2

PCH_PWR_EN#_R

0.75VR_EN#<58>

R8

100K_0402_5%

@

SUSP

Q144A

2N7002KDWH_SOT363-6

Q144A

C

AP4800BGM VGS=10V, ID=9A, Rds=18m ohm VGS=+-25V

+3VS+3VALW

1 2

10U_0603_6.3V6M

1

3

C840

C841

C841 1U_0603_10V4Z

1U_0603_10V4Z

2

4

3VS_GATE_R

2

2N7002KDWH_SOT363-6

1

C843

0.01U_0402_25V7K

2

+5VALW to +5V_PCH

JUMP_43X79

+5VALW +5V_PCH

J14

2

112

@

Q149

AO3413_SOT23

D

S

D

S

13

DS3@

@C38

@

12

R6

R6 100K_0402_5%

100K_0402_5%

34

D

S

DS3@

1

2

C1089

DS3@

0.1U_0402_16V4Z

Q144B

Q144B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

@

G

2

C1090

DS3@

0.01U_0402_16V7K

Q100B

1

2

12

R1474

R1474 470_0603_5%

470_0603_5%

@

34

D

S

1

C39

@C39

@

0.1U_0402_16V4Z

2

DGPU_PWR_EN<18,2 3>

D

+1.5V_CPU_VDDQ

+1.5V to +1.5VS

S

D

13

10U_0603_6.3V6M

1

C856 10U_0805_10V4Z

10U_0805_10V4Z

2

5

SUSP

G

SUSP#

+3VALW

12

@

100K_0402_5%

100K_0402_5% R1087

R1087

R1090

0_0402_5%

61

D

2

G

SUSP<10,38,56,58>

Q101A

S

2N7002KDWH_SOT363-6

SUSP

SUSP#< 32,45,56,58,59>

G

@C856

@

2

LP2301ALT1G 1P SOT-23-3

@R1090

@

12

1.5VS_GATE

@

+5VALW

2

G

12

61

1

Q120

@

2

1

C845 .1U_0402_16V7K

.1U_0402_16V7K

2

R1097

R1097 100K_0402_5%

100K_0402_5%

D

Q107A

Q107A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

S

10U_0603_6.3V6M

C857

@C845

@

E

J15

112

@

JUMP_43X79

1

@C857

@

C835 1U_0603_10V4Z

1U_0603_10V4Z

2

1.5VS_GATE

Q107B

+1.5VS

2

12

@C835

@

R1481

@

470_0603_5%

34

D

@

5

G

+0.75VS

12

R1094

R1094 22_0603_5%

22_0603_5%

34

D

S

2N7002KDWH_SOT363-6

@

Q101B

S

2N7002KDWH_SOT363-6

5

SUSP

G

For Intel S3 Power Reduction.

+3VS to +3VS_VGA

+3VS +3VS_VGA

+5VALW

12

R1449

47K_0402_5%

DGPU_PWR_EN#<25>

R1452

12

R_short 0_0402_5%

12

2

G

R1454

R1454 100K_0402_5%

100K_0402_5%

61

D

S

C1058

0.1U_0402_16V4Z

1 2

R1451

R1451 10K_0402_5%

10K_0402_5%

Q146A

1

2

1

@

2

0.1U_0402_10V7K

Q145

AO3413_SOT23

D

S

D

S

G

2

C1011

13

1

C1059

2

0.01U_0402_25V7K

12

C37 10U_0603_6.3 V6MC37 10U_060 3_6.3V6M

R1450

R1450 470_0603_5%

470_0603_5%

@

34

D

5

G

S

Q146B

S

Q146B

DGPU_PWR_EN#

2N7002KDWH_SOT363-6

+3VS to +3VS_SLI

+5VALW

12

SLI@

R1594

47K_0402_5%

S_DGPU_PWR_EN#<32>

S_DGPU_PWR_EN<19,3 2>

4 4

R_short 0_0402_5%

A

R1596

12

2

G

R1597

R1597 100K_0402_5%

100K_0402_5%

SLI@

61

D

S

+3VS +3VS_SLI

C1062

0.1U_0402_16V4Z

1 2

R1513

SLI@R1513

SLI@

10K_0402_5%

Q162A

SLI@

0.1U_0402_10V7K

2N7002KDWH_SOT363-6

Q147

AO3413_SOT23

S

1

G

SLI@

2

1

@

C1110

2

S_DGPU_PWR_EN#

B

SLI@

D

13

1

C1063

2

SLI@

2

R1595

470_0603_5%

0.01U_0402_25V7K

5

G

Q162B

SLI@

2

12

C48

C48 10U_0603_6.3V6M

10U_0603_6.3V6M

1

SLI@

@

SLI@

34

D

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

2N7002KDWH_SOT363-6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

C

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

D

Title

DC Interface

Size Do cument Number Rev

Custom

Date: Sheet of

2N7002KDWH_SOT363-6

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

E

52 66

0.2

5

TP41TP41

TP42TP42

DC030006J00

4

APDIN

4

3

2

4602-Q04C-09R 4P P2.5@

4602-Q04C-09R 4P P2.5@ JDCIN1

JDCIN1

2

1

D D

TP40TP40

1

PF1

PF1 12A_65V_451012MRL

12A_65V_451012MRL

21

1

TP44TP44

TP43TP43

TP45TP45

SMB3025500YA_2P

1 2

12

PC2

PC1

100P_0402_50V8J

1000P_0402_50V7K

1

2012/03/02 add TP40~45(HW request)

4

VIN

PL1

12

PC3

PC4

100P_0402_50V8J

1000P_0402_50V7K

SLI_B+_ON#<32>

VIN

200K_0402_1%

3

B+ to SLI_B+

B+ SLI_B+

PR398

1 2

SLI@

PC516

1 2

SLI@

PR400

47K_0402_1%

1 2

SLI@

PQ69

PQ69 AON7403L_DFN8-5

AON7403L_DFN8-5

1

3

4

SLI@

0.22U_0603_25V7K

52

SLI@

2

12

PC515

0.1U_0603_25V7K

200K_0402_1%

SLI_5V_ON#<32>

+5VS to +5V_SLI

JUMP_43X79

1

2

1 2

PR401

47K_0402_1%

1 2

JUMP_43X79

PJ19

112

AO6409AL 1P TSOP-6

PQ70

4

SLI@

PC517

0.1U_0402_16V4Z

SLI@

+5VS +5V_SLI

PR399

SLI@

@

2

D

SLI@

S

6 5 2 1

G

3

PC518

SLI@

0.01U_0402_16V7K

1

2

1

PC519

PC519 10U_0603_6.3V6M

10U_0603_6.3V6M

2

SLI@

PD1

LL4148_LL34-2

PD2

<BOM Structure>PD 2

C C

+3VLP

PR8

B B

BATT+

PR3

200_0402_1%

1 2

51_ON#<51>

0_0402_5%

1 2

LL4148_LL34-2

@PR3

@

PR5

22K_0402_1%

1 2

12

PR4

+CHGRTC

3.3V

12

PC7

PC7 10U_0603_6.3V6M

10U_0603_6.3V6M

@

51ON-2

PC5

1 2

0.22U_0603_25V7K

100K_0402_1%

51ON-3

PU1

@PU1

@

APL5156-33DI-TRL_SOT89-3

3

VOUT

GND

1

PJ1

PJ1 JUMP_43X39@

JUMP_43X39@

2

112

PQ1

TP0610K-T1-E3_SOT23-3

2

12

PR9

PR9 200_0603_5%@

200_0603_5%@

2

CHGRTCIN

VIN

12

PC8

PC8 1U_0805_25V6K

1U_0805_25V6K

@

LL4148_LL34-2

1 2

51ON-1

12

PR2

PR1

68_1206_5%

13

12

PC6

0.1U_0603_25V7K

VS

JRTC1

- +

MAXEL_ML1220T10@

PR7

PR6

560_0603_5%

12

1 2

PR7

560_0603_5%

1 2

RB751V-40_SOD323-2

RTC Battery

2012/05/25 change Netname from +5VALW to +5VS

PD3

12

+RTCBATT

RB751V-40_SOD323-2

+CHGRTC

PD4

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

Vin Detector

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

53 66

0.2

5

4

3

2

1

JBATT1

VMB2

JBATT1

1

2

3

EC_SMCA

3

4

EC_SMDA

4

5

D D

C C

5

6

7

8

GND

9

GND

TYCO_1775789-1

@

12

PR11

PR10

100_0402_1%

+3VALW

1 2

PR12

6.49K_0402_1%

1 2

PR14

PR14 10K_0402_5%

10K_0402_5%

PR396

100K_0402_5%

PR397

PF2

PF2 12A_65V_451012MRL

12A_65V_451012MRL

12

100K_0402_5%

21

VMB

+3VALW

for power adapter ID 3V--- 90W

1.5V--- 120W 0V--- 170W

AD_ID <45>

PL2

SMB3025500YA_2P

1 2

12

PC9

PC9 1000P_0402_50V7K

1000P_0402_50V7K

EC_SMB_CK1 <45,49,63>

EC_SMB_DA1 <45,49,63>

BATT_TEMP <45>

12

A/D

BATT+

PC10

0.01U_0402_25V7K

PH1 under CPU botten side : CPU thermal protection at 92+-3 degree C Recovery at 56 +-3 degree C

VL

12

PC11

+3VS

0.1U_0603_25V7K

H_PROCHOT#< 45,6>

PQ3

2N7002KW_SOT323-3

PROCHOT<45>

0.1U_0603_25V7K

PR18

1 2

13

D

S

2

ADP_OCP_1

G

PR22 0_0402_5%

0_0402_5%

1 2

100K_0402_1%

@PR22

@

OTP_N_003

0_0402_5%

PR23

1

2

3

4

PU2

VCC

GND

OT1

OT2

G718TM1U_SOT23-8

TMSNS1

RHYST1

TMSNS2

RHYST2

12

ADP_I<45,63>

8

7

OTP_N_002

6

5

ADP_OCP_2

MAINPWON <55>

For KB930 --> Keep PU1 circuit (Vth = 0.825V)

For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206 PH201, PR205,PR211,PQ201,PR208,PR212

PR15

1 2

16.5K_0402_1%

Turbo_V

1 2

PR20

76.8K_0402_1%

Turbo_V

PR20

57.6K:90W (SD03457628J)

+3VLP

PR19

10K_0402_1%

PR21

1 2

10K_0402_1%

12

PR16

@ P R16

@

13.7K_0402_1%

12

NTC_V

PR15

4.42K(SD000004J8J) :90W

12

9.1K(SD03491018J):120W

16.5k(SD03416528J):170w

PR17

21.5K_0402_1%

12

PH1

100K_0402_1%_NCP15WF104F03RC

82.5k:120W (SD00000278J)

76.8k:170w (SD03476828J)

B B

VMB2

PR27

PR27 768K_0402_1%

768K_0402_1%

PR29

10K_0402_1%

1 2

PR31

PR31 221K_0402_1%

221K_0402_1%

1 2

A A

5

12

P2

PC12

0.01U_0402_25V7K

8

3

P

+

2

-

G

4

PR34

@PR34

@

10K_0402_1%

PR36

10K_0402_1%

PR28

10M_0402_5%

1 2

1

O

PU3A

AS393MTR-E1 SO 8P OP

12

+CHGRTC

12

2VREF_8205

BATT_LEN#<45>

+3VALW

PR24

1 2

100K_0402_1%

10K_0402_1%

+3VALW

PR25

1 2

PQ5

2N7002KW_SOT323-3

PR37

+3VALW

13

D

2

G

S

PR35

1 2

100K_0402_1%

2

12

G

100K_0402_1%

PQ7

13

D

2N7002KW_SOT323-3

S

4

BATT_OUT <63>

PQ4

TP0610K-T1-E3_SOT23-3

B+

VL

PR32

100K_0402_1%

SPOK<55>

PR33

1 2

1K_0402_1%

1 2

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

22K_0402_1%

13

D

2

G

S

PC15

1U_0402_6.3V6K

2012/07/01

12

PR26

100K_0402_1%

PR30

1 2

PQ6

2N7002KW_SOT323-3

100K_0402_1%

LC Future Center Secret Data

12

PC13

0.22U_0603_25V7K

Deciphered Date

13

2

2014/07/01

2

12

PC14

0.1U_0603_25V7K

+VSBP

PJ2

PJ2 JUMP_43X39@

JUMP_43X39@

2

112

Title

BATTERY CONN/OTP

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

+VSB

LA-8692P

LA-8692PLA-8692P

1

54 66

0.2

5

Note: Use TPS51125 IC can remove RTC refernece LDO Use TPS51427 IC must keep RTC refernece LDO

4

3

2

1

2VREF_8205

+3VALW P +3VALW

D D

PR38

13K_0402_1 %

1 2

PR40

154K_0402_ 1%

BST_3V

UG_3V

LX_3V

LG_3V

PC35

1U_0603_10V6K

PR50

0_0402_5%

PR52

0_0402_5%

PR54

0_0402_5%

PR40

20K_0402_1 %

1 2

PR43

1 2

PU4

25

P PAD

7

VO2

8

VREG3

9

BOOT2

10

UGATE2

11

PHASE2

12

LGATE2

12

@PR52

@

12

@PR54

@

12

3

RT8205_B+

PJ5

B+

PC22

C C

B B

ACPRN

A A

PJ5

2

112

JUMP_43X118@

12

PC17

PC18

0.1U_0603_25V7K

PC18

0.1U_0603_25V7K

+3VALWP

2012/02/29 change PC29, PC32, PC34 from SGA00001E0J to SGA00002N8J

PR51

0_0402_5%

EC_ON<45,51 ,55>

PR56

2

0_0402_5%

PR55

@ PR55

@

0_0402_5%

12

5

13

MAINPWON<54>

200K_0402_ 1%

EC_ON<45,51 ,55>

12

PC19

4.7U_0805_25V6-K

12

2

G

DTC115EUA_S C70-3

12

PC20

4.7U_0805_25V6-K

4.7U_0805_25V6-K 2200P_0402_50V7K

2200P_0402_50V7K

3.3UH +-20% PCMC0 63T-3R3MN 6A

1

+

PC29

2

150U_B2_6.3VM_R35M

2N7002KDW -2N_SOT363-6

VL

PQ14

2N7002KW _SOT323-3

13

D

S

PQ15

VS

100K_0402_ 1%

1 2

PR57

AO4466L_SO8

PL3

1 2

PQ12A

12

PQ8

PR46

4.7_1206_5%

PC30

680P_0603_50V7K

61

100K_0402_ 1%

PR58

40.2K_0402_1%

6

578

4

123

PR53

PC38

578

PQ10

PQ10 AO4712_SO8

AO4712_SO8

3 6

241

12

13

2

2.2U_0603_10V7K

4

12

2

12

Typ: 175mA

PC24

PQ12B

34

2N7002KDW -2N_SOT363-6

5

PQ13

PQ13 DTC115EUA_S C70-3

DTC115EUA_S C70-3

+3VLP

12

4.7U_0805_10V6K

PR44

1 2

2.2_0603_5%

PC27

0.1U_0603_25 V7K

PR48

499K_0402_ 1%

1 2

B+

ENTRIP2ENT RIP1

12

PR49

100K_0402_1%

2VREF_8205

VL

+3.3VALWP Imax=7.5A ; Ipeak=9A 1/2 Delta I=1.113A (F=375K Hz) Vtrip=0.169V Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical) Ilimit_min=0.169/18m=9.388A Ilimit_max=0.169/15=11.26A Iocp=Ilimit+1/2Delta I=10.5A~12.373A

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PC16

1U_0603_10V6K

ENTRIP2

5

6

ENTRIP2

VFB=2.0V

EN

14

13

RT8205_B+

2012/07/ 01

12

PR39

30K_0402_1 %

1 2

PR41

20K_0402_1 %

1 2

88.7K_0402_ 1%

1 2

ENTRIP1

2

3

1

4

FB2

SKIPSEL

FB1

REF

TONSEL

15

ENTRIP1

VO1

PGOOD

BOOT1

UGATE1

PHASE1

LGATE1

NC18VREG5

VIN16GND

17

12

PC36

4.7U_0805_10V6K

12

PC37

0.1U_0603_25V7K

LC Future Center Secret Data

Deciphered Date

PR42

24

23

22

21

20

19

RT8205LZQW _WQFN24_4 X4

BST_5V

UG_5V

LX_5V

LG_5V

2.2_0603_5%

1 2

VL

Typ: 175mA

+5VALW P +5VALW

RT8205_B+

12

PC23

PC21

4.7U_0805_25V6-K

SPOK <54>

PR45

PC28

0.1U_0603_25 V7K

1 2

RT8205 TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP)

TPS51125A TONSEL=VREF (1) SMPS1=245KHZ ( +5VALWP) (2) SMPS2=305KHZ(+ 3VALWP)

+5VALWP Imax=11.1A ; Ipeak=13.32A 1/2 Delta I=1.33A (F=300K Hz) Vtrip=0.098V Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical) Ilimit_min=0.098/7m=14.03A Ilimit_max=0.098/5.1m=19.21A Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A

2014/07/ 01

2

12

PC26

PC25

0.1U_0603_25V7K

2200P_0402_50V7K

AO4456_SO8

578

3 6

5

4

Title

3VALWP/5VALWP

Size Document Num ber Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

PJ3

2

112

JUMP_43X118@

PJ4

2

112

JUMP_43X118

@

PQ9

PQ9 AO406AL_SO8

AO406AL_SO8

241

PL4

12

PL4

1 2

PR47

4.7_1206_5%

PC33

680P_0603_50V7K

LA-8692P

LA-8692PLA-8692P

1

4.7UH_VMPI1004A R-4R7M-Z01_10A_20%

786

PQ11

123

PC31

1U_0603_10V6K@

12

PC32

150U_B2_6.3VM_R35M

55 66

1

+

2

+5VALWP

1

+

PC34

2

150U_B2_6.3VM_R35M

0.2

A

Freq= 266~314KHz , 290KHz(typ)

Iocp=13.58A~23.10A

PR59

0_0402_5%

1 1

2 2

FBVDDQ_PWR_EN

SUSP#

3 3

Freq= 266~314KHz , 290KHz(typ)

Iocp=12.25A~20.77A

4 4

SYSON<45>

1 2

PR67

0_0402_5%

1 2

PR68

0_0402_5%@

1 2

DGPU_PWROK<19,27,59>

A

@

PR60

@PR69

@

PR69

47K_0402_5%

12

PC44

1 2

47K_0402_5%

1 2

SUSP#<32,45,52,56,58,59>

.1U_0402_16V7K

12

PR63

PR65

1 2

12

11.5K_0402_1%

PR66

PR66 10K_0402_1%

10K_0402_1%

@

12

PC54

.1U_0402_16V7K

12

PR72

75K_0402_1%

PR74

1 2

12

11.5K_0402_1%

PR76

PR76 10K_0402_1%

10K_0402_1%

PR82

0_0402_5%

1 2

PR83

0_0402_5%@

1 2

12

PC64

PR64

84.5K_0402_1%

1 2

PR73

1 2

+5VALW

12

34

PQ22B

5

1U_0603_10V6K@

1

2

3

4

5

470K_0402_1%

1

PGOOD

2

TRIP

3

EN

4

VFB

5

RF

TPS51212DSCR_SON10_3X 3

470K_0402_1%

PR78

PR78 10K_0402_1%

10K_0402_1%

2N7002KDW-2N_SOT363-6

B

PU5

PGOOD

TRIP

EN

VFB

RF

TPS51212DSCR_SON10_3X 3

VFB=0.7V

PU6

VBST

DRVH

V5IN

DRVL

VBST

DRVH

V5IN

DRVL

SW

TP

10

9

8

SW

7

6

11

TP

10

9

8

7

6

11

VFB=0.7V

+5VALW

PQ22A

2

B

C

PQ16

AO4406AL 1N SO8

241

786

PQ17

AO4456 1N SO8

123

12

PR80

0_0402_5%@

PR84

0_0402_5%@

Deciphered Date

C

1.5V_B+

12

PC39

10U_0805_25V6K

S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A

1 2

12

@PR62

@

PR62

4.7_1206_5%

@PC48

@

12

PC48

1000P_0603_50V7K

1.5VSP_VGA_B+

12

PC49

10U_0805_25V6K

PL6

1UH_PCMC063T-1R0M N_11A_20%

1 2

12

PR71

4.7_1206_5%

12

PC59

1000P_0603_50V7K

PR77

PC62

1 2

470K_0603_5%@

2

G

470K_0603_5%@

13

D

2N7002KW_S OT323-3

S

1U_0603_10V6K

578

PC45

PR61

2.2_0603_5%

1 2

BST_1.5V

DH_1.5V

LX_1.5V

DL_1.5V

BST_1.5VSP_VGA

DH_1.5VSP_VGA

LX_1.5VSP_VGA

DL_1.5VSP_VGA

12

PR79

PR79 100K_0402_1%

100K_0402_1%

1 2

61

2N7002KDW-2N_SOT363-6

12

PR70

2.2_0603_5%

1 2

BST_1.5VSP_VGA-1

12

1U_0603_10V6K

12

PC60

10U_0805_25V6K

PR81

100K_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

0.22U_0603_16V7K

BST_1.5V-1

+5VALW

PC47

1U_0603_10V6K

PC55

0.22U_0603_16V7K

1 2

+5VALW

PC57

+1.05VS

12

PC63

0.01u_0603_10V6K

PC45

1 2

PQ18

AO4456 1N SO8

PQ20

4

PQ18

PQ19

MDV1525URH 1N PD FN33-8

S TR AON6784 1N DFN

8 7 6 5

SUSP<10,38,52,58>

2012/07/01

3 6

5

4

5

4

5

4

+1.05VS_VGA

1 2

12

3

PC61

10U_0805_25V6K

1 2

LC Future Center Secret Data

12

PC40

10U_0805_25V6K

PL5

12

PC50

10U_0805_25V6K

PJ10

2

JUMP_43X118@

PQ21

@

PQ21

@

2014/07/01

PJ6

2

JUMP_43X118@

12

PC43

PC42

PC41

0.1U_0402_25V6

PC43

470P_0603_50V7K

2200P_0402_50V7K

D

112

B+

+1.5VP

1

+

PC46

2

PJ7

220U_B2_6.3VM_R15M

12

PC51

PC52

0.1U_0402_25V6

12

PC53

2200P_0402_50V7K

+1.5VP

470P_0603_50V7K

PJ8

2

JUMP_43X118@

2

112

JUMP_43X118@

112

B+

+1.5V

+1.5VSP_VGA

1

+

PC56

1 2

2

PC58

0.1U_0402_10V7K

220U_B2_6.3VM_R15M

112

0.1U_0402_10V7K

+1.5VSP_VGA

PR75

0_0402_5%

+1.05VS_VGA+1.05VS

Title

1.5VP/1.5VSP_VGA/1.05VSP_VGA

Size D ocument Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

12

PJ9

2

JUMP_43X118@

LA-8692P

LA-8692PLA-8692P

D

112

+1.5VS_VGA

VDDQ_SENSE <25>

56 66

0.2

5

VID [0] VID[1] VCCSA Vout 0 0 0.9V 0 1 0.8V 1 0 0.725V 1 1 0.675V

output voltage adjustable netw ork

D D

1

PC77

2

2200P_0402_50V7K

+VCCSA_PWR_SRC

2200P_0402_50V7K

PJ12

+3VALW

C C

2

112

JUMP_43X118@

2

PC78

1 2

0.1U_0603_25V7K

2

PC79

PC80

1

10U_0805_6.3V6M

2.2U_0603_10V7K

+VCCSA_PWR_SRC

4

PC66

1 2

PC81

0.22U_0402_10V6K

SA_PGOOD<45>

+5VALW

12

3300P_0402_50V7K

10_0402_1%

19

20

21

22

23

24

PC82

PR88

PU7

12

PGND

VIN

4.99K_0402_1%

+3VS

12

PR86

100K_0402_5%

+VCCSA_PWRGD

PC65

1 2

1U_0603_10V6K

12

18

16

17

V5FILT

V5DRV

PGOOD

TPS51461RGER_QFN24_4X4

COMP

GND

VREF

3

1

2

12

PR94

PC83

0.01U_0402_25V7K

3

PR85

1K_0402_1%

12

H_VCCSA_VID1 <10>

12

+VCCSA_BT

+VCCSA_PHASE

@ PR92

@

33K_0402_5%

H_VCCSA_VID0 <10>

PR89

0_0402_5%

1 2

PR90

2.2_0603_5%

1 2

PR92

12

+VCCSA_BT_1

12

PC68

1000P_0603_50V7K

12

PR91

4.7_1206_5%

+V1.05S_VCCP_PWRGOOD <52,58>

PC67

0.22U_0603_16V7K

1 2

PR87

1K_0402_1%

+VCCSA_VID0

+VCCSA_VID1

15

VID1

SLEW

4

1 2

+VCCSA_EN

13

14

EN

VID0

12

BST

11

SW

10

SW

9

SW

8

SW

7

SW

25

TP

VOUT

MODE

5

6

+VCC_SAP TDC 4.2A Peak Current 6 A OCP current 7.2 A

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

PL7

0.47UH_FDVE0630-H-R47M=P3_17.7A_20%

1 2

2

+VCCSAP

1 2

PAD-OPEN 4x4m

1

PJ11

+VCCSA

+VCCSAP

@

PC69

1 2

22U_0805_6.3V6M

12

PC70

1 2

PC71

0.1U_0402_10V7K

22U_0805_6.3V6M

PR93

100_0402_5%

PR95

0_0402_5%

PC73

PC72

1 2

22U_0805_6.3V6M

12

1 2

22U_0805_6.3V6M

@

12

PC74

2200P_0402_50V7K

+VCCSA_SENSE <10>

@

PC75

PC76

1 2

22U_0805_6.3V6M

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

VCCSAP/1.05S_VCCPP

Size Document Number Rev

C

Tuesday, June 05, 2012

Date: Sheet of

LA-8692P

LA-8692PLA-8692P

1

57 66

0.2

5

PL8

HCB1608KF-12 1T30_0603

+5VALW

D D

1 2

SUSP#<32,45,52,56,58,59>

C C

0.75VR_EN#<52>

SUSP<10,38,52,56>

PR105

0_0402_5%

PC100

0.1U_0402_25V6

0_0402_5%

1 2

12

PR114

1 2

10_0402_1%

PR111

1 2

PR112

1 2

SUSP#

B B

VCCIO_SENSE< 9>

A A

+V1.05S_VCCP_PW RGOOD<52,57>

5

PR98

1 2

0_0402_5%

PR106

10.7K_0402_1%

1 2

12K_0402_1%

PC109

1 2

1.8VSP_VIN

12

PC84

PC84 22U_0805_6 .3VAM

22U_0805_6 .3VAM

EN_1.8VSP

1M_0402_5%

0_0402_5%@

1 2

47K_0402_1 %

1 2

12

10K_0402_1%@

1 2

PR108

PR108 0_0402_5%

0_0402_5%

1 2

PC104

0.01U_0402_2 5V7K

@PR116

@

PR116

1 2

1000P_0402_50V7K

PR99

PR102

PR103

PC97

.1U_0402_16V7K@

0_0402_5%

1 2

4

1 2

12

PC96

0.1U_0402_10V7K

PU10

1

VREF

2

REFIN

3

GSNS

4

VSNS

PC107

1 2

0.01U_0402_2 5V7K

PR117

1 2

10_0402_1%

PC110

PC110 1000P_0402 _50V7K

1000P_0402 _50V7K

4

PU8 SY8033BDBC_DFN1 0_3X3PU8 SY8033BDBC_DFN1 0_3X3

4

10

PVIN

PG

9

PVIN

8

SVIN

5

EN

TP

NC

7

11

@PC89

@

12

PC89

0.1U_0402_10V7K

13

D

PQ23

2

G

PQ23

2N7002KW _SOT323-3

S

+3VS

PR107

1 2

100K_0402_1%

PR109

100K_0402_1%

1 2

16

15EN14

17

PAD

MODE

PGOOD

TPS51219RTE R_QFN16_3X3

COMP5TRIP6GND

7

12

PR115

54.9K_0402_1%

3

PL9

1UH_PH041H-1 R0MS_3.8A_20%

2

1.8VSP_LX

LX

3

LX

6

FB

NC

1

FB=0.6Volt

1UH_PH041H-1 R0MS_3.8A_20%

12

+1.5V

1

PJ15

1

JUMP_43X118

@

2

PC90

4.7U_0805_6.3 V6K

1 2

PR110

0_0603_5%

1 2

BST_1.05VS_V CCP

13

BST

12

SW

11

DH

10

DL

9

V5

PGND

8

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

PR101

1K_0402_1%

LX_1.05VS_VC CP

DH_1.05VS_VC CP

12

PR104

0.1U_0603_25 V7K

PL9

1 2

20K_0402_1 %

PR96

4.7_1206_5%

PC86

1.8VSP_FB

680P_0603_50V7K

10K_0402_1 %

12

PC95

1K_0402_1%

0.1U_0402_16V4Z

PC103

1 2

DL_1.05VS_VC CP

12

PC108

1U_0603_10 V6K

2012/07/ 01

3

PR97

PR100

12

PC93

10U_0603_6.3V6M

+5VALW

12

PC85

12

68P_0402_50V8J

PC87

PU9

1

VIN

2

GND

3

VREF

4

VOUT

APL5336KAI-TRL_ SOP8P8

VCNTL

8

NC

7

NC

6

5

NC

9

TP

+0.75VSP

PC94

10U_0603_6.3V6M

5

4

123

PQ25

5

4

123

LC Future Center Secret Data

Deciphered Date

12

22U_0805_6.3VAM

12

1.05VS_B+

PQ24

AON6428L_DF N8-5

12

AON6504 1N DFN

12

2

+1.8VSP

PC88

22U_0805_6.3VAM

+3VALW

PC91

1U_0603_10 V6K

12

PC101

0.1U_0402_25V6

1UH_PCMB062 D-1R0MS_9A_20%

1 2

PR113

4.7_1206_5%

PC106

1000P_0603_50V7K

2014/07/ 01

2

+1.05VS_VCCPP OCP(min)=22.38A

PJ18

2

JUMP_43X118@

12

PC102

4.7U_0805_25V6-K

1

+

2 3

Title

1.8VSP/0.75VSP/1.05VS_VCCPP

Size Document Num ber Rev

Custom

Date: Sheet of

PC98

PL10

12

PC99

4.7U_0805_25V6-K

2200P_0402_50V7K

112

330U_D2_2VM_R6M

PC105

Tuesday, June 05, 2012

PJ13

2

112

JUMP_43X118

@

PJ14

2

112

JUMP_43X118@

PJ16

2

112

JUMP_43X118@

JUMP_43X118@ PJ17

PJ17

2

112

JUMP_43X118@

B+

+1.05VS_VCCPP

1

+1.05VS+1.05VS_VCCP P

LA-8692P

LA-8692PLA-8692P

1

+1.8VS+1.8VSP

+0.75VS+0 .75VSP

58 66

B+

1

+

@

PC92

2

68U_25V_M_R0.36

0.2

A

+VDD33MISC

B

C

D

GL1:0.9V(110000) GT:0.975V(101010)

2012/04/26

1 1

DGPU_PWROK

2 2

PR337

1 2

4.02K_0402_1%

@PR338

@

PR338

1 2

249K_0402_1%

3 3

PC394

150P_0402_50V8J

4 4

change PC352 from @ to Mount

2012/04/26 change PR313 from 0 to 75K

DPRSLPVR_VGA<23,59>

+3VS

PR331

PR331 0_0402_5%

0_0402_5%

1 2

DPRSLPVR_VGA<23,59>

VGA_AC_DET<23,32,45>

470K_0402_5%_TSM0B474J4702RE

1 2

PH8

12

PC383

PR339

8.06K_0402_1%

1000P_0402_50V7K

PC385

47P_0402_50V8J

1 2

FB2_VGA

PR344

267K_0402_1%

+VGA_CORE

VCCSENSE_VGA<24>

VSSSENSE_VGA<24>

+3VS

PR330

NVDD_PWR_EN<18>

1 2

0_0402_5%

1 2

10K_0402_1%

1.91K_0402_1%

1 2

12

1.91K_0402_1%

+3VS

PR340

499_0402_1%

1 2

PR341

1.58K_0402_1%

1 2

12

PR347

PR347 75K_0402_1%

75K_0402_1%

SUSP#<32,45,52,56, 58>

PR316

@PR316

@

PR317

PR329

@PR329

@

100K_0402_1%

1 2

PR333 0_0402_5%PR333 0_0402_5%

PR334

147K_0402_1%

PR335

100K_0402_5%@

1 2

PR336

@PR336

@

0_0402_5%

VW_VGA

1 2

PC370

22P_0402_50V8J

1 2

FB1_VGA

390P_0402_50V7K

ISEN2_VGA

ISEN1_VGA

1 2

PR348

@

10_0402_1%

1 2

PR352

0_0402_5%

PR359

0_0402_5%

1 2

PR360

@

10_0402_1%

1 2

A

PR313

PR313 75K_0402_1%

75K_0402_1%

1 2

PR314

0_0402_5%

1 2

PC352 .1U_0402_16V7KPC352 .1U_0402_16V7K

DPRSLPVR_VGA-1

CLK_ENABLE#_VGA

RB751V-40_SOD323-2

PR332

12

PSI#_VGA

RBIAS_VGA

COMP_VGA

FB_VGA

ISEN3_VGA

PC384

12

PC396

0.22U_0402_10V6K

VSUM-_VGA

PC405

330P_0402_50V7K

PC410

1000P_0402_50V7K

12

@PR314

@

PD8

1 2 3 4 5 6 7 8 9

10

41

VSEN_VGA

PC397

VRON_VGA

@PD8

@

PU18

PGOOD PSI# RBIAS VR_TT# NTC VW COMP FB ISEN3 ISEN2

AGND

0.22U_0402_10V6K

12

PR312

0_0402_5%

12

@PC411

@

PC411

38

39

40

VR_ON

CLK_EN#

DPRSLPVR

ISEN111VSEN12RTN13ISUM-14ISUM+15VDD

RTN_VGA

12

330P_0402_50V7K

1 2

GPU_VID6

37

ISUM-_VGA

12

VSUM_VGA_N001

12

1 2

PR300 10K_0402_1%PR300 10K_0402_1%

GPU_VID5

35

VID4

VIN

17

16

VDD_VGA

12

PC398

@PR349

@

PR349

82.5_0402_5%

@PC412

@

PC412

0.01U_0402_25V7K

PR361

1.33K_0402_1%

1 2

PR301 10K_0402_1%@PR301 10K_0402_1%

PR303 10K_0402_1%@PR303 10K_0402_1%

PR302 10K_0402_1%PR302 10K_0402_1%

GPU_VID3

GPU_VID4

@

GPU_VID4

GPU_VID5

PR318

PR319

0_0402_5%

1 2

VID031VID132VID233VID334VID536VID6

30

BOOT2

29

UGATE2

28

PHASE2

27

VSSP2

26

LGATE2

25

VCCP

24

PWM3

23

LGATE1

22

VSSP1

21

PHASE1

IMON18BOOT119UGATE1

ISL62883CHRTZ-T_TQFN40_5X5

20

PR343 0_0402_5%PR343 0_0402_5%

1 2

VIN_VGA

PR346

1_0402_5%

1 2

12

PC399

1U_0603_10V6K

0.22U_0603_25V7K

12

PC406

0.22U_0603_10V7K

1 2

PR304 10K_0402_1%PR304 10K_0402_1%

PR305 10K_0402_1%@PR305 10K_0402_1%

1 2

PR306 10K_0402_1%@PR306 10K_0402_1%

PR307 10K_0402_1%PR307 10K_0402_1%

1 2

PR310 10K_0402_1%@PR310 10K_0402_1%

PR308 10K_0402_1%@PR308 10K_0402_1%

PR309 10K_0402_1%PR309 10K_0402_1%

PR311 10K_0402_1%PR311 10K_0402_1%

PQ801@GL1

GPU_VID2

GPU_VID1

GPU_VID0

@

<23>

GPU_VID1

GPU_VID2

GPU_VID3

PR320

PR322

PR321

0_0402_5%

1 2

+VGA_B+

+5VS

PC407

0.022U_0603_25V7K

0_0402_5%

1 2

PC395

12

PC414

0.1U_0402_16V7K

0_0402_5%

1 2

PC357

PC357 1U_0603_10V6K

1U_0603_10V6K

12

0.068U_0402_16V7K

12

PR358

11K_0402_1%

GPU_VID3

GPU_VID5

GPU_VID4

@

<23>

GPU_VID0

PR323

0_0402_5%

1 2

+5VS

PC371

PC371 1U_0603_10V6K

1U_0603_10V6K

PR342 0_0402_5%@PR342 0_0402_5%@

1 2

VGA_IMON <45>

PR345

1 2

11.8K_0402_1%

VSUM+_VGA

12

PR351

2.61K_0402_1%

NTC_VGA

12

PH9

PH9 10K_0402_1%_TSM0A103F34D1RZ

10K_0402_1%_TSM0A103F34D1RZ

Layout Note: Place near Phase1 Choke

VSUM-_VGA

B

GPU_VID2

GPU_VID1

GPU_VID0

@

<23>

BOOT2_VGA BOOT2_2_VGA

PR315

2.2_0603_5%

12

+VGA_CORE

+5VS

BOOT1_VGA

UGATE1_VGA

PR350

2.2_0603_5%

PHASE1_VGA

LGATE1_VGA

PQ802@GL1

5

4

PC351

0.22U_0603_10V7K

1 2

UGATE2_VGA

LGATE2_VGA

PQ52

5

4

123

5

4

AON6504 1N DFN

123

Under VGA Core

12

PC358

4.7U_0603_6.3V6M

12

PC372

4.7U_0603_6.3V6M

12

PC386

0.1U_0402_10V7K

12

PC360

PC359

PC373

PC389

PC361

4.7U_0603_6.3V6M

0.1U_0402_10V7K

4.7U_0603_6.3V6M

12

PC375

PC374

4.7U_0603_6.3V6M

12

PC391

PC390

0.1U_0402_10V7K

PQ806@GL1 PQ808@GL1

PC404

0.22U_0603_10V7K

12

BOOT1_1_VGA

0.22U_0603_10V7K

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

12

PC362

4.7U_0603_6.3V6M

12

PC376

4.7U_0603_6.3V6M

12

PC387

0.1U_0402_10V7K

4

2012/07/01

C

12

PC364

PC365

PC363

PC377

PC388

5

PC365

4.7U_0603_6.3V6M

0.1U_0402_10V7K

4.7U_0603_6.3V6M

12

PC378

4.7U_0603_6.3V6M

12

PC393

PC392

0.1U_0402_10V7K

5

4

PQ55

5

4

AON6504 1N DFN

123

LC Future Center Secret Data

Deciphered Date

+VGA_B+

12

PC347

PC348

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

PQ51

AON6428L_DFN8-5

PHASE2_VGA

PQ53

@PR324

@

PR324

AON6504 1N DFN

@PC356

@

PC356

PC818 PC825,PC827,PC8 28,PC829 PC839,PC841,PC8 44,PC845

PQ54

PC520

1000P_0402_50V7K

AON6428L_DFN8-5

123

PQ56

123

AON6504 1N DFN

2200P_0402_50V7K

12

4.7_1206_5%

SNUB2_VGA

12

680P_0402_50V7K

12

PC400

@PR355

@

PR355

@PC413

@

PC413

12

0.1U_0402_25V6

12

4.7_1206_5%

SNUB1_VGA

12

680P_0402_50V7K

12

PR325

3.65K_0402_1%

VSUM+_VGA

+VGA_CORE

12

PC401

2200P_0402_50V7K

2014/07/01

12

PC349

PC350

10U_0805_25V6K

PL23

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

12

ISEN2_VGA

PL23

1

2

PR326

10K_0402_1%

Near VGA Core

1

12

PC367

PC366

2

22U_0805_6.3V6M

12

PC379

PC380

4.7U_0805_6.3V6K

+VGA_B+

12

PC403

PC402

10U_0805_25V6K

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

LF1_VGA

12

PR353

PR356

10K_0402_1%

3.65K_0402_1%

ISEN1_VGA

VSUM+_VGA

Title

VGA_COREP

Size Document Number Rev

C

Date: Sheet of

HCB4532KF-800T90_1812

1 2

4

3

12

ISEN1_VGA

1

12

PC368

2

47U_0805_6.3V6M

22U_0805_6.3V6M

12

PC381

4.7U_0805_6.3V6K

PL24

4

3 <BOM Structure>

Tuesday, June 05, 2012

PL22

V2N_VGALF2_VGA

12

PR328

1

1_0402_1%

PR327

10K_0402_1%

PC369

4.7U_0805_6.3V6K

PC382

4.7U_0805_6.3V6K

V1N_VGA

12

PR354

10K_0402_1%

ISEN2_VGA

D

VSUM-_VGA

12

PR357

VSUM-_VGA

LA-8692P

LA-8692PLA-8692P

2

1_0402_1%

LA-8692P

+

PC353

1

+

2

1

+

2

470U_D2_2VM_R9M

1

+

PC408

2

470U_D2_2VM_R9M

59 66

PC354

470U_D2_2VY_R9M

PC409

B+

+VGA_CORE

1

+

PC355

2

+VGA_CORE

470U_D2_2VM_R9M

470U_D2_2VY_R9M

0.2

5

PC174

PR188

VGATE<16,6>

PR247

1K_0402_1%

CPU2@

0.033u_0402_16V7K

1 2

FBA3

VR_RDYA

PC191

PR216

54.9_0402_1%

1 2

PR220

1 2

PC174

GFX@

PC178

0.033u_0402_16V7K

GFX@

12

.1U_0402_16V7K

0_0402_5%

PR238

10_0402_1%

8.06K_0402_1%

CPU3@ PR247

CPU3@

3P: 806 2P: 1K

FBA1

12

VR_SVID_DAT1

+3VS

12

PR227

PR227 10K_0402_5%

10K_0402_5%

FB_CPU3

PR241

1 2

PR247

1 2

806_0402_1%

PR189

1 2

806_0402_1%

GFX@

+3VS

12

VR_ON<45>

CPU_B+

PR222 1K_0402_1%PR222 1K_0402_1%

PR229

1 2

0_0402_5%

PR232

1 2

0_0402_5%

49.9_0402_1%

PC204

1 2

0.033u_0402_16V7K

FB_CPU2

PC207

DROOP

PR186

10_0402_1%

1 2

GFX@

D D

TRBSTA#

C C

PC190

VR_SVID_DAT<9>

VR_SVID_ALRT#<9>

VR_SVID_CLK<9>

GFX@

1 2

8.06K_0402_1%

GFX@

VCC_AXG_SENSE<10>

VSS_AXG_SENSE<10>

+1.05VS

12

PR215

.1U_0402_16V7K

130_0402_1%

1 2

+1.05VS

12

PR226

PC196

@PC196

@

43P_0402_50V7K

75_0402_1%

VR_HOT#<45>

VSSSENSE<9>

VCCSENSE<9>

B B

A A

1 2

TRBST#

5

PR193

1 2

10_0402_1%

GFX@

PR195

1 2

1K_0402_1%

GFX@

PR210

PR210 10K_0402_1%

10K_0402_1%

+5VS

PR221

95.3K_0402_1%

1 2

12

PR236

1 2

12

0.033u_0402_16V7K

PC212

1 2

1000P_0402_50V7K

4

GFX@

1 2

FBA2

560P_0402_50V7K

1000P_0402_50V7K

PR213

1 2

2_0603_5%

PC188

1 2

2.2U_0603_10V7K

2.2U_0603_10V7K PR217

PR217

1 2

0_0402_5%

PR219

1 2

10K_0402_1%

12

PC194

VSN

PC197

PC197 1000P_0402_50V7K

1000P_0402_50V7K

VSP

PR234

1 2

1K_0402_1%

PC202

1 2

FB_CPU1

470P_0402_50V7K

PR242

1 2

806_0402_1%

PR244

24.9K_0402_1%

CPU2@

CSREFCSCOMP

4

PC180

0.01U_0402_25V7K

PC184

GFX@

6132_VCC

VR_ON_CPU

VBOOT

DIFF_CPU

10P_0402_50V8J

CPU2@

PR237

IMVP_IMON<45>

PR190

0_0402_1%

SLI@

2P: 24K 1P: 24.9K

PR196

1 2

5.11K_0402_1%

GFX@

2P: 21.5K 1P: 15.8K

1 2

VR_RDYA

VR_SVID_DAT1 VR_SVID_ALRT# VR_SVID_CLK

ROSC_CPU VRMP VR_HOT# VGATE

PC200

3P: 22p 2P: 10p

CPU3@ PC200

CPU3@

12

COMP_CPU1

6.04K_0402_1%

3P: 23.7K 2P: 24.9K

PC181

1 2

10P_0402_50V8J

COMPA1

2200P_0402_50V7K

PR202

1 2

0_0402_5%

SLI@

PR207

SLI@

1 2

0_0402_5%

PU14

1

VCC

2

VDDBP

3

VRDYA

4

EN

5

SDIO

6

ALERT#

7

SCLK

8

VBOOT

9

ROSC

10

VRMP

11

VRHOT#

12

VRDY

13

VSN

14

VSP

15

DIFF

PC200

12

22P_0402_50V8J

2200P_0402_50V7K

CPU3@

PR244

1 2

PUT COLSE TO VCORE Phase 1 Inductor

PC175

1 2

.1U_0402_16V7K

1 2

PR190

GFX@

24K_0402_1%

GFX@

GFX@PC181

GFX@

PC182

1 2

0_0402_5%

PR199

SLI@ PR199

SLI@

FBA

DIFFA

TRBSTA#

COMPA

IMONAIMONA

54

57

59

58

56

55

60

61

FBA

PAD

VSPA

VSNA

DIFFA

COMPA

TRBSTA#

NCP6132AMNR2G_QFN60_7X7

COMP

DROOP21FB

IOUT

ILIM

TRBST#

18

17

19

20

16

FB_CPU

TRBST#

COMP_CPU

DROOP

ILIM_CPU

CPU3@

1 2

PC203

12

PR233 21K_0402_ 1%

CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP

1 2

PC209

23.7K_0402_1%

.1U_0402_16V7K

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

3

GFX@

1 2

PC176

1200P_0402_50V7K

12

1 2

GFX@

PR197

0_0402_5%SLI@

1 2

GFX@PR203

GFX@

PC185

1000P_0402_50V7K

1000P_0402_50V7K PR204

PR204

1 2

0_0402_5% SLI@

CSCOMPA

PR203

1 2

21.5K_0402_1%

DROOPA

CSSUMA

ILIMA

52

49

50

48

53

51

ILIMA

IOUTA

CSP2A

CSREFA

CSSUMA

DROOPA

CSCOMPA

CSCOMP22CSP325CSREF24CSSUM

CSP1

CSP2

TSNS

23

27

26

28

TSENSETSENSE CSP2A

3P: 21K 2P: 12.4K

PC205

PC205 1000P_0402_50V7K

1000P_0402_50V7K

1 2

PC969@QC

PR248

1 2

NTC_PH201

75K_0402_1%

PH7

220K_0402_5%_ERTJ0EV224J

Issued Date

3

GFX@

1 2

GFX@

PC177

330P_0402_50V8J

PR194

165K_0402_1%

PR198

SWN2A

91K_0603_1%

SWN1A

PR200

91K_0603_1% GFX@

GFX@PC185

GFX@

12

PR205

12

0_0402_5% SLI@

PR208

12

0_0402_5%

1 2

CSP1A

PC187

.1U_0402_16V7K

TSENSEA

PR211

0_0402_5%

46

47

SLI@

CSP1A

TSNSA

45

PWMA

44

BSTA

43

HGA

42

SWA

41

LGA

40

BST2

39

HG2

38

SW2

37

LG2

36

PVCC

35

PGND

34

LG1

33

SW1

32

HG1

31

BST1

DRVEN

PWM

29

30

1 2

PC198

1 2

.1U_0402_16V7K

CSP1 CSP2 CSP3

CSSUM

PC208

CPU3@PC208

CPU3@

1 2

1500P_0402_50V7K

1 2

PC210

PC210 330P_0402_50V7K

330P_0402_50V7K

1 2

PC211

PC211 330P_0402_50V7K

330P_0402_50V7K

1 2

165K_0402_1%

12

GFX@

PR191

75K_0402_1%

1 2

12

NTC_PH203

2P: install 1P: @

CSREFA <61>

SLI@PR208

SLI@

GFX@

12

BST2

6132P_VCCP

BST1

PR228

73.2K_0402_1%

CPU3@

PR233

12.4K_0402_1%

CPU2@

CSREF <61>

3P: 1500p 2P: 1200p

PR249

2012/07/01

12

PH4

220K_0402_5%_ERTJ0EV224J

GFX@

CSREFA

CSP1A

CSREFA

CSP2A

+5VS

PR212

1 2

36K_0402_1%

GFX@

BSTA1

HG1A <61>

LG1A <61>

HG2 <61>

LG2 <61>

1 2

0_0402_5%

LG1 <61>

HG1 <61>

3P: 73.2K 2P: 41.2K

6132_PWM <61>

DRVEN <61>

PC208

1200P_0402_50V7K

CPU2@

LC Future Center Secret Data

PUT COLSE TO GT Inductor

PC183

0.047U_0402_16V7K

GFX@

PR201 5.49K_0402_1%

1 2

PC186

0.047U_0402_16V7K

1 2

GFX@

2P: 36K 1P: 26.1K

PR214

1 2

BSTA1_1

2.2_0603_5%

GFX@

1 2

BST2_1

PR218

4.7_0603_5%

PR223

1 2

BST1_1

PR225

4.7_0603_5%

PR228

41.2K_0402_1%

CPU2@

CSP3CSP3

PR268

CSREF

@ PR268

@

1 2

21K_0402_1%

PR269

CSREF

@ PR269

@

1 2

21K_0402_1%

PR270

@ PR270

@

1 2

CSREF

PR243

1 2

130K_0603_1%

130K_0603_1% PR245

PR245

1 2

130K_0603_1%

PR246

1 2

130K_0603_1%

CPU3@

3P: install 2P: @

Deciphered Date

2

GFX@

1 2

2P: install 1P: @

1 2

PR209

5.49K_0402_1%

GFX@

6132_PWMA <61>

PC189

12

GFX@

0.22U_0603_10V7K

0.22U_0603_10V7K PC192

PC192

12

0.22U_0603_10V7K

12

PC193

2.2U_0603_10V7K

12

PC195 0.22U_0603_10V7KPC195 0.22U_0603_10V7K

CPU3@

1 2

PR231

12

6.98K_0402_1%

PC199

0.047U_0402_16V7K

CSP2

12

PC201

0.047U_0402_16V7K

CSP1

12

PC206

0.047U_0402_16V7K

21K_0402_1%

SWN1

SWN2

SWN3

2

CSCOMPA

SWN1A <61>

SWN2A <61>

3P: install 2P: @

1 2

PR235

6.98K_0402_1%

PR239

1 2

6.98K_0402_1%

2014/07/01

+5VS

PR192

0_0402_1%

SLI@

1 2

1.65K_0402_1%

2P: 1.65K 1P: 1K

SW1A <61>

SW2 <61>

SW1 <61>

SWN3 <61>

SWN2 <61>

SWN1 <61>

1

GFX@

PR192

GFX@

PC179

1 2

1000P_0402_50V7K

TSENSEA

12

PR206

8.25K_0402_1%

@

PUT COLSE TO V_GT HOT SPOT

CSREFADROOPA

PH5

100K_0402_1%_TSM0B104F4251RZ

1 2

GFX@

+5VS

0_0402_5%

2Phase: @ 1Phase: install

Option for 1 phase GFX

CSP2A

12

@PR224

@

PR224

+5VS

Option for 2 phase CPU

Title

CPU_CORE

Size Document Number Rev

Custom

Date: Sheet of

12

PR230

CPU2@

CSP3

TSENSE

12

PH6

100K_0402_1%_TSM0B104F4251RZ

PR240

1 2

8.25K_0402_1%

@

PUT COLSE TO VCORE HOT SPOT

Tuesday, June 05, 2012

0_0402_5%

LA-8692P

LA-8692PLA-8692P

1

3Phase: @ 2Phase: install

60 66

0.2

5

4

3

2

1

CPU_B+

5

PQ27

9

8

7

6

5

BST3_1

4

PC228

0.22U_0603_10V7K

1 2

CPU3@

HG3

SW3

LG3

123

5

123

AON6504 1N DFN

AON6428L_DFN8-5

PQ29

AON6504 1N DFN

PQ32

5

4

123

5

4

123

HG1<60>

D D

SW1<60>

LG1<60>

PR254

1 2

BST3

4.7_0603_5%

CPU3@

PU15

1

BST

C C

6132_PWM<60>

DRVEN<60>

+5VS

CPU3@

PR255

PR255 2K_0402_1%

2K_0402_1%

PR256

12

0_0402_5% CPU3@

PC233

2.2U_0603_10V7K

CPU3@

12

EN_CPU3

12

VCC_CPU3

FLAG

2

PWM

DRVH

3

EN

SW

4

VCC

GND

DRVL

NCP5911MNTBG_DFN8_2X2

CPU3@

3Phase: install 2Phase:: @

12

PC213

PC521

1000P_0402_50V7K

12

PR250

4.7_1206_5%

SNUB_CPU1

12

PC226

680P_0402_50V7K

PQ31

CPU3@

AON6428L_DFN8-5

CPU3@PQ32

CPU3@

12

10U_0805_25V6K

12

CPU3@

SNUB_CPU3

12

CPU3@

12

PC215

PC216

PC214

4.7_1206_5%

680P_0402_50V7K

PC216

10U_0805_25V6K

0.1U_0402_25V6

PL15

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

1

2

PC229

10U_0805_25V6K

PR257

PC234

12

2200P_0402_25V7K

4

3

12

CPU3@

PL17

1

2

PC230

10U_0805_25V6K

CPU3@

V1N_CPU

+VCC_CORE

PR252

10_0402_1%

CPU_B+

12

PC232

PC231

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_25V7K

2200P_0402_25V7K

CPU3@

4

3

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

V3N_CPU

2012/03/02 change PC222 from OS-cap to D2 size

B+

12

+VCC_CORE

CPU3@

PR258

10_0402_1%

CPU3@

12

1

+

PC221

2

470P_0603_50V7K

CSREF <60>

SWN1 <60>

CSREF

HCB4532KF-800T90_1812

PC222

68U_25V_M_R0.36

SWN3 <60>

PL14

1 2

CPU_B+

5

PQ28

CPU_B+

1

12

+

PC224

PC223

2

68U_25V_M_R0.36

1000P_0603_50V7K

HG2<60>

PC225

470P_0603_50V7K

SW2<60>

LG2<60>

QC 45W CPU VID1=0.9V IccMax=94A Icc_Dyn=66A Icc_TDC=52A R_LL=1.9m ohm OCP~110A

4

123

5

123

PQ28

AON6428L_DFN8-5

PQ30

AON6504 1N DFN

DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=36A R_LL=1.9m ohm OCP~65A

0.36UH_VMPI1004AR-R36M-Z03_30A_20%

12

PR251

4.7_1206_5%

SNUB_CPU2

12

PC227

680P_0402_50V7K

12

PC218

PC217

10U_0805_25V6K

PL16

1

2

12

PC220

PC219

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_25V7K

2200P_0402_25V7K

+VCC_CORE

4

3

12

PR253

10_0402_1%

CSREF

SWN2 <60>

V2N_CPU

B B

5

HG1A<60>

SW1A<60>

LG1A<60>

A A

4

GFX@

5

4

GFX@

5

PQ33

AON6428L_DFN8-5

123

PQ35

AON6504 1N DFN

123

12

PC235

10U_0805_25V6K

GFX@

12

PC236

10U_0805_25V6K

GFX@

PR261

PC245

12

PC237

PC238

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_25V7K

2200P_0402_25V7K

GFX@

PL18

0.36UH 20% PDME064T-R36MS1R405 24A

12

4.7_1206_5%@

SNUB_GFX1

12

680P_0402_50V7K@

1 2

GFX@

12

PR265

0_0402_5%

GFX@

4

+VCC_GFXCORE_AXG

12

PR267

10_0402_1%

GFX@

CSREFA <60>

SWN1A <60>

QC 45W GT2 VID1=1.23V IccMax=46A Icc_Dyn=37A Icc_TDC=38A R_LL=3.9m ohm OCP~55A

DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A

3

2Phase: install 1Phase:: @

1 2

PR259

2.2_0603_5%

GFX@

BST

FLAG

PWM

DRVH

EN

SW

VCC

GND

DRVL

Deciphered Date

2

BSTA2_1

9

8

7

6

5

PC240

0.22U_0603_10V7K

1 2

GFX@

HG2A

SW2A

AON6504 1N DFN

2014/07/01

LG2A

PQ36

4

BSTA2

PU16

1

6132_PWMA<60>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF LC F UTURE CENTER. AND CONTAINS CON FIDENTIAL AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF LC FUTURE CENT ER.

+5VS

DRVEN

GFX@

2K_0402_1%

PR262

PR262 0_0402_5%

0_0402_5%

GFX@

12

GFX@

PR260

PC244

2.2U_0603_10V7K

2012/07/01

2

12

3

EN_GFX2

12

4

VCC_GFX2

NCP5911MNTBG_DFN8_2X2

GFX@

LC Future Center Secret Data

12

PC241

PC239

5

PQ34

GFX@

AON6428L_DFN8-5

123

5

GFX@

12

PR263

4.7_1206_5%

123

SNUB_GFX2

12

680P_0402_50V7K

Title

CPU_CORE

Size Document Number Rev

C

Date: Sheet of

PC239

10U_0805_25V6K

GFX@

PL19

0.36UH 20% PDME064T-R36MS1R405 24A

1 2

GFX@

12

@PR263

@

PR264

0_0402_5%

GFX@

PC246

@PC246

@

LA-8692P

LA-8692PLA-8692P

Tuesday, June 05, 2012

LA-8692PLA-8692P

1

12

PC242

0.1U_0402_25V6

GFX@

LA-8692P

12

PC243

2200P_0402_25V7K

GFX@

+VCC_GFXCORE_AXG

10_0402_1%

GFX@

PR266

12

CSREFA

61 66

SWN2A <60>

0.2

CPU_B+CPU_B+

5

4

3

2

1

+VCC_CORE

1

PC247

10U_080 5_6.3VAM

2

D D

1

PC252

PC252 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC248

PC248 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC253

PC253 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC249

PC249 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC254

PC254 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC250

PC250 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC255

PC255 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

+CPU_CORE +VCC_GFXCORE_AXG

1

PC251

PC251 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC256

PC256 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

1

PC257

PC257 10U_080 5_6.3VAM

10U_080 5_6.3VAM

2

+VCC_GFXCORE_AXG

22U_0805_6.3V6M

PC258

1

2

PC260

PC259

1

2

22U_0805_6.3V6M

PC263

PC261

1

2

PC263

PC262

1

2

22U_0805_6.3V6M

PC265

PC264

1

2

+VCC_CORE

GFX@

1

PC266

PC266 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC290

PC290 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

C C

1

PC306

PC306 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC313

PC313 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC267

PC267 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC291

PC291 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC307

PC307 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC314

PC314 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC268

PC268 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC292

PC292 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC308

PC308 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC315

PC315 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC269

PC269 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC293

PC293 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC309

PC309 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC316

PC316 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC270

PC270 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC294

PC294 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

1

PC310

PC310 22U_080 5_6.3V6M

22U_080 5_6.3V6M

2

GFX@

22U_0805_6.3V6M

PC282

1

2

GFX@

330U_D2_2VM_R9M

1

PC303

+

2 3

GFX@

PC283

1

+

2 3

GFX@

PC284

1

2

GFX@

330U_D2_2VM_R9M

1

PC304

+

2 3

GFX@

22U_0805_6.3V6M

GFX@

22U_0805_6.3V6M

PC285

PC286

1

2

GFX@

330U_D2_2VM_R9M

PC305

GFX@

22U_0805_6.3V6M

PC287

GFX@

22U_0805_6.3V6M

PC288

PC289

GFX@

PC289

1

2

1

2

Below is 458544_CRV_PDDG_0.5 Table 5-8.

5 x 22 µF (0805)

Socket Bottom

5 x (0805) no-stuff sites

7 x 22 µF (0805)

Socket Top

2 x (0805) no-stuff sites

+1.05VS

22U_0805_6.3V6M

1

PC271

2

22U_0805_6.3V6M

1

PC272

2

+1.05VS

22U_0805_6.3V6M

1

PC273

PC274

PC275

2

22U_0805_6.3V6M

1

PC295

PC296

2

22U_0805_6.3V6M

1

2

1

2

PC277

PC276

2

22U_0805_6.3V6M

1

PC298

PC297

2

22U_0805_6.3V6M

1

PC278

2

22U_0805_6.3V6M

1

PC299

2

1

+

2 3

22U_0805_6.3V6M

1

PC279

2

1

PC300

2

330U_D2_2VM_R6M

PC311

PC281

PC280

2

22U_0805_6.3V6M

1

PC301

PC302

2

330U_D2_2VM_R6M

1

PC312

+

2 3

+VCC_CORE

1

CPU3@

+

PC317

B B

PC317

2

PC318

330U_D2_2VM_R9M

1

+

PC320

PC319

2 3

@

330U_D2_2VM_R9M

1

+

PC321

2 3

330U_D2_2VM_R9M

1

+

PC322

2 3

PC322

2

330U_D2_2VM_R9M

2012/02/29 DC:PC317, PC319, PC321, PC322 (330uF/9m +-20% *4) QC:PC317, PC318, PC319, PC321, PC322 (330uF/9m +-20% *5) P/N:SGA0000610J (no link)

A A

Title

Security Class ification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.

2012/07/ 01

3

LC Future Center Secret Data

Deciphered Date

2014/07/ 01

2

Title

CPU_CORE1

Size Do cument Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

62 66

0.2

5

<54,63>

PQ57

AO4423L 1P SO8

DTA144EUA_SC70-3

47K_0402_5%

13

2

PQ63A

PACIN

PQ67

DTC115EUA_SC70-3

PR382

1 2

10K_0402_5%

8 7

5

PQ60

2

1 3

PQ61

DTC115EUA_SC70-3

PR378

47K_0402_1%

1 2

2

ACOFF-1

12

PR387

PR387 0_0402_5%

0_0402_5%

34

PQ64B

5

2N7002KDW-2N_SOT363-6

4

VIN

D D

12

PR363

61

2

2N7002KDW -2N_SOT363-6

C C

PACIN<63>

ACOFF<45>

BATT_OUT

B B

A A

P2

1 2 36

12

PR364

PC496

0.1U_0603_25V7K

P2-1

12

P2-2

34

PQ63B

5

13

EC_SMB_DA1<45,49,54>

EC_SMB_CK1<45,49,54>

AO4423L 1P SO8

1 2 3 6

200K_0402_1%

12

PR368

PR368 20K_0402_1%

20K_0402_1%

61

PQ64A

2N7002KDW -2N_SOT363-6

PR369

150K_0402_1%

64.9K_0603_1%

1 2

PC507 .1U_0603_25V7KPC507 .1U_0603 _25V7K

2N7002KDW-2N_SOT363-6

PQ58

2

PR379

4

12

5600P_0402_25V7K

0.1U_0603_25V7K

8 7

5

PC491

1 2

PC497

@PC497

@

BATT_OUT <54,63>

VIN

12

PR374

390K_0603_1%

PR380

0_0402_5%

1 2

PR383

0_0402_5%

1 2

+3VALWP

4

P3

+3VALWP

@PR376

@

@PR375

@

PR376

PR375

10K_0402_5%

1 2

147K_0402_1%

2012/02/29 change PR362 from 1206 to 2512 size

1

2

ACPRN<55,63>

PR372

@PR372

@

39.2K_0402_1%

ADP_I<45,54>

6

ACDET

PC505

1 2

7

100P_0603_50V8

PR384

PR388

100K_0402_1%

BM#

IOUT

8

SDA

9

SCL

10

12

ILIM

B+

PR3620.01_2512_1% PR3620.01_2512_1%

ACP

@PR370

@

PR370

PR373

1 2

12

1 2

4.7M_0603_1%

5

ACOK

BQ24737RGRR_VQFN20_ 3P5X3P5

11

@PR391

@

6.8_0603_5%

PR391

0.1U_0603_25V7K

10K_0402_5%

1 2

+3VS

4

3

+3VALWP

12

PR371

100K_0402_1%

@PR373

@

3

4

CMPIN

CMPOUT

PU19

SRN12BM

SRP

12 13

12

PR389

PC513

12

PC514

0.1U_0603_25V7K

PC501

1 2

0.1U_0603_25V7K

10K_0603_1%@

PR390

10_0603_5%

1UH_PCMB061H-1R0M S_7A_20%

ACN

PC503

2

14

3

1 2

SH00000AA0J

1 2

PC492

10U_0805_25V6K@

PC502

12

0.1U_0603_25V7K

12

1

ACP

ACN

TP

VCC

PHASE

HIDRV

BTST

REGN

LODRV

GND

15

47K_0402_1%

ACPRN <55,63>

Charge Option() bit[8]=1

PL25

21

20

19

18

17

BST_CHG

PD11

RB751V-40_SOD323-2

16

12

PC512

PC512 1U_0603_25V6

1U_0603_25V6

12

PR393

1 2

PC493

10U_0805_25V6K@

10_1206_5%

1 2

DH_CHG

12

BQ24737_VDD

DL_CHG

BQ24737_VDD

12

34

PQ65B

5

1 2

PC499

PC494

4.7U_0805_25V6-K

P2

PR377

PC506

1 2

1U_0603_25V6

LX_CHG

PR385

4.7_0603_5%

1 2

PR394

PR394 10K_0402_1%

10K_0402_1%

2N7002KDW-2N_SOT363-6

For disable pre -charge circui t.

0.047U_0603_16V7K

PR392

10K_0402_1%

1 2

12

PR395

12K_0402_1%

PC508

12

1 2

4.7U_0805_25V6-K

2

1 2

PC500

4.7U_0805_25V6-K

ACIN <45>

PACIN <63>

PC495

578

CHG_B+

DISCHG_G

2200P_0402_50V7K

PR366

PR366 10K_0402_1%

10K_0402_1%

1 2

DISCHG_G-1

PQ62

13

DTC115EUA_SC70-3

PQ66

PQ66 AO4406AL_SO8

AO4406AL_SO8

3 6

241

4.7UH_PCMB104E-4R 7MS_10A_20%

PQ68

3 6

241

TPC8A03-H 1N SO8

PR365

47K_0402_1%

1 2

2

SH000005Y8J

12

PR386

6251_SN

12

PC511

1 2 3 6

ACOFF-1

PD9

1 2

PL26

1 2

4.7_1206_5%

680P_0603_50V7K

PQ59

AO4423L 1P SO8

4

1SS355_SOD323-2

PD10

PD10 1SS355_SOD323-2

1SS355_SOD323-2

1 2

PC504

1

CHGCHG

2

1

8 7

5

VIN

PR367

PR367 200K_0402_1%

200K_0402_1%

1 2

61

PQ65A

12

2N7002KDW -2N_SOT363-6

2

PACIN

0.1U_0603_25V7K

PR381

4

0.01_2512_1%

3

PC509

10U_0805_25V6K

2012/02/29 change PR381 from 1206 to 2512 size

BATT+

12

PC510

10U_0805_25V6K

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

CHARGER

Size D ocument Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

63 66

0.2

5

4

3

2

1

D D

AC MODE

BATT MODE

A1

VIN

BATT

B1

V

PU2

A3

B4

+3VALW

B5

V

A5

B7 2

V

A2

PU3

V

B+

V

B2

B+

PCH_PWR_EN#

2

V

PQ2

EC

VV

A5

A4

ON/OFF

B7

B6

V

PBTN_OUT#

PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_A#

V

PM_SLP_SUS#

SYSON

DGPU_PWR_EN

SUSP#,SUSP

B3

51ON#

C C

EC_ON

2

4

PCH_RSMRST#

5

7 SYSON#

(DIS)

8a

8

6

U14,+3VALW_PCH

V

QH4,+5VALW_PCH

+3VALW_PCH

3

+5VALW_PCH

V

PCH

V V

+1.5V

V

PU5

VGA_ON

U49

V

+5VS

V

SYS_PWROK

PM_DRAM_PWRGD

H_CPUPWRGD

PLT_RST#

+3VSDGPU

V

Q6

+1.5VSDGPU

V

13

V

14

CPU

V

15

V

VVVV

11

VGATE

U40

U20

V

+3VS

B B

V

U13 +1.5VS

+1.8VSDGPU

V

U37

+1.0VSDGPU

V

VGA

V

PU28

PU8

VCCPPWRGOOD

V

PU9 +1.05VS_VCCP

VR_ON

9

PU1000 +CPU_CORE

V

VV

+0.75V

PU7 +VCCSA

+VGA_CORE

V

PU998

VGA_PWROK

(DIS)

8b

U47 CK505

V

10

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2

2014/07/01

Title

Power sequence

Size Document Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

64 66

0.2

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

Reserve 0.1uF for Charger IC Reserve PC321

D D

C C

2

EMI Request

3

Combine 1.05V

4

Discharge for +1.05VS_VGA by NV Request 53 Reserve PR528

5

Set VGA_CORE VBOOT voltage

6

For VGA_CORE power saving by NV Request add PR838 0ohm

7

for CPU_CORE load line adjust add PC969

8

to prevent MOS over temperature change PQ702,PQ901,PQ902,PQ905 TPCA806555/58

9

for CPU_CORE test 59 Reserve PC77,PC78

10

for VGA VID R-short 59 change PR318,PR319,PR320,PR321,PR322,PR323 footprint

11

Charger boost resistor For EMI 63 Change PR385 from 2.2ohm to 4.7ohm

12

51

change PR322,PR407,PR408,PR503,PR511,PR606,PR804,PR827 to 2.2 ohm add PC526,PC527,PC970,PC971(470uF)

Remove one power rail +V1.05S_VCCPP

51

Pop PR722,PR712,PR718

unpop PR806

56

change PR813 to 147K ohm

56

57

201109/27

201205/31

201206/04

B test

13

14

B B

15

16

17

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

PIR (PWR)

Size D ocument Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

65 66

0.2

5

4

3

2

1

QIWY3 HW PIR List

NO DATE PAGE MODIFICATION LIST PURPOSE

2 Reserve SUSACK#,SUSWARN#,SLP_SUS# control signal for Deep S3P16 Reserve R1457,R1455,R1447

Reserve EC DRAMRST control pin for Deep S31 P7 Reserve R64

D D

3 P16 Reserve Q118,R1120,R1121 Reverse SLP_SUS# to control +3V_PCH&+5V_PCH 4 Change AC_PRESENT Pull high source to +3V_DSWP16 For Deep S3 function 5 P21 Remove R289 +5V_PCH control circuit change for Deep S3

P366 Reserve J8,Q104,C533,C526,R436 Reserve for AOAC function P367 Change JP1 pin2,24,52 power source to +3VS_WLAN_AOAC Reserve for AOAC function P428 Change EC GPIO pin setting (Impact pin 18,71,72,126,128) For DeepS3/AOAC function

P489 Reserve J11,J14,Q148,Q149,C38,C39 +3V_PCH&+5V_PCH control circuit for Deep S3 10 P45 change U49 symbol (without GND pad) 11 P46 change U40,U69 symbol (without GND pad)

For DFx issue

For DFx issue 12 P47 change JP10 type to SP01001B800 For DFx issue 13 P19 Reserve R207,R224 to contact WLAN wake even Reserve for AOAC function 14 P41 Change JSPK1 type to SP02000H700 For DFx issue 14 P19 Reserve R704 and R706 for GPIO69 PU&PD For SKU ID 15 P23 Change CV37,CV38 to 22P For Crystal EA request

For Crystal EA requestChange C968,C969 to 33PP3716

C C

EVT TO DVT

B B

A A

Title

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTUR E CENTER. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF LC FUTURE CENTER.

3

2012/07/01

LC Future Center Secret Data

Deciphered Date

2014/07/01

2

Title

PIR (HW)

Size D ocument Number Rev

Custom

Tuesday, June 05, 2012

Date: Sheet of

Tuesday, June 05, 2012

LA-8692P

LA-8692PLA-8692P

1

66 66

0.2

COMPAL LA-8692P Schematics

Specifications and Main Features

Frequently Asked Questions

User Manual