Page 1
A
1 1
B
C
D
E
QIQY5
Whisky3.0 (Y490)
2 2
LA-8691P Rev0.2 Schematic
Intel IVY Bridge Processor with DDRIII + Panther Point PCH
3 3
4 4
A
nVIDIA N13P GT1-A2 + 2nd VGA N13P GT1-A2
2012-02-05 Rev0.2
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
C
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
E
0.2
0.2
0.2
1 65Tuesday, March 20, 2 012
1 65Tuesday, March 20, 2 012
1 65Tuesday, March 20, 2 012
Page 2
A
B
C
D
E
PCI-Express 16X Gen3
PEG 0~7PEG 8~15
2nd VGA, N13P-GT1
1 1
VRAM 64*32
GDDR5* 8
Sub/B
Page 32 Page 23,24,25,26,27,28,29,30,31
N13P-GT1
VRAM 64*32
GDDR5* 8
Intel CPU
Ivy Bridge
rPGA-989
37.5mm*37.5mm
Page 5,6,7,8,9,10,11
Memory BUS (DDRIII)
Dual Channel
1.5V DDRIII 1066/1333/1600 MT/s
DDR3-SO-DIMM X2
BANK 0, 1, 2, 3
UP TO 16G
FDI *8
2.7GT/s
HDMI Conn.
HDMI1.4b
2 2
Page 36 Page 35 Page 34
RJ45 Conn.
Page 39
CRT Conn.
Atheros
AR8161 1G
AR8151 1G
PCIe port 1
LVDS Conn.
Page 38
PCIe Gen1 1x
1.5V 5GT/s
Intel PCH
Panther Point
FCBGA-989 Balls
CardReader
JMB38C
SD/MMC/MS/XD
PCIe port 4
3 3
SPI ROM
(4MB+2MB)
Page 44
Page 14
PCIe Gen1 1x
1.5V 5GT/s
SPI BUS
3.3V 33MHz
25mm*25mm
Page 14,15,16,17,18,19,20,21,22
LPC BUS
3.3V 33MHz
DMI *4
5GT/s
USB 2.0 4x
5V 480MHz
USB 3.0 2x
5V 5GT/s
USB 2.0 1x
5V 480MHz
PCIe Gen1 1x
5V 480MHz
SATA Gen3 Port 0
5V 6GHz(600MB/s)
SATA Gen3 Port 1
5V 6GHz(600MB/s)
SATA Gen1 Port2
5V 3GHz(300MB/s)
HD Audio
3.3V 24MHz
USB Left
USB 2.0 Port 2
USB 3.0 Port 2
Int. Camera
USB 3.0 Port 0
PCIeMini Card
WLAN
PCIeMini Card
WLAN
SATA HDD
SATA ODD
USB Right
USB 2.0 Port 9
Page 48 Page 49
Page 34
USB 2.0 Port 5, Cha
Sub/B
BT
USB 2.0 Port 13
mSATA SSD
PCIe Port 2
page 37
USB Port 10
page 37
SATA Port 1
page 41
SATA Port 1
page 41
Page 47
SATA Port 0
page 37
Debug Port
Page 45
Power Circuit DC/DC
Page 52,53 ,54,55,56, 57,
58,59 ,60,61,62
4 4
DC/DC Interface CKT.
POWER/B Conn. AUDIO, USB/B Conn.
ODD/B Conn.
Page 51
Page 40 Page 49
page 41
A
RTC CKT.
NOVO/B Conn.
Page 52
Page 40
Touch Pad
B
EC
ITE IT8580E-HX
Page 46
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Int.KBD
Issued Date
Issued Date
Issued Date
Page 46
C
Page 45
Thermal Sensor
EMC 1403
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Page 40
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Codec
ALC269Q-VC3
Int. MIC Conn.
(JCMOS Conn.)
Page 42
Page 34 Page 49
D
AMP
MAX98400B
Page 43
Ext. MIC Conn.
Sub/B
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
HP Conn.
Sub/B
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Block Diagram
Block Diagram
Block Diagram
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
SPK Conn.
Page 49
E
Page 43
2 65Tuesday, March 20, 2012
2 65Tuesday, March 20, 2012
2 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 3
A
B
C
D
E
Voltage Rails
Power Plane
1 1
State
S0
S3
2 2
S5 S4/AC Only
S5 S4
Battery only
S5 S4
AC & Battery
don't exist
SMBUS Control Table
3 3
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
SMB_CLK_S3
SMB_DATA_S3
( O --> Means ON , X --> Means OFF )
+3VALW
B+
+1.5V
+5VALW
O
O O O
O
O
O
O
X X
X X
SOURCE
IT8580EEC_SMB_CK1
+3VALW
IT8580E
+3VS
PCH
+3VS
Main
VGA
+3VS +3VS
2nd
VGA
X
V
BATT SODIMM
X X XV
+3VALW
V
X
IT8580E
X X X X X
+5VS
+3VS
+1.5VS
+VCCSA
+V1.5S_VCC P
+CPU_CORE
+VGA_CORE
+GFX_CORE
+1.8VS
+1.05VS
+0.75VS
+3.3VS_VGA
+1.5VS_VGA
+1.05VS_VG A
OO
X
X
X
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
USB Port Table
EHCI1
X
EHCI2
X
X
X
X
WLAN
WiMAX
X
X
X
Thermal
Sensor
V
+3VS
PCH
V
+3V_PCH
TP
Module
XX
X
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
HIGH HIGH HIGH HIGH
USB 3.0USB 2.0 Port
XHCI
1
2
2
3
3
4
4
0
1
5
6
7
8
9
10
11
12
13
PCIE PORT LIST
Port Device
1
2
3
4
5
6
LOW
LOW
LOW
LOW LOW LOW LOW
HIGH
LOWLOWLOW
HIGHHIGHHIGH
HIGH
HIGH
4 External
USB Port
Camera
USB Port (Left Side)
USB Port (Right Side)
USB Port (Right Side)
Mini Card(WLAN)
Blue Tooth
LAN
WLAN
Card Reader
ON
ON
ON ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
BOM Structure Table
HDMI@
CHG@
NOCHG@
CMOS@
8161@
8151@
8161S@
8151S@
SURGE@
61@
51@
X76@
GC6@
NOGC6@
AOAC@
KBL@
ME@
OPT@
SLI@
DS3@
S3@
GT@
@
LOW
OFF
OFF
OFF
BTO ItemBOM Structure
HDMI part
USB charger part
No USB charger part
CMOS Camera part
AR8161 LAN part
AR8151 LAN part
AR8161 LAN surge part
AR8151 LAN surge part
AR8151&8161 LAN surge part
X76 P/N for AR8161
X76 P/N for AR8151
X76 Level part for VRAM
NV CG6 support part
NV no CG6 support part
AOAC support part
K/B Light part
ME part
For optimus function part
For SLI function part
Deep S3 support part
For S3 function part
NV chip part
Unpop
7
V V
+3VS
V
+3V_PCH+3VS
V
+3VS
8
A
Address
0001 011X b
EC SM Bus2 address
Device
Thermal Sen sor EMC1403-2
Master VGA
Slave VGA
B
Address
1001_101xb
0x9E
0x9C
PCH SM Bus address
Device Address
DDR DIMM0
DDR DIMM2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
1001 000Xb
1001 010Xb
Compal Secret Data
Compal Secret Data
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
4 4
EC SM Bus1 address
Device
Smart Battery
ZZZ1
ZZZ1
DA80000T10J
DA80000T10J
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
E
3 65Tuesday, March 20, 2012
3 65Tuesday, March 20, 2012
3 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 4
5
4
3
2
1
Hot plug detect for IFP link E
VGA and GDDR5 Voltage Rails (N13Px GPIO)
GPIO I/O ACTIVE Function Description
GPIO0
D D
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
C C
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
B B
+3VS_VGA
+VGA_CORE
+1.5VS_VGA
+1.05VS_VGA
OUT GPU VID4-
-
GPU VID3OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
VGA_BL_PWM
-
-
VGA_ENVDD
- VGA_ENBKL
GPU VID1
-
GPU VID2
-
DPRSLPVR_VGA
-
Thermal Catastrophic Over Temperature
-
GPIO9
-
Memory VREF Control
-
GPU VID0-OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
1. all power ra il ramp up tim e should be la rger than 40us
AC Power Detect Input
GPU VID5-
FB_CLAMP_TOGGLE_REQ#
-
N/A (100K pull low)
FRMLCK#
-
N/A
-
dGPU_HDMI_HPD
HPD_IRQ
-
tNVVDD >0
tFBVDDQ >0
tPEX_VDD >0
(10K pull High)
Performance Mode P0 TDP at Tj = 102 C* (GDDR5)
GPU Mem NVCLK
(4) (1,5) (6)
Products
(W) (W) (MHz)
N13X
128bit
1GB
GDDR5
Physical
Strapping pin
ROM_SCLK
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
N13P-GT
(28nm)
/MCLK NVVDD
(V) (A) (W) (A) (W)
TBD TBDTBD TBD TBD TBD TBD TBD T BD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Power Rail
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Device ID
0x0FDB
Logical
Strapping Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
3GIO_PAD_CFG_AD R[2] 3GIO_PAD_CFG_AD R[1]3GIO_PAD_CFG_AD R[3]
setting
SMB_ALT_ADDR
(ROM_SO Bit 1)
0
1
ROM_SO ROM_SCLK
GPU
N13P-GT1
28nm
FB Memory (GDDR5)
Samsung
2500MHz
Hynix
2500MHz
Samsung
2500MHz
2500MHz
PU 25K
PU 45KPU 10K PD 10K
PU 25K PD 35KPU 45KPU 20K PD 10K PD 5K PD 10K
GPU
K4G10325FG-HC04
32Mx32
H5GQ1H24BFR-T2C
32Mx32 PD 35K
K4G20325FD-FC04
64Mx32
H5GQ2H24MFR-T2CHynix
64Mx32
PD 35K
N13P-GT
ROM_SI
PD 45K
PD 30K
PD 25K
FBVDDQ PCI Express I/O and
FBVDD
(GPU+Mem)
(1.35V)(1.35V)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
Logical
Strapping Bit2
SUB_VENDOR
USER[2] USER[1] USER[0]USER[3]
SOR2_EXPOSED SOR1_EXPOSED
CHANGE_GEN3
I2C Slave addrees ID
0x9E
0x9C
STRAP2STRAP1STRAP0
(1.05V)
Logical
Strapping Bit1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG[ 2]
PCIE_MAX_SPEED DP_PLL_VDD33V
STRAP3
STRAP4
PU 5K PD 10K
PLLVDD
Master
Slave
I/O and
PLLVDD
Logical
Strapping Bit0
PEX_PLL_EN_TERM
RAM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PAD_CFG_AD R[0]
SOR0_EXPOSED
Other
(3.3V)(1.05V)(1.8V)
Other Power rail
A A
+3VS_VGA
Tpower-off <10m s
1.all GPU power rails should be turned off within 10ms
2. Optimus syst em VDD33 avoid s drop down ea rlier than NVD D and FBVDDQ
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
VGA Notes List
VGA Notes List
VGA Notes List
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
4 65Tuesday, March 20, 2012
4 65Tuesday, March 20, 2012
4 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 5
5
D D
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
C C
B B
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
+1.05VS
eDP_COMPIO and ICOMPO signals
should be short ed near balls
and routed with typical
impedance <25 m ohms
R7
R7
1 2
24.9_0402_1%
24.9_0402_1%
4
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
FDI_LSYNC1
EDP_COMP
JCPU1A
ME@
JCPU1A
ME@
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD#
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
3
1. PEG_ICOMPI and RCOMPO signals should be shorted and routed with
a. max length = 500 mils
b. typical impedance = 43 mohms
2. PEG_ICOMPO signals should be routed with
+1.05VS
R1
R1
J22
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
J21
H22
K33
PCIE_CRX_GTX_N0
M35
PCIE_CRX_GTX_N1
L34
PCIE_CRX_GTX_N2
J35
PCIE_CRX_GTX_N3
J32
PCIE_CRX_GTX_N4
H34
PCIE_CRX_GTX_N5
H31
PCIE_CRX_GTX_N6
G33
PCIE_CRX_GTX_N7
G30
PCIE_CRX_GTX_N8
F35
PCIE_CRX_GTX_N9
E34
PCIE_CRX_GTX_N10
E32
PCIE_CRX_GTX_N11
D33
PCIE_CRX_GTX_N12
D31
PCIE_CRX_GTX_N13
B33
PCIE_CRX_GTX_N14
C32
PCIE_CRX_GTX_N15
J33
PCIE_CRX_GTX_P0
L35
PCIE_CRX_GTX_P1
K34
PCIE_CRX_GTX_P2
H35
PCIE_CRX_GTX_P3
H32
PCIE_CRX_GTX_P4
G34
PCIE_CRX_GTX_P5
G31
PCIE_CRX_GTX_P6
F33
PCIE_CRX_GTX_P7
F30
PCIE_CRX_GTX_P8
E35
PCIE_CRX_GTX_P9
E33
PCIE_CRX_GTX_P10
F32
PCIE_CRX_GTX_P11
D34
PCIE_CRX_GTX_P12
E31
PCIE_CRX_GTX_P13
C33
PCIE_CRX_GTX_P14
B32
PCIE_CRX_GTX_P15
M29
PCIE_CTX_GRX_C_N0
M32
PCIE_CTX_GRX_C_N1
M31
PCIE_CTX_GRX_C_N2
L32
PCIE_CTX_GRX_C_N3
L29
PCIE_CTX_GRX_C_N4
K31
PCIE_CTX_GRX_C_N5
K28
PCIE_CTX_GRX_C_N6
J30
PCIE_CTX_GRX_C_N7
J28
PCIE_CTX_GRX_C_N8
H29
PCIE_CTX_GRX_C_N9
G27
PCIE_CTX_GRX_C_N10
E29
PCIE_CTX_GRX_C_N11
F27
PCIE_CTX_GRX_C_N12
D28
PCIE_CTX_GRX_C_N13
F26
PCIE_CTX_GRX_C_N14
E25
PCIE_CTX_GRX_C_N15
M28
PCIE_CTX_GRX_C_P0
M33
PCIE_CTX_GRX_C_P1
M30
PCIE_CTX_GRX_C_P2
L31
PCIE_CTX_GRX_C_P3
L28
PCIE_CTX_GRX_C_P4
K30
PCIE_CTX_GRX_C_P5
K27
PCIE_CTX_GRX_C_P6
J29
PCIE_CTX_GRX_C_P7
J27
PCIE_CTX_GRX_C_P8
H28
PCIE_CTX_GRX_C_P9
G28
PCIE_CTX_GRX_C_P10
E28
PCIE_CTX_GRX_C_P11
F28
PCIE_CTX_GRX_C_P12
D27
PCIE_CTX_GRX_C_P13
E26
PCIE_CTX_GRX_C_P14
D25
PCIE_CTX_GRX_C_P15
PEG_COMP
12
24.9_0402_1%
24.9_0402_1%
C1 0.22U_0402_10V 6KC1 0.22U_0402_10V 6K
C2 0.22U_0402_10V 6KC2 0.22U_0402_10V 6K
C3 0.22U_0402_10V 6KC3 0.22U_0402_10V 6K
C4 0.22U_0402_10V 6KC4 0.22U_0402_10V 6K
C5 0.22U_0402_10V 6KC5 0.22U_0402_10V 6K
C6 0.22U_0402_10V 6KC6 0.22U_0402_10V 6K
C7 0.22U_0402_10V 6KC7 0.22U_0402_10V 6K
C8 0.22U_0402_10V 6KC8 0.22U_0402_10V 6K
C9 0.22U_0402_10V 6KSLI@ C9 0.22U_0402_10V 6KSLI@
C10 0.22U_0402_10V6KSLI@ C10 0.22U_0402_10V6KS LI@
C11 0.22U_0402_10V6KSLI@ C11 0.22U_0402_10V6KS LI@
C12 0.22U_0402_10V6KSLI@ C12 0.22U_0402_10V6KS LI@
C13 0.22U_0402_10V6KSLI@ C13 0.22U_0402_10V6KS LI@
C14 0.22U_0402_10V6KSLI@ C14 0.22U_0402_10V6KS LI@
C15 0.22U_0402_10V6KSLI@ C15 0.22U_0402_10V6KS LI@
C16 0.22U_0402_10V6KSLI@ C16 0.22U_0402_10V6KS LI@
C20 0.22U_0402_10V6KC20 0.22U_0402_10V6K
C23 0.22U_0402_10V6KC23 0.22U_0402_10V6K
C25 0.22U_0402_10V6KC25 0.22U_0402_10V6K
C30 0.22U_0402_10V6KC30 0.22U_0402_10V6K
C18 0.22U_0402_10V6KC18 0.22U_0402_10V6K
C22 0.22U_0402_10V6KC22 0.22U_0402_10V6K
C28 0.22U_0402_10V6KC28 0.22U_0402_10V6K
C32 0.22U_0402_10V6KC32 0.22U_0402_10V6K
C19 0.22U_0402_10V6KSLI@ C19 0.22U_0402_10V6KS LI@
C24 0.22U_0402_10V6KSLI@ C24 0.22U_0402_10V6KS LI@
C29 0.22U_0402_10V6KSLI@ C29 0.22U_0402_10V6KS LI@
C17 0.22U_0402_10V6KSLI@ C17 0.22U_0402_10V6KS LI@
C21 0.22U_0402_10V6KSLI@ C21 0.22U_0402_10V6KS LI@
C27 0.22U_0402_10V6KSLI@ C27 0.22U_0402_10V6KS LI@
C26 0.22U_0402_10V6KSLI@ C26 0.22U_0402_10V6KS LI@
C31 0.22U_0402_10V6KSLI@ C31 0.22U_0402_10V6KS LI@
a. max length = 500 mils
b. typical impedance = 14.5 mohms
PCIE_CRX_GTX_N[0..15] <23,32>
PCIE_CRX_GTX_P[0..15] <23,32>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P15
1: Normal Operation; Lane # definition matches
socket pin map definition
0:Lane Reversed
*
PCIE_CTX_GRX_N[0..15] <23,32>
PCIE_CTX_GRX_P[0..15] <23,32>
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
PROCESSOR(1/7) DMI,FDI,PEG
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
5 65Tuesday, March 20, 2012
5 65Tuesday, March 20, 2012
5 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 6
5
D D
PROC_SEL
H : Sandy Bridg e
L : IVY Bridge
+1.05VS
R9
R9
1 2
62_0402_5%
62_0402_5%
C C
H_CPUPWRGD<19>
C550
C550
100P_0402_50V8J
100P_0402_50V8J
9/23 ESD Reques t
1
2
R27
R27
10K_0402_5%
10K_0402_5%
1 2
H_PROCHOT#<45,53>
H_PM_SYNC<16>
4
H_SNB_IVB#<19>
T14 PADT14 PAD
H_PECI<45>
H_PROCHOT#H_PROCHOT#
H_THRMTRIP#<19>
H_PM_SYNC
H_CPUPWRGD
R15
R15
1 2
56_0402_5%
56_0402_5%
R22
R22
1 2
0_0402_5%
0_0402_5%
R26
R26
1 2
0_0402_5%
0_0402_5%
R29
R29
1 2
130_0402_5%
130_0402_5%
H_SNB_IVB#
H_CATERR#
H_PROCHOT#_R
H_THRMTRIP#
H_PM_SYNC_R
H_CPUPWRGD_R
PM_DRAM_PWR GD_RPM_SYS_PWRGD_BUF
BUF_CPU_RST#
H_PECI
AN34
AL33
AN33
AL32
AN32
AM34
AP33
AR33
JCPU1B
JCPU1B
C26
V8
3
ME@
ME@
PROC_SELECT#
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWR OK
RESET#
2
A28
A27
A16
A15
R8
AK1
A5
A4
CLK_CPU_DMI
CLK_CPU_DMI#
H_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
R12 1K_0402_5%R12 1K_0402_5%
R13 1K_0402_5%R13 1K_0402_5%
R16 140_0402_1%R16 140_0402_1%
R17 25.5_0402_1%R17 25.5_0402_1%
R18 200_0402_1%R18 200_0402_1%
BCLK
BCLK#
CLOCKS
CLOCKS
DDR3
DDR3
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
12
12
H_DRAMRST# <7>
12
12
12
+1.05VS
1
DDR3 Compensation Signals
AP29
PRDY#
AP27
PREQ#
AR26
XDP_TCK
TCK
AR27
XDP_TMS
TMS
AP30
TDO
XDP_TRST#
AR28
XDP_TDI
TDI
AP26
XDP_TDO
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
TRST#
DBR#
BPM#[0]
BPM#[1]
JTAG & BPM
JTAG & BPM
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TRST#
R20 51_0402_5%R20 51_0402_5%
R21 51_0402_5%R21 51_0402_5%
R23 51_0402_5%
R23 51_0402_5%
R24 51_0402_5%R24 51_0402_5%
R25 51_0402_5%R25 51_0402_5%
PU/PD for JTAG signals
12
12
12
12
@
@
12
+1.05VS
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
B B
Buffered Reset to CPU
+3VS
1
C33
5
P
B
O
A
G
U1
U1
74AHC1G09GW_TSSOP5
74AHC1G09GW_TSSOP5
3
4
C33
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4
R338
R338
10K_0402_5%
10K_0402_5%
1 2
1 2
SYS_PWROK<16>
PM_DRAM_PWR GD<16>
A A
5
R65 0_0402_5%@R65 0_0402_5%@
1
2
+1.5V_CPU_VDDQ+3VALW
12
R30
R30
200_0402_5%
200_0402_5%
PM_SYS_PWRGD_BUF
1.05V
12
R35
@R35
@
0_0402_5%
0_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
+1.05VS +3VS
12
R32
R32
75_0402_5%
75_0402_5%
R34
R34
1 2
43_0402_1%
43_0402_1%
Compal Secret Data
Compal Secret Data
Compal Secret Data
BUFO_CPU_RST#BUF_CPU_ RST#
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C34
C34
2
5
1
This is NC pin
P
NC
4
Y
2
PLT_RST#
A
G
U2
U2
3
SN74LVC1G07DCKR_SC70-5
SN74LVC1G07DCKR_SC70-5
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
3V
PLT_RST# <18,23,32,37,38,44,45>
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
PROCESSOR(2/7) PM,XDP,CLK
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
6 65Tuesday, March 20, 2012
6 65Tuesday, March 20, 2012
6 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 7
5
JCPU1C
ME@
JCPU1C
ME@
4
3
JCPU1D
JCPU1D
2
ME@
ME@
1
DDR_A_D[0..63]<12>
D D
C C
B B
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_A_WE#<12>
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AE8
AD9
AF9
F10
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CK[0]
SA_CLK#[0]
SA_CKE[0]
SA_CK[1]
SA_CLK#[1]
SA_CKE[1]
SA_CK[2]
SA_CLK#[2]
SA_CKE[2]
SA_CK[3]
SA_CLK#[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>
DDR_B_D[0..63]<13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_WE#<13>
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
J10
C9
A7
C8
A9
A8
D9
D8
G4
F4
F1
G1
G5
F5
F2
G2
J7
J8
K9
J9
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CK[0]
SB_CLK#[0]
SB_CKE[0]
SB_CK[1]
SB_CLK#[1]
SB_CKE[1]
SB_CK[2]
SB_CLK#[2]
SB_CKE[2]
SB_CK[3]
SB_CLK#[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
M_CLK_DDR#3 <13>
DDR_CKE3_DIMMB <13>
DDR_CS2_DIMMB# <13>
DDR_CS3_DIMMB# <13>
M_ODT2 < 13>
M_ODT3 < 13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
+1.5V
12
R37
R37
1K_0402_5%
1K_0402_5%
D
S
D
S
13
H_DRAMRST#<6>
R39
R39
4.99K_0402_1%
A A
DRAMRST_CNTRL_PC H<15>
DRAMRST_CNTRL<10>
DRAMRST_CNTRL_EC<45>
Reserve for Dee p S3
5
4.99K_0402_1%
1 2
@
@
R40 0_0402_5%
R40 0_0402_5%
1 2
DS3@
DS3@
R64 0_0402_5%
R64 0_0402_5%
1 2
DRAMRST_CNTRL
DDR3_DRAMRST#_RH_DRAMRST#
Q2
Q2
G
G
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
2
1
C35
C35
0.047U_0402_16V4Z
0.047U_0402_16V4Z
2
Module design u sed 0.047u
4
R38
R38
1 2
1K_0402_5%
1K_0402_5%
DDR3_DRAMRST# <12,13>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
TYCO_2013620-2_IVY BRIDGE
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
7 65Tuesday, March 20, 2012
7 65Tuesday, March 20, 2012
7 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 8
5
D D
JCPU1E
ME@
JCPU1E
ME@
AK28
CFG[0]
AK29
CFG[1]
CFG2
CFG5
CFG6
CFG7
C C
11/24 --> Intel recommend
to reserve test point
B B
T56 PADT56 PAD
T57 PADT57 PAD
T58 PADT58 PAD
T59 PADT59 PAD
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
J15
RSVD27
CFG
CFG
RESERVED
RESERVED
4
VCC_DIE_SENSE
VSS
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF1
RSVD_NCTF2
RSVD_NCTF3
RSVD_NCTF4
RSVD_NCTF5
RSVD_NCTF6
RSVD_NCTF7
RSVD_NCTF8
RSVD_NCTF9
RSVD_NCTF10
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
RSVD_NCTF11
RSVD_NCTF12
RSVD_NCTF13
KEY
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
AT2
AT1
AR1
B1
3
CFG Straps for Processor
CFG2
CFG6
CFG5
1K_0402_1%
1K_0402_1%
CFG7
12
R41
R41
@
@
1K_0402_1%
1K_0402_1%
12
12
R44
R44
R43
R43
@
@
1K_0402_1%
1K_0402_1%
12
R45
R45
@
@
1K_0402_1%
1K_0402_1%
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
Display Port Presence Strap
CFG4
PCIE Port Bifurcation Straps
CFG[6:5]
PEG DEFER TRAINING
CFG7
2
1: Normal Operation; Lane # definition matches
*
socket pin map definition
0:Lane Reversed
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
*
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2
*
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
1: (Default) PEG Train immediately following xxRESETB
de assertion
0: PEG Wait for BIOS for training
1
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
PROCESSOR(4/7) RSVD,CFG
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
8 65Tuesday, March 20, 2012
8 65Tuesday, March 20, 2012
8 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 9
5
JCPU1F
ME@
JCPU1F
ME@
4
POWER
POWER
3
2
1
+VCC_CORE
D D
C C
B B
A A
5
QC=94A
DC=53A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
8.5A
AH13
VCCIO1
AH10
VCCIO2
AG10
VCCIO3
AC10
VCCIO4
Y10
VCCIO5
U10
VCCIO6
P10
VCCIO7
L10
VCCIO8
J14
VCCIO9
J13
VCCIO10
J12
VCCIO11
J11
VCCIO12
H14
VCCIO13
H12
VCCIO14
H11
VCCIO15
G14
VCCIO16
G13
VCCIO17
G12
VCCIO18
F14
VCCIO19
F13
VCCIO20
F12
VCCIO21
F11
VCCIO22
E14
VCCIO23
E12
VCCIO24
E11
VCCIO25
D14
VCCIO26
D13
VCCIO27
D12
VCCIO28
D11
VCCIO29
C14
VCCIO30
C13
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
C12
C11
B14
B12
A14
A13
A12
A11
J23
AJ29
H_CPU_SVIDALRT#
AJ30
H_CPU_SVIDCLK
AJ28
H_CPU_SVIDDAT
AJ35
VCCSENSE_R VCCSENSE
AJ34
VSSSENSE_R
B10
VCCIO_SENSE
A10
VSSIO_SENSE
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
4
+1.05VS
+1.05VS
12
1
C36
@C36
@
R46
0.1U_0402_10V7K
0.1U_0402_10V7K
2
Reserve 0.1u to avoid noise
1 2
R47 43_0402_5%R47 43_0402_5%
1 2
R48 0_0402_5%R48 0_0402_5%
1 2
R49 0_0402_5%R49 0_0402_5%
R50 130_0402_5%R50 130_0402_5%
Place the PU re sistor close t o CPU
1 2
R52 0_0402_5%R52 0_0402_5%
1 2
R53 0_0402_5%R53 0_0402_5%
R1294 10_0402_1%R1294 10_0402_1%
R1297 10_0402_1%R1297 10_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
12
12
12
3
+1.05VS
+1.05VS
VSSSENSE
VCCIO_SENSE <57>
Compal Secret Data
Compal Secret Data
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
R46
75_0402_5%
75_0402_5%
Place the PU re sistor close t o CPU
VR_SVID_ALRT# <59>
VR_SVID_CLK <59>
VR_SVID_DAT <59>
+VCC_CORE
12
R51
R51
100_0402_1%
100_0402_1%
VCC_SENCE 100oh m +-1% pull-up to VCC near p rocessor
12
R54
R54
100_0402_1%
100_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
VSS_SENCE 100oh m +-1% pull-do wn to GND near processor
2
VCCSENSE <59>
VSSSENSE <59>
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
PROCESSOR(5/7) PWR,BYPASS
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
9 65Tuesday, March 20, 2012
9 65Tuesday, March 20, 2012
9 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 10
5
4
3
2
1
+1.5V_CPU_VDDQ
For Deep S3
D D
SUSP<37,51,55,57>
CPU1.5V_S3_GATE<45>
C C
0_0402_5%
0_0402_5%
B B
+1.8VS
R67
R67
1 2
A A
0_0805_5%
0_0805_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
1
+
+
C130
C130
C279
@
C279
@
2
330U_B2_2.5VM_R15M
330U_B2_2.5VM_R15M
1
1
C131
C131
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
C132
C132
+3VALW
R1537
100K_0402_5%
100K_0402_5%
R1538
R1538
1 2
0_0402_5%
0_0402_5%
2
G
G
+VCC_GFXCORE_AXG
RV174
RV174
SLI@
SLI@
1 2
+1.8VS_VCCPLL
1
2
12
@R1537
@
13
D
D
@
@
Q156
Q156
S
S
2N7002_SOT23
2N7002_SOT23
46A
11/24 change 22 U X2 to 330U B 2 size
5
+VSB
12
R56 need to che ck on SDV
R56
R56
100K_0402_5%
100K_0402_5%
61
D
D
2
G
G
S
S
Q4A
Q4A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
JCPU1G
JCPU1G
AT24
VAXG1
AT23
VAXG2
AT21
VAXG3
AT20
VAXG4
AT18
VAXG5
AT17
VAXG6
AR24
VAXG7
AR23
VAXG8
AR21
VAXG9
AR20
VAXG10
AR18
VAXG11
AR17
VAXG12
AP24
VAXG13
AP23
VAXG14
AP21
VAXG15
AP20
VAXG16
AP18
VAXG17
AP17
VAXG18
AN24
VAXG19
AN23
VAXG20
AN21
VAXG21
AN20
VAXG22
AN18
VAXG23
AN17
VAXG24
AM24
VAXG25
AM23
VAXG26
AM21
VAXG27
AM20
VAXG28
AM18
VAXG29
AM17
VAXG30
AL24
VAXG31
AL23
VAXG32
AL21
VAXG33
AL20
VAXG34
AL18
VAXG35
AL17
VAXG36
AK24
VAXG37
AK23
VAXG38
AK21
VAXG39
AK20
VAXG40
AK18
VAXG41
AK17
VAXG42
AJ24
VAXG43
AJ23
VAXG44
AJ21
VAXG45
AJ20
VAXG46
AJ18
VAXG47
AJ17
VAXG48
AH24
VAXG49
AH23
VAXG50
AH21
VAXG51
AH20
VAXG52
AH18
VAXG53
AH17
VAXG54
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
RUN_ON_CPU1.5VS3
POWER
POWER
1.8V RAIL
1.8V RAIL
4
GRAPHICS
GRAPHICS
+1.5V
12
R57
R57
470K_0402_5%
470K_0402_5%
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
VREFMISC
VREFMISC
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
1 2
C287 0.1U_0402_10V 6KC287 0.1U_0402_10V6K
1 2
C286 0.1U_0402_10V 6KC286 0.1U_0402_10V6K
1 2
C96 0.1U_0402_10V6KC96 0.1U_0402_10V6K
1 2
C95 0.1U_0402_10V6KC95 0.1U_0402_10V6K
U3
U3
8
7
6
5
AO4304L_SO8
AO4304L_SO8
R1349
R1349
1 2
470K_0402_5%
470K_0402_5%
SM_VREF
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
VCCIO_SEL
4
1
2
AK35
VCC_AXG_SENSE_R
AK34
VSS_AXG_SENSE_R
+V_SM_VREF_CNT
AL1
B4
D1
5A
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
6A
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
A19
1
2
3
AO4304L
Vgs=10V,Id=18A,
Rds<6.7m ohm
P/N: SB00000RV0 0
C97
C97
0.01U 50V K X7R 0603
0.01U 50V K X7R 0603
+V_DDR_REFA_R
+V_DDR_REFB_R
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
+1.5V_CPU_VDDQ
R1488
OPT@R1488
OPT@
0_0402_5%
0_0402_5%
1 2
1 2
0_0402_5%
0_0402_5%
R1489
R1489
OPT@
OPT@
10U_0603_6.3V6M
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
1
1
2
2
+VCCSA
C124
10U_0805_6.3V6M
C124
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1
1
2
2
H_VCCSA_VID0 <56>
H_VCCSA_VID1 <56>
Issued Date
Issued Date
Issued Date
3
DRAMRST_CNTRL<7>
12
R1487
@ R1487
@
470_0603_5%
470_0603_5%
34
D
D
5
SUSP
G
G
S
S
Q4B
Q4B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
+VCC_GFXCORE_AXG
R66
R66
100_0402_1%
100_0402_1%
OPT@
OPT@
1 2
R89 100_0402_1%
R89 100_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C118
C118
C125
C125
R68 0_0402_5%
R68 0_0402_5%
C114
C114
C119
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
1
2
C126
10U_0805_6.3V6M
C126
10U_0805_6.3V6M
1
2
@
@
1 2
1
2
C120
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
2
2
+VCCSA
C127
10U_0805_6.3V6M@C127
10U_0805_6.3V6M
1
@
2
+VCCSA_SENSE <56>
12
OPT@
OPT@
+1.5V_CPU_VDDQ
C121
C121
1
2
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
C128
C128
1
+
+
2
6/8: Add M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
VCC_AXG_SENSE <59>
VSS_AXG_SENSE < 59>
+1.5V_CPU_VDDQ
12
R77
R77
1K_0402_1%
1K_0402_1%
12
R88
R88
1K_0402_1%
1K_0402_1%
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
C123
C123
1
C122
10U_0603_6.3V6M
C122
10U_0603_6.3V6M
+
+
@
@
2
@
@
6/3 modify for VCCSA 4-Level voltage
Compal Secret Data
Compal Secret Data
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+VREF_DQ_DIMMA
+VREF_DQ_DIMMB
2
DRAMRST_CNTRL
DRAMRST_CNTRL
Place the PU/PD
resistor c lose
to CPU wit hin 2
inch
(Reserve p ower
side)
2
G
G
Q8 BSS138_SOT23
Q8 BSS138_SOT23
1 3
D
S
D
S
1 2
R74 0_0402_5%@R74 0_0402_5%@
1 2
R75 0_0402_5%
R75 0_0402_5%
@
@
1 3
D
S
D
S
Q7 BSS138_SOT23
Q7 BSS138_SOT23
G
G
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
PROCESSOR(6/7) PWR
R139
1K_0402_1%
1K_0402_1%
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
+V_DDR_REFA_R
+V_DDR_REFB_R
12
12
R132
@ R132
@
@R139
@
1K_0402_1%
1K_0402_1%
10 65Tuesday, March 20, 2012
10 65Tuesday, March 20, 2012
1
10 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 11
5
D D
C C
B B
4
JCPU1H
JCPU1H
AT35
AT32
AT29
AT27
AT25
AT22
AT19
AT16
AT13
AT10
AR25
AR22
AR19
AR16
AR13
AR10
AR7
AR4
AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10
AP7
AP4
AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10
AN7
AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10
AM7
AM4
AM3
AM2
AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10
AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10
AK7
AK4
AJ25
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
3
JCPU1I
JCPU1I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
VSS
VSS
2
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
1
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
TYCO_2013620-2_IVY BRIDGE
TYCO_2013620-2_IVY BRIDGE
ME@
ME@
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
PROCESSOR(7/7) VSS
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
11 65Tuesday, March 20, 2012
11 65Tuesday, March 20, 2012
11 65Tuesday, March 20, 2012
0.2
Page 12
5
4
3
2
1
DDR3 SO-DIMM A
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
RAS#
ODT0
ODT1
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQS7
DQ62
DQ63
VTT2
+1.5V+1.5V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
DDR3_DRAMRST#
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT1
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
SMB_DATA_S3
SMB_CLK_S3
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
4
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
C51
C51
C52
C52
@
@
@
@
2
DDR3_DRAMRST# <13,7>
DDR_CKE1_DIMMA <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_ODT1 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C149
C149
+0.75VS
1
C150
C150
2
2
SMB_DATA_S3 <13,15,37,46>
SMB_CLK_S3 <13,15,37,46>
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
1
C53
C53
@
@
2
2
+1.5V +1.5V
12
R80
R80
1K_0402_1%
1K_0402_1%
+VREF_CA
12
R81
R81
1K_0402_1%
1K_0402_1%
DDR_A_D[0..63] <7>
DDR_A_DQS[0..7] <7>
DDR_A_DQS#[0..7] <7>
DDR_A_MA[0..15] <7>
Layout Note:
Place near DIMM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C151
C151
@
@
Layout Note:
Place near DIMM
+0.75VS
C288
C288
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
1
C143
C143
C142
C142
@
@
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
C159
C159
C158
C158
2
2
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
OSCON (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C160
C160
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C144
C144
C152
C152
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C145
C145
2
2
10U_0603_6.3V6M
1
1
C153
C153
2
2
Layout Note:
Place near DIMM
DDR_A_DM[0:7] connect to GND
C146
C146
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C154
C154
2
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.1U_0402_10V6K
1
C155
C155
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
1
C147
C147
2
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C156
C156
2
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
1
+
+
C148
C148
220U_6.3V_M
220U_6.3V_M
2
0.2
0.2
12 65Tuesday, March 20, 2012
12 65Tuesday, March 20, 2012
12 65Tuesday, March 20, 2012
0.2
+1.5V
12
R78
R78
1K_0402_1%
1K_0402_1%
+VREF_DQ_DIMMA
D D
C C
B B
A A
1K_0402_1%
1K_0402_1%
12
R79
R79
+3VS
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C141
C141
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
5
C290
C290
1
2
C140
C140
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
+VREF_DQ_DIMMA
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C162
C162
0.1U_0402_10V6K
0.1U_0402_10V6K
2
3A@1.5V
JDIMM1
JDIMM1
ME@
ME@
VREF_DQ1VSS1
3
VSS2
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D9
DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#
DDR_A_CAS# M_ODT0
DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32
DDR_A_D33
DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
R82
R82
1 2
10K_0402_5%
10K_0402_5%
12
R83
R83
10K_0402_5%
10K_0402_5%
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LCN_DAN06-K4806-0103
LCN_DAN06-K4806-0103
DQS#0
VSS10
VSS19
VSS21
VDD12
VDD14
VDD16
VDD18
VREF_CA
VSS28
VSS30
VSS31
VSS33
VSS35
DQS#5
VSS38
VSS40
VSS42
VSS43
VSS45
VSS47
DQS#7
VSS50
VSS52
EVENT#
Page 13
5
+1.5V
12
R84
R84
1K_0402_1%
1K_0402_1%
+VREF_DQ_DIMMB
12
C289
C289
R85
D D
C C
B B
A A
1K_0402_1%
1K_0402_1%
R85
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+3VS
DDR_CKE2_DIMMB<7>
DDR_B_BS2<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
5
1
2
C177
C177
C157
C157
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+VREF_DQ_DIMMB
1
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
2
2
R97 10K_0402_5%R97 10K_0402_5%
C178
C178
0.1U_0402_10V6K
0.1U_0402_10V6K
DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_DQS#1
DDR_B_DQS1
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_CKE2_DIMMB
DDR_B_BS2
DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_MA10
DDR_B_BS0
DDR_B_WE#
DDR_B_CAS#
DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D32
DDR_B_D33
DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
R95
R95
1 2
10K_0402_5%
10K_0402_5%
1 2
DDR3 SO-DIMM B
3A@1.5V
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013287-1
TYCO_2-2013287-1
ME@JDIMM2
ME@
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
VTT2
4
+1.5V+1.5V
2
4
DDR_B_D4
6
DDR_B_D5
8
10
DDR_B_DQS#0
12
DDR_B_DQS0
14
16
DDR_B_D6
18
DDR_B_D7
20
22
DDR_B_D12
24
DDR_B_D13
26
28
30
DDR3_DRAMRST#
32
34
DDR_B_D14
36
DDR_B_D15
38
40
DDR_B_D20
42
DDR_B_D21
44
46
48
50
DDR_B_D22
52
DDR_B_D23
54
56
DDR_B_D28
58
DDR_B_D29
60
62
DDR_B_DQS#3
64
DDR_B_DQS3
66
68
DDR_B_D30
70
DDR_B_D31
72
74
DDR_CKE3_DIMMB
76
78
A15
A14
A11
A7
A6
A4
A2
A0
CK1
BA1
S0#
SCL
G2
DDR_B_MA15
80
DDR_B_MA14
82
84
DDR_B_MA11
86
DDR_B_MA7
88
90
DDR_B_MA6
92
DDR_B_MA4
94
96
DDR_B_MA2
98
DDR_B_MA0
100
102
M_CLK_DDR3
104
M_CLK_DDR#3
106
108
DDR_B_BS1
110
DDR_B_RAS#
112
114
DDR_CS2_DIMMB#
116
M_ODT2
118
120
M_ODT3
122
124
126
128
130
DDR_B_D36
132
DDR_B_D37
134
136
138
140
DDR_B_D38
142
DDR_B_D39
144
146
DDR_B_D44
148
DDR_B_D45
150
152
DDR_B_DQS#5
154
DDR_B_DQS5
156
158
DDR_B_D46
160
DDR_B_D47
162
164
DDR_B_D52
166
DDR_B_D53
168
170
172
174
DDR_B_D54
176
DDR_B_D55
178
180
DDR_B_D60
182
DDR_B_D61
184
186
DDR_B_DQS#7
188
DDR_B_DQS7
190
192
DDR_B_D62
194
DDR_B_D63
196
198
200
SMB_DATA_S3
202
SMB_CLK_S3
204
206
4
0.65A@0.75V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
For RF request
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
C54
C54
@
@
2
DDR3_DRAMRST# <12,7>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C280
C280
C281
C281
2
SMB_DATA_S3 <12,15,37,46>
SMB_CLK_S3 <12,15,37,46>
+0.75VS
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
C55
C55
@
@
2
+VREF_CB
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
1
2
3
C163
C163
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
DDR_B_D[0..63] <7>
DDR_B_DQS[0..7] <7>
DDR_B_DQS#[0..7] <7>
DDR_B_MA[0..15] <7>
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C164
C164
2
1
C176
C176
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
0.047U_0402_16V4Z
0.047U_0402_16V4Z
1
C56
C56
@
@
2
Layout Note:
Place near DIMM
+1.5V
12
R86
R86
1K_0402_1%
1K_0402_1%
12
R87
R87
1K_0402_1%
1K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
+1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C282
C282
C161
C161
@
@
@
@
2
Layout Note:
Place near DIMM
+0.75VS
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C173
C173
1
C174
C174
2
2
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C175
C175
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
10U_0603_6.3V6M
10U_0603_6.3V6M
C165
C165
1U_0402_6.3V6K
1U_0402_6.3V6K
Deciphered Date
Deciphered Date
Deciphered Date
2
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
1
C166
C166
2
1
C167
C167
2
2
Layout Note:
Place near DIMM
DDR_B_DM[0:7] connect to GND
2
1
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
C168
C168
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C169
C169
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.1U_0402_10V6K
1
C170
C170
C171
C171
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
DDRIII-SODIMM SLOT2
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C172
C172
2
2
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
13 65Tuesday, March 20, 2012
13 65Tuesday, March 20, 2012
13 65Tuesday, March 20, 2012
0.2
Page 14
5
4
3
2
1
W=20mils W=20mils
+RTCBATT +RTCVCC
D D
+RTCVCC
INTVRMEN
H
*
L
R99
R99
12
1K_0402_5%
1K_0402_5%
1 2
R101 1M_0402_5%R101 1M_0402_5%
1 2
R102 330K_0402_5%R 102 330K_0402_5%
：：：：
Integrated VRM enable (Defaul t)
：：：：
Integrated VRM disable
1
C179
C179
1U_0603_10V4Z
1U_0603_10V4Z
2
SM_INTRUDER#
PCH_INTVRMEN
+RTCVCC
1 2
R103 20K_0402_5 %R 103 20K_0402_5%
1 2
R100 20K_0402_5 %R 100 20K_0402_5%
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
(INTVRMEN should always be pull high.)
+3VS
*
C C
+3V_PCH
*
+3V_PCH
1 2
R105 1K_0402_5%@R105 1K_0402_5%@
HIGH= Enable ( No Reboot )
LOW= Disable (D efault)
R106 1K_0402_5%@R106 1K_0402_5%@
Low = Disabled (Default)
High = Enabled
[Flash De scriptor Secur ity Overide]
R108 1K_0402_5%R108 1K_0402_5%
12
12
HDA_SPKR
HDA_SDOUT
HDA_SYNC
ME_FLASH<45>
This signal has a weak intern al pull-down
On Die PLL VR S elect is suppl ied by
1.5V when smapl ed high (Defau lt)
*
1.8V when sampl ed low
Needs to be pul led High for C hief River pla tfrom
ME_FLASH
+3V_PCH
SPI_CLK_PCH_0
SPI_CLK_PCH_1
SPI_SB_CS0#_R
SPI_CS1#_R
SPI_SI_R
SPI_SI_R1 SPI_SI
SPI_SO_L
SPI_SO_L1
CMOS
1
2
1
@ JME
@
2
HDA_SPKR<42>
HDA_SDIN0<42>
1 2
1 2
1 2
1 2
1 2
1 2
12
JCMOS
JCMOS
SHORT PADS@
SHORT PADS@
12
JME
SHORT PADS
SHORT PADS
12
12
12
12
12
12
C183
C183
C182
C182
R109 0_0402_5%R109 0_0402_5%
R107 1K_0402_1%@R107 1K_0402_1%@
R317 10K_0402_5 %@R317 10K_0 402_5%@
R110 51_0402_5%R110 51_0402_5%
R298 33_0402_5%R298 33_0402_5%
R299 33_0402_5%R299 33_0402_5%
R130 0_0402_5%R130 0_0402_5%
R303 0_0402_5%R303 0_0402_5%
R133 33_0402_5%R133 33_0402_5%
R204 33_0402_5%R204 33_0402_5%
R131 33_0402_5%R131 33_0402_5%
R294 33_0402_5%R294 33_0402_5%
U4A
U4A
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN SERIRQ
HDA_BIT_CLK
HDA_SYNC
HDA_SPKR
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_GPIO33
PCH_GPIO13
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
SPI_CLK_PCH
SPI_SB_CS0#
SPI_CS1#
SPI_SO_R
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ0#
LDRQ1# / GPIO23
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
EC and Mini car d debug port
C38
LPC_AD0
A38
LPC_AD1
B37
LPC_AD2
C37
LPC_AD3
D36
LPC_FRAME#
E36
K36
V5
AM3
SATA_DTX_C_IRX_N0
AM1
SATA_DTX_C_IRX_P0
AP7
SATA_ITX_C_DRX_N0
AP5
SATA_ITX_C_DRX_P0
AM10
SATA_DTX_C_IRX_N1
AM8
SATA_DTX_C_IRX_P1
AP11
SATA_ITX_C_DRX_N1
AP10
SATA_ITX_C_DRX_P1
AD7
SATA_DTX_C_IRX_N2
AD5
SATA_DTX_C_IRX_P2
AH5
SATA_ITX_C_DRX_N2
AH4
SATA_ITX_C_DRX_P2
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
SATA_COMP
AB12
AB13
SATA3_COMP
AH1
RBIAS_SATA3
P3
HDD_LED#
V14
PCH_GPIO21
P1
SATA_DET#
LPC_AD0 <37,45>
LPC_AD1 <37,45>
LPC_AD2 <37,45>
LPC_AD3 <37,45>
LPC_FRAME# <37,45>
SERIRQ <45>
R104 10K_0402_5%R104 10K_0402_5%
12
12
C184 0.01U_0402_16V7KC184 0.01U_0402_16V7K
12
C185 0.01U_0402_16V7KC185 0.01U_0402_16V7K
12
C273 0.01U_0402_16V7KC273 0.01U_0402_16V7K
12
C272 0.01U_0402_16V7KC272 0.01U_0402_16V7K
12
C186 0.01U_0402_16V7KC186 0.01U_0402_16V7K
12
C187 0.01U_0402_16V7KC187 0.01U_0402_16V7K
1 2
R111 37.4_0402_1%R111 37.4_0402_1%
1 2
R113 49.9_0402_1%R113 49.9_0402_1%
1 2
R115 750_0402_1%R115 750_0402_1%
R120 10K_0402_5%R120 10K_0402_5%
R119 10K_0402_5%R119 10K_0402_5%
R316 10K_0402_5%R316 10K_0402_5%
12
12
12
+3VS
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
SATA_ITX_DRX_N2_CONN
SATA_ITX_DRX_P2_CONN
+1.05VS_VCC_SATA
+1.05VS_SATA3
HDD_LED# <47>
SATA_DET# <37>
+3VS
+3VS
+3VS
SSD
HDD
ODD
SATA_DTX_C_IRX_N0 <3 7>
SATA_DTX_C_IRX_P0 <37>
SATA_ITX_DRX_N0 <37>
SATA_ITX_DRX_P0 <37>
SATA_DTX_C_IRX_N1 <4 1>
SATA_DTX_C_IRX_P1 <41>
SATA_ITX_DRX_N1 <41>
SATA_ITX_DRX_P1 <41>
SATA_DTX_C_IRX_N2 <4 1>
SATA_DTX_C_IRX_P2 <41>
SATA_ITX_DRX_N2_CONN <41>
SATA_ITX_DRX_P2_CONN <41>
B B
HDA AUDIO
HDA_BITCLK_AUDIO<42>
HDA_SYNC_AUDIO<42>
HDA_RST_AUDIO#<42>
HDA_SDOUT_AUDIO<42>
1 2
R112
R112
33_0402_5%
33_0402_5%
1 2
R114
R114
33_0402_5%
33_0402_5%
1 2
R116
R116
33_0402_5%
33_0402_5%
1 2
R118
R118
33_0402_5%
33_0402_5%
HDA_BIT_CLK
HDA_SYNC_R
HDA_RST#
HDA_SDOUT
12
R1353
R1353
1M_0402_5%
1M_0402_5%
+5VS
G
G
2
S
S
13
HDA_SYNC
D
D
Q10
Q10
BSS138_NL_SOT23-3
BSS138_NL_SOT23-3
1
2
R98
R98
1 2
10M_0402_5%
10M_0402_5%
Y1
Y1
1 2
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
C180
C180
18P_0402_50V8J
18P_0402_50V8J
PCH_RTCX1
PCH_RTCX2
1
C181
C181
18P_0402_50V8J
18P_0402_50V8J
2
For EMI
SPI_CLK_PCH
33_0402_5%
33_0402_5%
22P_0402_50V8J
22P_0402_50V8J
R124
C190
12
@R124
@
@C190
@
4MB P/N : SA00003K800 2MB P/N : SA00003FO10
+3V_PCH +3V_PCH +3V_PCH
12
R123
R123
@
@
200_0402_5%
200_0402_5%
12
R128
R128
@
@
100_0402_1%
100_0402_1%
4
5
12
R122
R122
@
@
200_0402_5%
200_0402_5%
12
R126
R126
@
@
100_0402_1%
100_0402_1%
12
R121
R121
@
@
200_0402_5%
A A
200_0402_5%
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
12
R125
R125
@
@
100_0402_1%
100_0402_1%
+3VS
1 2
R127 3.3K_0402_5%R 127 3.3K_0402_5%
1 2
R129 3.3K_0402_5%R 129 3.3K_0402_5%
U5
U5
SPI_SB_CS0#_R
SPI_SO_L
SPI_WP#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
1
CS#
2
DO
HOLD#
3
WP#
4
GND
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
3
VCC
CLK
8
7
6
5
DI
SPI_WP#
SPI_HOLD#
SPI_HOLD#
SPI_CLK_PCH_0
SPI_SI_R
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+3VS
1
C191
C191
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
+3VS
1 2
R292 3.3K_0402_5%R 292 3.3K_0402_5%
1 2
R246 3.3K_0402_5%R 246 3.3K_0402_5%
SPI_CS1#_R
SPI_SO_L1
SPI_WP#_1
1
2
3
4
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SPI_WP#_1
U9
U9
CS#
DO(IO1)
HOLD#(IO3)
WP#(IO2)
GND
DI(IO0)
W25Q16BVSSIG_SO8
W25Q16BVSSIG_SO8
VCC
CLK
SPI_HOLD#_1
8
7
SPI_HOLD#_1
6
SPI_CLK_PCH_1
5
SPI_SI_R1
+3VS
1
C275
C275
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Compal Electronics, Inc.
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
14 65Tuesday, March 20, 2012
14 65Tuesday, March 20, 2012
14 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 15
5
4
3
2
1
VGA, EC, Thermal Sensor
10K_0402_5%
10K_0402_5%
1K_0402_5%
1K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
3
OSC
2
NC
10P_0402_50V8J
10P_0402_50V8J
C198
@C198
@
1 2
C199
@C199
@
1 2
+3V_PCH
+3V_PCH
C197
C197
1
2
U4B
U4B
PCIE_PRX_DTX_N1<38>
LAN
D D
WLAN
Card Reader
C C
PCIE_PRX_DTX_P1<38>
PCIE_PTX_C_DRX_N1<38>
PCIE_PTX_C_DRX_P1<38>
PCIE_PRX_DTX_N2<37>
PCIE_PRX_DTX_P2<37>
PCIE_PTX_C_DRX_N2<37>
PCIE_PTX_C_DRX_P2<37>
PCIE_PRX_DTX_N4<44>
PCIE_PRX_DTX_P4<44>
PCIE_PTX_C_DRX_N4<44>
PCIE_PTX_C_DRX_P4<44>
LAN
WLAN
1 2
C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K
1 2
C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K
1 2
C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K
1 2
C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K
1 2
C277 0.1U_0402_10V7KC277 0.1U_0402_10V7K
1 2
C276 0.1U_0402_10V7KC276 0.1U_0402_10V7K
CLK_PCIE_LAN#<38>
CLK_PCIE_LAN<38>
CLKREQ_LAN#<38>
CLK_PCIE_WLAN1#<37>
CLK_PCIE_WLAN1<37>
WLAN_CLKREQ1#<37>
Only for 15" TV function
Card Reader
B B
2nd VGA
+3V_PCH
R152 10K_0402_5%R152 10K_0402_5%
R168 10K_0402_5%R168 10K_0402_5%
R165 10K_0402_5%R165 10K_0402_5%
R147 10K_0402_5%R147 10K_0402_5%
R170 10K_0402_5%R170 10K_0402_5%
R172 10K_0402_5%R172 10K_0402_5%
R174 10K_0402_5%R174 10K_0402_5%
+3VS
A A
R158 10K_0402_5%R158 10K_0402_5%
R308 10K_0402_5%R308 10K_0402_5%
12
12
12
12
12
12
12
12
12
CLK_PCIE_CARD_PCH#<44>
CLK_PCIE_CARD_PCH<44>
CLKREQ_LAN#
PCH_GPIO25
PCH_GPIO26
PCH_GPIO44
CLK2_REQ_GPU#_R
PCH_GPIO45
PCH_GPIO46
WLAN_CLKREQ1#
CLKREQ_TV#_R
CLK_PCIE_2VGA#<32>
CLK_PCIE_2VGA<32>
CLK2_REQ_GPU#_R<32>
PCIE_PRX_DTX_N1
PCIE_PRX_DTX_P1
PCIE_PTX_DRX_N1
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4
CLK_PCIE_LAN#
CLK_PCIE_LAN
CLKREQ_LAN#
CLK_PCIE_WLAN1#
CLK_PCIE_WLAN1
WLAN_CLKREQ1#
CLKREQ_TV#_R
CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH
PCH_GPIO25
PCH_GPIO26
PCH_GPIO44
CLK_PCIE_2VGA#
CLK_PCIE_2VGA
CLK2_REQ_GPU#_R
PCH_GPIO45
PCH_GPIO46
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
SMBALERT# / GPIO11
SML0ALERT# / GPIO60
SML1CLK / GPIO58
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_OUT
XCLK_RCOMP
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
XTAL25_IN
E12
PCH_GPIO11
H14
PCH_SMBCLK
C9
PCH_SMBDATA
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
K43
F47
H47
K49
DRAMRST_CNTRL_PC H <7>
SML0CLK
SML0DATA
PCH_HOT#
SML1CLK
SML1DATA
CLK_REQ_GPU#_R
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_CPU_DMI#
CLK_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLKIN_DMI2#
CLKIN_DMI2
CLK_BUF_DREF_96M#
CLK_BUF_DREF_96M
CLK_BUF_PCIE_SATA#
CLK_BUF_PCIE_SATA
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
S_DGPU_RST_R
PCH_GPIO67
BIOS Request SKU ID
+3V_PCH
1 2
R202 10K_0402_5%R202 10K_0402_5%
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
1 2
R155 10K_0402_5%R155 10K_0402_5 %
1 2
R157 10K_0402_5%R157 10K_0402_5 %
1 2
R159 10K_0402_5%R159 10K_0402_5 %
1 2
R160 10K_0402_5%R160 10K_0402_5 %
1 2
R162 10K_0402_5%R162 10K_0402_5 %
1 2
R163 10K_0402_5%R163 10K_0402_5 %
1 2
R164 10K_0402_5%R164 10K_0402_5 %
1 2
R166 10K_0402_5%R166 10K_0402_5 %
1 2
R167 10K_0402_5%R167 10K_0402_5 %
CLK_PCI_LPBACK <18>
1 2
R171 90.9_0402_1%R171 90.9_0402_1%
R182 10K_0402_5%@R 182 10K_0402_5%@
1 2
R1504 0_0402_5%@R1504 0_0402_5%@
PCH_GPIO67 <19>
R136
R136
1 2
2.2K_0402_5%
2.2K_0402_5%
R135
R135
1 2
2.2K_0402_5%
2.2K_0402_5%
PCH_SMBCLK
PCH_SMBDATA SMB_DATA_S3
R141
R141
+3V_PCH +3V_PCH
CLK_REQ_GPU#_R <23>
12
1 2
R142
R142
1 2
SML1CLK
SML1DATA
+3V_PCH
+1.05VS_VCCDIFFCLKN
+3VS
5
G
G
3 4
D
D
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
S_DGPU_RST <18,32>
2N7002KDWH
Vth= min 1V, max 2.5V
2
ESD 2KV
G
G
6 1
D
D
S
S
SMB_CLK_S3
S
S
Q60A
Q60A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q60B
Q60B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
5
G
G
3 4
D
D
2
G
G
6 1
D
D
S
S
Q61A
Q61A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q61B
Q61B
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
PCH_GPIO11
DRAMRST_CNTRL_PC H
SML0CLK
SML0DATA
PCH_HOT#
XTAL25_IN
XTAL25_OUT
10P_0402_50V8J
10P_0402_50V8J
Change C196, C1 97 value of Ca p
from 33pF to 10 pF for TXC rec ommend
Reserve for EMI please close to PCH
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
R137
R137
12
2.2K_0402_5%
2.2K_0402_5%
R138
R138
12
2.2K_0402_5%
2.2K_0402_5%
SMB_CLK_S3 <12,13,37,46>
SMB_DATA_S3 <12,13,37,46>
DIMM1, DIMM2, Mini CARD, TP
EC_SMB_CK2
EC_SMB_DA2
C196
C196
@R175
@
33_0402_5%
33_0402_5%
@R176
@
33_0402_5%
33_0402_5%
EC_SMB_CK2 <23,32,40,45>
EC_SMB_DA2 <23,32,40,45>
R134
R134
12
R329
R329
12
R335
R335
1 2
R336
R336
1 2
R140
R140
12
R169
R169
1 2
1M_0402_5%
1M_0402_5%
Y2
Y2
4
NC
1
OSC
25MHZ_12PF_X3G025000DC1H~D
25MHZ_12PF_X3G025000DC1H~D
1
2
R175
R176
12
12
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
PCH (2/9) PCIE, SMBUS, CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
15 65Tuesday, March 20, 2012
15 65Tuesday, March 20, 2012
15 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 16
5
D D
+3VS
1
C1060
C1060
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VGATE<59>
C C
B B
+3V_PCH
MC74VHC1G08DFT2G SC70 5P
MC74VHC1G08DFT2G SC70 5P
R192 200_0402_5%R192 200_0402_5%
R194 10K_0402_5%R194 10K_0402_5%
VGATE
PCH_PWROK
12
12
2
2
B
1
A
U6
U6
For Deep S3
For Deep S3
PM_DRAM_PWR GD
SUSWARN#
5
P
4
Y
12
G
3
R180
@ R180
@
100K_0402_1%
100K_0402_1%
SUSACK#<45 > DPWROK_EC <45>
PCH_PWROK<45>
APWROK can be c onnect to
PWROK if iAMT d isable
PM_DRAM_PWR GD<6>
SUSWARN#<45>
PBTN_OUT#<45>
AC_PRESENT<45>
+3V_PCH
SYS_PWROK <6>
+3VS
+3VS
R1290 200_0402_5%@R1290 200_0402_5%@
7/28 Modify fol low Module Des ign.
4
DMI_CTX_PRX_N0<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P2<5>
DMI_CTX_PRX_P3<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_P0<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
+1.05VS
DS3@
DS3@
R1457 0_0402_5%
R1457 0_0402_5%
R184 10K_0402_5%R184 10K_0402_5%
R190
R190
1 2
0_0402_5%
0_0402_5%
1 2
R193 0_0402_5%R193 0_0402_5%
DS3@
DS3@
R1455 0_0402_5%
R1455 0_0402_5%
1 2
R198 0_0402_5%R198 0_0402_5%
1 2
R208 0_0402_5%R208 0_0402_5%
1 2
R200 8.2K_0402_5%R200 8.2K_0402_5%
R201 10K_0402_5%R201 10K_0402_5%
12
R177
R177
1 2
49.9_0402_1%
49.9_0402_1%
R178
R178
1 2
750_0402_1%
750_0402_1%
4mil width and place
within 500mil o f the PCH
12
12
R191
R191
0_0402_5%
0_0402_5%
12
12
PM_DRAM_PWR GD
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_IRCOMP
RBIAS_CPY
SUSACK#_R
SYS_RST#
SYS_PWROK
PWROK
12
APWROK
PM_DRAM_PWR GD
PCH_RSMRST#_R
SUSWARN#_R
PBTN_OUT#_R
AC_PRESENT_R
PCH_GPIO72
RI#
U4C
U4C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPW RDNACK/GPIO30
E20
PWRBTN#
H20
ACPRESENT / GPIO31
E10
BATLOW# / GPIO72
A10
RI#
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3
DMI
FDI
DMI
FDI
CLKRUN# / GPIO32
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
System Power Management
System Power Management
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
2
BJ14
FDI_CTX_PRX_N0
AY14
FDI_CTX_PRX_N1
BE14
FDI_CTX_PRX_N2
BH13
FDI_CTX_PRX_N3
BC12
FDI_CTX_PRX_N4
BJ12
FDI_CTX_PRX_N5
BG10
FDI_CTX_PRX_N6
BG9
FDI_CTX_PRX_N7
BG14
FDI_CTX_PRX_P0
BB14
FDI_CTX_PRX_P1
BF14
FDI_CTX_PRX_P2
BG13
FDI_CTX_PRX_P3
BE12
FDI_CTX_PRX_P4
BG12
FDI_CTX_PRX_P5
BJ10
FDI_CTX_PRX_P6
BH9
FDI_CTX_PRX_P7
AW16
FDI_INT
AV12
FDI_FSYNC0
BC10
FDI_FSYNC1
AV14
FDI_LSYNC0
BB10
FDI_LSYNC1
A18
DSWODVREN
E22
PCH_DPWROK_R
B9
N3
PM_CLKRUN#
G8
SUS_STAT#
N14
SUSCLK
D10
PM_SLP_S5#
H4
PM_SLP_S4#
F4
PM_SLP_S3#
G10
Can be left NC when IAMT is n ot support on the platfrom
G16
PM_SLP_SUS#_R
AP14
H_PM_SYNC
K14
PCH_GPIO29
Can be left NC if no use inte grated LAN.
10/06 Test poin t request
FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>
FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>
FDI_INT <5>
FDI_FSYNC0 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_LSYNC1 <5>
1 2
R181 0_0402_5%R181 0_0402_5%
1 2
R185 0_0402_5%R185 0_0402_5%
1 2
R253 10K_0402_5%R253 10K_0402_5%
T60PAD T60PAD
T61PAD T61PAD
T62PAD T62PAD
PM_SLP_S4# <45>EC_RSMRST#<45>
PM_SLP_S3# <45>
DS3@
DS3@
R1447 0_0402_5%
R1447 0_0402_5%
12
H_PM_SYNC <6>
T74PAD T74PAD
DPWROK_EC
PCIE_WAKE#WAKE#
1
DSWODVREN
DSWODVREN - On Die DSW VR Ena ble
*
H
：：：：
Enable
L
：：：：
Disable
For Deep S3
PCIE_WAKE# <19,37,38>
WAKE#
PM_SLP_SUS# <45,51>
1 2
R186 10K_0402_5%R186 10K_0402_5%
For Deep S3
+RTCVCC
12
12
+3V_PCH
R179
R179
330K_0402_5%
330K_0402_5%
R183
R183
330K_0402_5%@
330K_0402_5%@
+3VALW
R195 200K_0402_5 %R195 200K_0402_5 %
A A
12
5
AC_PRESENT_R
R197 10K_0402_5%R197 10K_0402_5%
12
4
PCH_RSMRST#_R
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
PCH (3/9) DMI,FDI,PM,
PCH (3/9) DMI,FDI,PM,
PCH (3/9) DMI,FDI,PM,
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
16 65Tuesday, March 20, 2012
16 65Tuesday, March 20, 2012
16 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 17
5
D D
4
3
2
1
+3VS
OPT@
OPT@
R836 2.2K_0402_5%
R836 2.2K_0402_5%
OPT@
OPT@
R835 2.2K_0402_5%
R835 2.2K_0402_5%
OPT@
OPT@
1 2
R205 2.2K_0402_5%
R205 2.2K_0402_5%
OPT@
OPT@
1 2
R261 2.2K_0402_5%
R261 2.2K_0402_5%
OPT@
OPT@
R257 2.37K_0402_1%
R257 2.37K_0402_1%
12
EDID_CLK
EDID_DATA
CTRL_CLK
CTRL_DATA CTRL_CLK
LVDS_IBG
PCH_ENBKL<34>
PCH_ENVDD<34>
PCH_PWM<34>
EDID_CLK<34>
EDID_DATA<34>
PCH_ENBKL
PCH_ENVDD
EDID_CLK
EDID_DATA
CTRL_DATA
LVDS_IBG
Remove netname LVD_REF
R211
R211
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A1#
LVDS_A2#
LVDS_A0
LVDS_A1
LVDS_A2
DAC_BLU
DAC_GRN
DAC_RED
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
CRT_IREF
12
LVDS_ACLK#<34>
LVDS_ACLK<34>
C C
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
1 2
OPT@
OPT@
1 2
12
12
12
R266 150_0402_1%
R266 150_0402_1%
R264 150_0402_1%
R264 150_0402_1%
R262 150_0402_1%
R262 150_0402_1%
B B
+3VS
R848 2.2K_0402_5%
R848 2.2K_0402_5%
R849 2.2K_0402_5%
R849 2.2K_0402_5%
DAC_BLU
DAC_GRN
DAC_RED
CRT_DDC_CLK
CRT_DDC_DATA
LVDS_A0#<34>
LVDS_A1#<34>
LVDS_A2#<34>
LVDS_A0<34>
LVDS_A1<34>
LVDS_A2<34>
DAC_BLU<35>
DAC_GRN<35>
DAC_RED<35>
CRT_DDC_CLK<35>
CRT_DDC_DATA<35>
CRT_HSYNC<35>
CRT_VSYNC<35>
1K_0402_1%
1K_0402_1%
U4D
U4D
J47
L_BKLTEN
M45
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
AF37
LVD_IBG
AF36
LVD_VBG
AE48
LVD_VREFH
AE47
LVD_VREFL
AK39
LVDSA_CLK#
AK40
LVDSA_CLK
AN48
LVDSA_DATA#0
AM47
LVDSA_DATA#1
AK47
LVDSA_DATA#2
AJ48
LVDSA_DATA#3
AN47
LVDSA_DATA0
AM49
LVDSA_DATA1
AK49
LVDSA_DATA2
AJ47
LVDSA_DATA3
AF40
LVDSB_CLK#
AF39
LVDSB_CLK
AH45
LVDSB_DATA#0
AH47
LVDSB_DATA#1
AF49
LVDSB_DATA#2
AF45
LVDSB_DATA#3
AH43
LVDSB_DATA0
AH49
LVDSB_DATA1
AF47
LVDSB_DATA2
AF43
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
M40
CRT_DDC_DATA
M47
CRT_HSYNC
M49
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
SDVO_INTN
SDVO_INTP
DDPB_HPD
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_HPD
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49
P46
P42
AP47
AP49
AT38
AY47
AY49
AY43
AY45
BA47
BA48
BB47
BB49
M43
M36
AT45
AT43
BH41
BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42
HDMICLK
HDMIDAT
TMDS_B_HPD
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
HDMICLK <36>
HDMIDAT <36>
TMDS_B_HPD <36>
TMDS_B_DATA2#_PCH <36>
TMDS_B_DATA2_PCH <36>
TMDS_B_DATA1#_PCH <36>
TMDS_B_DATA1_PCH <36>
TMDS_B_DATA0#_PCH <36>
TMDS_B_DATA0_PCH <36>
TMDS_B_CLK#_PCH <36>
TMDS_B_CLK_PCH <36>
HDMICLK
HDMIDAT
OPT@
OPT@
OPT@
OPT@
12
12
R203 2.2K_0402_5%
R203 2.2K_0402_5%
R267 2.2K_0402_5%
R267 2.2K_0402_5%
+3VS
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
CRT
CRT
DDPD_AUXP
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
PCH (4/9) LVDS,CRT,DP,HDMI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
17 65Tuesday, March 20, 2012
17 65Tuesday, March 20, 2012
17 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 18
5
4
3
2
1
+3VS
D D
+3VS
C C
GPIO53 => This Signal has a weak internal pull-up.
NOTE: The internal pull-up is disabled after
PLTRST# deasserts.
B B
RP2
RP2
18
PCI_PIRQA#
27
PCI_PIRQD#
36
PCI_PIRQC#
45
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
8.2K_0804_8P4R_5%
R305 8.2K_0402_5%@R305 8.2K_ 0402_5%@
R297 8.2K_0402_5%@R297 8.2K_ 0402_5%@
R213 8.2K_0402_5%R213 8.2K_0402_5%
R225 8.2K_0402_5%R225 8.2K_0402_5%
R212 8.2K_0402_5%R212 8.2K_0402_5%
R252 8.2K_0402_5%R252 8.2K_0402_5%
R306 8.2K_0402_5%
R306 8.2K_0402_5%
R214 8.2K_0402_5%
R214 8.2K_0402_5%
R215 1K_0402_5%@R215 1K_0402_5%@
A16 swap overide Strap/Top-Block
Swap Override jumper
PCI_GNT3#
PCI_PIRQB#
RP1
RP1
18
PCH_GPIO2
27
DGPU_PWR_EN
36
PCH_GPIO4
45
ODD_DA#_R
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
1 2
@
@
12
Low = A16 swap
override/Top-Block
Swap Override enabled
**High=Default
*
PPT EDS DOC#474146
PCH_GPIO51
DGPU_GC6_EN
PCH_GPIO5
PCH_WL_OFF#
NVDD_PWR_EN
DGPU_HOLD_RST#
DGPU_GC6_EN
DGPU_HOLD_RST#
PCH_WL_OFF#
U4E
U4E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
USB3.0
USB30_RX_N1<34>
USB30_RX_N3<48>
USB30_RX_P1<34>
USB30_RX_P3<48>
USB30_TX_N1<34>
USB30_TX_N3<48>
USB30_TX_P1<34>
USB30_TX_P3<48>
12
Camera USB
LEFT USB
USB30_RX_N1
USB30_RX_N3
USB30_RX_P1
USB30_RX_P3
USB30_TX_N1
USB30_TX_N3
USB30_TX_P1
USB30_TX_P3
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
DGPU_HOLD_RST#
NVDD_PWR_EN
DGPU_PWR_EN
PCH_GPIO51
DGPU_GC6_EN
PCH_WL_OFF#
PCH_GPIO2
ODD_DA#_R
PCH_GPIO4
PCH_GPIO5
20111024 Del PC I_PME#
PLT_RST#
CLK_PCI_LPBACK_R
CLK_PCI_EC_R
CLK_PCI_DB_R
Port1
Port2
Port3
Port4
DGPU_HOLD_RST#<23>
1 2
S_DGPU_RST<15,32>
CLK_PCI_LPBACK<15>
CLK_PCI_EC<45>
CLK_PCI_DB<37>
R1505 0_0402_5%R1505 0_0402_5%
NVDD_PWR_EN<58>
DGPU_PWR_EN<23,51>
DGPU_GC6_EN<27>
PCH_WL_OFF#<37>
ODD_DA#_R<41>
PLT_RST#<23,32,37,38,44,45,6>
1 2
R219 22_0402_5%R219 22_0402_5%
1 2
R220 22_0402_5%R220 22_0402_5%
R173 22_0402_5%
R173 22_0402_5%
@
@
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
USB3Rn1
BC30
USB3Rn2
BE32
USB3Rn3
BJ32
USB3Rn4
BC28
USB3Rp1
BE30
USB3Rp2
BF32
USB3Rp3
BG32
USB3Rp4
AV26
USB3Tn1
BB26
USB3Tn2
AU28
USB3Tn3
AY30
USB3Tn4
AU26
USB3Tp1
AY26
USB3Tp2
AV28
USB3Tp3
AW30
USB3Tp4
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
RSVD
RSVD
PCI
PCI
USB
USB
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
USB DEBUG= PORT1 AND PORT9
C24
USB20_N0
A24
USB20_P0
C25
B25
C26
USB20_N2
A26
USB20_P2
K28
H28
E28
D28
C28
USB20_N5
A28
USB20_P5
C29
B29
N28
M28
Some PCH config not support U SB port 6 & 7.
L30
K30
G30
USB20_N9
E30
USB20_P9
C30
USB20_N10
A30
USB20_P10
L32
K32
G32
E32
C32
USB20_N13
A32
USB20_P13
C33
USBRBIAS
Within 500 mils
B33
A14
USB_OC0#
K20
USB_OC1#
B17
USB_OC2#
C16
USB_OC3#
L16
USB_OC4#
A16
USB_OC5#
D14
USB_OC6#
C14
USB_OC7#
USB20_N0 <34>
USB20_P0 <34>
USB20_N2 <48>
USB20_P2 <48>
USB20_N5 <49>
USB20_P5 <49>
USB20_N9 <49>
USB20_P9 <49>
USB20_N10 <37>
USB20_P10 <37>
USB20_N13 <47>
USB20_P13 <47>
1 2
22.6_0402_1%
22.6_0402_1%
USB_OC1# <48>
USB_OC2# <49>
USB_OC4# <49>
Camera
LEFT USB
RIGHT USB 1 (CHARGER PORT, SUB/B)
RIGHT USB 2 (SUB/B)
WLAN
BT
R218
R218
USB_OC5#
USB_OC2#
USB_OC7#
USB_OC0#
USB_OC6#
USB_OC1#
USB_OC4#
USB_OC3#
RP3
RP3
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
RP4
RP4
4 5
3 6
2 7
1 8
10K_1206_8P4R_5%
10K_1206_8P4R_5%
+3V_PCH
PCH_GPIO51
Boot BIOS Strap bit1 BBS1
A A
GNT1#/
GPIO51
1 2
R221 1K_0402_5%@R221 1K_0402_5%@
Bit11
Bit10
0 1
1
1
0
5
0
1
0
Boot BIOS
Destination
Reserved
Reserved
SPI
*
LPC
(Default)
PLT_RST#
12
R223
R223
100K_0402_5%
100K_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
PCH (5/9) PCI, USB
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
18 65Tuesday, March 20, 2012
18 65Tuesday, March 20, 2012
18 65Tuesday, March 20, 2012
0.2
Page 19
5
D D
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
C C
*
B B
+3V_PCH
+3VS
10K_0402_5%
10K_0402_5%
+3V_PCH
R235 10K_0402_5%R235 10K_0402_5 %
H：On-Die voltage regulator enab le
*
L：On-Die PLL Volt age Regulator disable
PCH_GPIO27 (Have internal Pull-High)
High: VCCVRM VR Enable
Low: VCCVRM VR Disable
+3VALW
1 2
R240 1K_0402_5%@R240 1K_0402_5%@
DS3@
DS3@
1 2
R251
R251
1 2
12
1 2
10K_0402_5%
10K_0402_5%
1 2
R207 10K_0402_5%
R207 10K_0402_5%
R245 10K_0402_5%@R245 10K_0402_5%@
200K_0402_5%
200K_0402_5%
+3VS
R259 10K_0402_5%R259 10K_0402_5 %
12
12
PCH_GPIO28
R250
R250
SLAVE_PRESENT#
R1493
R1493
DS3_WAKE#_R
PCH_GPIO37
EC_SCI#
EC_SMI#
ODD_DETECT#
+3VS
+3VS
+3V_PCH
EC_LID_OUT#<45>
+3VS
DGPU_PWROK<27,32,55,58>
PCH_BT_DISABLE#<37>
PCH_BT_ON#<37,47>
+3VS
PCIE_WAKE#<16,37,38>
+3VS
+3VS
4
GC6_EVENT#<23,32>
1 2
R233 10K_0402_5%R233 10K_0402_5 %
1 2
R227 10K_0402_5%R227 10K_0402_5 %
1 2
R228 10K_0402_5%R228 10K_0402_5 %
1 2
R229 10K_0402_5%@R229 10K_0402_5%@
1 2
R230 10K_0402_5%R230 10K_0402_5 %
1 2
R231 10K_0402_5%R231 10K_0402_5 %
1 2
R232 10K_0402_1%
R232 10K_0402_1%
1 2
R238 10K_0402_5%R238 10K_0402_5 %
1 2
R241 10K_0402_5 % R241 10K_0402_5%
+3V_PCH
+3VS
1 2
1 2
R243 10K_0402_5%R243 10K_0402_5 %
1 2
R247 10K_0402_5%R247 10K_0402_5 %
1 2
R248 10K_0402_5%R248 10K_0402_5 %
1 2
R249 10K_0402_5%R249 10K_0402_5 %
SLAVE_PRESENT#<32>
R242
R242
3
PECI
RCIN#
DF_TVS
NC_1
PCH_GPIO70
C40
PCH_GPIO68
B41
S_DGPU_PWR_EN
C41
A40
S_NVDD_PWR_EN
P4
AU16
P5
KBRST#
AY11
AY10
PCH_THRMTRIP#_R
T14
AY1
NV_CLE
AH8
AK11
AH10
AK10
P37
BG2
BG48
BH3
BH47
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
X
X
X
X
0
1
PCH_GPIO70
Function
Optimus
Reserve
DIS
(SLI)
Reserve
14"
GC6_EVENT#
PCH_GPIO1
PCH_GPIO6
EC_SCI#<45>
EC_SMI#<45>
@
@
ODD_EN<41>
@
@
12
R2240_0402_5%
R2240_0402_5%
10K_0402_5%
10K_0402_5%
ODD_DETECT#<41>
EC_SCI#
EC_SMI#
PCH_GPIO12
EC_LID_OUT#
PCH_GPIO16
DGPU_PWROK
PCH_BT_DISABLE#
ODD_EN
DS3_WAKE#_R
PCH_GPIO28
PCH_BT_ON#
PCH_GPIO35
ODD_DETECT#
PCH_GPIO37
PCH_GPIO38
PCH_GPIO39
PCH_GPIO48
PCH_GPIO49
SLAVE_PRESENT#
15"
U4F
U4F
T7
BMBUSY# / GPIO0
A42
TACH1 / GPIO1
H36
TACH2 / GPIO6
E38
TACH3 / GPIO7
C10
GPIO8
C4
LAN_PHY_PWR_CTRL / GPIO12
G2
GPIO15
U2
SATA4GP / GPIO16
D40
TACH0 / GPIO17
T5
SCLOCK / GPIO22
E8
GPIO24
E16
GPIO27
P8
GPIO28
K1
STP_PCI# / GPIO34
K4
GPIO35
V8
SATA2GP / GPIO36
M5
SATA3GP / GPIO37
N2
SLOAD / GPIO38
M3
SDATAOUT0 / GPIO39
V13
SDATAOUT1 / GPIO48
V3
SATA5GP / GPIO49 / TEMP_ALERT#
D6
GPIO57
A4
VSS_NCTF_1
A44
VSS_NCTF_2
A45
VSS_NCTF_3
A46
VSS_NCTF_4
A5
VSS_NCTF_5
A6
VSS_NCTF_6
B3
VSS_NCTF_7
B47
VSS_NCTF_8
BD1
VSS_NCTF_9
BD49
VSS_NCTF_10
BE1
VSS_NCTF_11
BE49
VSS_NCTF_12
BF1
VSS_NCTF_13
BF49
VSS_NCTF_14
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
PCH_GPIO38
0 0
0 1
1 0
1 1
X X
X X
GPIO
GPIO
NCTF
NCTF
PCH_GPIO67
TACH4 / GPIO68
TACH5 / GPIO69
TACH6 / GPIO70
TACH7 / GPIO71
A20GATE
PROCPWRGD
THRMTRIP#
INIT3_3V#
CPU/MISC
CPU/MISC
TS_VSS1
TS_VSS2
TS_VSS3
TS_VSS4
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
VSS_NCTF_32
2
S_DGPU_PWR_EN <32,51>
9/18 Reseve for SKU ID
S_NVDD_PWR_EN <32>
1 2
R236 10K_0402_5%R236 10K_0402_5 %
KBRST# <45>
1 2
R239 390_0402_5%R239 390_0402_5%
H_CPUPWRGD <6>
H_THRMTRIP#
INIT3_3V
This signal has weak internal
PU, can't pull low
Intel schematic reviwe recommand.
SKU ID
S_DGPU_PWR_EN
S_NVDD_PWR_EN
+3VS
GATEA20 <45 >
H_THRMTRIP# <6>
PCH_THRMTRIP#_R <23,32>
NV_CLE
1
R711
R711
PCH_GPIO38
PCH_GPIO67<15>
PCH_THRMTRIP#_R
PROC_SEL
PCH_GPIO67
PCH_GPIO70
R712
R712
1 2
R268 10K_0402_5%R268 10K_0402_5 %
1 2
R237 10K_0402_5%R237 10K_0402_5 %
PCH_GPIO68
KBRST#
1 2
R255 10K_0402_5%R255 10K_0402_5 %
1 2
R226 10K_0402_5%R226 10K_0402_5 %
R244 10K_0402_5%R244 10K_0402_5 %
H : Sandy Bridge
L : IVY Bridge
+1.8VS
1 2
R217 1K_0402_5%R217 1K_0402_5%
CLOSE TO THE BRANCHING POINT
R708
R708
SLI@
SLI@
1 2
R709
R709
OPT@
OPT@
1 2
1 2
R216
R216
2.2K_0402_5%
2.2K_0402_5%
+3VS
R704
R704
@
@
@
@
1 2
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R706
R706
1 2
1 2
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
+3VS
+3VS
H_SNB_IVB# <6>
+3VS
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
PCH (6/9) GPIO, CPU, MISC
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
19 65Tuesday, March 20, 2012
19 65Tuesday, March 20, 2012
19 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 20
5
+1.05VS
+1.05VS
C210
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C209
10U_0603_6.3V6M
C209
10U_0603_6.3V6M
1
1
D D
+1.05VS
C C
B B
+1.05VS
del R296 for 14' layout
+3VS
2
R254 0_0603_5%R254 0_0603_5%
This pin can be left as no connect in
On-Die VR enabled mode (default).
+1.05VS
C222
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C221
10U_0603_6.3V6M
C221
10U_0603_6.3V6M
1
1
2
2
1 2
R260
R260
0_0603_5%
0_0603_5%
+1.05VS
2
12
1
2
1
2
1
2
T47PAD @T47PAD @
C223
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C227
C227
0.1U_0402_10V7K
0.1U_0402_10V7K
T48PAD @T48PAD @
1 2
R263
R263
0_0603_5%
0_0603_5%
C212
1U_0402_6.3V6K
C212
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
C211
1U_0402_6.3V6K
1
2
+1.05VS_VCCDPLLEXP
+VCCAPLLEXP
C224
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2
2
+3VS_VCCA3GBG
+VCCAFDI_VRM
+1.05VS_VCCAPLL_FDI
+1.05VS_VCCDPLL_FDI
+VCCP_VCCDMI
C225
C225
4
U4G
U4G
1700mA
AA23
VCCCORE[1]
AC23
VCCCORE[2]
AD21
VCCCORE[3]
AD23
VCCCORE[4]
AF21
VCCCORE[5]
AF23
VCCCORE[6]
AG21
VCCCORE[7]
AG23
VCCCORE[8]
AG24
VCCCORE[9]
AG26
VCCCORE[10]
AG27
VCCCORE[11]
AG29
VCCCORE[12]
AJ23
VCCCORE[13]
AJ26
VCCCORE[14]
AJ27
VCCCORE[15]
AJ29
VCCCORE[16]
AJ31
VCCCORE[17]
AN19
VCCIO[28]
BJ22
VCCAPLLEXP
AN16
VCCIO[15]
AN17
VCCIO[16]
AN21
VCCIO[17]
AN26
VCCIO[18]
AN27
VCCIO[19]
AP21
VCCIO[20]
AP23
VCCIO[21]
AP24
VCCIO[22]
AP26
VCCIO[23]
AT24
VCCIO[24]
AN33
VCCIO[25]
AN34
VCCIO[26]
BH29
VCC3_3[3]
AP16
VCCVRM[2]
BG6
VccAFDIPLL
AP17
VCCIO[27]
AU20
VCCDMI[2]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
3711mA
POWER
POWER
VCC CORE
VCC CORE
VCCIO
VCCIO
FDI
FDI
CRTLVDS
CRTLVDS
40mA
DMI
DMI
70mA
190mA
DFT / SPI HVCMOS
DFT / SPI HVCMOS
63mA
1mA
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
VCCCLKDMI
VCCDFTERM[1]
VCCDFTERM[2]
VCCDFTERM[3]
VCCDFTERM[4]
10mA
VCCADAC
VSSADAC
VCCALVDS
VSSALVDS
VCC3_3[6]
VCC3_3[7]
VCCVRM[3]
VCCDMI[1]
VCCSPI
U48
+VCCADAC
U47
AK36
+VCCA_LVDS
AK37
AM37
AM38
AP36
AP37
V33
+3VS_VCC3_3_6
V34
AT16
+VCCAFDI_VRM
AT20
+VCCP_VCCDMI
AB36
+1.05VS_VCC_DMI_CCI
AG16
AG17
AJ16
AJ17
V1
+3V_VCCPSPI
3
1
C213
C213
0.01U_0402_16V7K
0.01U_0402_16V7K
2
+VCCTX_LVDS
1
C216
C216
0.01U_0402_16V7K
0.01U_0402_16V7K
2
1
C219
C219
0.1U_0402_10V7K
0.1U_0402_10V7K
2
C226
C226
1U_0402_6.3V6K
1U_0402_6.3V6K
1
C228
C228
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C230
C230
1U_0402_6.3V6K
1U_0402_6.3V6K
2
R256
R256
0_0603_5%
0_0603_5%
1
2
L1 change to 1 ohm P/N
S RES 1/10W 1 +-1% 0603
1
C214
C214
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+3VS
R293
R293
0_0603_5%
0_0603_5%
R399
R399
0_0603_5%
0_0603_5%
1
2
+1.8VS+VCC PNAND
12
12
1
C217
C217
0.01U_0402_16V7K
0.01U_0402_16V7K
2
12
+VCCP_VCCDMI
L1
L1
1_0603_1%
1_0603_1%
1
C215
C215
10U_0603_6.3V6M
10U_0603_6.3V6M
2
0_0603_5%
0_0603_5%
0.1UH_MLF1608DR10KT_10%_1608
0.1UH_MLF1608DR10KT_10%_1608
R295
R295
+3VS
12
L2
L2
0.1uH inductor, 200mA
C218
C218
22U_0805_6.3V6M
22U_0805_6.3V6M
+1.05VS
12
R300
R300
0_0603_5%
0_0603_5%
+3VS
12
2
+3VS
12
+1.8VS
1
C220
C220
1U_0402_6.3V6K
1U_0402_6.3V6K
2
R258
R258
0_0603_5%
0_0603_5%
+1.05VS
12
1
PCH Power Rail Table
Refer to CPU EDS R1.5
Voltage Rail
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccADAC
VccADPLLA
VccADPLLB
VccCore
VccDMI
Voltage
1.05
3.3
3.3
1.05
1.05
1.05
1.05
S0 Iccmax
Current (A)
0.001
5
5
0.001
0.001
0.228
0.063
0.08
0.08
1.7
0.047
1.05VccIO 3.711
1.05VccASW 0.903
3.3VccSPI 0.01
3.3VccDSW 0.001
1.8 0.00 2VccDFTERM
3.3VccRTC 6 uA
3.3VccSus3_3
3.3 / 1.5VccSusHDA
0.095
0.01
VccVRM 1.8 / 1.5 0.167
1.05VccCLK DMI
0.07
VccSSC 1.05 0.095
VccDIFFCLKN 1.05 0.055
VccALVDS 3.3
0.001
1.8VccTX_LVDS 0.04
+1.5VS
R265 0_0603_5%R265 0_0603_5%
Intel reco mmand
stuff R265 and unstu ff R266
12
+VCCAFDI_VRM
+VCCAFDI_VRM
VCCVRM==>1.5V FOR MOBILE
VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 1 60mA detal waiting for newest spec
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (7/9) PWR
PCH (7/9) PWR
PCH (7/9) PWR
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
20 65Tuesday, March 20, 2012
20 65Tuesday, March 20, 2012
20 65Tuesday, March 20, 2012
0.2
Page 21
5
+3VS
4
Have internal VRM
3
2
1
VCC3_3 = 2 66mA detal waiting for newest spec
VCCDMI = 4 2mA detal waiting f or newest spec
R280
R280
0_0603_5%
0_0603_5%
12
D D
On-Die PLL Voltage Regulator
H：On-Die PLL volt age regulator enable
VCCFDIPLL, VCCAPLLEXP ,VCCAPLLD MI2
,VCCAPLLSA TA
+1.05VS
C C
L5
L5
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
L6
L6
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
+3VS_VCC_CLKF33
10U_0805_10V4Z
10U_0805_10V4Z
1
2
+1.05VS_VCCA_B_DPL
C250
22U_0805_6.3V6M
C250
22U_0805_6.3V6M
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
2
1U_0402_6.3V6K
C231
C231
+1.05VS_VCCA_A_DPL
C251
C251
1
2
+1.05VS
1
2
1U_0402_6.3V6K
22U_0805_6.3V6M
22U_0805_6.3V6M
C232
C232
+1.05VS
C252
C252
Before gerber out change to 22u_0805
B B
+1.05VS
+1.05VS
+1.05VS
A A
R274
R274
0_0603_5%
0_0603_5%
R304
R304
0_0603_5%
0_0603_5%
R284
R284
0_0603_5%
0_0603_5%
12
12
12
1
C256
C256
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C259
C259
1U_0402_6.3V6K
1U_0402_6.3V6K
2
1
C262
C262
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+1.05VS_VCCDIFFCLKN
1
2
C253
1U_0402_6.3V6K
C253
1U_0402_6.3V6K
+3VALW
1 2
R277
R277
0_0805_5%
0_0805_5%
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05VS
R286
R286
0_0603_5%
0_0603_5%
R269
R269
0_0603_5%
0_0603_5%
R271
R271
0_0603_5%
0_0603_5%
1
2
C258
C258
C263
C263
12
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
2
12
12
C244
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
1
2
1
2
C265
C265
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
+VCCPDSW
1
C234
C234
0.1U_0402_10V7K
0.1U_0402_10V7K
2
+3VS_VCC_CLKF33
+VCCDPLL_CPY
+VCCSUS1
1
C239
@C239
@
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+1.05VM_VCCASW
C242
22U_0805_6.3V6M
C242
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
1
1
2
2
C246
1U_0402_6.3V6K
C246
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
1
1
2
2
+VCCRTCEXT
+VCCAFDI_VRM
+1.05VS_VCCA_A_DPL
+1.05VS_VCCA_B_DPL
+VCCDIFFCLK
+1.05VS_VCCDIFFCLKN
+1.05VS_SSCVCC
+VCCSST
C266
C266
C267
0.1U_0402_10V7K@C267
0.1U_0402_10V7K
1
+RTCVCC
2
@
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+V_CPU_IO
0.1U_0402_10V7K
0.1U_0402_10V7K
C268
C268
1
2
AD49
T16
V12
T38
BH23
AL29
AL24
AA19
AA21
AA24
AA26
AA27
AA29
AA31
AC26
AC27
AC29
AC31
AD29
AD31
W21
W23
W24
W26
W29
W31
W33
N16
Y49
BD47
BF47
AF17
AF33
AF34
AG34
AG33
V16
T17
V19
BJ8
A22
C269
C269
C270
0.1U_0402_10V7K@C270
0.1U_0402_10V7K
1
@
2
POWER
903mA
55mA
95mA
1mA
POWER
1mA
Clock and Miscellaneous
Clock and Miscellaneous
80mA
80mA
CPURTC
CPURTC
U4J
U4J
VCCACLK
VCCDSW3_3
DCPSUSBYP
VCC3_3[5]
VCCAPLLDMI2
VCCIO[14]
DCPSUS[3]
VCCASW[1]
VCCASW[2]
VCCASW[3]
VCCASW[4]
VCCASW[5]
VCCASW[6]
VCCASW[7]
VCCASW[8]
VCCASW[9]
VCCASW[10]
VCCASW[11]
VCCASW[12]
VCCASW[13]
VCCASW[14]
VCCASW[15]
VCCASW[16]
VCCASW[17]
VCCASW[18]
VCCASW[19]
VCCASW[20]
DCPRTC
VCCVRM[4]
VCCADPLLA
VCCADPLLB
VCCIO[7]
VCCDIFFCLKN[1]
VCCDIFFCLKN[2]
VCCDIFFCLKN[3]
VCCSSC
DCPSST
DCPSUS[1]
DCPSUS[2]
V_PROC_IO
VCCRTC
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
228mA
PCI/GPIO/LPCMISC
PCI/GPIO/LPCMISC
SATA USB
SATA USB
HDA
HDA
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[6]
1mA
VCCSUS3_3[1]
1mA
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCAPLLSATA
VCCASW[22]
VCCASW[23]
VCCASW[21]
10mA
VCCSUSHDA
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
V5REF_SUS
DCPSUS[4]
V5REF
VCC3_3[1]
VCC3_3[8]
VCC3_3[4]
VCC3_3[2]
VCCIO[5]
VCCIO[12]
VCCIO[13]
VCCIO[6]
VCCVRM[1]
VCCIO[2]
VCCIO[3]
VCCIO[4]
N26
P26
P28
T27
T29
T23
T24
V23
V24
P24
T26
M26
AN23
AN24
P34
N20
N22
P20
P22
AA16
W16
T34
AJ2
AF13
AH13
AH14
AF14
AK1
AF11
AC16
AC17
AD17
+1.05VS
T21
V21
T19
P32
+1.05VS_VCCUSBCORE
1
2
1
2
+1.05VS_VCCAUPLL
+PCH_V5REF_SUS
+VCCA_USBSUS
+3V_VCCPSUS
+PCH_V5REF_RUN
+3V_VCCPSUS
+3VS_VCCPCORE
+3VS_VCCPPCI
+VCC3_3_2
+VCCAFDI_VRM
+VCCAFDI_VRM
+1.05VS_VCC_SATA
+VCCSUSHDA
1
C271
C271
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C233
C233
1U_0402_6.3V6K
1U_0402_6.3V6K
+3V_VCCPUSB
C236
0.1U_0402_10V7K
C236
0.1U_0402_10V7K
+3V_VCCAUBG
R283
R283
0_0603_5%
0_0603_5%
1
C255
C255
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+1.05VS_VCC_SATA
R270
R270
0_0603_5%
0_0603_5%
R272
R272
0_0603_5%
0_0603_5%
1
C238
C238
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1 2
C243 1U_0402_6.3V6K@C243 1U_0402_6.3V6K@
+3VS
12
+1.05VS_SATA3
1
2
R287
R287
0_0603_5%
0_0603_5%
+1.05VS
12
+3V_PCH
12
12
R273
R273
0_0603_5%
0_0603_5%
12
R276
R276
0_0603_5%
0_0603_5%
+1.05VS_SATA3
R288
R288
0_0603_5%
0_0603_5%
C261
C261
1U_0402_6.3V6K
1U_0402_6.3V6K
12
+3V_PCH
+1.05VS
1
C247
C247
1U_0402_6.3V
1U_0402_6.3V
2
1
C249
C249
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C254
C254
0.1U_0402_10V7K
0.1U_0402_10V7K
2
1
C257
C257
1U_0402_6.3V6K
1U_0402_6.3V6K
2
+1.05VS
12
+3V_PCH
+3V_PCH
12
R278
R278
0_0603_5%
0_0603_5%
+3VS
12
R281
R281
0_0603_5%
0_0603_5%
+3VS
12
R282
R282
0_0603_5%
0_0603_5%
+1.05VS
12
R285
R285
0_0603_5%
0_0603_5%
On-Die PLL Voltage Regulator
H：On-Die PLL volt age regulator enable
VCCFDIPLL, VCCAPLLEXP ,VCCAPLLD MI2
,VCCAPLLSA TA
R275
R275
10_0402_5%
10_0402_5%
R279
R279
10_0402_5%
10_0402_5%
+3V_PCH+5V_PCH
12
+3VS+5VS
12
21
D1
D1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
+PCH_V5REF_SUS
1
C240
C240
0.1U_0603_25V7K
0.1U_0603_25V7K
2
21
D2
D2
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
+PCH_V5REF_RUN
1
C248
C248
1U_0603_10V6K
1U_0603_10V6K
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (8/9) PWR
PCH (8/9) PWR
PCH (8/9) PWR
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
21 65Tuesday, March 20, 2012
21 65Tuesday, March 20, 2012
21 65Tuesday, March 20, 2012
0.2
Page 22
5
D D
C C
B B
A A
U4H
U4H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
4
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
3
U4I
U4I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
PANTHER-POINT_FCBGA989
PANTHER-POINT_FCBGA989
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PCH (9/9) VSS
PCH (9/9) VSS
PCH (9/9) VSS
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
22 65Tuesday, March 20, 2012
22 65Tuesday, March 20, 2012
22 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 23
5
PCIE_CTX_GRX_N[0..15]<32,5>
PCIE_CTX_GRX_P[0..15]<32,5>
PCIE_CRX_GTX_N[0..15]<32,5>
PCIE_CRX_GTX_P[0..15]<32,5>
D D
+VDD33MISC
RV24
RV24
2.2K_0402_5%
2.2K_0402_5%
VGA_SMB_CK2
C C
VGA_SMB_DA2
B B
A A
1 2
PLT_RST#<18,32,37,38,44,45,6>
DGPU_HOLD_RST#<18>
RV25
RV25
2.2K_0402_5%
2.2K_0402_5%
1 2
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
RV126 0_0402_5%@RV126 0_0402_5%@
2
QV1A
QV1A
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1 2
RV137 0_0402_5%@RV137 0_0402_5%@
DGPU_HOLD_RST#
+VDD33MISC
5
4
1 2
61
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PLT_RST#
5
+1.05VS_VGA
180ohms (ESR=0.2) Bead
QV1B
QV1B
3
PU AT EC SIDE, +3VS AND 4.7K
+3VS
1
C1061
C1061
2
5
2
B
1
A
3
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
R1495
R1495
LV1 BLM18PG181SN1D_2PLV1 BLM18PG181SN1D_2P
1 2
EC_SMB_CK2 <15,32,40,45>
EC_SMB_DA2 <15,32,40,45>
UV2
UV2
P
4
PLT_RST_VGA#
Y
G
@
@
1 2
0_0402_5%
0_0402_5%
RV111
RV111
10K_0402_5%
10K_0402_5%
1 2
DGPU_PWR_EN<18,51>
PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
Under GPU(below 150mils)
1
CV112
CV112
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P1 PCIE_CRX_C_GTX_P1
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
Differential signal
CLK_REQ_GPU#_R< 15>
4
1
1
CV113
CV113
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
CV24 0.22U_0402_10V6KCV24 0.22U_0402_10V6K
CV26 0.22U_0402_10V6KCV26 0.22U_0402_10V6K
CV21 0.22U_0402_10V6KCV21 0.22U_0402_10V6K
CV23 0.22U_0402_10V6KCV23 0.22U_0402_10V6K
CV25 0.22U_0402_10V6KCV25 0.22U_0402_10V6K
CV27 0.22U_0402_10V6KCV27 0.22U_0402_10V6K
CV29 0.22U_0402_10V6KCV29 0.22U_0402_10V6K
CV31 0.22U_0402_10V6KCV31 0.22U_0402_10V6K
CV33 0.22U_0402_10V6KCV33 0.22U_0402_10V6K
CV28 0.22U_0402_10V6KCV28 0.22U_0402_10V6K
CV30 0.22U_0402_10V6KCV30 0.22U_0402_10V6K
CV32 0.22U_0402_10V6KCV32 0.22U_0402_10V6K
CV36 0.22U_0402_10V6KCV36 0.22U_0402_10V6K
CV41 0.22U_0402_10V6KCV41 0.22U_0402_10V6K
CV34 0.22U_0402_10V6KCV34 0.22U_0402_10V6K
CV35 0.22U_0402_10V6KCV35 0.22U_0402_10V6K
+3VS_VGA
RV231
RV231
12
10K_0402_5%
10K_0402_5%
QV16
QV16
1 3
D
D
2N7002H 1N_SOT23-3
2N7002H 1N_SOT23-3
@
@
1 2
RV233 0_0402_5%
RV233 0_0402_5%
4
CV4
CV4
0.1U_0402_10V7K
0.1U_0402_10V7K
RV230
RV230
10K_0402_5%
10K_0402_5%
1 2
2
G
G
S
S
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
@
@
1
CV5
CV5
2
CLK_PCIE_VGA#<15>
150mA
+SP_PLLVDD
CLK_PCIE_VGA<15>
1 2
@
@
RV20 200_0402_1%
RV20 200_0402_1%
RV22 2.49K_0402_1%RV22 2.49K_0402_1%
+3VS_VGA
1 2
1 2
1 2
RV32
RV32
10K_0402_5%
10K_0402_5%
CLK_REQ_GPU#
RV232
@RV232
@
10K_0402_5%
10K_0402_5%
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CRX_C_GTX_P7
PCIE_CRX_C_GTX_N7
PCIE_CRX_C_GTX_P6
PCIE_CRX_C_GTX_N6
PCIE_CRX_C_GTX_P5
PCIE_CRX_C_GTX_N5
PCIE_CRX_C_GTX_P4
PCIE_CRX_C_GTX_N4
PCIE_CRX_C_GTX_P3
PCIE_CRX_C_GTX_N3
PCIE_CRX_C_GTX_P2
PCIE_CRX_C_GTX_N2
PCIE_CRX_C_GTX_N1
PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_REQ_GPU#
PEX_TSTCLK_OUT
PEX_TSTCLK_OUT#
PLT_RST_VGA#
PEX_TERMP
UV1A
UV1A
AN12
PEX_RX0
AM12
PEX_RX0_N
AN14
PEX_RX1
AM14
PEX_RX1_N
AP14
PEX_RX2
AP15
PEX_RX2_N
AN15
PEX_RX3
AM15
PEX_RX3_N
AN17
PEX_RX4
AM17
PEX_RX4_N
AP17
PEX_RX5
AP18
PEX_RX5_N
AN18
PEX_RX6
AM18
PEX_RX6_N
AN20
PEX_RX7
AM20
PEX_RX7_N
AP20
PEX_RX8
AP21
PEX_RX8_N
AN21
PEX_RX9
AM21
PEX_RX9_N
AN23
PEX_RX10
AM23
PEX_RX10_N
AP23
PEX_RX11
AP24
PEX_RX11_N
AN24
PEX_RX12
AM24
PEX_RX12_N
AN26
PEX_RX13
AM26
PEX_RX13_N
AP26
PEX_RX14
AP27
PEX_RX14_N
AN27
PEX_RX15
AM27
PEX_RX15_N
AK14
PEX_TX0
AJ14
PEX_TX0_N
AH14
PEX_TX1
AG14
PEX_TX1_N
AK15
PEX_TX2
AJ15
PEX_TX2_N
AL16
PEX_TX3
AK16
PEX_TX3_N
AK17
PEX_TX4
AJ17
PEX_TX4_N
AH17
PEX_TX5
AG17
PEX_TX5_N
AK18
PEX_TX6
AJ18
PEX_TX6_N
AL19
PEX_TX7
AK19
PEX_TX7_N
AK20
PEX_TX8
AJ20
PEX_TX8_N
AH20
PEX_TX9
AG20
PEX_TX9_N
AK21
PEX_TX10
AJ21
PEX_TX10_N
AL22
PEX_TX11
AK22
PEX_TX11_N
AK23
PEX_TX12
AJ23
PEX_TX12_N
AH23
PEX_TX13
AG23
PEX_TX13_N
AK24
PEX_TX14
AJ24
PEX_TX14_N
AL25
PEX_TX15
AK25
PEX_TX15_N
AJ11
PEX_WAKE_N
AL13
PEX_REFCLK
AK13
PEX_REFCLK_N
AK12
PEX_CLKREQ_N
AJ26
PEX_TSTCLK_OUT
AK26
PEX_TSTCLK_OUT_N
AJ12
PEX_RST_N
AP29
PEX_TERMP
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
GT@
GT@
3
Part 1 of 7
Part 1 of 7
GPIO
GPIO
PCI EXPRESS
PCI EXPRESS
CV37
CV37
15P_0402_50V8J
15P_0402_50V8J
3
P6
GPIO0
M3
GPIO1
L6
GPIO2
P5
GPIO3
P7
GPIO4
L7
GPIO5
M7
GPIO6
N8
GPIO7
M1
GPIO8
M2
GPIO9
L1
GPIO10
M5
GPIO11
N3
GPIO12
M4
GPIO13
N4
GPIO14
P2
GPIO15
R8
GPIO16
M6
GPIO17
R1
GPIO18
P3
GPIO19
P4
GPIO20
P1
GPIO21
AK9
DACA_RED
AL10
DACA_GREEN
AL9
DACA_BLUE
AM9
DACA_HSYNC
AN9
DACA_VSYNC
DACs
DACs
DACA_VREF
DACA_RSET
I2C
I2C
DACA_VDD
I2CA_SCL
I2CA_SDA
I2CB_SCL
I2CB_SDA
I2CC_SCL
I2CC_SDA
I2CS_SCL
I2CS_SDA
AG10
AP9
AP8
R4
R5
R7
R6
R2
R3
T4
T3
VGA_CRT_CLK
VGA_CRT_DATA
VGA_EDID_CLK
VGA_EDID_DATA
60mA
AD8
PLLVDD
45mA
AE8
SP_PLLVDD
VID_PLLVDD
CLK
CLK
XTAL_OUTBUFF
XTAL_SSIN
XTAL_IN
XTAL_OUT
45mA
AD7
H3
H2
J4
H1
Internal Thermal Sensor
1 2
RV23 10M_0402_5%RV23 10M_0402_5%
YV1
YV1
4
NC
1
XTAL_IN
OSC
27MHZ 16PF +-30PPM X3G027000FG1H-HX
27MHZ 16PF +-30PPM X3G027000FG1H-HX
1
2
2
GPU_VID4
GPU_VID3
VGA_BL_PWM
VGA_ENVDD
VGA_ENBKL
GPU_VID1
GPU_VID2
OVERT#
GPIO9
GPU_VID0
GPU_VID5
FB_CLAMP_TOGGLE_REQ#
DGPU_HDMI_HPD
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC
+DACA_VDD
+DACA_VREF
DACA_RSET
I2CB_SCL
I2CB_SDA
VGA_SMB_CK2
VGA_SMB_DA2
+PLLVDD
1 2
RV112 0_0402_5%@RV112 0_0402_5%@
XTAL_IN
XTAL_OUT
XTALOUT
1 2
XTALSSIN
3
XTAL_OUT
OSC
2
NC
CV38
CV38
15P_0402_50V8J
15P_0402_50V8J
GPU_VID4 <58>
GPU_VID3 <58>
VGA_BL_PWM <34>
VGA_ENVDD <34>
VGA_ENBKL <34>
GPU_VID1 <58>
GPU_VID2 <58>
GPU_VID0 <58>
DPRSLPVR_VGA <58>
DGPU_HDMI_HPD <36>
Vendor recommand reserve PU/PD resistor
VGA_CRT_R <35>
VGA_CRT_G <35>
VGA_CRT_B <35>
VGA_CRT_HSYNC <35>
VGA_CRT_VSYNC <35>
RV107
RV107
124_0402_1%
124_0402_1%
SLI@
SLI@
VGA_CRT_CLK <35>
VGA_CRT_DATA <35>
VGA_EDID_CLK <34>
VGA_EDID_DATA <34>
RV2610K_0402_5% RV2610K_0402_5%
RV27
RV27
10K_0402_5%
10K_0402_5%
1
2
VGA_AC_DET
GPU_VID5 <58>
12
0.1U_0402_10V7K
0.1U_0402_10V7K
CRT
LVDS
+SP_PLLVDD
12
SLI@
SLI@12
CV130
CV130
+DACA_VDD
+PLLVDD
+VDD33MISC
RV65
RV65
@
@
10K_0402_5%
10K_0402_5%
1 2
VGA_AC_DET <32,45,58>
12
RV223
RV223
10K_0402_5%
10K_0402_5%
MEM_VREF <28,29,30,31>
FB_CLAMP_TOGGLE_REQ#
GPIO 14 of GPU connect to PCH GPIO 0
SLI@
VGA_BL_PWM
SLI@
RV16 10K_0402_5%
RV16 10K_0402_5%
Close to GPU
SLI@
SLI@
1 2
RV106 150_0402_1%
RV106 150_0402_1%
SLI@
SLI@
1 2
RV108 150_0402_1%
RV108 150_0402_1%
SLI@
SLI@
1 2
RV109 150_0402_1%
RV109 150_0402_1%
Under GPU Near GPU
0.1U_0402_10V7K
0.1U_0402_10V7K
CV131
CV131
1
CV126
@C V126
@
2
1
CV40
CV40
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV139
CV139
2
SLI@
SLI@
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
LV7 0_0402_5%LV7 0_0402_5%
1
CV125
@C V125
@
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
120mA
VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
OVERT#
+VDD33MISC
12
1
CV122
CV122
2
SLI@
SLI@
0.1U_0402_10V7K
0.1U_0402_10V7K
Under GPU Near GPU
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
1
+VDD33MISC
12
RV208
RV208
10K_0402_5%@
10K_0402_5%@
61
@
@
QV7A
QV7A
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
2
RV52
RV52
10K_0402_5%
10K_0402_5%
@
@
1 2
1
CV127
2
SLI@ CV127
SLI@
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05VS_VGA
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH_THRMTRIP#_R
3
QV7B
QV7B
DMN66D0LDW-7 2N_SOT363-6
DMN66D0LDW-7 2N_SOT363-6
5
@
@
4
1 2
RV170 0_0402_5%GC6@RV170 0_0402_5%GC6@
GPIO9
VGA_EDID_CLK
VGA_EDID_DATA
VGA_CRT_DATA
VGA_CRT_CLK
I2CB_SCL
I2CB_SDA
OVERT#
VGA_AC_DET
220 ohms @100MHz (ESR=0.05)
LV5
LV5
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
1
CV128
CV128
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CV126
CV126
SLI@
SLI@
OPT@
OPT@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
N13P-PCIE/DAC/GPIO
N13P-PCIE/DAC/GPIO
N13P-PCIE/DAC/GPIO
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
PCH_THRMTRIP#_R <19,32>
GC6_EVENT# <19,32>
1 2
RV15 2.2K_0402_5%RV15 2.2K_0402_5%
1 2
RV4 2.2K_0402_5%RV4 2.2K_0402_5%
1 2
RV7 2.2K_0402_5%RV7 2.2K_0402_5%
1 2
RV10 2.2K_0402_5%RV10 2.2K_0402_5%
1 2
RV11 2.2K_0402_5%RV11 2.2K_0402_5%
1 2
RV12 2.2K_0402_5%RV12 2.2K_0402_5%
1 2
RV13 2.2K_0402_5%RV13 2.2K_0402_5%
1 2
RV1 10K_0402_5%RV1 10K_0402_5%
1 2
RV2 10K_0402_5%RV2 10K_0402_5%
12
10K_0402_5%
10K_0402_5%
+3VS_VGA
+VDD33MISC
23 65Tuesday, March 20, 2012
23 65Tuesday, March 20, 2012
23 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 24
5
VGA_TXCLK+<34>
VGA_TXCLK-<34>
VGA_TXOUT0+<34>
VGA_TXOUT0-<34>
VGA_TXOUT1+<34>
VGA_TXOUT1-<34>
VGA_TXOUT2+<34>
VGA_TXOUT2-<34>
D D
for 15" dual channel
C C
VGA_HDMI_TX2+<36>
VGA_HDMI_TX2-<36>
VGA_HDMI_TX1+<36>
VGA_HDMI_TX1-<36>
VGA_HDMI_TX0+<36>
VGA_HDMI_TX0-<36>
VGA_HDMI_CLK+<36>
VGA_HDMI_CLK-<36>
B B
+VDD33MISC
SLI@
SLI@
1 2
RV113 4.7K_0402_5%
RV113 4.7K_0402_5%
SLI@
SLI@
1 2
RV114 4.7K_0402_5%
RV114 4.7K_0402_5%
HDMI
VGA_HDMI_DATA
VGA_HDMI_CLK<36>
VGA_HDMI_DATA<36>
4
VGA_TXCLK+
VGA_TXCLKVGA_TXOUT0+
VGA_TXOUT0VGA_TXOUT1+
VGA_TXOUT1VGA_TXOUT2+
VGA_TXOUT2-
VGA_HDMI_TX2+
VGA_HDMI_TX2-
VGA_HDMI_TX1+
VGA_HDMI_TX1-
VGA_HDMI_TX0+
VGA_HDMI_TX0-
VGA_HDMI_CLK+
VGA_HDMI_CLK-
VGA_HDMI_CLKVGA_HDMI_CLK
VGA_HDMI_DATA
UV1D
UV1D
AM6
IFPA_TXC
AN6
IFPA_TXC_ N
AP3
IFPA_TXD0
AN3
IFPA_TXD0 _N
AN5
IFPA_TXD1
AM5
IFPA_TXD1 _N
AL6
IFPA_TXD2
AK6
IFPA_TXD2 _N
AJ6
IFPA_TXD3
AH6
IFPA_TXD3 _N
AJ9
IFPB_TXC
AH9
IFPB_TXC_ N
AP6
IFPB_TXD4
AP5
IFPB_TXD4 _N
AM7
IFPB_TXD5
AL7
IFPB_TXD5 _N
AN8
IFPB_TXD6
AM8
IFPB_TXD6 _N
AK8
IFPB_TXD7
AL8
IFPB_TXD7 _N
AK1
IFPC_L0
AJ1
IFPC_L0_N
AJ3
IFPC_L1
AJ2
IFPC_L1_N
AH3
IFPC_L2
AH4
IFPC_L2_N
AG5
IFPC_L3
AG4
IFPC_L3_N
AM1
IFPD_L0
AM2
IFPD_L0_N
AM3
IFPD_L1
AM4
IFPD_L1_N
AL3
IFPD_L2
AL4
IFPD_L2_N
AK4
IFPD_L3
AK5
IFPD_L3_N
AD2
IFPE_L0
AD3
IFPE_L0_N
AD1
IFPE_L1
AC1
IFPE_L1_N
AC2
IFPE_L2
AC3
IFPE_L2_N
AC4
IFPE_L3
AC5
IFPE_L3_N
AE3
IFPF_L0
AE4
IFPF_L0_N
AF4
IFPF_L1
AF5
IFPF_L1_N
AD4
IFPF_L2
AD5
IFPF_L2_N
AG1
IFPF_L3
AF1
IFPF_L3_N
AG3
IFPC_AUX_ I2CW _SCL
AG2
IFPC_AUX_ I2CW _SDA_N
AK3
IFPD_AUX_ I2CX_SCL
AK2
IFPD_AUX_ I2CX_SDA _N
AB3
IFPE_AUX_ I2CY_SCL
AB4
IFPE_AUX_ I2CY_SDA_N
AF3
IFPF_AUX_ I2CZ_SC L
AF2
IFPF_AUX_ I2CZ_SD A_N
Part 4 of 7
Part 4 of 7
VDD_SEN SE
GND_SEN SE
TEST
TEST
TESTMOD E
JTAG_TR ST_N
SERIAL
SERIAL
ROM_CS_ N
ROM_SCL K
LVDS/TMDS
LVDS/TMDS
GENERAL
GENERAL
MULTI_STR AP_REF0_GND
3
NC
NC
JTAG_TC K
JTAG_TD I
JTAG_TD O
JTAG_TM S
ROM_SI
ROM_SO
BUFRST_ N
CEC
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
THERMDP
THERMDN
P8
NC
AC6
NC
AJ28
NC
AJ4
NC
AJ5
NC
AL11
NC
C15
NC
D19
NC
D20
NC
D23
NC
D26
NC
H31
NC
T8
NC
V32
NC
L4
VCCSENSE_VGA
L5
VSSSENSE_VGA
AK11
AM10
AM11
AP12
AP11
AN11
H6
H4
H5
H7
RV35 10K_0402_5%RV35 10K_0402_5%
L2
L3
J1
J2
J7
J6
J5
J3
K3
K4
VCCSENSE_VGA <58>
TV2TV2
TV3TV3
TV4TV4
TV5TV5
ROM_SCLK <33>
ROM_SI <33>
ROM_SO <33>
12
VSSSENSE_VGA <58>
STRAP0 <33>
STRAP1 <33>
STRAP2 <33>
STRAP3 <33>
STRAP4 <33>
trace width: 16mils
differential voltage sensing.
differential signal routing.
TESTMODE
1 2
RV34 10K_0402_5%RV34 10K_0402_5%
ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO
1 2
RV38 40.2K_0402_1%RV38 40.2K_0402_1%
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
12
10K_0402_5%
10K_0402_5%
RV33
RV33
2
1
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
CV295
CV295
12
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ROM_CS#
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
@
@
@
RV224 0_0402_5%
RV224 0_0402_5%
1 2
1 2
RV226 0_0402_5%
RV226 0_0402_5%
@
@
1MB SPI ROM FOR VBIOS ROM (SLI)
+3VS_VGA
20mils
12
@
@
RV229
RV229
10K_0402_5%
10K_0402_5%
ROM_CS#_R
2
@
@
UV15
UV15
1
CS#
2
HOLD#
DO
3
WP#
4
GND
MX25L1005AMC-12G SOP
MX25L1005AMC-12G SOP
12
@
@
RV225
RV225
10K_0402_5%
10K_0402_5%
8
VCC
7
ROM_HOLD#ROM_SO_RROM_SO
6
CLK
5
DIO
ROM_SCLK_R
ROM_SI_R
Title
Title
Title
N13P-LVDS/HDMI/DP/THM
N13P-LVDS/HDMI/DP/THM
N13P-LVDS/HDMI/DP/THM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
@
@
RV228 0_0402_5%
RV228 0_0402_5%
1 2
1 2
RV227 0_0402_5%
RV227 0_0402_5%
@
@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
ROM_SCLK
ROM_SI
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
24 65Tuesday, March 20, 2012
24 65Tuesday, March 20, 2012
24 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 25
5
+1.5VS_VGA
D D
+1.5VS_VGA
1
CV277
CV277
2
1U_0402_6.3V6K
1U_0402_6.3V6K
C C
B B
+3VS_VGA
A A
300ohms @100MHz (ESR=0.25)
P/N: SM01003168 0
CV147
CV147
OPT@
OPT@
220ohms @100MHz (ESR=0.05)
+1.05VS_VGA
CV172
CV172
OPT@
OPT@
For GDDR5 setti ng. Near GPU
1
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV264
CV264
CV263
CV263
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
CV267
CV267
CV266
CV266
CV265
CV265
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Under GPU(below 150mils)
1
1
1
CV282
CV282
CV281
CV281
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV278
CV278
CV279
CV279
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
VDDQ_SENSE<55>
CALIBRATION PIN
FB_CAL_x_PD_VDDQ
FB_CAL_x_PU_GND
FB_CAL_xTERM_GND
LV9
LV9
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
12
SLI@
SLI@
LV10
LV10
12
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
SLI@
SLI@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
SLI@
SLI@
1
1
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
SLI@
SLI@
CV147
CV147
CV149
CV149
2
1U_0402_6.3V6K
1U_0402_6.3V6K
SLI@
SLI@
1
1
CV152
CV152
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
SLI@
SLI@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
SLI@
SLI@
1
2
1
CV280
CV280
2
1
2
2
2
CV268
CV268
CV269
CV269
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV292
CV292
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV173
CV173
CV171
CV171
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
SLI@
SLI@
SLI@
SLI@
Place near ball s
CV172
0.1U_0402_10V7K
0.1U_0402_10V7K
SLI@
SLI@
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
SLI@
SLI@
1
1
CV158
CV158
CV153
CV153
CV172
Place near ball s
2
CV270
CV270
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV287
CV287
2
GDDR5
40.2Ohm
40.2Ohm
60.4Ohm
220mA
+IFPEF_PLLVDD
1
CV150
CV150
2
570mA
+IFPE_IOVDD +IFPAB_IOVDD
2
CV271
CV271
1
10U_0603_6.3V6M
10U_0603_6.3V6M
1
CV294
CV294
2
0.1U_0402_10V7K
0.1U_0402_10V7K
4
1
1
CV273
CV273
CV272
CV272
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CV284
CV284
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1 2
RV141 0_0402_5%RV141 0_0402_5%
1 2
RV142 0_0402_5%RV142 0_0402_5%
+1.5VS_VGA
Place near ball s
+1.05VS_VGA
+3VS_VGA
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
CV176
CV176
10K_0402_5%
10K_0402_5%
OPT@
OPT@
3.5A
AA27
AA30
LV6
LV6
SLI@
SLI@
AB27
AB33
AC27
AD27
AE27
AF27
AG27
B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24
H8
H9
L27
M27
N27
P27
R27
T27
T30
T33
V27
W27
W30
W33
Y27
F1
F2
J27
H27
H25
12
1
2
SLI@
SLI@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
1
2
CV176
CV176
CV156
CV156
2
1U_0402_6.3V6K
1U_0402_6.3V6K
SLI@
SLI@
1
1
CV276
CV274
CV274
RV6 40.2_0402_1%RV6 40.2_0402_1%
RV8 40.2_0402_1%RV8 40.2_0402_1%
RV9 60.4_0402_1%RV9 60.4_0402_1%
CV140
CV140
10K_0402_5%
10K_0402_5%
OPT@
OPT@
CV276
CV275
CV275
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV286
CV286
CV285
CV285
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FB_VDDQ_SENSE
FB_VSS_SENSE
1 2
1 2
1 2
120ohms @100MHz (ESR=0.18)
P/N:SM01000BZ00
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
180ohms @100MHz (ESR=0.2)
P/N: SM01003071 0
LV4
LV4
12
SLI@
SLI@
SLI@
SLI@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
UV1E
UV1E
Part 5 of 7
Part 5 of 7
FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CAL_TERM_GND
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
200mA
1
1
CV146
CV146
CV140
CV140
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1U_0402_6.3V6K
1U_0402_6.3V6K
SLI@
SLI@
SLI@
SLI@
Place near ball s
1
1
CV197
CV197
CV216
CV216
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
SLI@
SLI@
SLI@
SLI@
Place near ball s
3
2000mA
PEX_PLLVDD
VDD33_0
VDD33_1
VDD33_2
VDD33_3
IFPAB_RSET
IFPA_IOVDD
IFPB_IOVDD
IFPC_RSET
IFPC_IOVDD
IFPD_RSET
IFPD_IOVDD
IFPEF_RSET
IFPE_IOVDD
IFPF_IOVDD
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AH12
AG12
AG26
J8
K8
L8
M8
AH8
AJ8
AG8
AG9
AF7
AF8
AF6
AG7
AN2
AG6
AB8
AD6
AC7
AC8
PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_PLL_HVDD
PEX_SVDD_3V3
POWER
POWER
IFPAB_PLLVDD
IFPC_PLLVDD
IFPD_PLLVDD
IFPEF_PLVDD
+IFPAB_PLLVDD
CV141
CV141
IFPA_IOVDD and
IFPB_IOVDD comb ined
1
CV43
CV43
2
1U_0402_6.3V6K
1U_0402_6.3V6K
Under GPU(below 150mils)
1
CV54
CV54
2
22U_0805_6.3V6M
22U_0805_6.3V6M
+PEX_PLLVDD
+VDD33MISC
+VDD33
+IFPAB_PLLVDD
+IFPAB_IOVDD
+IFPC_PLLVDD
+IFPC_IOVDD
+IFPD_PLLVDD
+IFPD_IOVDD
+IFPEF_PLLVDD
+IFPE_IOVDD
1 2
1 2
1 2
1 2
2
Near GPU
1
1
CV44
CV44
CV45
CV45
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
CV53
CV53
CV56
CV56
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
CV70
CV70
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CV47
CV47
CV46
CV46
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
+1.05VS_VGA
1
CV55
CV55
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
CV73
CV73
CV74
CV74
2
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
1
CV49
CV49
CV48
CV48
1
2
10U_0603_6.3V6M
10U_0603_6.3V6M
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
+3VS_VGA
2
2
CV51
CV51
CV50
CV50
1
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
+VDD33MISC
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
DGPU_PWR_EN#<51>
+VDD33MISC
+1.05VS_VGA
CV52
CV52
For N13P-GT
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
CV72
CV72
0.1U_0402_10V7K
0.1U_0402_10V7K
1
QV8 AO3413_SOT23
QV8 AO3413_SOT23
1 3
1
CV105
CV105
2
2
D
D
+3VS_VGA
G
G
S
S
Under GPU(below 150mils)
Place near ball s Place near G PU
1
1
1
CV111
CV111
CV109
12
RV401K_0402_1%@RV401K_0402_1%
@
SLI@
SLI@
12
RV431K_0402_1%@RV431K_0402_1%
@
IFPAB & IFPEF have to use
12
RV461K_0402_1%@RV461K_0402_1%
@
12
RV501K_0402_1%
RV501K_0402_1%
RV4210K_0402_5% RV4210K_0402_5%
RV4410K_0402_5% RV4410K_0402_5%
RV4510K_0402_5% RV4510K_0402_5%
RV4710K_0402_5% RV4710K_0402_5%
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+PEX_PLLVDD
CV109
0.1U_0402_10V7K
0.1U_0402_10V7K
2
2
1U_0402_6.3V6K
1U_0402_6.3V6K
120mA
1
1
CV65
CV65
2
2
1U_0603_10V6K
1U_0603_10V6K
0.1U_0402_10V7K
0.1U_0402_10V7K
0_0603_5%
0_0603_5%
1
CV75
CV75
CV293
CV293
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1
CV3
CV3
CV66
CV66
2
4.7U_0805_25V6-K
4.7U_0805_25V6-K
+3VS_VGA
12
RV5
RV5
+1.05VS_VGA
LV2
LV2
0_0603_5%
0_0603_5%
12
Place near ball s
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
N13P-POWER
N13P-POWER
N13P-POWER
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
25 65Tuesday, March 20, 2012
25 65Tuesday, March 20, 2012
25 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 26
5
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y17
Y18
Y20
Y22
U1
U2
U3
U4
U5
U6
U7
U8
V1
V2
V3
V4
V5
V6
V7
V8
W2
W3
W4
W5
W7
W8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
+VGA_CORE
UV1G
+VGA_CORE
D D
C C
B B
A A
UV1G
AA12
VDD_0
AA14
VDD_1
AA16
VDD_2
AA19
VDD_3
AA21
VDD_4
AA23
VDD_5
AB13
VDD_6
AB15
VDD_7
AB17
VDD_8
AB18
VDD_9
AB20
VDD_10
AB22
VDD_11
AC12
VDD_12
AC14
VDD_13
AC16
VDD_14
AC19
VDD_15
AC21
VDD_16
AC23
VDD_17
M12
VDD_18
M14
VDD_19
M16
VDD_20
M19
VDD_21
M21
VDD_22
M23
VDD_23
N13
VDD_24
N15
VDD_25
N17
VDD_26
N18
VDD_27
N20
VDD_28
N22
VDD_29
P12
VDD_30
P14
VDD_31
P16
VDD_32
P19
VDD_33
P21
VDD_34
P23
VDD_35
R13
VDD_36
R15
VDD_37
R17
VDD_38
R18
VDD_39
R20
VDD_40
R22
VDD_41
T12
VDD_42
T14
VDD_43
T16
VDD_44
T19
VDD_45
T21
VDD_46
T23
VDD_47
U13
VDD_48
U15
VDD_49
U17
VDD_50
U18
VDD_51
U20
VDD_52
U22
VDD_53
V13
VDD_54
V15
VDD_55
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
Part 7 of 7
Part 7 of 7
POWER
POWER
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
XVDD_1
XVDD_2
XVDD_3
XVDD_4
XVDD_5
XVDD_6
XVDD_7
XVDD_8
XVDD_9
XVDD_10
XVDD_11
XVDD_12
XVDD_13
XVDD_14
XVDD_15
XVDD_16
XVDD_17
XVDD_18
XVDD_19
XVDD_20
XVDD_21
XVDD_22
XVDD_23
XVDD_24
XVDD_25
XVDD_26
XVDD_27
XVDD_28
XVDD_29
XVDD_30
XVDD_31
XVDD_32
XVDD_33
XVDD_34
XVDD_35
XVDD_36
XVDD_37
XVDD_38
4
3
2
AA17
AA18
AA20
AA22
AB12
AB14
AB16
AB19
AB21
AB23
AB28
AB30
AB32
AC13
AC15
AC17
AC18
AA13
AC20
AC22
AE28
AE30
AE32
AE33
AH10
AA15
AH13
AH16
AH19
AH22
AH24
AH28
AH29
AH30
AH32
AH33
AK10
AL12
AL14
AL15
AL17
AL18
AL20
AL21
AL23
AL24
AL26
AL28
AL30
AL32
AL33
AM13
AM16
AM19
AM22
AM25
AN10
AN13
AN16
AN19
AN22
AN25
AN30
AN34
AP33
UV1F
UV1F
A2
AB2
A33
AB5
AB7
AE2
AE5
AE7
AH2
AH5
AH7
AJ7
AK7
AL2
AL5
AN1
AN4
AN7
AP2
B1
B10
B22
B25
B28
B31
B34
B4
B7
C10
C13
C19
C22
C25
C28
C7
GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99
Part 6 of 7
Part 6 of 7
GND
GND
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192
GND_193
GND_194
GND_195
GND_196
GND_197
GND_198
GND_199
GND_OPT
GND_OPT
1
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
N13P-VGA CORE, GND
N13P-VGA CORE, GND
N13P-VGA CORE, GND
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
of
26 65Tuesday, March 20, 2012
26 65Tuesday, March 20, 2012
26 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 27
5
FBA_D[0..63]<28,29>
30ohms (ESR=0.01) Bead
P/N;SM010007W00
+1.05VS_VGA +FB_PLLAVDD
FBMA-L11-160808300LMA25T_2P
FBMA-L11-160808300LMA25T_2P
D D
C C
B B
A A
1 2
Place close to BGA
DGPU_GC6_EN<18>
LV3
LV3
GC6@
GC6@
GC6@
GC6@
200mA
+FB_PLLAVDD
FBA_EDC[3..0]< 28>
FBA_EDC[7..4]< 29>
RV169
RV169
1 2
0_0402_5%
0_0402_5%
1 2
DGPU_PWROK<19,32,55,58>
GC6@
GC6@
+3VS
13
D
@GD
@
2
QV4
QV4
G
2N7002_SOT23
2N7002_SOT23
S
S
GC6_ENFB_CLAMP
RV181K_0402_1%
RV181K_0402_1%
12
RV6810K_0402_5%
RV6810K_0402_5%
5
FBA_D[0..63]
FBA_DBI0#<28>
FBA_DBI1#<28>
FBA_DBI2#<28>
FBA_DBI3#<28>
FBA_DBI4#<29>
FBA_DBI5#<29>
FBA_DBI6#<29>
FBA_DBI7#<29>
GC6_EN <32>
DV3
DV3
DAN202UT106_SC70-3
DAN202UT106_SC70-3
2
1
3
GC6@
GC6@
1 2
RV156 0_0402_5%
RV156 0_0402_5%
NOGC6@
NOGC6@
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DBI0#
FBA_DBI1#
FBA_DBI2#
FBA_DBI3#
FBA_DBI4#
FBA_DBI5#
FBA_DBI6#
FBA_DBI7#
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
FBVDDQ_PWR_EN <55>
12
RV29
RV29
200K_0402_5%
200K_0402_5%
GC6@
GC6@
UV1B
UV1B
L28
FBA_D0
M29
FBA_D1
L29
FBA_D2
M28
FBA_D3
N31
FBA_D4
P29
FBA_D5
R29
FBA_D6
P28
FBA_D7
J28
FBA_D8
H29
FBA_D9
J29
FBA_D10
H28
FBA_D11
G29
FBA_D12
E31
FBA_D13
E32
FBA_D14
F30
FBA_D15
C34
FBA_D16
D32
FBA_D17
B33
FBA_D18
C33
FBA_D19
F33
FBA_D20
F32
FBA_D21
H33
FBA_D22
H32
FBA_D23
P34
FBA_D24
P32
FBA_D25
P31
FBA_D26
P33
FBA_D27
L31
FBA_D28
L34
FBA_D29
L32
FBA_D30
L33
FBA_D31
AG28
FBA_D32
AF29
FBA_D33
AG29
FBA_D34
AF28
FBA_D35
AD30
FBA_D36
AD29
FBA_D37
AC29
FBA_D38
AD28
FBA_D39
AJ29
FBA_D40
AK29
FBA_D41
AJ30
FBA_D42
AK28
FBA_D43
AM29
FBA_D44
AM31
FBA_D45
AN29
FBA_D46
AM30
FBA_D47
AN31
FBA_D48
AN32
FBA_D49
AP30
FBA_D50
AP32
FBA_D51
AM33
FBA_D52
AL31
FBA_D53
AK33
FBA_D54
AK32
FBA_D55
AD34
FBA_D56
AD32
FBA_D57
AC30
FBA_D58
AD33
FBA_D59
AF31
FBA_D60
AG34
FBA_D61
AG32
FBA_D62
AG33
FBA_D63
P30
FBA_DQM0
F31
FBA_DQM1
F34
FBA_DQM2
M32
FBA_DQM3
AD31
FBA_DQM4
AL29
FBA_DQM5
AM32
FBA_DQM6
AF34
FBA_DQM7
M31
FBA_DQS_WP0
G31
FBA_DQS_WP1
E33
FBA_DQS_WP2
M33
FBA_DQS_WP3
AE31
FBA_DQS_WP4
AK30
FBA_DQS_WP5
AN33
FBA_DQS_WP6
AF33
FBA_DQS_WP7
M30
FBA_DQS_RN0
H30
FBA_DQS_RN1
E34
FBA_DQS_RN2
M34
FBA_DQS_RN3
AF30
FBA_DQS_RN4
AK31
FBA_DQS_RN5
AM34
FBA_DQS_RN6
AF32
FBA_DQS_RN7
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
Part 2 of 7
Part 2 of 7
4
MEMORY INTERFACE
A
MEMORY INTERFACE
A
4
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD_RFU0
FBA_CMD_RFU1
FBA_DEBUG0
FBA_DEBUG1
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FBA_WCKB01
FBA_WCKB01_N
FBA_WCKB23
FBA_WCKB23_N
FBA_WCKB45
FBA_WCKB45_N
FBA_WCKB67
FBA_WCKB67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
FB_VREF
U30
FBA_CS#_L
T31
FBA_MA3_BA3_L
U29
FBA_MA2_BA0_L
R34
FBA_MA4_BA2_L
R33
FBA_MA5_BA1_L
U32
FBA_WE#_L
U33
FBA_MA7_MA8_L
U28
FBA_MA6_MA11_L
V28
FBA_ABI#_L
V29
FBA_MA12_RFU_L
V30
FBA_MA0_MA10_L
U34
FBA_MA1_MA9_L
U31
FBA_RAS#_L
V34
FBA_RST#_L
V33
FBA_CKE_L
Y32
FBA_CAS#_L
AA31
FBA_CS#_H
AA29
FBA_MA3_BA3_H
AA28
FBA_MA2_BA0_H
AC34
FBA_MA4_BA2_H
AC33
FBA_MA5_BA1_H
AA32
FBA_WE#_H
AA33
FBA_MA7_MA8_H
Y28
FBA_MA6_MA11_H
Y29
FBA_ABI#_H
W31
FBA_MA12_RFU_H
Y30
FBA_MA0_MA10_H
AA34
FBA_MA1_MA9_H
Y31
FBA_RAS#_H
Y34
FBA_RST#_H
Y33
FBA_CKE_H
V31
FBA_CAS#_H
R32
AC32
1 2
R28
AC28
1 2
@
R30
FBA_CLK0
R31
FBA_CLK0#
AB31
FBA_CLK1
AC31
FBA_CLK1#
K31
FBA_WCK0
L30
FBA_WCK0_N
H34
FBA_WCK1
J34
FBA_WCK1_N
AG30
FBA_WCK2
AG31
FBA_WCK2_N
AJ34
FBA_WCK3
AK34
FBA_WCK3_N
J30
J31
J32
J33
GC6 suppor t on 15"
AH31
AJ31
FB_CLAMP
AJ32
AJ33
RV66 10K_0402_5%NOGC6@RV66 10K_0402_5%NOGC6@
E1
CV106 0.1U_0402_10V7KCV106 0.1U_0402_10V7K
1 2
K27
Place close to ball
U27
H26
Place close to ball Place close to BGA
FBA_RST#_L
FBA_RST#_H
@
RV5860.4_0402_1%@RV5860.4_0402_1%
RV5960.4_0402_1%@RV5960.4_0402_1%
12
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
12
FBA_CS#_L <28>
FBA_MA3_BA3_L <28>
FBA_MA2_BA0_L <28>
FBA_MA4_BA2_L <28>
FBA_MA5_BA1_L <28>
FBA_WE#_L <28>
FBA_MA7_MA8_L <28>
FBA_MA6_MA11_L <28>
FBA_ABI#_L <28>
FBA_MA12_RFU_L <28>
FBA_MA0_MA10_L <28>
FBA_MA1_MA9_L <28>
FBA_RAS#_L <28>
FBA_RST#_L <28>
FBA_CAS#_L <28>
FBA_CS#_H <29>
FBA_MA3_BA3_H <29>
FBA_MA2_BA0_H <29>
FBA_MA4_BA2_H <29>
FBA_MA5_BA1_H <29>
FBA_WE#_H <29>
FBA_MA7_MA8_H <29>
FBA_MA6_MA11_H <29>
FBA_ABI#_H <29>
FBA_MA12_RFU_H <29>
FBA_MA0_MA10_H <29>
FBA_MA1_MA9_H <29>
FBA_RAS#_H <29>
FBA_RST#_H <29>
FBA_CAS#_H <29>
FBA_CLK0 <28>
FBA_CLK0# <28>
FBA_CLK1 <29>
FBA_CLK1# <29>
FBA_WCK0 <28>
FBA_WCK0_N <28>
FBA_WCK1 <28>
FBA_WCK1_N <28>
FBA_WCK2 <29>
FBA_WCK2_N <29>
FBA_WCK3 <29>
FBA_WCK3_N <29>
+FB_PLLAVDD
1
CV107
CV107
CV110
CV110
2
1U_0402_6.3V6K
1U_0402_6.3V6K
12
RV71
RV71
10K_0402_5%
10K_0402_5%
+1.5VS_VGA
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
RV72
RV72
10K_0402_5%
10K_0402_5%
+FB_PLLAVDD
CV39
CV39
FBC_D[0..63]<30,31>
+1.5VS_VGA
12
+1.5VS_VGA
12
RV209
RV209
10K_0402_5%
10K_0402_5%
RV221
RV221
10K_0402_5%
10K_0402_5%
FBC_EDC[3..0]<30>
FBC_EDC[7..4]<31>
3
FBC_D[0..63]
FBA_CKE_L <28>
FBA_CKE_H <29>
FBC_DBI0#<30>
FBC_DBI1#<30>
FBC_DBI2#<30>
FBC_DBI3#<30>
FBC_DBI4#<31>
FBC_DBI5#<31>
FBC_DBI6#<31>
FBC_DBI7#<31>
3
2
UV1C
UV1C
Part 3 of 7
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DBI0#
FBC_DBI1#
FBC_DBI2#
FBC_DBI3#
FBC_DBI4#
FBC_DBI5#
FBC_DBI6#
FBC_DBI7#
FBC_EDC0
FBC_EDC1
FBC_EDC2
FBC_EDC3
FBC_EDC4
FBC_EDC5
FBC_EDC6
FBC_EDC7
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
E11
E3
A3
C9
F23
F27
C30
A24
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
Part 3 of 7
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
FBB_DQS_RN0
FBB_DQS_RN1
FBB_DQS_RN2
FBB_DQS_RN3
FBB_DQS_RN4
FBB_DQS_RN5
FBB_DQS_RN6
FBB_DQS_RN7
N13P-GT1-A2_FCBGA908
N13P-GT1-A2_FCBGA908
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
FBB_CMD_RFU0
FBB_CMD_RFU1
MEMORY INTERFACE B
MEMORY INTERFACE B
FBB_WCKB01_N
FBB_WCKB23_N
FBB_WCKB45_N
FBB_WCKB67_N
D13
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_DEBUG0
FBB_DEBUG1
FBB_CLK0
FBB_CLK0_N
FBB_CLK1
FBB_CLK1_N
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_WCKB01
FBB_WCKB23
FBB_WCKB45
FBB_WCKB67
FBB_PLL_AVDD
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
FBC_CS#_L
E14
FBC_MA3_BA3_L
F14
FBC_MA2_BA0_L
A12
FBC_MA4_BA2_L
B12
FBC_MA5_BA1_L
C14
FBC_WE#_L
B14
FBC_MA7_MA8_L
G15
FBC_MA6_MA11_L
F15
FBC_ABI#_L
E15
FBC_MA12_RFU_L
D15
FBC_MA0_MA10_L
A14
FBC_MA1_MA9_L
D14
FBC_RAS#_L
A15
FBC_RST#_L
B15
FBC_CKE_L
C17
FBC_CAS#_L
D18
FBC_CS#_H
E18
FBC_MA3_BA3_H
F18
FBC_MA2_BA0_H
A20
FBC_MA4_BA2_H
B20
FBC_MA5_BA1_H
C18
FBC_WE#_H
B18
FBC_MA7_MA8_H
G18
FBC_MA6_MA11_H
G17
FBC_ABI#_H
F17
FBC_MA12_RFU_H
D16
FBC_MA0_MA10_H
A18
FBC_MA1_MA9_H
D17
FBC_RAS#_H
A17
FBC_RST#_H
B17
FBC_CKE_H
E17
FBC_CAS#_H
C12
C20
G14
G20
D12
FBC_CLK0
E12
FBC_CLK0#
E20
FBC_CLK1
F20
FBC_CLK1#
F8
FBC_WCK0
E8
FBC_WCK0_N
A5
FBC_WCK1
A6
FBC_WCK1_N
D24
FBC_WCK2
D25
FBC_WCK2_N
B27
FBC_WCK3
C27
FBC_WCK3_N
D6
D7
C6
B6
F26
E26
A26
A27
H17
0.1U_0402_10V7K
0.1U_0402_10V7K
Place close to ball
Compal Secret Data
Compal Secret Data
Compal Secret Data
2
1 2
1 2
@
1
CV108
CV108
2
Deciphered Date
Deciphered Date
Deciphered Date
@
RV6060.4_0402_1%@RV6060.4_0402_1%
RV6160.4_0402_1%@RV6160.4_0402_1%
FBC_CLK0 <30>
FBC_CLK0# <30>
FBC_CLK1 <31>
FBC_CLK1# <31>
FBC_CS#_L <30>
FBC_MA3_BA3_L <30>
FBC_MA2_BA0_L <30>
FBC_MA4_BA2_L <30>
FBC_MA5_BA1_L <30>
FBC_WE#_L <30>
FBC_MA7_MA8_L <30>
FBC_MA6_MA11_L <30>
FBC_ABI#_L <30>
FBC_MA12_RFU_L <30>
FBC_MA0_MA10_L <30>
FBC_MA1_MA9_L <30>
FBC_RAS#_L <30>
FBC_RST#_L <30>
FBC_CAS#_L <30>
FBC_CS#_H <31>
FBC_MA3_BA3_H <31>
FBC_MA2_BA0_H <31>
FBC_MA4_BA2_H <31>
FBC_MA5_BA1_H <31>
FBC_WE#_H <31>
FBC_MA7_MA8_H <31>
FBC_MA6_MA11_H <31>
FBC_ABI#_H <31>
FBC_MA12_RFU_H <31>
FBC_MA0_MA10_H <31>
FBC_MA1_MA9_H <31>
FBC_RAS#_H <31>
FBC_RST#_H <31>
FBC_CAS#_H <31>
+1.5VS_VGA
FBC_WCK0 <30>
FBC_WCK0_N <30>
FBC_WCK1 <30>
FBC_WCK1_N <30>
FBC_WCK2 <31>
FBC_WCK2_N <31>
FBC_WCK3 <31>
FBC_WCK3_N <31>
+FB_PLLAVDD
FBC_RST#_L
FBC_RST#_H
PU for X16 modePU for X16 mode
+1.5VS_VGA
12
+1.5VS_VGA
12
1
GDDR5
Mode H - Mirror Mode Mapping
RV210
RV210
10K_0402_5%
10K_0402_5%
FBC_CKE_L <30>
RV222
RV222
10K_0402_5%
10K_0402_5%
FBC_CKE_H <31>
12
12
RV74
RV74
RV73
RV73
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
A3_BA3
A2_BA0
A4_BA2
A5_BA1
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
N13P-MEM Interface
N13P-MEM Interface
N13P-MEM Interface
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
CS#
WE#
RAS#
RST#
CKE#
CAS#
DATA Bus
27 65Tuesday, March 20, 2012
27 65Tuesday, March 20, 2012
27 65Tuesday, March 20, 2012
32..630..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
0.2
0.2
0.2
Page 28
5
Memory - Lower 32 bits
FBA_EDC0
FBA_D[0..31]<27>
FBA_EDC[3..0]<27>
D D
Follow DG
1 2
FBA_CLK0
RV21 40.2_0402_1%RV 21 40.2_0402_1%
RV123
RV123
160_0402_1%
160_0402_1%
@
FBA_CLK0#
MEM_VREF<23,29,30,31>
@
1 2
1 2
RV28 40.2_0402_1%RV 28 40.2_0402_1%
2
G
G
1
CV155
CV155
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV212
RV212
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
13
D
D
QV9
QV9
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
549_0402_1%
549_0402_1%
2
1
10U_0603_6.3V6M
10U_0603_6.3V6M
C C
B B
A A
FBA_DBI0#<27>
FBA_DBI2#<27> FBA_DBI1#<27>
FBA_CLK0<27>
FBA_CLK0#<27>
FBA_CKE_L<27>
FBA_MA2_BA0_L<27>
FBA_MA5_BA1_L<27>
FBA_MA4_BA2_L<27>
FBA_MA3_BA3_L<27>
FBA_MA7_MA8_L<27>
FBA_MA1_MA9_L<27>
FBA_MA0_MA10_L<27>
FBA_MA6_MA11_L<27>
FBA_MA12_RFU_L<27>
RV119
RV119
121_0402_1%
121_0402_1%
FBA_ABI#_L<27>
FBA_RAS#_L<27>
FBA_CS#_L<27>
FBA_CAS#_L<27>
FBA_WE#_L<27>
FBA_WCK0_N<27>
FBA_WCK0<27>
FBA_WCK1_N<27>
FBA_WCK1<27>
FBA_RST#_L<27>
+1.5VS_VGA
12
RV127
RV127
12
1
RV128
RV128
2
820P_0402_25V7
820P_0402_25V7
+1.5VS_VGA
RV129
RV129
549_0402_1%
549_0402_1%
RV213
RV213
1 2
931_0402_1%
931_0402_1%
RV130
RV130
1.33K_0402_1%
1.33K_0402_1%
UV3 SIDE
1
CV68
CV68
CV166
CV166
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBA_EDC2
FBA_DBI0#
FBA_DBI2#
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA12_RFU_L
12
RV115
RV115
1K_0402_1%
1K_0402_1%
12
RV117
RV117
12
1K_0402_1%
1K_0402_1%
FBA_ABI#_L
FBA_RAS#_L
FBA_CS#_L
FBA_CAS#_L
FBA_WE#_L
FBA_WCK0_N
FBA_WCK0
FBA_WCK1_N
FBA_WCK1
+FBA_VREFD_L
+FBA_VREFC0
FBA_RST#_L
+FBA_VREFC0
16 mil
CV42
CV42
+1.5VS_VGA +1.5VS_VGA
12
+FBA_VREFD_L
12
820P_0402_25V7
820P_0402_25V7
1
1
CV69
CV69
CV77
CV77
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
UV3
UV3
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WC K23#
D4
WCK01 WCK23
P5
WCK23# WC K01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
1
CV58
CV58
2
1
2
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
1
CV78
CV78
CV129
CV129
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
1
CV132
CV132
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
CV133
CV133
4
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
3
UV4
UV4
MF=0 MF=1 MF=0MF=1
A4
FBA_D0
A2
FBA_D1
B4
FBA_D2
B2
FBA_D3
E4
FBA_D4
E2
FBA_D5
F4
FBA_D6
F2
FBA_D7
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D16
U13
FBA_D17
T11
FBA_D18
T13
FBA_D19
N11
FBA_D20
N13
FBA_D21
M11
FBA_D22
M13
FBA_D23
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CV174
CV174
BYTE0
BYTE2
UV4 SIDE
1
CV71
CV71
2
1U_0603_25V6
1U_0603_25V6
FBA_DBI3#<27>
+1.5VS_VGA
RV120
RV120
121_0402_1%
121_0402_1%
1
1
1
CV76
CV76
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1
CV79
CV79
CV80
CV80
CV134
CV134
2
2
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
12
1
CV135
CV135
2
FBA_CLK0
FBA_CLK0#
FBA_CKE_L
FBA_MA4_BA2_L
FBA_MA3_BA3_L
FBA_MA2_BA0_L
FBA_MA5_BA1_L
FBA_MA0_MA10_L
FBA_MA6_MA11_L
FBA_MA7_MA8_L
FBA_MA1_MA9_L
FBA_MA12_RFU_L
12
RV116
RV116
1K_0402_1%
1K_0402_1%
12
RV118
RV118
1K_0402_1%
1K_0402_1%
FBA_ABI#_L
FBA_CAS#_L
FBA_WE#_L
FBA_RAS#_L
FBA_CS#_L
FBA_WCK1_N
FBA_WCK1
FBA_WCK0_N
FBA_WCK0
+FBA_VREFD_L
+FBA_VREFC0
FBA_RST#_L
1
CV136
CV136
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_EDC3
FBA_EDC1
FBA_DBI3#
FBA_DBI1#
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WC K23#
D4
WCK01 WCK23
P5
WCK23# WC K01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
2
A4
FBA_D24
A2
FBA_D25
B4
FBA_D26
B2
FBA_D27
E4
FBA_D28
E2
FBA_D29
F4
FBA_D30
F2
FBA_D31
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
FBA_D10
T13
FBA_D11
N11
FBA_D12
N13
FBA_D13
M11
FBA_D14
M13
FBA_D15
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBA_D8
FBA_D9
BYTE3
GDDR5
BYTE1
+1.5VS_VGA+1.5VS_VGA
Mode H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
1
DATA Bus
0..31 32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
N13P-VRAM A Lower
N13P-VRAM A Lower
N13P-VRAM A Lower
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
28 65Tuesday, March 20, 2012
28 65Tuesday, March 20, 2012
28 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 29
5
Memory - Upper 32 bits
C2
FBA_EDC4
C13
R13
FBA_CLK1
FBA_CLK1#
FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA12_RFU_H
12
+FBA_VREFC1
16 mil
CV59
CV59
+FBA_VREFD_H
820P_0402_25V7
820P_0402_25V7
1
CV138
CV138
2
FBA_CKE_H
12
RV131
RV131
1K_0402_1%
1K_0402_1%
12
RV133
RV133
1K_0402_1%
1K_0402_1%
FBA_ABI#_H
FBA_RAS#_H
FBA_CS#_H
FBA_CAS#_H
FBA_WE#_H
FBA_WCK2_N
FBA_WCK2
FBA_WCK3_N
FBA_WCK3
+FBA_VREFD_H
+FBA_VREFC1
FBA_RST#_H
+1.5VS_VGA
1
CV60
CV60
2
1
CV142
CV142
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_EDC6
FBA_DBI4#
FBA_DBI6#
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
R2
D2
D13
P13
P2
J12
J11
J3
H11
K10
K11
H10
K4
H5
H4
K5
J5
A5
U5
J1
J10
J13
J4
G3
G12
L3
L12
D5
D4
P5
P4
A10
U10
J14
J2
H1
K1
B5
G5
L5
T5
B10
D10
G10
L10
P10
T10
H14
K14
G1
L1
G4
L4
C5
R5
C10
R10
D11
G11
L11
P11
G14
L14
CV137
CV137
FBA_D[63..32]<27>
D D
FBA_EDC[7..4]<27>
Follow DG
1 2
FBA_CLK1
RV31 40.2_0402_1%RV 31 40.2_0402_1%
RV139
RV139
160_0402_1%
C C
B B
MEM_VREF<23,28,30,31>
A A
FBA_CLK1#
160_0402_1%
@
@
1 2
1 2
RV36 40.2_0402_1%RV 36 40.2_0402_1%
13
D
D
2
G
G
QV11
QV11
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
UV5 SIDE
2
CV179
CV179
1
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
0.01U_0402_25V7K
0.01U_0402_25V7K
1
2
1
CV175
CV175
2
RV214
RV214
1 2
931_0402_1%
931_0402_1%
RV215
RV215
1 2
931_0402_1%
931_0402_1%
CV84
CV84
1U_0603_25V6
1U_0603_25V6
1.33K_0402_1%
1.33K_0402_1%
1.33K_0402_1%
1.33K_0402_1%
1
CV81
CV81
2
549_0402_1%
549_0402_1%
549_0402_1%
549_0402_1%
1U_0603_25V6
1U_0603_25V6
FBA_MA2_BA0_H<27>
FBA_MA5_BA1_H<27>
FBA_MA4_BA2_H<27>
FBA_MA3_BA3_H<27>
FBA_MA7_MA8_H<27>
FBA_MA1_MA9_H<27>
FBA_MA0_MA10_H<27>
FBA_MA6_MA11_H<27>
FBA_MA12_RFU_H<27>
RV143
RV143
RV144
RV144
RV145
RV145
RV146
RV146
1
2
FBA_CLK1<27>
FBA_CLK1#<27>
FBA_CKE_H<27>
FBA_ABI#_H<27>
FBA_RAS#_H<27>
FBA_CS#_H<27>
FBA_CAS#_H<27>
FBA_WE#_H<27>
FBA_WCK2_N<27>
FBA_WCK2<27>
FBA_WCK3_N<27>
FBA_WCK3<27>
FBA_RST#_H<27>
+1.5VS_VGA
+1.5VS_VGA
CV82
CV82
1U_0603_25V6
1U_0603_25V6
12
12
12
12
1
2
RV135
RV135
CV83
CV83
FBA_DBI4#<27>
FBA_DBI6#<27>
121_0402_1%
121_0402_1%
1
2
820P_0402_25V7
820P_0402_25V7
0.1U_0402_10V7K
0.1U_0402_10V7K
4
UV5
UV5
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
EDC0 EDC3
EDC1 EDC2
EDC2 EDC1
EDC3 EDC0
DBI0# DBI3#
DBI1# DBI2#
DBI2# DBI1#
DBI3# DBI0#
CK
CK#
CKE#
BA0/A2 BA2/A4
BA1/A5 BA3/A3
BA2/A4 BA0/A2
BA3/A3 BA1/A5
A8/A7 A10/A0
A9/A1 A11/A6
A10/A0 A8/A7
A11/A6 A9/A1
A12/RFU/NC
VPP/NC
VPP/NC
MF
SEN
ZQ
ABI#
RAS# CAS#
CS# WE#
CAS# RAS#
WE# CS#
WCK01# WC K23#
WCK01 WCK23
WCK23# WC K01#
WCK23 WCK01
VREFD
VREFD
VREFC
RESET#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
3
UV6
UV6
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
A4
FBA_D32
A2
FBA_D33
B4
FBA_D34
B2
FBA_D35
E4
FBA_D36
E2
FBA_D37
F4
FBA_D38
F2
FBA_D39
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D48
U13
FBA_D49
T11
FBA_D50
T13
FBA_D51
N11
FBA_D52
N13
FBA_D53
M11
FBA_D54
M13
FBA_D55
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CV187
CV187
BYTE4
BYTE6
UV6 SIDE
1
CV87
CV87
2
1U_0603_25V6
1U_0603_25V6
FBA_DBI7#<27>
FBA_DBI5#<27>
FBA_CLK1
FBA_CLK1#
FBA_CKE_H
FBA_MA4_BA2_H
FBA_MA3_BA3_H
FBA_MA2_BA0_H
FBA_MA5_BA1_H
FBA_MA0_MA10_H
FBA_MA6_MA11_H
FBA_MA7_MA8_H
FBA_MA1_MA9_H
FBA_MA12_RFU_H
+1.5VS_VGA
RV132
RV132
1K_0402_1%
1K_0402_1%
RV134
RV134
12
RV136
RV136
1
1
2
1U_0603_25V6
1U_0603_25V6
1
CV85
CV85
CV88
CV88
CV86
CV86
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
121_0402_1%
121_0402_1%
1
CV145
CV145
2
0.1U_0402_10V7K
0.1U_0402_10V7K
+FBA_VREFD_H
+FBA_VREFC1
+1.5VS_VGA
1
CV143
CV143
2
1K_0402_1%
1K_0402_1%
FBA_ABI#_H
FBA_CAS#_H
FBA_WE#_H
FBA_RAS#_H
FBA_CS#_H
FBA_WCK3_N
FBA_WCK3
FBA_WCK2_N
FBA_WCK2
FBA_RST#_H
0.1U_0402_10V7K
0.1U_0402_10V7K
FBA_EDC7
FBA_EDC5
FBA_DBI7#
FBA_DBI5#
12
12
1
2
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WC K23#
D4
WCK01 WCK23
P5
WCK23# WC K01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
CV144
CV144
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
2
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
1
A4
FBA_D56
A2
FBA_D57
B4
FBA_D58
B2
FBA_D59
E4
FBA_D60
E2
FBA_D61
F4
FBA_D62
F2
FBA_D63
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBA_D40
U13
FBA_D41
T11
FBA_D42
T13
FBA_D43
N11
FBA_D44
N13
FBA_D45
M11
FBA_D46
M13
FBA_D47
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYTE7
BYTE5
GDDR5
Mode H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUS TODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
N13P-VRAM A Upper
N13P-VRAM A Upper
N13P-VRAM A Upper
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
29 65Tuesday, March 20, 2012
29 65Tuesday, March 20, 2012
29 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 30
5
4
3
2
1
Memory Partition C - Lower 32 bits
UV8
UV7
UV7
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
FBC_EDC0
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA12_RFU_L
RV147
RV147
RV149
RV149
FBC_ABI#_L
FBC_RAS#_L
FBC_CS#_L
FBC_CAS#_L
FBC_WE#_L
FBC_WCK0_N
FBC_WCK0
FBC_WCK1_N
FBC_WCK1
+FBC_VREFD_L
+FBC_VREFC0
+FBC_VREFC0
1
CV61
CV61
2
+1.5VS_VGA
+FBC_VREFD_L
1
2
820P_0402_25V7
820P_0402_25V7
1
CV157
CV157
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC2
FBC_DBI0#
FBC_DBI2#
12
1K_0402_1%
1K_0402_1%
12
1K_0402_1%
1K_0402_1%
FBC_RST#_L
CV62
CV62
1
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_D[0..31]<27>
D D
C C
B B
A A
FBC_EDC[3..0]<27>
Follow DG
FBC_CLK0
FBC_CLK0#
MEM_VREF<23,28,29,31>
+1.5VS_VGA
1 2
RV37 40.2_0402_1%RV37 40.2_0402_1%
RV155
RV155
160_0402_1%
160_0402_1%
@
@
1 2
1 2
RV39 40.2_0402_1%RV39 40.2_0402_1%
13
D
D
2
G
G
S
S
UV7 SIDE
1
2
CV91
CV91
CV199
CV199
2
1
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
FBC_MA12_RFU_L<27>
1
CV195
CV195
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV216
RV216
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
549_0402_1%
549_0402_1%
RV217
RV217
1 2
931_0402_1%
931_0402_1%
1.33K_0402_1%
1.33K_0402_1%
QV13
QV13
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
1
1
CV92
CV92
CV89
CV89
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
FBC_CLK0<27>
FBC_CLK0#<27>
FBC_CKE_L<27>
FBC_MA2_BA0_L<27>
FBC_MA5_BA1_L<27>
FBC_MA4_BA2_L<27>
FBC_MA3_BA3_L<27>
FBC_MA7_MA8_L<27>
FBC_MA1_MA9_L<27>
FBC_MA0_MA10_L<27>
FBC_MA6_MA11_L<27>
FBC_ABI#_L<27>
FBC_RAS#_L<27>
FBC_CS#_L<27>
FBC_CAS#_L<27>
FBC_WE#_L<27>
FBC_WCK0_N<27>
FBC_WCK0<27>
FBC_WCK1_N<27>
FBC_WCK1<27>
FBC_RST#_L<27>
+1.5VS_VGA
RV159
RV159
549_0402_1%
549_0402_1%
RV160
RV160
+1.5VS_VGA
RV161
RV161
RV162
RV162
1
2
1U_0603_25V6
1U_0603_25V6
CV90
CV90
RV151
RV151
12
12
12
12
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_DBI0#<27>
FBC_DBI2#<27>
12
121_0402_1%
121_0402_1%
820P_0402_25V7
820P_0402_25V7
1
CV160
CV160
2
CV159
CV159
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D0
A2
FBC_D1
B4
FBC_D2
B2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
+1.5VS_VGA
BYTE0
BYTE2
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
CV207
CV207
UV8 SIDE
1
CV95
CV95
2
1U_0603_25V6
1U_0603_25V6
FBC_DBI3#<27>
FBC_DBI1#<27>
+1.5VS_VGA
12
RV152
RV152
121_0402_1%
121_0402_1%
1
1
1
CV96
CV96
2
1U_0603_25V6
1U_0603_25V6
CV94
CV94
CV93
CV93
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
E4
E2
F4
F2
A11
A13
B11
B13
E11
E13
F11
F13
U11
U13
T11
T13
N11
N13
M11
M13
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
FBC_MA4_BA2_L
FBC_MA3_BA3_L
FBC_MA2_BA0_L
FBC_MA5_BA1_L
FBC_MA0_MA10_L
FBC_MA6_MA11_L
FBC_MA7_MA8_L
FBC_MA1_MA9_L
FBC_MA12_RFU_L
1
CV163
CV163
2
FBC_CLK0
FBC_CLK0#
FBC_CKE_L
12
RV148
RV148
1K_0402_1%
1K_0402_1%
12
RV150
RV150
1K_0402_1%
1K_0402_1%
FBC_ABI#_L
FBC_CAS#_L
FBC_WE#_L
FBC_RAS#_L
FBC_CS#_L
FBC_WCK1_N
FBC_WCK1
FBC_WCK0_N
FBC_WCK0
+FBC_VREFD_L
+FBC_VREFC0
FBC_RST#_L
+1.5VS_VGA
1
CV161
CV161
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC3
FBC_EDC1
FBC_DBI3#
FBC_DBI1#
UV8
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
1
CV162
CV162
2
0.1U_0402_10V7K
0.1U_0402_10V7K
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D24
A2
FBC_D25
B4
FBC_D26
B2
FBC_D27
E4
FBC_D28
E2
FBC_D29
F4
FBC_D30
F2
FBC_D31
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D8
U13
FBC_D9
T11
FBC_D10
T13
FBC_D11
N11
FBC_D12
N13
FBC_D13
M11
FBC_D14
M13
FBC_D15
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYTE3
GDDR5
Mode H - Mirror Mode Mapping
BYTE1
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
2011/11/01 2011/12
2011/11/01 2011/12
2011/11/01 2011/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
N12P-VRAM C Lower
N12P-VRAM C Lower
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
N12P-VRAM C Lower
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
30 65Tuesday, March 20, 2012
30 65Tuesday, March 20, 2012
30 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 31
5
4
3
2
1
Memory Partition C - Upper 32 bits
UV9
UV9
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
FBC_EDC4
FBC_CLK1#
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA12_RFU_H
1
CV64
CV64
2
820P_0402_25V7
820P_0402_25V7
CV167
CV167
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC6
FBC_DBI4#
FBC_DBI6#
FBC_CLK1
FBC_CKE_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA7_MA8_H
FBC_MA1_MA9_H
12
RV163
RV163
1K_0402_1%
1K_0402_1%
12
RV165
RV165
1K_0402_1%
1K_0402_1%
FBC_ABI#_H
FBC_RAS#_H
FBC_CS#_H
FBC_CAS#_H
FBC_WE#_H
FBC_WCK2_N
FBC_WCK2
FBC_WCK3_N
FBC_WCK3
+FBC_VREFD_H
+FBC_VREFC1
FBC_RST#_H
+1.5VS_VGA
1
1
CV164
CV164
2
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_D[63..32]<27>
D D
FBC_EDC[7..4]<27>
Follow DG
1 2
FBC_CLK1
RV41 40.2_0402_1%RV41 40.2_0402_1%
RV171
FBC_CLK1#
RV171
160_0402_1%
160_0402_1%
@
@
1 2
1 2
RV48 40.2_0402_1%RV48 40.2_0402_1%
1 2
1 2
13
D
D
2
G
G
QV15
QV15
S
S
2N7002W-T/R7_SOT323-3
2N7002W-T/R7_SOT323-3
+1.5VS_VGA
UV9 SIDE
1
2
CV245
CV245
2
1
1U_0603_25V6
1U_0603_25V6
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
0.01U_0402_25V7K
0.01U_0402_25V7K
RV218
RV218
931_0402_1%
931_0402_1%
RV219
RV219
931_0402_1%
931_0402_1%
CV99
CV99
1U_0603_25V6
1U_0603_25V6
CV215
CV215
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
549_0402_1%
549_0402_1%
1.33K_0402_1%
1.33K_0402_1%
1
CV100
CV100
2
1U_0603_25V6
1U_0603_25V6
+1.5VS_VGA
RV175
RV175
RV176
RV176
+1.5VS_VGA
RV177
RV177
RV178
RV178
1
CV97
CV97
2
C C
B B
MEM_VREF<23,28,29,30>
A A
FBC_DBI4#<27>
FBC_DBI6#<27>
FBC_CLK1<27>
FBC_CLK1#<27>
FBC_CKE_H<27>
FBC_MA2_BA0_H<27>
FBC_MA5_BA1_H<27>
FBC_MA4_BA2_H<27>
FBC_MA3_BA3_H<27>
FBC_MA7_MA8_H<27>
FBC_MA1_MA9_H<27>
FBC_MA0_MA10_H<27>
FBC_MA6_MA11_H<27>
FBC_MA12_RFU_H<27>
12
RV167
RV167
121_0402_1%
121_0402_1%
FBC_ABI#_H<27>
FBC_RAS#_H<27>
FBC_CS#_H<27>
FBC_CAS#_H<27>
FBC_WE#_H<27>
FBC_WCK2_N<27>
FBC_WCK2<27>
FBC_WCK3_N<27>
FBC_WCK3<27>
FBC_RST#_H<27>
12
+FBC_VREFC1
12
1
CV63
CV63
2
820P_0402_25V7
820P_0402_25V7
12
+FBC_VREFD_H
12
1
1
CV98
CV98
2
2
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
CV165
CV165
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
A4
FBC_D32
A2
FBC_D33
B4
FBC_D34
B2
FBC_D35
E4
FBC_D36
E2
FBC_D37
F4
FBC_D38
F2
FBC_D39
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D48
U13
FBC_D49
T11
FBC_D50
T13
FBC_D51
N11
FBC_D52
N13
FBC_D53
M11
FBC_D54
M13
FBC_D55
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
+1.5VS_VGA
10U_0603_6.3V6M
10U_0603_6.3V6M
2
1
BYTE4
BYTE6
UV10 SIDE
CV227
CV227
1U_0603_25V6
1U_0603_25V6
FBC_DBI7#<27>
FBC_DBI5#<27>
+1.5VS_VGA
12
RV168
RV168
121_0402_1%
121_0402_1%
1
2
1
1
CV103
CV103
2
1U_0603_25V6
1U_0603_25V6
1
CV101
CV101
CV102
CV104
CV104
CV102
2
2
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
1U_0603_25V6
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_CLK1
FBC_CLK1#
FBC_CKE_H
FBC_MA4_BA2_H
FBC_MA3_BA3_H
FBC_MA2_BA0_H
FBC_MA5_BA1_H
FBC_MA0_MA10_H
FBC_MA6_MA11_H
FBC_MA7_MA8_H
FBC_MA1_MA9_H
FBC_MA12_RFU_H
RV164
RV164
RV166
RV166
FBC_ABI#_H
FBC_CAS#_H
FBC_WE#_H
FBC_RAS#_H
FBC_CS#_H
FBC_WCK3_N
FBC_WCK3
FBC_WCK2_N
FBC_WCK2
+FBC_VREFD_H
+FBC_VREFC1
+1.5VS_VGA
1
CV170
CV170
2
0.1U_0402_10V7K
0.1U_0402_10V7K
FBC_EDC7
FBC_EDC5
FBC_DBI7#
FBC_DBI5#
12
1K_0402_1%
1K_0402_1%
12
1K_0402_1%
1K_0402_1%
FBC_RST#_H
1
CV168
CV168
2
0.1U_0402_10V7K
0.1U_0402_10V7K
1
CV169
CV169
2
UV10
UV10
MF=0 MF=1 MF=0MF=1
MF=0 MF=1 MF=0MF=1
C2
EDC0 EDC3
C13
EDC1 EDC2
R13
EDC2 EDC1
R2
EDC3 EDC0
D2
DBI0# DBI3#
D13
DBI1# DBI2#
P13
DBI2# DBI1#
P2
DBI3# DBI0#
J12
CK
J11
CK#
J3
CKE#
H11
BA0/A2 BA2/A4
K10
BA1/A5 BA3/A3
K11
BA2/A4 BA0/A2
H10
BA3/A3 BA1/A5
K4
A8/A7 A10/A0
H5
A9/A1 A11/A6
H4
A10/A0 A8/A7
K5
A11/A6 A9/A1
J5
A12/RFU/NC
A5
VPP/NC
U5
VPP/NC
J1
MF
J10
SEN
J13
ZQ
J4
ABI#
G3
RAS# CAS#
G12
CS# WE#
L3
CAS# RAS#
L12
WE# CS#
D5
WCK01# WCK23#
D4
WCK01 WCK23
P5
WCK23# WCK01#
P4
WCK23 WCK01
A10
VREFD
U10
VREFD
J14
VREFC
J2
RESET#
H1
VSS
K1
VSS
B5
VSS
G5
VSS
L5
VSS
T5
VSS
B10
VSS
D10
VSS
G10
VSS
L10
VSS
P10
VSS
T10
VSS
H14
VSS
K14
VSS
G1
VDD
L1
VDD
G4
VDD
L4
VDD
C5
VDD
R5
VDD
C10
VDD
R10
VDD
D11
VDD
G11
VDD
L11
VDD
P11
VDD
G14
VDD
L14
VDD
170-BALL
170-BALL
SGRAM GDDR5
SGRAM GDDR5
X76@
X76@
DQ24 DQ0
DQ25 DQ1
DQ26 DQ2
DQ27 DQ3
DQ28 DQ4
DQ29 DQ5
DQ30 DQ6
DQ31 DQ7
DQ16 DQ8
DQ17 DQ9
DQ18 DQ10
DQ19 DQ11
DQ20 DQ12
DQ21 DQ13
DQ22 DQ14
DQ23 DQ15
DQ8 DQ16
DQ9 DQ17
DQ10 DQ18
DQ11 DQ19
DQ12 DQ20
DQ13 DQ21
DQ14 DQ22
DQ15 DQ23
DQ0 DQ24
DQ1 DQ25
DQ2 DQ26
DQ3 DQ27
DQ4 DQ28
DQ5 DQ29
DQ6 DQ30
DQ7 DQ31
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
H5GQ1H24AFR-T2L_BGA170
H5GQ1H24AFR-T2L_BGA170
A4
FBC_D56
A2
FBC_D57
B4
FBC_D58
B2
FBC_D59
E4
FBC_D60
E2
FBC_D61
F4
FBC_D62
F2
FBC_D63
A11
A13
B11
B13
E11
E13
F11
F13
U11
FBC_D40
U13
FBC_D41
T11
FBC_D42
T13
FBC_D43
N11
FBC_D44
N13
FBC_D45
M11
FBC_D46
M13
FBC_D47
U4
U2
T4
T2
N4
N2
M4
M2
B1
D1
F1
M1
P1
T1
G2
L2
B3
D3
F3
H3
K3
M3
P3
T3
E5
N5
E10
N10
B12
D12
F12
H12
K12
M12
P12
T12
G13
L13
B14
D14
F14
M14
P14
T14
A1
C1
E1
N1
R1
U1
H2
K2
A3
C3
E3
N3
R3
U3
C4
R4
F5
M5
F10
M10
C11
R11
A12
C12
E12
N12
R12
U12
H13
K13
A14
C14
E14
N14
R14
U14
+1.5VS_VGA
BYTE7
BYTE5
GDDR5
Mode H - Mirror Mode Mapping
Address
FBx_CMD0
FBx_CMD1
FBx_CMD2
FBx_CMD3
FBx_CMD4
FBx_CMD5
FBx_CMD6
FBx_CMD7
FBx_CMD8
FBx_CMD9
FBx_CMD10
FBx_CMD11
FBx_CMD12
FBx_CMD13
FBx_CMD14
FBx_CMD15
FBx_CMD16
FBx_CMD17
FBx_CMD18
FBx_CMD19
FBx_CMD20
FBx_CMD21
FBx_CMD22
FBx_CMD23
FBx_CMD24
FBx_CMD25
FBx_CMD26
FBx_CMD27
FBx_CMD28
FBx_CMD29
FBx_CMD30
FBx_CMD31
0..31
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
DATA Bus
32..63
CS#
A3_BA3
A2_BA0
A4_BA2
A5_BA1
WE#
A7_A8
A6_A11
ABI#
A12_RFU
A0_A10
A1_A9
RAS#
RST#
CKE#
CAS#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
3
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .
2011/11/01 2011/12
2011/11/01 2011/12
2011/11/01 2011/12
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
N12P-VRAM C Upper
N12P-VRAM C Upper
N12P-VRAM C Upper
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
31 65Tuesday, March 20, 2012
31 65Tuesday, March 20, 2012
31 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 32
5
4
3
2
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
B+
+5VS
+3VS_SLI
SLI_FAN_SPEED
SLI_FAN_PWM
S_DGPU_PWR_EN#
CLK2_REQ_GPU#_R
S_DGPU_RST
SLAVE_PRESENT#
PLT_RST#
GC6_EVENT_SLI#
GC6_SLI_EN
S_DGPU_PWR_EN
CLK_PCIE_2VGA#
CLK_PCIE_2VGA
1 2
RV234 0_0402_5%
RV234 0_0402_5%
NOGC6@
NOGC6@
SUSP# <45,51,55,57,58>
SLI_FAN_SPEED <41,45>
SLI_FAN_PWM <41,45>
VGA_AC_DET <23,45,58>
DGPU_PWROK <19,27,55,58>
S_DGPU_PWR_EN# <51>
CLK2_REQ_GPU#_R <15>
S_NVDD_PWR_EN <19>
S_DGPU_RST <15,18>
PCH_THRMTRIP#_R <19,23>
PLT_RST# <18,23,37,38,44,45,6>
EC_SMB_DA2 <15,23,40,45>
EC_SMB_CK2 <15,23,40,45>
S_DGPU_PWR_EN <19,51>
CLK_PCIE_2VGA# <15>
CLK_PCIE_2VGA <15>
1 2
RV173 0_0402_5%
RV173 0_0402_5%
GC6@
GC6@
1 2
RV158 0_0402_5%
RV158 0_0402_5%
@
@
GC6_EN <27>
GC6_EVENT# <19,23>
1
CV177
CV177
Close to SLI connector
2
0.01U_0402_25V7K
0.01U_0402_25V7K
SLAVE_PRESENT# <19>
follow MXM 3.0 spec
JSLI1
D D
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N10
C C
SLI@
SLI@
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N8
B B
PCIE_CRX_GTX_P8
12
CV200.22U_0402_10V6K
CV200.22U_0402_10V6K
SLI@
SLI@
12
CV220.22U_0402_10V6K
CV220.22U_0402_10V6K
SLI@
SLI@
12
CV160.22U_0402_10V6K
CV160.22U_0402_10V6K
SLI@
SLI@
12
CV180.22U_0402_10V6K
CV180.22U_0402_10V6K
SLI@
SLI@
12
CV190.22U_0402_10V6K
CV190.22U_0402_10V6K
SLI@
SLI@
12
CV140.22U_0402_10V6K
CV140.22U_0402_10V6K
SLI@
SLI@
12
CV150.22U_0402_10V6K
CV150.22U_0402_10V6K
SLI@
SLI@
12
CV170.22U_0402_10V6K
CV170.22U_0402_10V6K
SLI@
SLI@
12
CV120.22U_0402_10V6K
CV120.22U_0402_10V6K
12
CV130.22U_0402_10V6K SLI@ CV130.22U_0402_10V6K SLI@
SLI@
SLI@
12
CV100.22U_0402_10V6K
CV100.22U_0402_10V6K
12
CV110.22U_0402_10V6K SLI@ CV110.22U_0402_10V6K SLI@
12
CV80.22U_0402_10V6K SLI@ CV80.22U_0402_10V6K SLI@
12
CV90.22U_0402_10V6K
CV90.22U_0402_10V6K
SLI@
SLI@
SLI@
SLI@
12
CV60.22U_0402_10V6K
CV60.22U_0402_10V6K
SLI@
SLI@
12
CV70.22U_0402_10V6K
CV70.22U_0402_10V6K
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P8
PCIE_CRX_C_GTX_N15
PCIE_CRX_C_GTX_P15
PCIE_CRX_C_GTX_N14
PCIE_CRX_C_GTX_P14
PCIE_CRX_C_GTX_N13
PCIE_CRX_C_GTX_P13
PCIE_CRX_C_GTX_N12
PCIE_CRX_C_GTX_P12
PCIE_CRX_C_GTX_N11
PCIE_CRX_C_GTX_P11
PCIE_CRX_C_GTX_N10
PCIE_CRX_C_GTX_P10
PCIE_CRX_C_GTX_N9
PCIE_CRX_C_GTX_P9
PCIE_CRX_C_GTX_N8
PCIE_CRX_C_GTX_P8
JSLI1
1
GND
3
NC
5
NC
7
NC
9
NC
11
NC
13
NC
15
NC
17
GND
19
PEG_RX_N7
21
PEG_RX_P7
23
GND
25
PEG_RX_N6
27
PEG_RX_P6
29
GND
31
GND
33
PEG_RX_N5
35
PEG_RX_P5
37
GND
39
PEG_RX_N4
41
PEG_RX_P4
43
GND
45
PEG_RX_N3
47
PEG_RX_P3
49
GND
51
PEG_RX_N2
53
PEG_RX_P2
55
GND
57
PEG_RX_N1
59
PEG_RX_P1
61
GND
63
PEG_RX_N0
65
PEG_RX_P0
67
GND
69
GND
71
PEG_TX_N7
73
PEG_TX_P7
75
GND
77
PEG_TX_N6
79
PEG_TX_P6
81
GND
PEG_TX_N583PWR_GOOD
85
PEG_TX_P5
87
GND
89
PEG_TX_N4
91
PEG_TX_P4
93
GND
PEG_TX_N395TH_OVERT#
97
PEG_TX_P3
99
GND
101
PEG_TX_N2
103
PEG_TX_P2
105
GND
107
PEG_TX_N1
109
PEG_TX_P1
111
GND
113
PEG_TX_N0
115
PEG_TX_P0
117
GND
119
GND
121
GND
TE_PT11-FBB0-PC-021
TE_PT11-FBB0-PC-021
ME@
ME@
+19V
+19V
+19V
+19V
+19V
+19V
+19V
+19V
TH_TACH
TH_PWN
PEX_STD_SW#
AC_DC
PWR_EN
CLK_REQ#
RSVD
RSVD
RSVD
SMB_DAT
SMB_CLK
WAKE#
RSVD
RSVD
CLK_PCIE_N
CLK_PCIE_P
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+5V
+5V
+5V
+5V
+5V
NC
+3V
+3V
NC
NC
NC
NC
NC
NC
NC
NC
NC
11/11 for 2nd VGA fan
need to notic EC
A A
PCIE_CTX_GRX_N[0..15]<23,5>
PCIE_CTX_GRX_P[0..15]<23,5>
PCIE_CRX_GTX_N[0..15]<23,5>
PCIE_CRX_GTX_P[0..15]<23,5>
5
PCIE_CTX_GRX_N[0..15]
PCIE_CTX_GRX_P[0..15]
PCIE_CRX_GTX_N[0..15]
PCIE_CRX_GTX_P[0..15]
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
DDRIII-SODIMM SLOT1
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
32 65Tuesday, March 20, 2012
32 65Tuesday, March 20, 2012
32 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 33
5
@
RV92
RV92
45.3K_0402_ 1%
45.3K_0402_ 1%
D D
STRAP0<24>
STRAP1<24>
STRAP2<24>
STRAP3<24>
STRAP4<24>
C C
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
1 2
RV95
@RV9 5
@
45.3K_0402_ 1%
45.3K_0402_ 1%
1 2
Change STRAP1 to
"0000" for N13P-GT
@
RV93
RV93
4.99K_0402_ 1%
4.99K_0402_ 1%
1 2
RV96
RV96
4.99K_0402_ 1%
4.99K_0402_ 1%
1 2
@
@
RV94
RV94
10K_0402_1 %
10K_0402_1 %
1 2
RV97
RV97
10K_0402_1 %
10K_0402_1 %
1 2
+3VS_VGA
4
1 2
1 2
SLI@
SLI@
RV121
RV121
4.99K_0402_ 1%
4.99K_0402_ 1%
OPT@
OPT@
RV124
RV124
4.99K_0402_ 1%
4.99K_0402_ 1%
+3VS_VGA
RV122
RV122
20K_0402_1 %
20K_0402_1 %
@
@
1 2
RV125
RV125
45.3K_0402_ 1%
45.3K_0402_ 1%
1 2
3
Physical
Strapping pin
ROM_SCLK
ROM_SI
ROM_SO FB[0]
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
Resistor Values
Power Rail
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
Pull-up to
+3VS_VGA
5K
10K
15K
20K
25K
30K
35K
45K
Logical
Strapping Bit3
PCI_DEVID[4]
FB[1]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
SOR3_EXPOSED
RESERVED PCIE_SPEED_
Pull-down to Gnd
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
2
Logical
Strapping Bit2
SUB_VENDOR
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
CHANGE_GEN3
Logical
Strapping Bit1
SLOT_CLK_CFG
RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
3GIO_PAD_CFG_ADR[0]
PCIE_MAX_SPEED DP_PLL_VDD33V
SLOT_CLK_CFG
0
GPU and MCH don't share a common reference clock
1
GPU and MCH share a common reference clock (Default)
SUB_VENDOR
0
No VBIOS ROM (Default)
1
BIOS ROM is present
1
Logical
Strapping Bit0
PEX_PLL_EN_TERM
RAM_CFG[0]
VGA_DEVICESMB_ALT_ADDR
3GIO_PADCFG
RV100
RV98
RV98
4.99K_0402_ 1%
4.99K_0402_ 1%
@
@
1 2
ROM_SI<24>
ROM_SO<24 >
ROM_SCLK<24>
B B
ROM_SI
ROM_SO
ROM_SCLK
X76
RV101
RV101
30K_0402_1 %
30K_0402_1 %
X76@
X76@
1 2
RV99
RV99
10K_0402_1 %
10K_0402_1 %
1 2
RV102
RV102
30K_0402_1 %
30K_0402_1 %
@
@
1 2
RV100
24.9K_0402_ 1%
24.9K_0402_ 1%
1 2
RV100
RV100
4.99K_0402_1%
4.99K_0402_1%
RV103
RV103
15K_0402_1 %
15K_0402_1 %
@
@
1 2
SLI@
SLI@
OPT@
OPT@
3GIO_PADCFG[3:0]
0000
PEX_PLL_EN_TERM
0
Disable (Default)
1
Enable
SMBUS_ALT_ADDR
0
0x9E (Default)
1
0x9C (Multi-GPU usage)
Notebook Default
XCLK_417
0
277MHz (Default)
1
Reserved
PCIE_MAX_SPEED
0
Limit to PCIE Gen1
1
PCIE Gen 2/3 Capable
VGA_DEVICE
0
3D Device (Class Code 302h)
1
VGA Device (Default)
USER Straps
User[3:0]
1000-1100
Customer defined
FB_0_BAR_SIZE
0
Reserved
1
Reserved
2
256MB (Default)
3
Reserved
X76
GPU
N13P-GT1
28nm
Samsung
Hynix
A A
FB Memory (GDDR5)
K4G20325FD-FC04 2G 64Mx32
K4G10325FG-HC04 1G 32Mx32
H5GQ2H24MFR-T2C 2G 64Mx32
H5GQ1H24BFR-T2C 1G 32Mx32
5
ROM_SI ROM_SO ROM_SCLK STRAP0 STRAP1 STRAP2 STRAP3 STRAP4
PD 30K
PD 45K
PD 25K
PU 10K
PU 25K
(SLI)
PU 5K
(OPT)
PU 45K PD 5K PD 10K PU 5K PD 10K
PD 35K
Security Classification
Security Classification
Security Classification
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIA L
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMA TION. THIS SHEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CON SENT OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
VRAM
Samsung
Hynix
X76
X76409JVL01 (2G 64Mx32) SA00005B70J
X76409JVL02 (2G 64Mx32)
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SA00004GD0J
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
N13P_MISC
N13P_MISC
N13P_MISC
VRAM P/N
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
0.2
0.2
0.2
33 65Tuesday, March 2 0, 2012
33 65Tuesday, March 2 0, 2012
33 65Tuesday, March 2 0, 2012
Page 34
5
+LCDVDD_CONN
LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN
LVDS_ACLK#_CONN
LVDS_ACLK_CONN
D D
C C
B B
PCH
VGA
ECR_EN<45>
EDID_CLK<17>
VGA_EDID_CLK<23>
EDID_DATA<17>
VGA_EDID_DATA<23>
INVPWM
PCH_ENBKL<17>
VGA_ENBKL<23>
LVDS_ACLK#<17>
LVDS_ACLK<17>
LVDS_A0#<17>
LVDS_A0<17>
LVDS_A1#<17>
LVDS_A1<17>
LVDS_A2#<17>
LVDS_A2<17>
VGA_TXCLK-<24>
VGA_TXCLK+<24>
VGA_TXOUT0-<24>
VGA_TXOUT0+<24>
VGA_TXOUT1-<24>
VGA_TXOUT1+<24>
VGA_TXOUT2-<24>
VGA_TXOUT2+<24>
JLVDS1ME@JLVDS1ME@
112
334
556
778
9910
111112
131314
151516
171718
191920
212122
232324
252526
272728
292930
GND31GND
EDID_CLK
VGA_EDID_CLK
EDID_DATA
VGA_EDID_DATA
12
R1515
R1515
0_0402_5%
0_0402_5%
@
@
12
R824
R824
0_0402_5%
0_0402_5%
12
R847
@ R847
@
0_0402_5%
0_0402_5%
OPT@ R1212
OPT@
1 2
0_0402_5%
0_0402_5%
SLI@ R1201
SLI@
1 2
0_0402_5%
0_0402_5%
LVDS_ACLK#
LVDS_ACLK LVDS_ACLK_CONN
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
VGA_TXCLKVGA_TXCLK+
VGA_TXOUT0VGA_TXOUT0+
VGA_TXOUT1VGA_TXOUT1+
VGA_TXOUT2VGA_TXOUT2+
+LEDVDD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
1 2
R1210
R1210
0_0402_5%
0_0402_5%
OPT@
OPT@
1 2
R1199
R1199
0_0402_5% S LI@
0_0402_5% S LI@
1 2
R1211
R1211
0_0402_5%
0_0402_5%
OPT@
OPT@
1 2
R1200
R1200
0_0402_5% S LI@
0_0402_5% S LI@
EC_INVT_PWM <45>
VGA_BL_PWM <23>
PCH_PWM <17>
R1212
R1201
R827
R827
100K_0402_1%
100K_0402_1%
1 2
R1255 0_0402_5%OPT@R1 255 0_0402_5%OPT @
R1257 0_0402_5%OPT@R1 257 0_0402_5%OPT @
R1259 0_0402_5%OPT@R1 259 0_0402_5%OPT @
R1261 0_0402_5%OPT@R12 61 0_0402_5%OPT @
R1262 0_0402_5%OPT@R1 262 0_0402_5%OPT @
R1265 0_0402_5%OPT@R1 265 0_0402_5%OPT @
R1267 0_0402_5%OPT@R1 267 0_0402_5%OPT @
R1269 0_0402_5%OPT@R1 269 0_0402_5%OPT @
R1260 0_0402_5%
R1260 0_0402_5%
R1264 0_0402_5%
R1264 0_0402_5%
R1263 0_0402_5%S LI@R12 63 0_0402_5%SLI@
R1266 0_0402_5%SLI@R1266 0_0402_5%SLI@
R1268 0_0402_5%SLI@R1268 0_0402_5%SLI@
R1270 0_0402_5%SLI@R1270 0_0402_5%SLI@
R1271 0_0402_5%SLI@R1271 0_0402_5%SLI@
R1272 0_0402_5%SLI@R1272 0_0402_5%SLI@
W=60mils
INVPWM
EDID_DATA_CONN
EDID_CLK_CONN
ENBKL <45>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
SLI@
SLI@
1 2
SLI@
SLI@1 2
1 2
1 2
1 2
1 2
1 2
1 2
R822 4.7K_0402_5%
R822 4.7K_0402_5%
R891 0_0402_5%R891 0_0402_5%
EDID_CLK_CONN
EDID_DATA_CONN
4
470P_0603_50V8J
470P_0603_50V8J
9/23 EMI Request
@
@
12
12
+3VS
1
2
C1101
0.1U_0402_16V7K
C1101
0.1U_0402_16V7K
2.49K_0402_1%
2.49K_0402_1%
LVDS_ACLK#_CONN
LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN
LVDS_ACLK#_CONN
LVDS_ACLK_CONN
LVDS_A0#_CONN
LVDS_A0_CONN
LVDS_A1#_CONN
LVDS_A1_CONN
LVDS_A2#_CONN
LVDS_A2_CONN
2A 80 mil
C523
C523
REP@
REP@
BKOFF#DISPOFF#
R1569
1
2
C1102
C1102
USB30_RX_N1<18>
USB30_RX_P1<18>
USB30_TX_N1<18>
USB30_TX_P1<18>
1
2
0.01U_0402_16V7K
0.01U_0402_16V7K
12
1
2
+3VS
BKOFF# <45>
REP@
REP@
REP@R1569
REP@
1 2
C524
C524
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2A 80 mil
R813 0_0805_5%R813 0_0805_5%
USB30_RX_N1
USB30_RX_P1
USB30_TX_N1
USB30_TX_P1
B_EQ0
B_DE0
B_EQ1
B_DE1
B_INn
B_INp
A_OUTn
A_OUTp
PS8710BTQFN24GTR-A0_TQFN24_4X4
PS8710BTQFN24GTR-A0_TQFN24_4X4
B++LEDVDD
+3VS
1
@
@
680P_0402_50V7K
680P_0402_50V7K
C528
C528
2
3
Close to Pin23 Close to Pin8
R1565 0_0402_5%NOREP @R1565 0_0402_5%NOREP@
R1566 0_0402_5%NOREP @R1566 0_0402_5%NOREP@
R1567 0_0402_5%NOREP @R1567 0_0402_5%NOREP@
R1568 0_0402_5%NOREP @R1568 0_0402_5%NOREP@
U75
REP@U75
REP@
1
VDD
2
B_EQ0
3
I2C_R0
4
I2C_R1
5
PD#
6
B_DE1
7
REXT
8
B_INn
B_INp9SCL_CTL
10
GND
11
A_OUTn
12
A_OUTp
1 2
1 2
1 2
1 2
EPAD
12C_EN
B_OUTn
B_OUTp
GND
A_INn
A_INp
A_DE1
A_EQ0
SDA_CTL
TEST
VDD
B_EQ0
B_EQ1
B_DE0
B_DE1
A_EQ0
A_EQ1
A_DE0
A_DE1
TEST
25
24
23
22
21
20
19
18
17
16
15
14
13
R1571 4.7K_0402_5%REP@R1571 4.7K_0402 _5%REP@
R1573 4.7K_0402_5%REP@R1573 4.7K_0402 _5%REP@
R1575 4.7K_0402_5%@R1575 4.7K_0402_5%@
R1577 4.7K_0402_5%@R1577 4.7K_0402_5%@
R1570 4.7K_0402_5%REP@R1570 4.7K_0402_5%R EP@
R1572 4.7K_0402_5%REP@R1572 4.7K_0402_5%R EP@
R1574 4.7K_0402_5%@R1574 4.7K_0402_5%@
R1576 4.7K_0402_5%@R1576 4.7K_0402_5%@
R1578 4.7K_0402_5%@R1578 4.7K_0402_5%@
USB30_RX_N1_R
USB30_RX_P1_R
USB30_TX_N1_R
USB30_TX_P1_R
B_OUTn
B_OUTp
A_INn
A_INp
A_DE1
A_EQ0
A_DE0
A_EQ1
TEST
預預預預預預預預預預預預預預預預
1 2
1 2
1 2
1 2
預預預預預預預預預預預預預預預預
1 2
1 2
1 2
1 2
1 2
1 2
R1579 0_0402_5%NOREP @R1579 0_0402_5%NOREP@
1 2
R1580 0_0402_5%NOREP @R1580 0_0402_5%NOREP@
1 2
R1581 0_0402_5%NOREP @R1581 0_0402_5%NOREP@
1 2
R1582 0_0402_5%NOREP @R1582 0_0402_5%NOREP@
close to U75
+3VS
+3VS
2
CMOS Camera
+3VS
R435
R435
B_INn
B_INp
A_OUTn
A_OUTp
USB30_RX_N1
USB30_RX_P1
USB30_TX_N1
USB30_TX_P1
1 2
100K_0402_5%
100K_0402_5%
A_OUTn
A_OUTp
CMOS_ON#<45>
12
C11040.1U_0402_16V7K REP@ C11040.1U_0402_16V7K REP@
12
C11030.1U_0402_16V7K REP@ C11030.1U_0402_16V7K REP@
12
C11050.1U_0402_16V7K REP@ C11050.1U_0402_16V7K REP@
12
C11060.1U_0402_16V7K REP@ C11060.1U_0402_16V7K REP@
Equalizer control and program for channel B
3.3V tolerant. Internally pulled down at ~150KΩ
[B_EQ1, B_EQ0] ==
LL: adaptive EQ enable
LH: program EQ for channel loss up to 7dB
HL: program EQ for channel loss up to 14.5dB
**HH: program EQ for channel loss up to 11.5dB
*
Equalizer control and program for channel A
3.3V tolerant. Internally pulled down at ~150KΩ
[A_EQ1, A_EQ0] ==
LL: adaptive EQ enable
LH: program EQ for channel loss up to 7dB
HL: program EQ for channel loss up to 14.5dB
**HH: program EQ for channel loss up to 11.5dB
*
Chip test mode enable.
3.3V tolerant. Internally pulled down at ~150KΩ.
TEST ==
**L: Normal operation (default)
*
H: Test mode enable
(40 MIL)
C1051
CMOS@C1051
CMOS@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CMOS@
CMOS@
1
@
@
2
+CMOS_PW
For CMOS
C304 0.1U_0402_10V 6KCMOS@C304 0.1U_0402_10V 6KCMOS@
C303 0.1U_0402_10V 6KCMOS@C303 0.1U_0402_10V 6KCMOS@
Q94 AO3413_SOT23-3
Q94 AO3413_SOT23-3
D
S
D
S
13
+CMOS_PW_R
CMOS@
CMOS@
G
G
2
1
2
C520
C520
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1052
CMOS@C1052
CMOS@
0.01U_0402_16V7K
0.01U_0402_16V7K
2
0.047U_0402_16V4Z
0.047U_0402_16V4Z
W=40mils
USB20_N0<18>
USB20_P0<18>
+3VS
DMIC_CLK<42>
DMIC_DATA<42>
1 2
1 2
Programmable output pre-emphasis level setting for channel B
3.3V tolerant. Internally pulled down at ~150KΩ
[B_DE1, B_DE0] ==
**LL: 3.5dB de-emphasis
*
LH: No de-emphasis
HL: 7dB de-emphasis
HH: 5dB with boost output swing
Programmable output pre-emphasis level setting for channel A
3.3V tolerant. Internally pulled down at ~150KΩ
[A_DE1, A_DE0] ==
**LL: 3.5dB de-emphasis
*
LH: No de-emphasis
HL: 7dB de-emphasis
HH: 5dB with boost output swing
C58
C58
For RF request
@
@
12
USB20_N0
USB20_P0
B_INn
B_INp
A_OUTn_C
A_OUTp_C
1
2
1
R432
R432
0_0603_5%
0_0603_5%
1 2
CMOS@
CMOS@
CMOS@
CMOS@
C518
C518
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
+CMOS_PW
JCMOS1JCM OS1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND1
GND2
1
2
W=40mils
C519
10U_0603_6.3V6M@C519
10U_0603_6.3V6M
@
15
16
LCDVDD
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
A A
VGA_ENVDD<23>
PCH_ENVDD<17>
+LCDVDD_CONN
R816
R816
150_0603_1%
150_0603_1%
61
Q67A
Q67A
2
SLI@
SLI@
1 2
R1197 0_0402_5%
R1197 0_0402_5%
OPT@
OPT@
1 2
R1195 0_0402_5%
R1195 0_0402_5%
5
R1467
R1467
100K_0402_5%
100K_0402_5%
LCD_ENVDD#
100K_0402_5%
100K_0402_5%
+5VALW
+3VS +3VS
12
12
R817
R817
@
@
100K_0402_5%
100K_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R820
R820
1 2
100K_0402_5%
R821
R821
5
12
100K_0402_5%
3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Q67B
Q67B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
C1050
C1050
1
2
@
@
W=60mils
1
C530
C530
2
2
1
C1046
0.01U_0402_16V7K
C1046
0.01U_0402_16V7K
2
C531
C531
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4
G
G
S
S
Q68
Q68
AO3413_SOT23-3
AO3413_SOT23-3
D
D
1 3
1
2
W=60mils
1
C532
C532
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+LCDVDD_CONN
EMI request
@
@
1 2
DMIC_CLK
R1498
R1498
0_0402_5%
0_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
1
@
@
C934
C934
2
100P_0402_50V8J
100P_0402_50V8J
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
INVPWM
C525
C525
@
@
1
2
470P_0402_50V7K
470P_0402_50V7K
Compal Secret Data
Compal Secret Data
Compal Secret Data
DISPOFF#
@
@
1
C527
C527
2
470P_0402_50V7K
470P_0402_50V7K
Deciphered Date
Deciphered Date
Deciphered Date
ESD request
D28
D28
9
B_INn
10
10
8
B_INp
9
9
7
A_OUTn_C
7
7
6
A_OUTp_C
6 5
6 5
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
2
@
@
1
B_INn
1
1
2
B_INp
2
2
4
A_OUTn_C
4
4
5
A_OUTp_C
3
3
3
8
8
Date: Sheet of
Date: Sheet of
Date: Sheet of
D59
@D59
@
USB20_P0
+3VS
USB20_N0
Title
Title
Title
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
LVDS/ CMOS/ USB-ReDriver
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
4
I/O3
5
VDD
6
I/O4
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
GND
1
DMIC_DATA
I/O1
2
3
DMIC_CLK
I/O2
34 65Tuesday, March 20, 2012
34 65Tuesday, March 20, 2012
34 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 35
A
VGA_CRT _R<23 >
1 1
2 2
3 3
VGA_CRT _G<23>
VGA_CRT _B< 23>
DAC_RED<17>
DAC_GRN<17>
DAC_BLU<17>
VGA_CRT _R
VGA_CRT _G
VGA_CRT _B
DAC_RED
DAC_GRN
DAC_BLU
CRT_HSYNC<17>
VGA_CRT _HSYNC<2 3>
CRT_VSYNC<17>
VGA_CRT _VSYNC<23>
1 2
R1276 0_0 402_5%
R1276 0_0 402_5%
SLI@
SLI@
1 2
R1273 0_0 402_5%
R1273 0_0 402_5%
SLI@
SLI@
1 2
R1275 0_0 402_5%
R1275 0_0 402_5%
SLI@
SLI@
1 2
R1274 0_0 402_5%
R1274 0_0 402_5%
OPT@
OPT@
1 2
R1181 0_0 402_5%
R1181 0_0 402_5%
OPT@
OPT@
1 2
R1182 0_0 402_5%
R1182 0_0 402_5%
OPT@
OPT@
CRT_HSYNC HSYNC_G
VGA_CRT _HSYNC
CRT_VSYNC
VGA_CRT _VSYNC VSYNC_G
1 2
R1183 0_0 402_5%
R1183 0_0 402_5%
R1184 0_0 402_5%
R1184 0_0 402_5%
1 2
R1185 0_0 402_5%
R1185 0_0 402_5%
OPT@
OPT@
1 2
R1186 0_0 402_5%
R1186 0_0 402_5%
SLI@
SLI@
OPT@
OPT@
1 2
SLI@
SLI@
B
12
R830
R830
150_040 2_1%
150_040 2_1%
C
+5VS +5VS +5VS
3
2
@
@
D31
D31
BAT54S-7 -F_SOT23-3
BAT54S-7 -F_SOT23-3
DAC_RED _1
DAC_GRN _1
DAC_BLU _1
12
R831
R831
150_040 2_1%
150_040 2_1%
CLOSE TO CONN
C544
C544
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
C546
C546
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
+3VS
1
12
R832
R832
150_040 2_1%
150_040 2_1%
+CRT_VC C
1
2
+CRT_VC C
1
2
5
P
A2Y
G
3
5
P
A2Y
G
3
3
2
1
1
C537
C537
C538
C538
2
2
10P_040 2_50V8J
10P_040 2_50V8J
R833
R833
1 2
1K_0402 _5%
1K_0402 _5%
OE#
1
OE#
U24
U24
SN74AHC T1G125DCKR_S C70-5
SN74AHC T1G125DCKR_S C70-5
OE#
1
OE#
U25
U25
SN74AHC T1G125DCKR_S C70-5
SN74AHC T1G125DCKR_S C70-5
+CRT_VC C
4
CRT_HSYNC _1
4
CRT_VSYNC _1
10P_040 2_50V8J
10P_040 2_50V8J
3
1
@
@
D32
D32
BAT54S-7 -F_SOT23-3
BAT54S-7 -F_SOT23-3
1 2
L16 NBQ1005 05T-800Y_0402L16 NBQ1005 05T-800Y_0402
1 2
L17 NBQ1005 05T-800Y_0402L17 NBQ1005 05T-800Y_0402
1 2
L18 NBQ1005 05T-800Y_0402L18 NBQ1005 05T-800Y_0402
1
C539
C539
10P_040 2_50V8J
10P_040 2_50V8J
2
R840
R840
1 2
33_0603 _5%
33_0603 _5%
R839
R839
1 2
33_0603 _5%
33_0603 _5%
2
1
C540
C540
2
10P_040 2_50V8J
10P_040 2_50V8J
CRT_HSYNC _2
CRT_VSYNC _2
@
@
D33
D33
NBQ1005 05T-800Y_0402
NBQ1005 05T-800Y_0402
NBQ1005 05T-800Y_0402
NBQ1005 05T-800Y_0402
1
REDGREENBLUE
BAT54S-7 -F_SOT23-3
BAT54S-7 -F_SOT23-3
1
1
C541
C541
C542
C542
10P_040 2_50V8J
10P_040 2_50V8J
2
2
10P_040 2_50V8J
10P_040 2_50V8J
1 2
L19
L19
1 2
L20
L20
D
+5VS
T75 PADT75 PAD
RED
CRT_DDC _DAT_CONN
GREEN
JVGA_HS
BLUE
JVGA_VS
CRT_DDC _CLK_CONN
1
@
@
C545
C545
10P_040 2_50V8J
10P_040 2_50V8J
2
1
C547
@C 547
@
10P_040 2_50V8J
10P_040 2_50V8J
2
D36
D36
2 1
RB491D_ SC59-3
RB491D_ SC59-3
JVGA_HS
JVGA_VS
+CRT_VC C
F1
F1
0.5A_8V_ KMC3S050RY
0.5A_8V_ KMC3S050RY
W=40mils
CRT_TES T
CRT_DDC _CLK_CONN
CRT Connector
21
1
C543
C543
100P_04 02_50V8J
100P_04 02_50V8J
2
JVGA_VS
+CRT_VC C_CONN
1
C536
C536
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
2
JCRT1
JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
3
2
1
16
G
G
17
G
G
5
SUYIN_070546 HR015M22BZR
SUYIN_070546 HR015M22BZR
ME@
ME@
D8
D8
@
@
I/O2
GND
I/O1
AZC099-0 4S.R7G_SOT23-6
AZC099-0 4S.R7G_SOT23-6
E
I/O4
VDD
I/O3
6
JVGA_HS
5
4
CRT_DDC _DAT_CONN
+5VS
12
G
G
5
R837
R837
CRT_DDC _DATA<17>
CRT_DDC _CLK<17>
VGA_CRT _DATA<23>
VGA_CRT _CLK<23>
4 4
CRT_DDC _DATA
CRT_DDC _CLK
VGA_CRT _DATA
VGA_CRT _CLK
A
1 2
R1189 0_0402_5 %
R1189 0_0402_5 %
OPT@
OPT@
1 2
R1190 0_0402_5 %
R1190 0_0402_5 %
OPT@
OPT@
1 2
R1191 0_0402_5 %
R1191 0_0402_5 %
SLI@
SLI@
1 2
R1192 0_0402_5 %
R1192 0_0402_5 %
SLI@
SLI@
CRT_DDC _DATA_R
CRT_DDC _CLK_R
B
G
G
2
S
S
Q73A
Q73A
2N7002K DWH_SOT36 3-6
2N7002K DWH_SOT36 3-6
Security Class ification
Security Class ification
Security Class ification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
34
D
D
S
S
Q73B
Q73B
2N7002K DWH_SOT36 3-6
2N7002K DWH_SOT36 3-6
61
D
D
100P_04 02_50V8J
100P_04 02_50V8J
Issued Date
Issued Date
Issued Date
12
R838
R838
2.2K_040 2_5%
2.2K_040 2_5%
2.2K_0402_5%
2.2K_0402_5%
C548
C548
CRT_DDC _DAT_CONN
CRT_DDC _CLK_CONN
1
1
@
@
@
@
C549
C549
68P_040 2_50V8K
68P_040 2_50V8K
2
2
Compal Secret Data
Compal Secret Data
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
C
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
CRT Connector
CRT Connector
CRT Connector
Custom
Custom
Custom
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
0.2
0.2
0.2
35 65Tuesday, March 20, 2 012
35 65Tuesday, March 20, 2 012
35 65Tuesday, March 20, 2 012
E
Page 36
5
WCM-2 012-900T_4P
WCM-2 012-900T_4P
HDMI_CLK+ _CK
HDMI_CLK-_ CK
D D
C C
B B
HDMI_TX0+ _CK
HDMI_TX0-_ CK
HDMI_TX1+ _CK
HDMI_TX1-_ CK
HDMI_TX2+ _CK
HDMI_TX2-_ CK
HDMI_CLK+ _CONN
HDMI_CLK-_ CONN
HDMI_TX0+ _CONN
HDMI_TX0-_ CONN
HDMI_TX1+ _CONN
HDMI_TX1-_ CONN
HDMI_TX2+ _CONN
HDMI_TX2-_ CONN
R327
R327
680_040 2_1%
680_040 2_1%
OPT@
OPT@
R324
R324
4
4
1
1
L23
L23
L24
L24
1
1
4
4
WCM-2 012-900T_4P
WCM-2 012-900T_4P
WCM-2 012-900T_4P
WCM-2 012-900T_4P
4
4
1
1
L26
L26
L27
L27
1
1
4
4
WCM-2 012-900T_4P
WCM-2 012-900T_4P
+3VS
R326
R326
680_040 2_1%
680_040 2_1%
OPT@
OPT@
R323
R323
3
3
2
2
2
2
3
3
3
3
2
2
2
2
3
3
SLI@
SLI@
1 2
SLI@
SLI@
1 2
R321 4 99_0402_1%
R321 4 99_0402_1%
SLI@
SLI@
1 2
R322 499_040 2_1%
R322 499_040 2_1%
SLI@
SLI@
1 2
R323 499_04 02_1%
R323 499_04 02_1%
SLI@
SLI@
1 2
R324 499_ 0402_1%
R324 499_ 0402_1%
SLI@
SLI@
1 2
R325 499_0 402_1%
R325 499_0 402_1%
SLI@
SLI@
1 2
R326 499_040 2_1%
R326 499_040 2_1%
SLI@
SLI@
1 2
R327 499_0402 _1%
R327 499_0402 _1%
1 2
@
@
R328 100K_0 402_5%
R328 100K_0 402_5%
HDMI_CLK+ _CONN
HDMI_CLK-_ CONN
HDMI_TX0+ _CONN
HDMI_TX0-_ CONN
HDMI_TX1+ _CONN
HDMI_TX1-_ CONN
HDMI_TX2+ _CONN
HDMI_TX2-_ CONN
R320
R320
499_040 2_1%
499_040 2_1%
1 2
C1016 3.3P_0402 _50V8C
C1016 3.3P_0402 _50V8C
@
@
1 2
C1015 3.3P_0402 _50V8C
C1015 3.3P_0402 _50V8C
@
@
1 2
C1018 3.3P_0402 _50V8C
C1018 3.3P_0402 _50V8C
@
@
1 2
C1017 3.3P_0402 _50V8C
C1017 3.3P_0402 _50V8C
@
@
1 2
C1020 3.3P_0402 _50V8C
C1020 3.3P_0402 _50V8C
@
@
1 2
C1019 3.3P_0402 _50V8C
C1019 3.3P_0402 _50V8C
@
@
1 2
C1022 3.3P_0402 _50V8C
C1022 3.3P_0402 _50V8C
@
@
1 2
C1021 3.3P_0402 _50V8C
C1021 3.3P_0402 _50V8C
@
@
13
D
D
2
G
G
2N7002H 1N_SOT23-3
2N7002H 1N_SOT23-3
S
S
Q114
Q114
HDMI@
HDMI@
4
HDMIDAT_R
HDMICLK_R
3
1
TMDS_B_ HPD<17>
DGPU_HD MI_HPD<23>
2
D57
D57
PJSOT24 C 3P C/A SOT-23
PJSOT24 C 3P C/A SOT-23
@
@
VGA_HDM I_CLK-<24>
VGA_HDM I_CLK+<24>
VGA_HDM I_TX0-<24>
VGA_HDM I_TX0+<24>
VGA_HDM I_TX1-<24>
VGA_HDM I_TX1+<24>
VGA_HDM I_TX2-<24>
VGA_HDM I_TX2+<24>
R1486
0_0402_ 5%
0_0402_ 5%
3
1 2
L67
L67
@
@
VGA_HDM I_CLK
VGA_HDM I_DATA
R885
R885
20K_040 2_5%
20K_040 2_5%
12
@
@
VGA_HDM I_CLK<2 4>
HDMICLK<17>
VGA_HDM I_DATA<24>
HDMIDAT<1 7>
+3VS
R862
R862
1M_0402 _5%
1M_0402 _5%
1 2
OPT@R 1486
OPT@
R1499
R1499
0_0402_ 5%
0_0402_ 5%
SLI@
SLI@
1 2
R859
R859
1K_0402 _5%
1K_0402 _5%
12
R864
R864
@
@
100K_0402_5%
100K_0402_5%
VGA_HDM I_CLK- HDMI_CL K-_CK
VGA_HDM I_CLK+ HDMI_CLK+ _CK
VGA_HDM I_TX0-
VGA_HDM I_TX0+
VGA_HDM I_TX1-
VGA_HDM I_TX1+
VGA_HDM I_TX2-
VGA_HDM I_TX2+
G
G
2
1 2
S
S
for NV recommend
@
@
12
Q85
Q85
13
D
D
2N7002_ SOT23
2N7002_ SOT23
HDMI_DET_ R
CV254 0.1U_0 402_10V6KSLI@ CV254 0.1U_ 0402_10V6KSLI@
CV253 0.1U_0 402_10V6KSLI@ CV253 0.1U_ 0402_10V6KSLI@
CV256 0.1U_0 402_10V6KSLI@ CV256 0.1U_ 0402_10V6KSLI@
CV255 0.1U_0 402_10V6KSLI@ CV255 0.1U_ 0402_10V6KSLI@
CV258 0.1U_0 402_10V6KSLI@ CV258 0.1U_ 0402_10V6KSLI@
CV257 0.1U_0 402_10V6KSLI@ CV257 0.1U_ 0402_10V6KSLI@
CV260 0.1U_0 402_10V6KSLI@ CV260 0.1U_ 0402_10V6KSLI@
CV259 0.1U_0 402_10V6KSLI@ CV259 0.1U_ 0402_10V6KSLI@
BLM18PG 181SN1D_0603
BLM18PG 181SN1D_0603
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
HDMICLK
HDMIDAT
R1473 0_0 402_5%OPT@R1 473 0_04 02_5%OPT@
1
C59
C59
220P_04 02_25V8J
220P_04 02_25V8J
2
HDMI_TX0-_ CK
HDMI_TX0+ _CK
HDMI_TX1-_ CK
HDMI_TX1+ _CK
HDMI_TX2-_ CK
HDMI_TX2+ _CK
2
1 2
R1470 0_0 402_5%SLI@R1470 0_04 02_5%SLI@
1 2
R1471 0_0 402_5%OPT@R1 471 0_04 02_5%OPT@
1 2
R1472 0_0 402_5%SLI@R1472 0_04 02_5%SLI@
1 2
+5VS
3
R866 0_040 2_5%@R866 0_ 0402_5%@
R865 0_040 2_5%@R865 0_ 0402_5%@
R868 0_040 2_5%@R868 0_ 0402_5%@
R867 0_040 2_5%@R867 0_ 0402_5%@
R870 0_040 2_5%@R870 0_ 0402_5%@
R869 0_040 2_5%@R869 0_ 0402_5%@
R872 0_040 2_5%@R872 0_ 0402_5%@
R871 0_040 2_5%@R871 0_ 0402_5%@
2
@
@
1
D38
D38
BAT54S-7 -F_SOT23-3
BAT54S-7 -F_SOT23-3
HDMI_DET
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R1468
R1468
0_0402_ 5%
0_0402_ 5%
OPT@
OPT@
3 1
BSH111_ SOT23-3
BSH111_ SOT23-3
+3VS_VG A
+3VS
R1469
R1469
0_0402_ 5%
0_0402_ 5%
SLI@
SLI@
1 2
1 2
BSH111_ SOT23-3
BSH111_ SOT23-3
2
3 1
SGD
SGD
2
SGD
SGD
Q80
Q80
HDMI@
HDMI@
PMEG2010AEH
IF=0.1A, 0.29V
IF=1A, 0.43V
R860
R860
2.2K_040 2_5%
2.2K_040 2_5%
HDMI@
HDMI@
1 2
HDMIDAT_R
HDMICLK_R
HDMI_CLK-_ CONN
HDMI_CLK+ _CONN
HDMI_TX0-_ CONN
HDMI_TX0+ _CONN
HDMI_TX1-_ CONN
HDMI_TX1+ _CONN
HDMI_TX2-_ CONN
HDMI_TX2+ _CONN
Q152
Q152
HDMI@
HDMI@
HDMICLK_R
HDMIDAT_R
+5VS
21
21
+5VS_HD MI
R861
R861
2.2K_040 2_5%
2.2K_040 2_5%
HDMI@
HDMI@
1 2
TAITW_ PDVBR0-19FLBS 4NN4N0
TAITW_ PDVBR0-19FLBS 4NN4N0
1
HDMI@
HDMI@
D37
D37
PMEG201 0AEH_SOD123
PMEG201 0AEH_SOD123
HDMI@
HDMI@
F2
F2
0.5A_8V_ KMC3S050RY
0.5A_8V_ KMC3S050RY
C561
C561
1
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
HDMI@
HDMI@
2
JHDMI1
JHDMI1
19
HP_DET
18
+5V
17
DDC/CEC_GND
16
SDA
15
SCL
14
Reserved
13
CEC
12
CKCK_shield
CK+
D0D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
ME@
ME@
GND
GND
GND
GND
11
10
9
8
7
6
5
4
3
2
1
20
21
22
23
680_040 2_1%
5
680_040 2_1%
OPT@
OPT@
R320
R320
680_040 2_1%
680_040 2_1%
OPT@
OPT@
R322
R322
680_040 2_1%
680_040 2_1%
OPT@
OPT@
TMDS_B_ DATA2#_PCH<17>
TMDS_B_ DATA2_PCH<1 7>
TMDS_B_ DATA1#_PCH<17>
TMDS_B_ DATA1_PCH<1 7>
TMDS_B_ DATA0#_PCH<17>
TMDS_B_ DATA0_PCH<1 7>
TMDS_B_ CLK#_PCH<17 >
TMDS_B_ CLK_PCH<17>
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
TMDS_B_ DATA2#_PCH
TMDS_B_ DATA2_PCH
TMDS_B_ DATA1#_PCH
TMDS_B_ DATA1_PCH
TMDS_B_ DATA0#_PCH
TMDS_B_ DATA0_PCH
TMDS_B_ CLK#_PCH
TMDS_B_ CLK_PCH
Compal Secret Data
Compal Secret Data
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1 2
C200 0 .1U_0402_10V6 KOPT@ C200 0.1U_0402_10V 6KOPT@
1 2
C201 0 .1U_0402_10V6 KOPT@ C201 0.1U_0402_10V 6KOPT@
1 2
C203 0 .1U_0402_10V6 KOPT@ C203 0.1U_0402_10V 6KOPT@
1 2
C206 0 .1U_0402_10V6 KOPT@ C206 0.1U_0402_10V 6KOPT@
1 2
C204 0 .1U_0402_10V6 KOPT@ C204 0.1U_0402_10V 6KOPT@
1 2
C205 0 .1U_0402_10V6 KOPT@ C205 0.1U_0402_10V 6KOPT@
1 2
C208 0 .1U_0402_10V6 KOPT@ C208 0.1U_0402_10V 6KOPT@
1 2
C207 0 .1U_0402_10V6 KOPT@ C207 0.1U_0402_10V 6KOPT@
2
HDMI_TX2-_ CK
HDMI_TX2+ _CK
HDMI_TX1-_ CK
HDMI_TX1+ _CK
HDMI_TX0-_ CK
HDMI_TX0+ _CK
HDMI_CLK-_ CK
HDMI_CLK+ _CK
Compal Electronics,Ltd.
Compal Electronics,Ltd.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics,Ltd.
HDMI CONN
HDMI CONN
HDMI CONN
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
46@
46@
HDMI+HDCP
HDMI+HDCP
1
of
36 65Tuesday, March 20, 2 012
36 65Tuesday, March 20, 2 012
36 65Tuesday, March 20, 2 012
0.2
0.2
0.2
680_040 2_1%
680_040 2_1%
OPT@
OPT@
R321
R321
680_040 2_1%
680_040 2_1%
OPT@
OPT@
R325
A A
R325
680_040 2_1%
680_040 2_1%
OPT@
OPT@
Page 37
A
B
C
D
E
Mini-Express Card for WLAN/WiMAX(Half)
Mini-Express Card for SSD(Full)
+3VS_WLAN
C57
C57
0.047U_0402_16V4Z
0.047U_0402_16V4Z
For RF request
+1.5VS
12
R400
R400
0_0603_5%
0_0603_5%
R1541 0_0402_5%@R1541 0_0402_5%@
1 2
R880 0_0402_5%R880 0_0402_5%
1 2
R881 0_0402_5%@R881 0_0402_5%@
1 2
R882 0_0402_5%R882 0_0402_5%
1 2
R883 0_0402_5%@R883 0_0402_5%@
1 2
R884 0_0402_5%@R884 0_0402_5%@
USB20_N10 <18>
USB20_P10 <18>
AOAC_ON#<51>
+1.5VS
1
C564
C564
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
12
PLT_RST#
AOAC@
AOAC@
+3VALW
+3VS_WLAN
R436
R436
1 2
100K_0402_5%
100K_0402_5%
EC_WL_OFF# <45>
PCH_WL_OFF# <18>
PLT_RST# <18,23,32,38,44,45,6>
SMB_CLK_S3 <12,13,15,46>
SMB_DATA_S3 <12,13,15,46>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
softstart (RC) will check on EVT PCB
9/18 JP1 Pin2,24,52 contact t o +3VS_WLAN for AOAC function
1 1
BT on module
Disable
L
H
2
G
G
COMBT@
COMBT@
PCIE_WAKE#<16,19, 38>
WLAN_CLKREQ1#<15>
61
D
D
S
S
COMBT@
COMBT@
1 2
R897 0_0402_5%
R897 0_0402_5%
1 2
BT_DISABLE#
R1556
R1556
1K_0402_5%
1K_0402_5%
COMBT@
For isolate Intel Rainbow Peak and
Compal debug card.
2 2
WLAN&BT Combo m odule circuits
BT_CRTL
PCH_BT_ON#
PCH_BT_DISABLE#<19>
COMBT@
BT on module
Enable
H
L
R1557
R1557
0_0402_5%
0_0402_5%
1 2
@
@
PCH_BT_ON#<19,47> SUSP <10,51,55,57>
Mini-Express Card(WLAN/WiMAX)
PCIE_WAKE#
BT_CTRL_RBT_CTRL
WLAN_CLKREQ1#
CLK_PCIE_WLAN1#<15>
BT_CTRL
Q157A
Q157A
CLK_PCIE_WLAN1<15>
PCIE_PRX_DTX_N2<15>
PCIE_PRX_DTX_P2<15>
PCIE_PTX_C_DRX_N2<15>
PCIE_PTX_C_DRX_P2<15>
EC_TX<45>
EC_RX<45>
34
D
D
Q157B
Q157B
S
S
EC_TX
EC_RX
For EC to detect
debug card insert.
5
G
G
COMBT@
COMBT@
PCI_RST#_R
CLK_PCI_DB
100_0402_1%
100_0402_1%
R887
R887
1 2
1 2
R888
R888
100_0402_1%
100_0402_1%
+3VS_WLAN
R889
R889
100K_0402_5%
100K_0402_5%
1 2
BT_DISABLE#
JWLN1
JWLN1
1
WAKE#
3
NC
5
NC
7
CLKREQ#
9
GND
11
REFCLK-
13
REFCLK+
15
GND
17
NC
19
NC
21
GND
23
PERn0
25
PERp0
27
GND
29
GND
31
PETn0
SMB_DATA
33
PETp0
35
GND
37
NC
39
NC
41
NC
LED_WWAN#
43
NC
LED_WLAN#
45
NC
LED_WPAN#
47
NC
49
NC
51
NC
53
GND
TAITW_PFPET0-AFGLBG1ZZ4N0
TAITW_PFPET0-AFGLBG1ZZ4N0
ME@
ME@
PERST#
+3.3Vaux
+1.5V
SMB_CLK
USB_D-
USB_D+
+1.5V
+3.3V
2
3.3V
4
GND
6
1.5V
8
NC
10
NC
12
NC
14
NC
16
NC
18
GND
20
NC
22
24
26
GND
28
30
32
34
GND
36
38
40
GND
42
44
46
48
50
GND
52
54
GND
1
@
@
2
+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
WL_OFF#
SMB_CLK_S3_R
SMB_DATA_S3_R
Reserve for SW mini-pcie debug card.
Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB
1
C565
C565
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+3VS
J8
J8
112
JUMP_43X79
C526
C526
Q104
Q104
AO3413_SOT23-3
AO3413_SOT23-3
1
AOAC@
AOAC@
2
1
@
@
C1055
C1055
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
JUMP_43X79
S
S
+3VALW
AOAC@
AOAC@
G
G
2
R873 0_0402_5%@R873 0_0402_5%@
R874 0_0402_5%@R874 0_0402_5%@
R875 0_0402_5%@R875 0_0402_5%@
R876 0_0402_5%@R876 0_0402_5%@
R878 0_0402_5%@R878 0_0402_5%@
R879 0_0402_5%@R879 0_0402_5%@
@
@
2
D
D
13
C1048
C1048
AOAC@
AOAC@
1 2
1 2
1 2
1 2
1 2
1 2
+3VS_WLAN
1
1
2
0.01U_0402_25V7K
0.01U_0402_25V7K
2
AOAC@
AOAC@
C533
C533
0.1U_0402_16V4Z
0.1U_0402_16V4Z
9/18 Increase for Intel AOAC f unction
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
PLT_RST#
LPC_FRAME# <14,45>
LPC_AD3 <14,45>
LPC_AD2 <14,45>
LPC_AD1 <14,45>
LPC_AD0 <14,45>
CLK_PCI_DB <18>
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
3 3
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C566
C566
2
0.01U_0402_25V7K
0.01U_0402_25V7K
SATA_DTX_C_IRX_P0<14>
SATA_DTX_C_IRX_N0<14>
SATA_ITX_DRX_N0<14>
SATA_ITX_DRX_P0<14>
4 4
SATA_DET#<14>
For SSD use:
A
Mini-Express Card(SSD)
+3VS_SSD
1
C567
C567
2
10U_0805_10V6K
10U_0805_10V6K
0.01U_0402_16V7K
SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0 SATA_DTX_IRX_N0
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
SATA_DET#
R896 0_0402_5%
R896 0_0402_5%
1
C568
C568
2
12
C572
C572
12
C573
C573
1 2
@
@
10U_0805_10V6K
10U_0805_10V6K
1
@
@
C569
C569
2
SATA_DTX_IRX_P0
+3VS_SSD
SSD Active:4.5W(1.5A)
112
+3VS_SSD
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Mini-Card
Mini-Card
Mini-Card
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
E
37 65Tuesday, March 20, 2012
37 65Tuesday, March 20, 2012
37 65Tuesday, March 20, 2012
0.2
0.2
0.2
+3VS
J5
J5
JUMP_43X79
JUMP_43X79
@
JSSD1
JSSD1
1
WAKE#
3
NC
5
NC
7
CLKREQ#
9
GND
11
REFCLK-
13
REFCLK+
15
GND
17
NC
19
NC
21
GND
23
PERn0
25
PERp0
27
GND
29
GND
31
PETn0
33
PETp0
35
GND
37
NC
39
NC
41
NC
43
NC
45
NC
47
NC
49
NC
51
NC
53
GND
ME@
ME@
B
@
3.3V
GND
1.5V
NC
NC
NC
NC
NC
GND
NC
PERST#
+3.3Vaux
GND
+1.5V
SMB_CLK
SMB_DATA
GND
USB_DUSB_D+
GND
LED_WWAN#
LED_WLAN#
LED_WPAN#
+1.5V
GND
+3.3V
GND
TAITW_PFPET0-AFGLBG1ZZ4N0
TAITW_PFPET0-AFGLBG1ZZ4N0
Page 38
5
Atheros request can't disable LAN power
Layout Notice : Place as close
chip as possible.
D D
LAN_PWR_ON#<45>
Vendor recommand reseve the
PU resistor close LAN chip
+3V_LAN
PLT_RST#<18,23,32,37,44,45,6>
C C
B B
A A
PCIE_PRX_DTX_N1<15>
PCIE_PRX_DTX_P1<15>
PCIE_PTX_C_DRX_N1<15>
PCIE_PTX_C_DRX_P1< 15>
CLK_PCIE_LAN#<15>
CLK_PCIE_LAN<15>
PCIE_WAKE#< 16,19,37>
LAN_WAKE#<45>
CLKREQ_LAN#<15>
1
C956
C956
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Pin13
5
LAN_PWR_ON#
1 2
R345 4.7K_0402_5%
R345 4.7K_0402_5%
@
@
Place Close to Chip
1 2
C946 0.1U_0402_16V7KC 946 0.1U_0402_16V7K
1 2
C947 0.1U_0402_16V7KC 947 0.1U_0402_16V7K
@
@
1 2
R1369 0_0402_5%
R1369 0_0402_5%
1 2
R1370 0_0402_5%R1370 0_040 2_5%
1
1
C957
C957
C958
C958
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Near
Pin19
Pin31
100K_0402_5%
100K_0402_5%
+3VALW
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R59
R59
12
PLT_RST#
PCIE_PRX_C_DTX_N1
PCIE_PRX_C_DTX_P1
PLT_RST#
PCIE_WAKE#_R
LAN_XTALO
LAN_XTALI
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL
+1.1_AVDDL_L
+1.1_AVDDL
1
C960
C960
C959
C959
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Near
Pin6
C552
C552
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15P_0402_50V8J
15P_0402_50V8J
Change C968, C969 value of Cap from 33pF to 15pF
for TXC recommend
4
J10
J10
2
112
@
@
JUMP_43X79
JUMP_43X79
Q70
Q70
D
S
D
S
13
G
G
1
LP2301ALT1G_SOT-23
LP2301ALT1G_SOT-23
2
2
1
C1056
C1056
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
U63
U63
29
TX_N
30
TX_P
36
RX_N
35
RX_P
32
REFCLK_N
33
REFCLK_P
2
PERST#
3
WAKE#
25
SMCLK
26
SMDATA
28
NC
27
TESTMODE
7
XTLO
8
XTLI
4
CLKREQ#
13
AVDDL
19
AVDDL
31
AVDDL
34
AVDDL
6
AVDDL_REG/AVDDL
41
GND
AR8161-AL3A-R_QFN40_5X5
AR8161-AL3A-R_QFN40_5X5
8161@
8161@
4
1
1
25MHZ_12PF_X3G025000DC1H~D
25MHZ_12PF_X3G025000DC1H~D
C968
C968
2
4
+3V_LAN
1
C1047
C1047
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Atheros
Atheros
AR8151/AR8161
AR8151/AR8161
DVDDL_REG/DVDD L
U63
U63
SA00003LE20
SA00003LE20
8151@
8151@
Y6
Y6
NC
OSC
OSC
NC
LED_0
LED_1
LED_2
TRXN0
TRXP0
TRXN1
TRXP1
TRXN2
TRXP2
TRXN3
TRXP3
RBIAS
VDD33
VDDCT/ISOLAN
DVDDL/PPS
AVDDH/AVDD33
AVDDH
AVDDH_REG
3
2
1
2
38
ACTIVITY#
39
LAN_LINK#
23
LAN_CLK_SEL
12
MDI0-
11
MDI0+
15
MDI1-
14
MDI1+
18
MDI2-
17
MDI2+
21
MDI3-
20
MDI3+
10
LAN_RBIAS
1
+3V_LAN
40
+LX
LX
5
+1.7_VDDCT
24
37
+1.1_DVDDL
16
22
+2.7_AVDDH
9
+2.7_AVDDH
Near
Pin9
LAN_XTALI
LAN_XTALO
C969
C969
15P_0402_50V8J
15P_0402_50V8J
+1.7_VDDCT
R1356 0_0402_5%8151@R1356 0_0402_5%81 51@
1 2
R1357 0_0402_5%8161@R1357 0_0402_5%81 61@
1 2
+1.1_DVDDL
R58
R58
1 2
R1371 2 .37K_0402_1%R1371 2.37K_0402_1%
Place Close to PIN10
R1372 30K_0402_5%8161@R1372 30K_0402_5%8161@
+LX
R1366 0_0402_5%
R1366 0_0402_5%
+AVDDH_AVDD3.3
1
1
C962
C962
C963
C961
C961
2
C963
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Pin22
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
H --> Overclocking mode
L --> Not overclocking mode
12
10K_0402_5%@
10K_0402_5%@
MDI0- <39>
MDI0+ <39>
MDI1- <39>
MDI1+ <39>
MDI2- <39>
MDI2+ <39>
MDI3- <39>
MDI3+ <39>
1 2
8151@
8151@
1 2
C955 0.1U_0402_16V4Z
C955 0.1U_0402_16V4Z
1 2
8151@
8151@
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Pin37
Issued Date
Issued Date
Issued Date
3
Close together
L74
L74
+LX_R +LX
C935
C936
C936
@ C935
@
1000P_0402_50V7K
1000P_0402_50V7K
Close to
Pin40
ACTIVITY# <39>
LAN_LINK# <39>
1 2
4.7UH_SIA4012-4R7M_20%
4.7UH_SIA4012-4R7M_20%
1
1
C937
C937
Note: Place Close to LAN chip
L39 DCR< 0.15 ohm
2
2
Rate current > 1A
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+LX
2011103 for ven dor comment
Place Close to PIN1
1
2
C952
C952
C951
C951
1U_0402_6.3V4Z
1U_0402_6.3V4Z
10U_0805_10V4Z
10U_0805_10V4Z
Deciphered Date
Deciphered Date
Deciphered Date
1
2
1
@
@
+3VS
+1.1_DVDDL+1.1_DVDDL_R
1
1
C964
C964
C965
C965
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Near
Pin24
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
1 2
2
C950
C950
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_50V7K
1000P_0402_50V7K
2
C966
C966
8151@
8151@
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
For AR8151: Stuff C966,R1366
For AR8161: NC
Compal Secret Data
Compal Secret Data
Compal Secret Data
+3V_LAN
C953
C953
10U_0805_10V4Z
10U_0805_10V4Z
2
LX Voltage
<Pin 40>
AR8151
AR8161
+1.7V
<VDDCT>
+1.1V
<DVDDL,AVDDL>
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
1
C980
C980
C967
C967
2
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
1
C278
C278
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
L75
L75
R1356,C955
R1357,R1372,L76
1
Configure
L76
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
L76
1 2
8161@
8161@
+1.1_DVDDL+1.1_AVDDL+1.1_AVDDL_L
Place close to Pin34
Place Close to LAN chip
49.9_0402_1%8151@
49.9_0402_1%8151@
R1358
R1358
R1359
R1359
R1360
R1360
R1361
R1361
R1362
R1362
R1363
R1363
R1364
R1364
R1365
R1365
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
49.9_0402_1%8151@
49.9_0402_1%8151@
1 2
MDI0+
MDI0-
MDI1+
MDI1-
1
@C954
@
2
C954
MDI2+
MDI2-
MDI3+
MDI3-
Note : C938, C940, C942, 944, reserved for EMI.
For AR8151: Stuff 49.9K and 0.1u
For AR8161: NC
+AVDDH_AVDD3.3 +2.7_AVDDH
1
C948
C948
2
Place close to Pin16
For AR8151: Stuff R1368 for +AVDD3.3
For AR8161: Stuff R1367,C949 for +AVDDH
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
2
Date: Sheet of
1 2
C938 1000P_0402_50V7K@ C938 1000P_0402_50V7K@
8151@
8151@
1 2
C939 0.1U_0402_16V4Z
C939 0.1U_0402_16V4Z
1 2
C940 1000P_0402_50V7K@ C940 1000P_0402_50V7K@
8151@
8151@
1 2
C941 0.1U_0402_16V4Z
C941 0.1U_0402_16V4Z
1 2
C942 1000P_0402_50V7K@ C942 1000P_0402_50V7K@
8151@
8151@
1 2
C943 0.1U_0402_16V4Z
C943 0.1U_0402_16V4Z
1 2
C944 1000P_0402_50V7K@ C944 1000P_0402_50V7K@
8151@
8151@
1 2
C945 0.1U_0402_16V4Z
C945 0.1U_0402_16V4Z
8161@
8161@
1 2
R1367 0_0402_5%
R1367 0_0402_5%
8151@
8151@
1 2
R1368 0_0402_5%
R1368 0_0402_5%
1
C949
C949
8161@
8161@
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LAN-AR8151/8161
LAN-AR8151/8161
LAN-AR8151/8161
Tuesday, March 20, 2012
Tuesday, March 20, 2012
Tuesday, March 20, 2012
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
+3V_LAN
+2.7_AVDDH
of
38 65
38 65
38 65
0.2
0.2
0.2
Page 39
5
4
3
2
1
+1.7_VDDCT
D D
C C
8151@
8151@
R1373
R1373
0_0603_5%
0_0603_5%
6/23 update
12
1
C976
C976
@
@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
C970
C970
8161S@
8161S@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C974
C974
8161S@
8161S@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.7_VDDCT_R
C972
C972
8161S@
8161S@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C975
C975
8161S@
8161S@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C970
C970
8151@
8151@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C972
C972
8151@
8151@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C974
C974
8151@
8151@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C975
C975
8151@
8151@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
Place close to T49(TCT) pin
MDI3+<38>
MDI3-<38>
MDI2+<38>
MDI2-<38>
MDI1+<38>
MDI1-<38>
MDI0+<38>
MDI0-<38>
MDI3+
MDI3-
MDI2+
MDI2-
MDI1+
MDI1-
MDI0+
MDI0-
10
11
12
T49
T49
1
TCT1
2
TD1+
3
TD1-
4
TCT2
5
TD2+
6
TD2-
7
TCT3
8
TD3+
9
TD3-
TCT4
TD4+
TD4-
NS892402 1G
NS892402 1G
LAN Transformer
1:1
1:1
1:1
1:1
1:1
1:1
1:1
1:1
MCT1
MX1+
MX1-
MCT2
MX2+
MX2-
MCT3
MX3+
MX3-
MCT4
MX4+
MX4-
R1374
24
MCT3
23
MDO3+
22
MDO3-
21
MCT2
20
MDO2+
19
MDO2-
18
MCT1
17
MDO1+
16
MDO1-
15
MCT0
14
MDO0+
13
MDO0-
R1374
0_0402_5%
0_0402_5%
R1375
R1375
0_0402_5%
0_0402_5%
R1377
R1377
0_0402_5%
0_0402_5%
R1376
R1376
0_0402_5%
0_0402_5%
12
12
12
12
If vendor test result is "ok", need to change as below
1. Change R1374,R1375,R1376,R1377 to 0 ohm
2. Change R1194 to 75 ohm
3. Mount F6
4. Un mount F3,F4,F5
--> 2012/02/20 : already implement to Sch
BOM option:
1. For GDTx4
R1374/R1375/R13 76/R1377=75 oh m
R1194=0 ohm
MCT0~3=Mount
2. For GDTx1
R1374/R1375/R13 76/R1377=0 ohm
R1194=75 ohm
MCT0=Mount
MCT1~3=Mount
12
R1194
R1194
75_0402_5%
75_0402_5%
1
C973
C973
10P_1206_2KV7K
10P_1206_2KV7K
2
Place Close to T49
D68
8151S@D68
8151S@
MDI2-
B B
MDI2+
MDI0-
MDI0+
1
2
3
4
1
2
3
4
10
1
10
9
2
9
8
3
8
7
4
7
6
556
GND
11
TCLAMP3302N.TCT_SLP2626P10-10
TCLAMP3302N.TCT_SLP2626P10-10
R02
D67
8151S@D67
8151S@
10
1
10
9
2
9
8
3
8
7
4
7
6
556
GND
11
TCLAMP3302N.TCT_SLP2626P10-10
TCLAMP3302N.TCT_SLP2626P10-10
R02
MDI3+
MDI3-
MDI1+
MDI1-
Place Close to T49
MCT3
MCT2
MCT1
MCT0
F6
F6
SURGE@
SURGE@
1 2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
Reserve for EMI go rural solu tion
SURGE@
SURGE@
LAN Conn.
JRJ1
ME@JRJ1
ME@
C978
C979
LAN_LINK#
1
@C978
@
2
ACTIVITY#
1
@C979
@
2
+3V_LAN
+3V_LAN
R1378
R1378
220_0402_5%
220_0402_5%
R1442
R1442
220_0402_5%
220_0402_5%
12
12
LAN_LINK#<38>
470P_0402_50V7K
470P_0402_50V7K
F3
F3
1 2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
SURGE@
SURGE@
F4
F4
1 2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
SURGE@
SURGE@
F5
F5
1 2
LSE-200NX3216TRLF_1206-2
LSE-200NX3216TRLF_1206-2
ACTIVITY#<38>
470P_0402_50V7K
470P_0402_50V7K
MDO0+
MDO0-
MDO1+
MDO2+
MDO2-
MDO1-
MDO3+
MDO3-
9
Green LED-
10
Green LED+
1
PR1+
2
PR1-
3
PR2+
4
PR3+
5
PR3-
6
PR2-
7
PR4+
8
PR4-
11
Yellow LED-
12
Yellow LED+
SANTA_130456-111
SANTA_130456-111
14
G2
13
G1
Reserve D67,D68 for EMI go ru ral solution
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LAN Transformer
LAN Transformer
LAN Transformer
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
39 65Tuesday, March 20, 2012
39 65Tuesday, March 20, 2012
39 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 40
5
4
3
2
1
D D
C C
B B
Close U29
C449
C449
2200P_0 402_50V7K
2200P_0 402_50V7K
C658
C658
2200P_0 402_50V7K
2200P_0 402_50V7K
1
2
1
2
REMOTE1 +
REMOTE1 -
REMOTE2 +
REMOTE2 -
+3VS
Remove +VDD netname
2
C443
C443
0.1U_040 2_16V4Z
0.1U_040 2_16V4Z
1
FAN_PWM & TACH
for PWM FAN
REMOTE1 +
REMOTE1 -
REMOTE2 +
REMOTE2 -
SMSC thermal sensor
placed near by VRAM
U29
U29
1
VDD
2
DP1
3
DN1
4
DP2
5
DN2
EMC1403 -2-AIZL-TR_MSOP10
EMC1403 -2-AIZL-TR_MSOP10
Address 1001_101xb
internal pull up 1.2K to 1.5V
R for initial thermal
shutdown temp
SMCLK
SMDATA
ALERT#
THERM#
GND
10
9
8
7
6
R624
R624
10K_040 2_5%
10K_040 2_5%
EC_SMB_ CK2
EC_SMB_ DA2
12
+3VS
@
@
EC_SMB_ CK2 <15,23,32,45>
EC_SMB_ DA2 <15,23,32,45>
REMOTE1 +
C982
C982
100P_04 02_50V8J
100P_04 02_50V8J
REMOTE1 -
REMOTE2 +
C984
C984
100P_04 02_50V8J
100P_04 02_50V8J
REMOTE2 -
1
@
@
2
Close to SSD side
1
@
@
2
C
C
2
Q137
Q137
B
B
MMST390 4-7-F_SOT323-3
MMST390 4-7-F_SOT323-3
E
E
3 1
C
C
2
Q138
Q138
B
B
MMST390 4-7-F_SOT323-3
MMST390 4-7-F_SOT323-3
E
E
3 1
Under VRAM
REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"
FAN1 Conn
+5VS
JFAN1
JFAN1
1
1
2
2
3
3
4
4
5
G5
6
G6
ACES_85 205-04001
ACES_85 205-04001
ME@
ME@
40 65Tuesday, March 20, 2 012
40 65Tuesday, March 20, 2 012
40 65Tuesday, March 20, 2 012
1
0.2
0.2
0.2
2
C986
C986
10U_080 5_10V6K
10U_080 5_10V6K
A A
Security Class ification
Security Class ification
Security Class ification
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/ 01 2012/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
0.1U_040 2_10V7K
0.1U_040 2_10V7K
1
2
C49
1
@C49
@
2
EC_FAN_ SPEED<45 >
EC_FAN_ PWM< 45>
Compal Electronics,Ltd.
Compal Electronics,Ltd.
Compal Electronics,Ltd.
Title
Title
Title
EMC1403/2103_Thermal sensor/FAN
EMC1403/2103_Thermal sensor/FAN
EMC1403/2103_Thermal sensor/FAN
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
Page 41
A
B
C
D
E
F
G
H
1 1
@J12
@
J12
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_DTX_IRX_N1SATA_DTX_C_IRX_N1
SATA_DTX_IRX_P1
2
+5VS_HDD
1
C635
C635
10U_0603_6.3V6M
10U_0603_6.3V6M
2
SATA_ITX_DRX_P1<14>
SATA_ITX_DRX_N1<14>
1 2
SATA_DTX_C_IRX_N1<14>
SATA_DTX_C_IRX_P1<14>
+5VS
2 2
1
C631
C631
1000P_0402_50V7K
1000P_0402_50V7K
2
SATA_DTX_C_IRX_P1
1
C632
C632
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C627 0.01U_0402_16V7KC627 0.01U_0402_16V7K
1 2
C628 0.01U_0402_16V7KC628 0.01U_0402_16V7K
+5VS
1
C633
C633
1U_0603_10V4Z
1U_0603_10V4Z
2
JUMP_43X79
JUMP_43X79
1
C634
C634
10U_0603_6.3V6M
10U_0603_6.3V6M
2
112
SATA HDD Conn.
JHDD1
ME@JH DD1
ME@
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
14
VCC5
15
VCC5
16
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12
22
VCC12
23
GND
24
GND
SANTA_190302-1
SANTA_190302-1
SATA_ITX_DRX_P2_CONN<14>
SATA_ITX_DRX_N2_CONN<14>
SATA_DTX_C_IRX_N2<14>
SATA_DTX_C_IRX_P2<14>
SATA_DTX_C_IRX_N2
SATA_DTX_C_IRX_P2
SLI_FAN_SPEED<32,45>
ODD_DETECT#<19>
+5VS_ODD
ODD_DA#_R<18>
SLI_FAN_PWM<32,45>
+3VS
1 2
C629 0.01U_0402_16V7KC629 0.01U_0402_16V7K
1 2
C630 0.01U_0402_16V7KC630 0.01U_0402_16V7K
1 2
R1479 0 _0402_5%R 1479 0_0402_5%
1 2
R1476 0 _0402_5%@R1476 0_0402_5%@
1 2
R710 0_0402_5%@R710 0_0402_5%@
1 2
R921 10K_0402_5%R921 10K_0402_5%
1 2
R1497 0 _0402_5%@R1497 0_0402_ 5%@
1 2
R1494 0 _0402_5%R 1494 0_0402_5%
SATA_ITX_DRX_P2_CONN
SATA_ITX_DRX_N2_CONN
SATA_DTX_IRX_N2
SATA_DTX_IRX_P2
SATA ODD Conn.
1
2
3
4
5
6
7
8
9
10
11
ODD_DA#
12
JODD2
ME@JODD 2
ME@
GND
A+
AGND
BB+
GND
DP
+5V
+5V
MD
GND
GND
GND13GND
SANTA_202404-1
SANTA_202404-1
15
14
ODD Power Control
J6
@ J6
@
2
112
JUMP_43X79
JUMP_43X79
Q88 AO3413_SOT23-3
Q88 AO3413_SOT23-3
S
S
G
G
1
2
2
2
1
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
D
D
13
2
C638
C638
0.01U_0402_16V7K
0.01U_0402_16V7K
1
C1057
C1057
0.01U_0402_16V7K@
0.01U_0402_16V7K@
1
C639
C639
10U_0603_6.3V6M
10U_0603_6.3V6M
2
+5VS_ODD
1
2
C637
C637
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ODD_EN#
5
G
G
+5VS_ODD
12
34
D
D
S
S
R1477
470_0603_5%
470_0603_5%
@R1477
@
Q89B
Q89B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
100K_0402_5% @
100K_0402_5% @
2
G
G
12
R1478
R1478
100K_0402_5%
100K_0402_5%
+5VALW +5VS
12
R923
R923
61
D
D
S
S
12
R1496
R1496
100K_0402_5%
100K_0402_5%
R1110
R1110
12
100K_0402_5%
100K_0402_5%
Q89A
Q89A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
C1049
C1049
0.1U_0402_16V4Z
0.1U_0402_16V4Z
ODD_EN#
3 3
ODD_EN<19>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
D
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
E
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
F
Date: Sheet of
Compal Electronics, Inc.
HDD/ODD Connector
HDD/ODD Connector
HDD/ODD Connector
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
G
0.2
0.2
41 65Tuesday, March 20, 2012
41 65Tuesday, March 20, 2012
41 65Tuesday, March 20, 2012
H
0.2
Page 42
A
B
C
D
E
F
G
H
LA1
LA1
+5VS
600ohms @100MHz 1A
1 1
P/N: SM01000BU00
1 2
FBMA-L11160808601LMA10T_2P
FBMA-L11160808601LMA10T_2P
1
CA13
CA13
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
+5VS_AVDD
1
CA14
CA14
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Place near UA8. Pin25
RA5
RA5
+5VS
600ohms @100MHz 2A
P/N: SM01000EE00
1 2
0_0805_5%
0_0805_5%
1
2
CA7
CA7
CA6
CA6
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Place near UA8. Pin39, Pin46
2 2
+3VS
RA475
RA475
4.7K_0402_5%@
4.7K_0402_5%@
HDA_RST_AUDIO#
1 2
CA1368
@ CA1368
@
100P_0402_50V8J~N
100P_0402_50V8J~N
3 3
MIC Sense --> RA1639 place near pin13
Capless HP Sense --> RA1638 place near pin34
MIC_JD<49>
PLUG_IN<49>
EAPD<43>
HDA_SDOUT_AUDIO<14> MIC2_R <49>
HDA_BITCLK_AUDIO<14>
HDA_SDIN0<14>
HDA_SYNC_AUDIO<14>
HDA_RST_AUDIO#<14>
PLUG_IN
EAPD
HDA_SDOUT_AUDIO
HDA_BITCLK_AUDIO
HDA_SDIN0 HDA_SDIN0_R
HDA_SYNC_AUDIO
HDA_RST_AUDIO#
RA1639 20K_0402_1%R A1639 20K_0402_1%
RA1638 39.2K_0402_1%R A1638 39.2K_0402_1%
CA1288 2.2U_0603_6.3V6KCA1288 2.2U_0603_6.3V6K
CA19 2.2U_0603_6.3V6KCA19 2.2U_0603_6.3V6K
CA20 4.7U_0603_6.3V6KCA20 4.7U_0603_6.3V6K
12
12
1 2
12
12
RA1637
RA1637
22_0402_5%
22_0402_5%
RA1640
RA1640
20K_0402_1%
20K_0402_1%
12
PC_BEEP
12
JDREF
CBN
CBP
CPVEE
LDO_CAP
SENSEAMIC_JD
Del RA3, RA4
+MIC1_VREFO_L
10 mils
For EMI
HDA_SDOUT_AUDIOHDA_SYNC_AUDIO
2
CA1278
CA1278
10P_0402_50V8J
10P_0402_50V8J
1
1
CA1282
@ CA1282
@
22P_0402_50V8J~N
22P_0402_50V8J~N
2
@
@
RA1635
RA1635
0_0402_5%
0_0402_5%
2
CA1285
@ CA1285
@
10P_0402_50V8J
10P_0402_50V8J
1
12
HDA_BITCLK_AUDIO
1
CA8
CA8
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
47
4
5
6
8
10
11
12
19
20
13
18
35
36
34
28
29
30
31
42
43
7
+5VS_PVDD
UA8
UA8
DAPD/COMB_JACK
PD#
SDATA-OUT
BIT-CLK
SDATA-IN
SYNC
RESET#
PCBEEP
JDREF
MONO-OUT(PORT-H)
Sense A
Sense-B
CBN
CBP
CPVEE
LDO-CAP
MIC2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L
PVSS1
PVSS2
DVSS
ALC269Q-VC2-GR_QFN48_6X6
ALC269Q-VC2-GR_QFN48_6X6
+5VS_AVDD
RA7
RA7
1 2
0_0603_5%
0_0603_5%
+3VS_DVDD
1
CA15
CA15
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Place near UA8. Pin1
+5VS_AVDD
+5VS_AVDD
2
1
CA22
CA22
CA21
CA21
1
VREF
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
Place near UA8. Pin38
30 mils
24
SPKOUT_R1
23
SPKOUT_L1
22
C_MIC2
21
17
16
15
14
40
41
44
45
33
32
48
3
2
CA1277 2.2U_0603_6.3V6KCA1277 2.2U_0603_6.3V6K
C_MIC1
CA1276 2.2U_0603_6.3V6KCA1276 2.2U_0603_6.3V6K
10 mils
10 mils
HPOUTR_R
HPOUTL_R
SPDIF SPDIF_OUT
DMIC_CLK_R
DMIC_DATA_R DMIC_DATA
10 mils
27
AC97_VREF
26
37
49
AGND
12
12
R3 75_0402_5%R3 75_0402_5%
R4 75_0402_5%R4 75_0402_5%
1 2
R945
R945
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
1 2
R955
R955
FBMA-10-100505-301T_2P
FBMA-10-100505-301T_2P
R954 0_0402_5%R954 0_0402_5%
10 mils
2
CA1290
CA1290
1
1U_0603_10V4Z
1U_0603_10V4Z
Close to UA8.Pin27
+3VS_DVDD
+3VS_DVDDIO
1
25
39
46
PVDD1
PVDD2
38
AVDD1
AVDD2
9
DVDD1
DVDD-IO
LINE1-R(PORT-C-R)
LINE1-L(PORT-C-L)
MIC1-R(PORT-B-R)
MIC1-L(PORT-B-L)
MIC2-R(PORT-F-R)
MIC2-L(PORT-F-L)
LINE2-R(PORT-E-R)
LINE2-L(PORT-E-L)
SPK-OUT-L+
SPK-OUT-L-
SPK-OUT-R-
SPK-OUT-R+
HPOUT-R(PORT-A-R)
HPOUT-L(PORT-A-L)
SPDIF-OUT
GPIO1/DMIC-CLK
GPIO0/DMIC-DATA
AVSS1
AVSS2
Thermal PAD
+3VS_DVDD +3VS_DVDDIO
RA6
RA6
P/N: SM01000DI0 0
SPKOUT_R1 <43>
SPKOUT_L1 <43>
12
12
EMI Request
12
1
CA1291
CA1291
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
0_0402_5%
0_0402_5%
MIC2_R
MIC1_R
+3VS_DVDDIO
1
CA17
CA17
2
@
@
10U_0603_6.3V6M
Place near UA8. Pin1
10U_0603_6.3V6M
11/07 -->
Change CA17 typ e to 0603
External SPK (One Channel)
MIC1_R <49>
HP_OUTR
HP_OUTL
DMIC_CLK
Ext. MIC
HP_OUTR <49>
HP_OUTL <49>
SPDIF_OUT <4 9>
DMIC_CLK <34 >
DMIC_DATA <34>
@
@
CA16
CA16
CA18
CA18
1
2
1U_0603_10V4Z
1U_0603_10V4Z
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS_DVDD+3VS
HeadPhone
SPDIF
Int. MIC
Pin Assignment Location Function
PC Beep
4 4
EC Beep
PCH Beep
BEEP#<45>
HDA_SPKR<14>
A
1 2
CA4 0.1U_0402_ 16V4ZCA4 0.1U_0402_16V4Z
1 2
CA5 0.1U_0402_ 16V4ZCA5 0.1U_0402_16V4Z
B
12
RA2
@ RA2
@
10K_0402_5%
10K_0402_5%
RA1
RA1
1 2
33_0402_5%
33_0402_5%
PC_BEEPPC_BEEP1
C
RA1647
@ RA1647
@
1 2
0_0402_5%
0_0402_5%
DGND AGND
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
D
2011/11/01 2012/03/09
2011/11/01 2012/03/09
2011/11/01 2012/03/09
E
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
SPK-OUT (Pin40/41/44/45)
Capless HP-OUT (Pin32/33)
MIC1(Pin21/22) External Mic in
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
F
Date: Sheet of
Internal
External
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
HD Audio ALC269Q-VC3
HD Audio ALC269Q-VC3
HD Audio ALC269Q-VC3
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
G
Int Speaker
Headphone out
42 65Tuesday, March 20, 2012
42 65Tuesday, March 20, 2012
42 65Tuesday, March 20, 2012
H
0.2
0.2
0.2
Page 43
A
B
C
D
E
F
G
H
B+
1 1
2 2
1A, W=40 mils
R899
R899
0_0402_5%
0_0402_5%
R898
R898
0_0402_5%
0_0402_5%
LA57
LA57
12
0_0603_5%
0_0603_5%
B+_PVDD
One channel analog input
+5VS
12
@
@
12
2
CA1
CA1
CA2
CA2
1
22U_1210_25V6K~D
22U_1210_25V6K~D
22uf*3, 10uf*8 for Damage issue
Stuff --> CA1, CA2, CA3, CA1374, CA1375 and CA1376
SPKOUT_L1<42>
SPKOUT_R1<42>
+3VALW
2
2
CA3
CA3
1
22U_1210_25V6K~D
22U_1210_25V6K~D
22U_1210_25V6K~D
22U_1210_25V6K~D
SPKOUT_L1
SPKOUT_R1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Change BOM stru cture to @
for leakage
12
@
@
CA1369
CA1369
1
10U_0805_25V6K
10U_0805_25V6K
B+_PVDD
1 2
C43 1U_0402_6.3V4ZC43 1U_0402_6.3V4Z
1 2
C44 1U_0402_6.3V4ZC44 1U_0402_6.3V4Z
1
C45
C45
2
@
@
R1407 10K_0402_5%
R1407 10K_0402_5%
12
CA1370
CA1370
10U_0805_25V6K
10U_0805_25V6K
12
@
@
12
@
@
CA1371
CA1371
10U_0805_25V6K
10U_0805_25V6K
C42
C42
1 2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
C46
C46
1 2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
AMP OFF#
1U_0402_6.3V4Z
1U_0402_6.3V4Z
12
12
@
@
@
@
CA1372
CA1372
CA1373
CA1373
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
+5VS
U73
U73
4
VS
21
PVDD
22
PVDD
8
INL+
12
INR+
9
INL-
11
INR-
7
LIM_TH
13
TEMPLOCK
15
SHUTDOWN
14
2
RELEASE
C47
C47
MAX98400BETGLFT_TQFN-EP24_4X4
MAX98400BETGLFT_TQFN-EP24_4X4
1
12
12
12
1U_0603_25V6
OUTL+
OUTLOUTL-
OUTROUTR-
OUTR+
GND
PGND
PGND
PGND
PGND
1U_0603_25V6
CA1376
CA1376
10U_0805_25V6K
10U_0805_25V6K
5
G1
6
G2
3
1
2
17
18
16
10
19
20
23
24
25
EP
CA1374
CA1374
CA1375
CA1375
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
1
C40
C40
2
SPKOUT_L1+
SPKOUT_L2-
SPKOUT_R2-
SPKOUT_R1+
1U_0603_25V6
1U_0603_25V6
GAIN1
GAIN2
C41
C41
B+_PVDD
B+ = 19V
1
2
LA56 0_06 03_5%LA 56 0_0603_5%
LA58 0_06 03_5%LA 58 0_0603_5%
LA61 0_06 03_5%LA 61 0_0603_5%
LA60 0_06 03_5%LA 60 0_0603_5%
12
12
12
12
Add JUMP for la yout route
W=30 mils
SPK_L1
SPK_L2
SPK_R2
SPK_R1
GAIN SETTING
GAIN1
GAIN2
GAIN1 GAIN2
GNDNCGND
*
GND NC
NC NC
12
R895
R895
0_0402_5%
0_0402_5%
GND
12
R890
0_0402_5%
0_0402_5%
@R890
@
GAIN
9
13
20.1
23.3
3 3
EC_MUTE#<45>
EAPD<42>
EC_MUTE#
1 2
R959 0_0402_5%R959 0_0402_5%
1
IN1
2
EAPD
IN2
1 2
R958 0_0402_5%
R958 0_0402_5%
+3VS
2
@ C1064
@
5
P
G
3
@
@
1
4
O
U74
@U74
@
SN74AHC1G08DCKR_SC70-5
SN74AHC1G08DCKR_SC70-5
C1064
0.1U_0402_10V7K
0.1U_0402_10V7K
AMP OFF#
SPK_R1
SPK_R2
SPK_L1
SPK_L2
D62
@D62
@
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1 2
CA9 1000P_0402_50V7K~N@ CA9 1000P_04 02_50V7K~N@
1 2
CA10 1000P_0402_50V7K~N@CA10 1000P_0402_50V7K ~N@
1 2
CA11 1000P_0402_50V7K~N@CA11 1000P_0402_50V7K ~N@
1 2
CA12 1000P_0402_50V7K~N@CA12 1000P_0402_50V7K ~N@
2009/11/02 Modify
2
3
2
3
D61
@D61
@
AZ5125-02S.R7G_SOT23-3
AZ5125-02S.R7G_SOT23-3
1
1
Speaker Conn.
SPK_L1
SPK_L2
SPK_R1
SPK_R2
JSPK1
ME@JSPK1
ME@
1
1
2
2
3
3
4
4
5
G5
6
G6
ACES_85205-04001
ACES_85205-04001
Reserve for ESD request.
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
D
2011/11/01 2012/03/09
2011/11/01 2012/03/09
2011/11/01 2012/03/09
E
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
F
Date: Sheet of
Compal Electronics, Inc.
AMP-MAX98400BETG+T
AMP-MAX98400BETG+T
AMP-MAX98400BETG+T
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
G
0.2
0.2
43 65Tuesday, March 20, 2012
43 65Tuesday, March 20, 2012
43 65Tuesday, March 20, 2012
H
0.2
Page 44
5
R1458
R1458
12
0_0603_5%
0_0603_5%
U71
D D
+1.8VS_CARD
+3VS_CARD
+1.8VS_CARD
1 2
C1027
C1027
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
Please close to pin43
PLT_RST#
+CRD_POWER
C C
B B
W=20mils
SD_CD#
MS_CD#
XD_CD#
U71
5
APVDD
10
APV18
36
TAV33
19
DV33
20
DV33
44
DV33
18
DV18
37
DV18
43
SDDV33_18
1
XRSTN
2
XTEST
13
CPPE_N
21
CR1_LEDN
17
CR1_PCTLN
16
CR1_CD0N/WAKEN
15
CR1_CD1N
14
CR2_CD2N
33
SPI_CSN
34
SPI_SO
35
SPI_SI
30
SPI_SCK
39
TXIN
6
APGND
31
GND
32
GND
38
GND
JMB389-LGAZ0C_LQFP48_7X7
JMB389-LGAZ0C_LQFP48_7X7
+3VS_CARD+3VS
JMB389
JMB389
Power
Power
System
System
GND
GND
PCIECard Reader
PCIECard Reader
1
2
C1034
C1034
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to pin10
XD_CD#
A A
SD_CD#
C1044
C1044
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
1
C1045
C1045
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
@
@
5
1
2
MDIO6
MDIO13
1 2
R1465
R1465
1K_0402_5%
1K_0402_5%
1 2
R1466
R1466
1K_0402_5%
1K_0402_5%
4
3
APCLKN
4
APCLKP
APREXT
APRXN
APRXP
APTXN
APTXP
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MIDO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
7
9
8
11
12
48
47
46
45
41
42
24
40
29
28
27
26
25
23
22
APREXT
PCIE_PRX_C_DTX_N4
PCIE_PRX_C_DTX_P4
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
+1.8VS_CARD
1
2
C1036
C1036
C1037
C1037
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to pin5->1000P->0.1u->10u
+CRD_POWER
Security Classification
Security Classification
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
CLK_PCIE_CARD_PCH#
CLK_PCIE_CARD_PCH
1 2
R1461
R1461
12K_0402_1%
12K_0402_1%
1 2
C1026 .1U_0402_16V7KC1026 .1U_040 2_16V7K
1 2
C1028 .1U_0402_16V7KC1028 .1U_040 2_16V7K
1 2
10U_0805_10V6K
10U_0805_10V6K
Issued Date
Issued Date
Issued Date
0_0402_5%
0_0402_5%
1
2
R1463
R1463
@
@
3
close to JREAD1 pin 9
close to JREAD1 pin 17
CLK_PCIE_CARD_PCH# <15>
CLK_PCIE_CARD_PCH <15>
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
1 2
MDIO5_R MDIO5_RR
1
C1031
C1031
22P_0402_50V8J
22P_0402_50V8J
2
@
@
0_0402_5%
0_0402_5%
1
2
C1038
C1038
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1464
R1464
10U_0805_10V6K
10U_0805_10V6K
Close to CONN.
+3VS_CARD
1
2
C1039
C1039
C1040
C1040
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to pin 44
Compal Secret Data
Compal Secret Data
2011/11/01 2010/11/11
2011/11/01 2010/11/11
2011/11/01 2010/11/11
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
close to JREAD1 pin 36
PCIE_PTX_C_DRX_N4 < 15>
PCIE_PTX_C_DRX_P4 <15>
PCIE_PRX_DTX_N4 <15>
PCIE_PRX_DTX_P4 <15>
+CRD_POWER
1
C1029
C1029
2
C1030
C1030
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
C1041
C1041
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Close to pin 36
(40mil)
800mA
1
2
MDIO0
MDIO1
MDIO2
MDIO3
MDIO8
MDIO9
MDIO10
MDIO4
MDIO6
MDIO14
XD_CD#
MDIO13
MDIO12
MDIO5_RR
MDIO7
2
MDIO5_R
MDIO5_R
MDIO5_RR
R1459
R1460
R1462
100_0402_5%
100_0402_5%
100_0402_5%
100_0402_5%
100_0402_5%
100_0402_5%
Close to connector for EMI request.
JREAD1
ME@JREAD1
22
30
29
28
27
26
25
24
23
33
32
34
39
38
37
36
35
31
40
41
42
ME@
XD-VCC
XD10-D0
XD11-D1
XD12-D2
XD13-D3
XD14-D4
XD15-D5
XD16-D6
XD17-D7
XD07-WE
XD08-WP
XD06-ALE
XD01-CD
XD02-R/B
XD03-RE
XD04-CE
XD05-CLE
XD GND
XD GND
SD CD/WP GND
SD CD/WP GND
T-SOL_144-131300 2600_40P_NR-T
T-SOL_144-131300 2600_40P_NR-T
1
C1042
C1042
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Close to pin 37Close to pin 19,20
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
B
B
B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
12
@R1459
@
12
@R1460
@
12
@R1462
@
+1.8VS_CARD
1
@
@
1 2
C1023
C1023
100P_0402_50V8J
100P_0402_50V8J
@
@
1 2
C1024
C1024
100P_0402_50V8J
100P_0402_50V8J
@
@
1 2
C1025
C1025
100P_0402_50V8J
100P_0402_50V8J
+CRD_POWER
11
SD4-VDD
18
MS9-VCC
SD5-CLK
SD7-DAT0
SD8-DAT1
SD9-DAT2
SD1-DAT3
SD2-CMD
SD-CD
SD-WP
SD6-VSS
SD3-VSS
MS8-SCLK
MS4-DATA0
MS3-DATA1
MS5-DATA2
MS7-DATA3
MS6-INS
MS2-BS
MS1-VSS
MS10-VSS
1
C1043
C1043
10U_0805_10V6K
10U_0805_10V6K
2
9
4
3
21
19
16
1
2
6
13
17
10
8
12
15
14
7
5
20
MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
SD_CD#MDIO11
MDIO6
MDIO5_R
MDIO0
MDIO1
MDIO2
MDIO3
MS_CD#
MDIO4
(40mil)
C1032
C1032
Close to pin 18
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Card reader JMB389
Card reader JMB389
Card reader JMB389
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
44 65T uesday, March 20, 2012
44 65T uesday, March 20, 2012
44 65T uesday, March 20, 2012
1
(40mil)
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
C1033
C1033
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.2
0.2
0.2
Page 45
EC_SCI#/ EC_SMI# pull up to PCH
EC_SMI#<19>
EC_SCI#<19>
pull up to PCH
+3VALW
1 2
R1404 100K_0402_5%R1404 100K_0402_5%
+3VL
1 2
@
@
R1405 100K_0402_5%
R1405 100K_0402_5%
For S3.5
KSO[0..15]<46>
KSI[0..7]< 46>
EC_SMB_CK1<49,53, 62>
EC_SMB_DA1<49,53, 62>
Please place R1435 close to EC within 790mil
C999
C999
1U_0402_6.3V6K
1U_0402_6.3V6K
KSO[0..15]
KSI[0..7]
Reserved SMBus channel 0 for debugging
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2<15,23,32,40>
EC_SMB_DA2<15,23,32,40>
H_PECI<6>
For Deep S3
D70
D70
12
EC_SMI#_R
RB751V-40_SOD323-2
RB751V-40_SOD323-2
D71
D71
12
EC_SCI#_R
RB751V-40_SOD323-2
RB751V-40_SOD323-2
SERIRQ< 14>
1
2
H_PECI PECI_EC
CPU1.5V_S3_GATE<10>
LPC_FRAME#<14,37>
CLK_PCI_EC<18>
EC_SMB_CK2
EC_SMB_DA2
ECR_EN<34>
KBRST#<19>
LPC_FRAME#
LPC_AD3<14,37>
LPC_AD2<14,37>
LPC_AD1<14,37>
LPC_AD0<14,37>
BATT_LEN#<53>
PLT_RST#<18,23,32, 37,38,44,6>
GATEA20<19>
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
GATEA20
12
R143543_0402_1% R143543_0402_1%
LAN_PWR_ON#<38>
PM_SLP_S3#<16>
PM_SLP_S4#<16>
EC_RSMRST#<16>
ON/OFF<50>
NOVO#<50>
USB_ON#<48,49>
DPWROK_EC<16>
NUM_LED# only for Y590
EC_LID_OUT#<19>
R1539
R1539
1 2
0_0402_5%
0_0402_5%
1 2
R1540
@R1540
@
0_0402_5%
0_0402_5%
EC_SMB_CK1
EC_SMB_DA1
ECR_EN_R
100K_0402_5%
100K_0402_5%
+RTCBATT
KBRST#
SERIRQ
WRST#
EC_SMI#_R
BATT_LEN#
EC_SCI#_R
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
LAN_PWR_ON#
NOVO#
USB_ON#
EC_LID_OUT#
R1102
R1102
close EC
C1082
C1082
1 2
VCOREVCC
@
@
12
0_0402_5%
0_0402_5%
12
0_0402_5%
0_0402_5%
U70
U70
4
KBRST#/GPB6
5
SERIRQ/GPM6
6
LFRAME#/GPM5
7
LAD3/GPM3
8
LAD2/GPM2
9
LAD1/GPM1
10
LAD0/GPM0
13
LPCCLK/GPM4
14
WRST#
15
ECSMI#/GPD4
16
PWUREQ#/BBO/SMCLK2ALT/GPC7
17
NC
22
LPCRST#/WUI4/GPD2
23
ECSCI#/GPD3
126
GA20/GPB5
58
KSI0/STB#
59
KSI1/AFD#
60
KSI2/INIT#
61
KSI3/SLIN#
62
KSI4
63
KSI5
64
KSI6
65
KSI7
36
KSO0/PD0
37
KSO1/PD1
38
KSO2/PD2
39
KSO3/PD3
40
KSO4/PD4
41
KSO5/PD5
42
KSO6/PD6
43
KSO7/PD7
44
KSO8/ACK#
45
KSO9/BUSY
46
KSO10/PE
51
KSO11/ERR#
52
KSO12/SLCT
53
KSO13
54
KSO14
55
KSO15
56
KSO16/SMOSI/GPC3
57
KSO17/SMISO/GPC5
110
SMCLK0/GPB3
111
SMDAT0/GPB4
115
SMCLK1/GPC1
116
SMDAT1/GPC2
117
SMCLK2/PECI/WUI22/GPF6
118
SMDAT2/PECIRQT#/WUI23/GPF7
94
WUI17/CRX1/SIN1/SMCLK3/GPH1/ID1
95
WUI18/CTX1/SOUT1/GPH2/SMDAT3/ID2
112
RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
125
PWRSW/GPE4
19
BAO/WUI24/GPE0
33
GINT/CTS0#/GPD5
35
RTS1#/WUI5/GPE5
93
CLKRUN#/WUI16/GPH0/ID0
2
CK32KE/GPJ7
128
CK32K/GPJ6
For factory EC flash
12
.1U_0402_16V7K
.1U_0402_16V7K
R1519
R1519
R1520
R1520
12
3
VBAT/VCC
LPC
LPC
Int. K/B
Int. K/B
Matrix
Matrix
1
GPG5
CMOS_ON#
GPG3
LED_KB_PWM
H_PROCHOT#_EC
WRST#
+3VS
11
VCORE/VCC
SM Bus
SM Bus
WAKE UP
WAKE UP
Clock
Clock
VSS/GND
VSS/GND20VSS/GND
21
VCC/VCC
GPIO
GPIO
27
18
VSS/GND
VSTBY/VCC
VSS/GND49VSS/GND
50
92
114
121
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC
VSTBY/VCC26VSTBY/VCC
ADC
ADC
ADC5/DCD1#/WUI29/GPI5
ADC6/DSR1#/WUI30/GPI6
ADC7/CTS1#/WUI31/GPI7
DAC
DAC
PS2
PS2
SPI Flash ROM
SPI Flash ROM
EXTERNAL SERIAL FLASH
EXTERNAL SERIAL FLASH
UART
UART
GPIO
GPIO
DTR1#/SBUSY/GPG1/ID7
VSS/GND
VSS/GND
75
91
113
122
ECAGND
1 2
R1524 0_0603_5%R1524 0_0603_5%
1 2
@
@
R1525 0_0603_5%
R1525 0_0603_5%
For S3.5
+3VALW_R
+3VALW_EC
minimum trace width 12 mil
74
127
AVCC
VSTBY/VCC
PWM
PWM
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7
TMRI0/WUI2/GPC4
TMRI1/WUI3/GPC6
ADC4/WUI28/GPI4
DAC2/TACH0B/GPJ2
DAC3/TACH1B/GPJ3
DAC4/DCD0#/GPJ4
DAC5/RIG0#/GPJ5
PS2CLK0/TMB0/GPF0
PS2DAT0/TMB1/GPF1
PS2CLK1/DTR0#/GPF2
PS2DAT1/RTS0#/GPF3
PS2CLK2/WUI20/GPF4
PS2DAT2/WUI21/GPF5
WUI19/GPH3/ID3
TXD/SOUT0/GPB1
EGAD/WUI25/GPE1
EGCS#/WUI26/GPE2
EGCLK/WUI27/GPE3
CTX0/TMA0/GPB2
TACH1A/TMA1/GPD7
AVSS/AGND
PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5
ADC0/GPI0
ADC1/GPI1
ADC2/GPI2
ADC3/GPI3
GPH4/ID4
GPH5/ID5
GPH6/ID6
GPG3
GPG4
GPG5
GPG7
RXD/SIN0/GPB0
GPJ1
SSCE0#/GPG2
SSCE1#/GPG0
DSR0#/GPG6
CRX0/GPC0
TACH2/GPJ0
TACH0A/GPD6
IT8580E-HX_LQFP128
IT8580E-HX_LQFP128
IT0PAD IT0PAD
IT1PAD IT1PAD
IT2PAD IT2PAD
IT3PAD IT3PAD
IT4PAD IT4PAD
IT5PAD IT5PAD
IT6PAD IT6PAD
IT7PAD IT7PAD
IT8PAD IT8PAD
24
25
28
29
30
31
32
34
120
124
66
67
68
69
70
71
72
73
78
79
80
81
85
86
87
88
89
90
96
97
98
99
101
102
103
105
108
109
82
83
84
77
100
106
104
107
119
123
76
48
47
+3VALW
+3VL
All capacitors close to EC
C1077
0.1U_0402_16V4Z
C1077
0.1U_0402_16V4Z
C1078
0.1U_0402_16V4Z
C1078
C1076
0.1U_0402_16V4Z
C1076
0.1U_0402_16V4Z
1
2
BATT_CHG_LED#
BATT_LOW_LED#
LED_KB_PWM
SLI_FAN_PWM
EC_FAN_PWM
BEEP#
EC_INVT_PWM
ACIN
BATT_TEMP
LAN_WAKE#
AD_ID
LID_SW#
EC_WL_OFF#
USB_CH#
TP_CLK
TP_DATA
CAPS_LED#
ACOFF
PCH_PWROK
GPG3
GPG5
SYSON
SUSP#
ENBKL
H_PROCHOT#_EC
EC_ON
A_DET#
VGA_AC_DET
SUSACK#
PCH_PWR_EN
SLI_FAN_SPEED
EC_FAN_SPEED
0.1U_0402_16V4Z
1
1
2
2
VGA_IMON
BATT_TEMP <53>
IMVP_IMON <59>
ADP_I <53,62>
LID_SW# <46>
PCH_PWR_EN <51>
EC_RX
EC_TX
R1429 0_0402_5%@R1429 0_0402_5%@
BKOFF#
AOAC_ON
A_DET# <49>
SLI_FAN_SPEED <32,41>
EC_FAN_SPEED <40>
EMC Request
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C1079
0.1U_0402_16V4Z
C1079
0.1U_0402_16V4Z
1
1
2
2
PWR_LED# <47>
BATT_CHG_LED# <47>
BATT_LOW_LED# <47>
LED_KB_PWM <46>
SLI_FAN_PWM <32,41>
EC_FAN_PWM <40>
BEEP# <42>
EC_INVT_PWM <34>
ACIN <62>
VGA_AC_DET <23,32,58>
VGA_IMON <58>
SA_PGOOD <56>
SUSWARN# <16>
AC_PRESENT <16>
DRAMRST_CNTRL_EC <7>
EC_WL_OFF# <37>
USB_CH# <49>
PBTN_OUT# <16>
PM_SLP_SUS# <16,51>
SUSACK# <16>
TP_CLK <46>
TP_DATA <46>
CAPS_LED# <47>
ACOFF <62>
PCH_PWROK <16>
CMOS_ON# <34>
EC_RX <37>
EC_TX <37>
SYSON <55>
SUSP# <32,51,55,57,58>
VR_ON <59>
12
BKOFF# <34>
AOAC_ON <51>
C1007
C1007
1
@
@
2
0.1U_0402_10V6K
0.1U_0402_10V6K
+3VALW_R
+3VALW_R
C1081
0.1U_0402_16V4Z
C1081
0.1U_0402_16V4Z
C1080
C1080
1
2
For 2nd fan
For fan
For EC beep
OPT@
OPT@
R1532
R1532
1 2
100K_0402_5%
100K_0402_5%
SLI@
SLI@
R1533 100K_0402_5%
R1533 100K_0402_5%
1 2
for power adapter ID
3V--- 90W
1.5V--- 120W
0V--- 170W
ENBKL <34>
PROCHOT <53>
ME_FLASH <14>
EC_ON <50,54>
BATT_TEMP
C1000 100P_0402_50V8JC1000 100P_0402_50V8J
ACINSYSON
C1001 100P_0402_50V8JC1001 100P_0402_50V8J
2011/11/01 2012/07/11
2011/11/01 2012/07/11
2011/11/01 2012/07/11
EC_MUTE# <43>
1 2
1 2
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
L80
L80
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
L81
L81
1 2
BLM18PG181SN1D_0603
BLM18PG181SN1D_0603
+3VALW
OPT,35W --> R1532
OPT,45W --> R1532, R1533
SLI --> R1533
SUSP#
12
100K_0402_5%
100K_0402_5%
R1101
R1101
ECAGND
1
C1072
C1072
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
PCH_PWROK
10K_0402_5% @
10K_0402_5% @
VR_HOT#<59>
SYSON
+3VS
C1075
0.1U_0402_16V4Z
C1075
+3VALW_EC
1
C1073
C1073
1000P_0402_50V7K
1000P_0402_50V7K
2
EC_SMB_CK1
R1417 2.2K_0402_5%R1417 2.2K_0402_5%
EC_SMB_DA1
R1424 2.2K_0402_5%R1424 2.2K_0402_5%
EC_FAN_SPEED
SLI_FAN_SPEED
TP_CLK
TP_DATA
EC_SMB_CK2
EC_SMB_DA2
12
R1433
R1433
VR_HOT#
H_PROCHOT#_EC
12
100K_0402_5%
100K_0402_5%
R1522
R1522
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
USB_CH#
USB_ON#
EC_FAN_PWM
LPC_FRAME#
1 2
R1427
R1427
0_0402_5%
0_0402_5%
13
D
D
2
G
G
Q141
Q141
S
2N7002H_SOT23-3
2N7002H_SOT23-3
S
+3VALW
LAN_WAKE#
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EC IT8580E
EC IT8580E
EC IT8580E
0.1U_0402_16V4Z
+3VALW +3VL
R1529
R1529
0_0603_5%
0_0603_5%
12
12
R1431 10K_0402_5%R1431 10K_0402_5%
R1485 10K_0402_5%R1485 10K_0402_5%
1 2
R1410 4.7K_0402_5%R1410 4.7K_0402_5%
1 2
R1412 4.7K_0402_5%R1412 4.7K_0402_5%
R1423 2.2K_0402_5%R1423 2.2K_0402_5%
R1422 2.2K_0402_5%R1422 2.2K_0402_5%
1 2
R1482 10K_0402_5%R1482 10K_0402_5%
1 2
10K_0402_5%
10K_0402_5%
R1409
R1409
@
@
R1402
R1402
10K_0402_5%
10K_0402_5%
R1521
R1521
1 2
10K_0402_5%
10K_0402_5%
H_PROCHOT# <53,6>
1
C1004
C1004
47P_0402_50V8J
47P_0402_50V8J
2
R1434
R1434
10K_0402_5%
10K_0402_5%
1 2
LAN_WAKE# <38>
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
12
12
45 65Tuesday, March 20, 2012
45 65Tuesday, March 20, 2012
45 65Tuesday, March 20, 2012
1
2
12
12
R1530
R1530
0_0603_5%@
0_0603_5%@
+3VS
+3VS
+3VS
12
12
+5VALW
+3VS
12
+3VS
0.2
0.2
0.2
Page 46
5
14" INT_KBD Conn.
4
3
2
1
KSI[0..7]
D D
KSO2
KSO15
KSO6
KSO8
KSO13
KSO12
KSO11
KSO10
KSO3
KSO4
KSI0
KSO0
C734 100P_0402_50V8J@C734 100P_0402_50V8J@
C736 100P_0402_50V8J@C736 100P_0402_50V8J@
C738 100P_0402_50V8J@C738 100P_0402_50V8J@
C740 100P_0402_50V8J@C740 100P_0402_50V8J@
C742 100P_0402_50V8J@C742 100P_0402_50V8J@
C744 100P_0402_50V8J@C744 100P_0402_50V8J@
C746 100P_0402_50V8J@C746 100P_0402_50V8J@
C748 100P_0402_50V8J@C748 100P_0402_50V8J@
C750 100P_0402_50V8J@C750 100P_0402_50V8J@
C752 100P_0402_50V8J@C752 100P_0402_50V8J@
C754 100P_0402_50V8J@C754 100P_0402_50V8J@
C756 100P_0402_50V8J@C756 100P_0402_50V8J@
KSO[0..15]
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CONN PIN define need double check
C C
KSI[0..7] <45>
KSO[0..15] <45>
KSO1
KSO7
KSI2
KSO5
KSI3
KSO14
KSI7
KSI6
KSI5
KSI4
KSO9
KSI1
1 2
C735 100P_0402 _50V8J@C735 1 00P_0402_50V8J@
1 2
C737 100P_0402 _50V8J@C737 1 00P_0402_50V8J@
1 2
C739 100P_0402 _50V8J@C739 1 00P_0402_50V8J@
1 2
C741 100P_0402 _50V8J@C741 1 00P_0402_50V8J@
1 2
C743 100P_0402 _50V8J@C743 1 00P_0402_50V8J@
1 2
C745 100P_0402 _50V8J@C745 1 00P_0402_50V8J@
1 2
C747 100P_0402 _50V8J@C747 1 00P_0402_50V8J@
1 2
C749 100P_0402 _50V8J@C749 1 00P_0402_50V8J@
1 2
C751 100P_0402 _50V8J@C751 1 00P_0402_50V8J@
1 2
C753 100P_0402 _50V8J@C753 1 00P_0402_50V8J@
1 2
C755 100P_0402 _50V8J@C755 1 00P_0402_50V8J@
1 2
C757 100P_0402 _50V8J@C757 1 00P_0402_50V8J@
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
JKB1
JKB1
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
G1
26
G2
ACES_85202-24051
ACES_85202-24051
ME@
ME@
KB Lighting CONN.4pin
+VCC_KB_LED
R1229
R1229
10K_0402_5%
10K_0402_5%
KBL@
KBL@
R1480
R1480
2
G
G
12
LED_KB_PWM<45>
100K_0402_5%
100K_0402_5%
KBL@
KBL@
2
C905
C905
@
@
1
0.1U_0402_10V6K
0.1U_0402_10V6K
12
C1053
C1053
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1232
R1232
1 2
100K_0402_5%
100K_0402_5%
KBL@
KBL@
13
D
D
Q122
Q122
2N7002_SOT23
2N7002_SOT23
S
S
KBL@
KBL@
JKBL1
JKBL1
1
1
2
2
3
3
4
4
5
G1
6
G2
E&T_6906-Q04N-00R
E&T_6906-Q04N-00R
ME@
ME@
+5VS
AO3413
VGS= -4.5V, Id=-3A, Rds<97m ohm
AO3413_SOT23-3
AO3413_SOT23-3
Q121
Q121
D
S
D
S
KBL@
KBL@
13
G
G
1
KBL@
KBL@
2
KBL@
@
@
KBL@
1
C907
C907
0.01U_0402_16V7K
0.01U_0402_16V7K
2
2
+VCC_KB_LED
1
2
0.01U_0402_25V7K
0.01U_0402_25V7K
C1054
C1054
KBL@
KBL@
2
C908
C908
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
To TP/B Conn.
JTP1
ME@JTP1
ME@
SMB_DATA_S3<12,13,15,37>
SMB_CLK_S3<12,13,15,37>
TP_DATA<45 >
B B
TP_CLK<45>
SMB_DATA_S3
SMB_CLK_S3
TP_DATA
TP_CLK
1
@
@
C761
C761
100P_0402_50V8J
100P_0402_50V8J
2
1
@
@
C762
C762
100P_0402_50V8J
100P_0402_50V8J
2
+3VALW
+3VS
C760
C760
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D58
D58
4
I/O3
5
VDD
6
I/O4
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
@
@
For ESD request
GND
1
I/O1
2
3
I/O2
1
1
2
2
3
3
4
4
5
5
6
6
7
GND
8
GND
ACES_88514-00601-071
ACES_88514-00601-071
+3VALW
Lid Switch
1 2
R1002 0_0402_5%R1002 0_0402_5%
C758
C758
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VCC_LID
1
2
1 2
R1003 100K_0402_5%R1003 100K_0402_5%
2
5711ACDL-M3T1S SOT-23
5711ACDL-M3T1S SOT-23
VDD
3
OUTPUT
GND
U37
U37
1
2
C759
C759
10P_0402_50V8J
10P_0402_50V8J
1
LID_SW# <45>
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
KB /SW /LPC Debug Conn.
KB /SW /LPC Debug Conn.
KB /SW /LPC Debug Conn.
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
46 65Tuesday, March 20, 2012
46 65Tuesday, March 20, 2012
46 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 47
+3VALW
12
R1562
R1562
@
@
@
5
G
G
@
1
C1100
C1100
@
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
34
D
D
2
Q160B
Q160B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
R1564
R1564
1 2
0_0402_5%
0_0402_5%
10K_0402_1%
10K_0402_1%
BATT_LOW_LED#<45>
2
G
G
@
@
BATT_LOW_LED#_R
61
D
D
Q160A
Q160A
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
BATT_CHG_LED#<45>
R1558
R1558
10K_0402_1%
10K_0402_1%
@
@
5
G
G
+3VALW
12
@
@
@
@
34
D
D
Q158B
Q158B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
1
C1098
C1098
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R1561
R1561
1 2
0_0402_5%
0_0402_5%
2
G
G
@
@
BATT_CHG_LED#_R
61
D
D
Q158A
Q158A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
BATT CHARGE/LOW LED
Amber
BATT_LOW_LED#_R
White
BATT_CHG_LED#_R
R1012
R1012
470_0402_5%
470_0402_5%
R1014
R1014
470_0402_5%
470_0402_5%
White
LED2
12
12
LED2
3
2
1
12-22-S2ST3D-C30-2C_WHI-ORG
12-22-S2ST3D-C30-2C_WHI-ORG
+5VALW
10K_0402_1%
10K_0402_1%
PWR_LED#<45>
BlueTooth DC
PCH_BT_ON#<19,37>
5
G
G
R1559
R1559
@
@
+3VALW
12
@
@
@
@
34
D
D
Q159B
Q159B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
1
C1099
C1099
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
R1560
R1560
1 2
0_0402_5%
0_0402_5%
R1526
R1526
1 2
100K_0402_5%
100K_0402_5%
BT@
BT@
PWR_LED#_R
R1490
R1490
10K_0402_1%
61
D
D
Q159A
@
Q159A
@
2
G
G
S
S
HDD_LED#<14>
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
+3VS +3VS_BT
Q154
BT@
Q154
BT@
AO3413_SOT23-3
AO3413_SOT23-3
D
S
D
S
13
1
2
1
2
C1070
C1070
0.1U_0402_16V4ZBT@
0.1U_0402_16V4ZBT@
C1084
C1084
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
G
G
2
10K_0402_1%
1
C1069
C1069
0.01U_0402_25V7KBT@
0.01U_0402_25V7KBT@
2
5
G
G
+5VS
12
@
@
34
D
D
@
@
S
S
USB20_P13<18>
USB20_N13<18>
R1491
R1491
1 2
+5VS
10K_0402_1%
10K_0402_1%
Q151B
Q151B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
R1492
R1492
1 2
0_0402_5%
0_0402_5%
30mils
1
C1083
C1083
0.1U_0402_16V4ZBT@
0.1U_0402_16V4ZBT@
2
+3VS_BT
USB20_P13
USB20_N13
@
@
HDD_LED#_R
61
D
D
Q151A
@
Q151A
@
2
G
G
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
PWR LED HDD LED
PWR_LED#_R<50>
HDD_LED#_R
CAPS_LED#<45>
CapsLK LED
White
LED3
LED3
LED1
LED1
LED4
LED4
21
21
21
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
12-21SYGCS530-E1S155TR8_W
R1013
R1013
300_0402_5%
300_0402_5%
R1322
R1322
300_0402_5%
300_0402_5%
R1323
R1323
300_0402_5%
300_0402_5%
12
+5VALW
12
+5VS
12
+5VS
LED3 LED2 LED1 LED4
POWER BATTERY HDD CapsLK
Screw Hole
MIN PCIE: H_3P3 X 1CPU and GPU: H_3P8X 6
H33
H33
HOLEA
HOLEA
1
E: H_3P3X 1
H28
H28
HOLEA
HOLEA
1
BT Conn.
JBT1
ME@JBT1
ME@
1
1
2
2
3
3
4
4
5
GND
6
GND
ACES_50209-0040N-001
ACES_50209-0040N-001
C: H_3P8X 3
H13
H13
H10
H10
H12
HOLEA
HOLEA
1
H12
HOLEA
HOLEA
HOLEA
HOLEA
1
1
B: H_3P8X 3
H14
H14
H15
HOLEA
HOLEA
1
H15
HOLEA
HOLEA
1
H11
H11
HOLEA
HOLEA
1
GPUCPU
ME: H_8P0 X 8; H_3P3X 1; H_4P0X3P0N X 2; H_2P0X 1
A: H_2P8X 8
H22
H22
H24
HOLEA
HOLEA
1
H24
HOLEA
HOLEA
1
H25
H25
HOLEA
HOLEA
1
H30
H30
HOLEA
HOLEA
1
H31
H31
HOLEA
HOLEA
1
H32
H32
HOLEA
HOLEA
1
H16
H16
HOLEA
HOLEA
1
PCB Fedical Mark PAD
FD3FD3
FD1FD1
FD2FD2
1
1
FD4FD4
1
1
E: H_3P3X 1 H_4P0X3P0NX 3 H_2P0X 2
H20
H20
H21
H29
H29
HOLEA
HOLEA
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
HOLEA
HOLEA
1
H21
HOLEA
HOLEA
1
Date: Sheet of
Date: Sheet of
Date: Sheet of
H23
H23
HOLEA
HOLEA
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Compal Electronics, Inc.
LED/EC SPI ROM/BT
LED/EC SPI ROM/BT
LED/EC SPI ROM/BT
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
47 65Tuesday, March 20, 2012
47 65Tuesday, March 20, 2012
47 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 48
A
B
C
D
E
LEFT SIDE USB3.0 PORT X1
U39
U39
1
GND
1 1
C767 0.1U_0402_16V4ZC767 0.1U_0402_16V4Z
12
USB_ON#<45,49>
2
VIN
VIN3VOUT
4
USB_ON# USB_OC1#
EN
G547I2P81U_MSOP8
G547I2P81U_MSOP8
Low Active 2A
For EMI request
USB2.0 choke --> SM070000I00
USB3.0 Choke --> SM070001U00
L68
L68
USB30_RX_N3
2 2
USB30_RX_P3
USB30_TX_C_N3
USB30_TX_C_P3
USB20_N2
USB20_P2 USB30_TX_R_P3
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L70
L70
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
L72
L72
2
2
3
3
WCM-2012-900T_4P
WCM-2012-900T_4P
1
1
4
4
1
1
4
4
1
1
4
4
+USB_VCCA+5VALW
8
VOUT
7
VOUT
6
5
FLG
USB30_RX_R_N3
USB30_RX_R_P3
USB30_TX_R_N3
USB30_TX_R_P3
USB20_N2_R
USB20_P2_R
1
C904
C904
1000P_0402_50V7K@
1000P_0402_50V7K@
2
USB_OC1# <18>
USB20_N2<18>
USB20_P2<18>
USB30_RX_N3<18>
USB30_RX_P3<18>
USB30_TX_N3<18>
USB30_TX_P3<18>
For ESD request
USB30_RX_R_N3
USB30_RX_R_P3
USB30_TX_R_N3
YSCLAMP0524P_SLP2510P8-10-9
YSCLAMP0524P_SLP2510P8-10-9
1 2
R1162 0_0402_5%
R1162 0_0402_5%
1 2
R1163 0_0402_5%
R1163 0_0402_5%
@
@
1 2
R1154 0_0402_5%
R1154 0_0402_5%
@
@
USB30_RX_P3 USB30_RX_R_P3
USB30_TX_N3 USB30_TX_C_N3 USB30_TX_R_N3
D27
D27
@
@
9
10
10
8
9
9
7
7
7
6
6 5
6 5
1
1
2
2
4
4
3
3
8
8
1 2
C300 0.1U_0402_10V6KC300 0.1U_0402_10V6K
1 2
C299 0.1U_0402_10V6KC299 0.1U_0402_10V6K
1
USB30_RX_R_N3
2
USB30_RX_R_P3
4
USB30_TX_R_N3
5
USB30_TX_R_P3
3
USB20_N2_R
USB30_TX_C_P3 USB 30_TX_R_P3USB30_TX_P3
D24
D24
@
@
3
I/O2
2
GND
1
I/O1
AZC099-04S.R7G_SOT23-6
AZC099-04S.R7G_SOT23-6
1 2
R1155 0_0402_5%
R1155 0_0402_5%
@
@
1 2
R1156 0_0402_5%
R1156 0_0402_5%
@
@
1 2
R1157 0_0402_5%
R1157 0_0402_5%
@
@
@
@
6
I/O4
5
4
+5VALW
USB20_P2_R
VDD
I/O3
+USB_VCCA
C814 220U_6.3V_M
C814 220U_6.3V_M
1 2
+
+
1 2
C816 470P_0402_50V7KC816 470P_0402_50V7K
JUSB1
JUSB1
1
VBUS
USB20_N2_RUSB20_N2
USB20_P2_RUSB20_P2
USB30_RX_R_N3USB30_RX_N3
2
D-
3
D+
4
GND_1
5
SSRX-
6
SSRX+
7
GND_2
8
SSTX-
9
SSTX+
SANTA_370300-1
SANTA_370300-1
ME@
ME@
GND_6
GND_5
GND_4
GND_3
13
12
11
10
3 3
4 4
Security Classification
Security Classification
Security Classification
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
C
Deciphered Date
Deciphered Date
Deciphered Date
For EMI request
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
USB3.0 ports
USB3.0 ports
USB3.0 ports
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
E
of
48 65Tuesday, March 20, 2012
48 65Tuesday, March 20, 2012
48 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 49
5
4
3
2
1
Sleep & Charge
Right side USB Charger Port (USB_Port5, near JMIC1)
D D
VBUS1
VBUS2
DPOUT
DMOUT
A_DET#
ALERT#
SEL
+5V_CHGUSB
3
4
17
16
18
13
11
12
6
5
Del C1095
USB20_P5_C
USB20_N5_C
A_DET#
USB_OC2#
EC_SMB_DA1
EC_SMB_CK1
CH_SEL
CH_ILIM
1 2
R1555
R1555
33K_0402_5%
33K_0402_5%
R1587
R1587
10K_0402_5%
10K_0402_5%
1 2
@
@
R1583
R1583
10K_0402_5%
10K_0402_5%
1 2
1 2
R1553
R1553
10K_0402_5%
10K_0402_5%
+3VALW
A_DET# <45>
USB_OC2# <18>
EC_SMB_DA1 <45,53,62>
EC_SMB_CK1 <45,53,62>
Active Mode Selection:
M1 M2 EM_EN ACTIVE MODE
0 0 1 Dedicated Charger Emulation Cycle
*
0 1 0 Date Pass-through
0 1 1 BC1.2 DCP
1 0 0 BC1.2 SDP
1 0 1 Dedicated Charger Emulation Cycle
1 1 0 Date Pass-through
1 1 1 BC1.2 CDP
ILIM SETTING
Pull Low
OR-500mA
10K-900mA
12K-1000mA
15K-1200mA
18K-1500mA
22K-1800mA
27K-2000mA
33K-2500mA
*
SEL Pin Decode
Pull Low
0R -1010_000
10K-1010_000
*
12K-1010_000
15K-1010_000
18K-0110_000
22K-0110_000
27K-0110_000
33K-0110_000
+5VALW
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
C1093
C1093
+5VALW
C C
+5VALW
10U_0603_6.3V6M
10U_0603_6.3V6M
C1096
C1096
0.01U_0402_16V7K
0.01U_0402_16V7K
1
2
R1551
R1551
10K_0402_5%
10K_0402_5%
R1585
R1585
10K_0402_5%
10K_0402_5%
R1586
R1586
10K_0402_5%
10K_0402_5%
1
C1097
C1097
2
1 2
@
@
1 2
@
@
1 2
USB20_P5<18>
USB20_N5<18>
EM_EN
CH_M1
CH_M2
USB_CH#<45>
R1584
R1584
10K_0402_5%
10K_0402_5%
R1552
R1552
10K_0402_5%
10K_0402_5%
R1554
R1554
10K_0402_5%
10K_0402_5%
USB20_P5
USB20_N5
USB_CH#
EM_EN
CH_M1
CH_M2
@
@
2
1
C1094
C1094
1
2
9
U8
U8
7
VS1
VS2
DPIN
DMIN
PWR_EN
EM_EN
M1
M2
GND FLAG21GND
VDD
SMDATA/LATCH
SMCLK/S0
COMM_SEL/ILIM
20
UCS1002-1-BP-TR_QFN20_4X4
UCS1002-1-BP-TR_QFN20_4X4
8
14
15
10
19
1
2
12
12
12
USB Power (USB20_P9)
+5VS
U69
B B
USB_ON#<45,48>
USB_ON# USB_OC4#
1
C988
C988
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Ext. MIC
U69
1
GND
VOUT
2
VOUT
VIN
VIN3VOUT
4
FLG
EN
G547I2P81U_MSOP8
G547I2P81U_MSOP8
Low Active 2A
+MIC1_VREFO_L
+USB_VCCB+5VALW
8
7
6
5
1
C989
C989
@
@
1000P_0402_50V7K
1000P_0402_50V7K
2
USB_OC4# <18>
USB20_P9<18>
USB20_N9<18>
MIC_JD<42>
HP_OUTR<42>
HP_OUTL<42>
SPDIF_OUT<42>
PLUG_IN<42>
+USB_VCCB
+5V_CHGUSB
USB20_P9
USB20_N9
USB20_P5_C
USB20_N5_C
EXT_MIC_L
EXT_MIC_R
MIC_JD
HP_OUTR
HP_OUTL
SPDIF_OUT
PLUG_IN
need change to
AUDIO/B Conn.
JSB1
ME@JSB1
ME@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
GND1
26
GND2
ACES_88514-02401-071
ACES_88514-02401-071
霧霧霧霧霧霧霧霧
material
COMPAL : SP010015W1J
A A
RA1622
RA1622
2.2K_0402_5%
2.2K_0402_5%
MIC2_R<42>
MIC1_R<42>
5
RA1634 1K_0402_5%RA1634 1K_0402_5%
RA1633 1K_0402_5%RA1633 1K_0402_5%
12
12
Remove Diode (DA1, DA2)
RA1623
RA1623
2.2K_0402_5%
2.2K_0402_5%
1 2
1 2
4
EXT_MIC_R
EXT_MIC_L
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Footprint : 88514-0240N-071
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Audio B Conn/USB charger
Audio B Conn/USB charger
Audio B Conn/USB charger
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
1
49 65Tuesday, March 20, 2012
49 65Tuesday, March 20, 2012
49 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 50
ON/OFF switch
SW2
SW2
ON/OFFBT N#
1
2
EC_ON<45 ,54>
1 2
SHORT PA DS
SHORT PA DS
Power Button
TOP Side
Bottom Side
SMT1-05_ 4P
SMT1-05_ 4P
5
6
J7
J7
@
@
3
4
EC_ON
R1531 0_ 0603_5%
R1531 0_ 0603_5%
DAN202U T106_SC70-3
DAN202U T106_SC70-3
R1523
R1523
10K_040 2_5%
10K_040 2_5%
1 2
@
@
D72
D72
1
1 2
R1116
R1116
100K_04 02_5%
100K_04 02_5%
3
2
2
G
G
+3VALW
1 2
13
D
D
S
S
+3VL
R1117
R1117
100K_04 02_5%@
100K_04 02_5%@
1 2
For S3.5
ON/OFF
51_ON#
Q153
Q153
2N7002_ SOT23-3
2N7002_ SOT23-3
ON/OFF <45>
51_ON# <52 >
Power Button/B link
to Function/B Conn. 10pin
PWR_ LED#_R< 47>
NOVO_BT N#
ON/OFFBT N#
100P_04 02_50V8J
100P_04 02_50V8J
9/23 ESD Reques t
C551
C551
+5VALW
JPW R1
ME@J PWR1
ME@
1
1
2
2
3
3
4
4
5
5
6
@
@
1
2
6
7
GND
8
GND
ACES_88 514-00601-071
ACES_88 514-00601-071
+3VALW
R1118
R1118
100K_04 02_5%
100K_04 02_5%
1 2
NOVO#<45>
NOVO#
51_ON#
ON/OFF
For S3.5
1 2
R19 0_ 0402_5%R19 0_ 0402_5%
1 2
@
@
R28 0_ 0402_5%
R28 0_ 0402_5%
+3VL
R1119
R1119
100K_04 02_5%@
100K_04 02_5%@
1 2
For S3.5
D56
D56
2
1
3
DAN202U T106_SC70-3
DAN202U T106_SC70-3
NOVO_BT N#
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
Security Class ification
Security Class ification
Security Class ification
2011/11/ 01 2012/12/ 31
2011/11/ 01 2012/12/ 31
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/11/ 01 2012/12/ 31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics,Ltd.
Compal Electronics,Ltd.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics,Ltd.
other IO connector
other IO connector
other IO connector
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
50 65Tuesday, March 20, 2 012
50 65Tuesday, March 20, 2 012
50 65Tuesday, March 20, 2 012
0.2
0.2
0.2
Page 51
A
B
C
D
E
+5VALW to +5VS +1.5V to +1.5VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+5VALW
U46
U46
8
7
1
1 1
2 2
3 3
C836
C836
2
10U_0805_10V6K
10U_0805_10V6K
PCH_PWR_EN<45>
PM_SLP_SUS#
AOAC_ON<45>
6
5
PCH_PWR_EN#_R
1
2
3
AP4800BGM-HF
AP4800BGM-HF
4
1
C842
C842
0.01U_0402_25V7K
0.01U_0402_25V7K
2
PCH_PWR_EN
PM_SLP_SUS#
AOAC_ON
+5VS
1 2
82K_0402_5%
82K_0402_5%
R60
R60
100K_0402_5%
100K_0402_5%
R117
0_0402_5%
0_0402_5%
R1448
0_0402_5%
0_0402_5%
AOAC_ON#<37>
R1453
R1453
0_0402_5%
0_0402_5%
1
C837
C837
10U_0603_6.3V6M
10U_0603_6.3V6M
2
R1088
R1088
R1484
R1484
820K_0402_5%
820K_0402_5%
1 2
1 2
DS3@R117
DS3@
@R1448
@
100K_0402_5%
100K_0402_5%
AOAC@
AOAC@
1 2
100K_0402_5%
100K_0402_5%
5VS_GATE5VS_GATE_R
12
@
@
100K_0402_5%
100K_0402_5%
PCH_PWR_EN#
12
R1121
100K_0402_5%
100K_0402_5%
AOAC_ON#
R1123
1
C838
C838
1U_0603_10V4Z
1U_0603_10V4Z
2
150K_0402_5%
150K_0402_5%
61
D
D
S
S
+5VALW
R1120
R1120
2
G
G
12
DS3@R1121
DS3@
+5VALW
R1122
R1122
2
G
G
12
AOAC@R1123
AOAC@
470_0603_5%
470_0603_5%
R1085
R1085
2
G
G
Q99A
Q99A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
12
13
D
D
S
S
12
13
D
D
S
S
+VSB +VSB
SUSP
Q99B
Q99B
DS3@
DS3@
DS3@
DS3@
Q118
Q118
2N7002_SOT23
2N7002_SOT23
AOAC@
AOAC@
AOAC@
AOAC@
Q119
Q119
2N7002_SOT23
2N7002_SOT23
12
R1475
R1475
@
@
34
D
D
5
G
G
S
S
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PCH_PWR_EN#_R PCH_PWR_EN#_R
+V1.05S_VCCP_PWRGOOD<56,57>
+3VALW to +3VS
AP4800BGM
VGS=10V, ID=9A, Rds=18m ohm
VGS=+-25V
+3VALW
1
C839
C839
2
10U_0805_10V6K
10U_0805_10V6K
U47
U47
8
7
6
5
+3VS
1
2
3
AP4800BGM-HF
AP4800BGM-HF
4
1
C843
C843
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C840
C840
10U_0603_6.3V6M
10U_0603_6.3V6M
2
R1089
R1089
1 2
0_0402_5%
0_0402_5%
820K_0402_5%
820K_0402_5%
R1483
R1483
3VS_GATE3VS_GATE_R
12
@
@
1
C841
C841
1U_0603_10V4Z
1U_0603_10V4Z
2
470K_0402_5%
470K_0402_5%
61
D
D
S
S
470_0603_5%
470_0603_5%
R1086
R1086
12
2
SUSP
G
G
Q100A
Q100A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q100B
Q100B
12
R1474
R1474
@
@
34
D
D
5
G
G
S
S
+3VALW to +3V_PCH +5VALW to +5V_PCH
+3VALW +3V _PCH +5VALW +5V_PCH
C1065
C1065
1
2
DS3@
DS3@
J11
@J11
@
2
112
JUMP_43X79
JUMP_43X79
Q148
Q148
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
DS3@
DS3@
G
G
2
DS3@ C1066
DS3@
100K_0402_5%
100K_0402_5%
SUSP
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
C38
@C38
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1. C38, C39 resistance change to 0.1u_0402
2. and the BOM structure as "@" for discharge
1
C1066
0.01U_0402_25V7K
0.01U_0402_25V7K
2
R6
R6
100K_0402_5%
100K_0402_5%
0.75VR_EN#<57>
R8
@R8
@
Q144A
Q144A
12
0.75VR_EN
2
G
G
5
G
G
61
D
D
@
@
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
+3VALW
12
34
0.1U_0402_16V4Z
0.1U_0402_16V4Z
@
@
D
D
@
@
Q144B
Q144B
S
S
C1067
C1067
+3VS to +3VS_VGA
For S3 CPU Power Saving
1
2
DS3@
DS3@
DGPU_PWR_EN<18,23>
J14
@J14
@
112
JUMP_43X79
JUMP_43X79
Q149
Q149
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
DS3@
DS3@
G
G
2
2
DS3@ C1068
DS3@
DGPU_PWR_EN#<25>
SUSP#
1
C39
@C39
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C1068
0.01U_0402_25V7K
0.01U_0402_25V7K
2
R1452
R1452
12
0_0402_5%
0_0402_5%
R1454
R1454
100K_0402_5%
100K_0402_5%
2
G
G
R1449
R1449
47K_0402_5%
47K_0402_5%
2
G
G
12
10U_0805_10V6K
10U_0805_10V6K
+3VALW
12
R1087
R1087
100K_0402_5%
100K_0402_5%
61
D
D
S
S
+5VALW
12
61
D
D
Q146A
Q146A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
+1.5V +1.5VS
1
C856
C856
2
SI2301BDS-T1-E3_SOT23-3
SI2301BDS-T1-E3_SOT23-3
R1090
R1090
12
1.5VS_GATE
0_0402_5%
0_0402_5%
Q101A
Q101A
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
100K_0402_5%
100K_0402_5%
SUSP<10,37,55,57>
SUSP#<32,45,55,57,58>
Q107A
C1058
C1058
C1011
C1011
Q107A
+3VS
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R1451
R1451
1 2
100K_0402_5%
100K_0402_5%
0.1U_0402_10V7K @
0.1U_0402_10V7K @
J15
@J15
@
+1.5V_CPU_VDDQ +1.5VS
S
S
D
D
13
C845
C845
.1U_0402_16V7K
.1U_0402_16V7K
12
61
D
D
S
S
1
C857
C857
10U_0603_6.3V6M
10U_0603_6.3V6M
2
Q120
Q120
G
G
2
1
2
+5VALW +0.75VS
R1097
R1097
SUSP
2
G
G
2
112
JUMP_43X79
JUMP_43X79
1.5VS_GATE
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
12
R1094
R1094
22_0603_5%
22_0603_5%
34
D
D
5
G
G
Q107B
Q107B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
S
S
1
C835
C835
1U_0603_10V4Z
1U_0603_10V4Z
2
470_0603_5%
470_0603_5%
SUSP
5
G
G
Q101B
Q101B
R1481
R1481
For Intel S3 Po wer Reduction.
+3VS_VGA
Q145
Q145
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
1
2
1
2
G
G
2
DGPU_PWR_EN#
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
1
C1059
C1059
0.01U_0402_25V7K
0.01U_0402_25V7K
2
470_0603_5%
470_0603_5%
Q146B
Q146B
5
G
G
R1450
12
@R1450
@
C37
C37
10U_0603_6.3V6M
10U_0603_6.3V6M
34
D
D
S
S
12
@
@
34
D
D
S
S
2
1
C1062
C1062
C1012
C1012
+3VS
1
2
1
2
+3VS to +3VS_SLI
+5VALW
12
0.1U_0402_16V4Z
R1502
R1502
47K_0402_5%
47K_0402_5%
4 4
S_DGPU_PWR_EN<19,32>
S_DGPU_PWR_EN#<32>
R1503
R1503
0_0402_5%
0_0402_5%
100K_0402_5%
100K_0402_5%
A
12
R1501
R1501
2
G
G
12
0.1U_0402_16V4Z
R1513
R1513
1 2
100K_0402_5%
100K_0402_5%
61
D
D
0.1U_0402_10V7K @
0.1U_0402_10V7K @
Q150A
Q150A
S
S
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q147
Q147
AO3413_SOT23
AO3413_SOT23
D
S
D
S
13
G
G
2
S_DGPU_PWR_EN#
B
+3VS_SLI
1
C1063
C1063
0.01U_0402_25V7K
0.01U_0402_25V7K
2
470_0603_5%
470_0603_5%
5
Q150B
2N7002KDWH_SOT363-6
2N7002KDWH_SOT363-6
Q150B
G
G
R1500
12
@R1500
@
C48
C48
10U_0603_6.3V6M
10U_0603_6.3V6M
34
D
D
S
S
2
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
2011/11/01 2012/12/31
2011/11/01 2012/12/31
2011/11/01 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
DC Interface
DC Interface
DC Interface
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
E
51 65Tuesday, March 20, 2012
51 65Tuesday, March 20, 2012
51 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 52
5
4
3
2
1
DC030006J00
PL1
PF1
PF1
12A_65V_451012MRL
4
4
3
3
2
4602-Q04C-09R 4P P2.5@
4602-Q04C-09R 4P P2.5@
JDCIN1
JDCIN1
2
1
1
D D
12A_65V_451012MRL
21
APDIN1APDIN
12
PC1
PC1
SMB3025500YA_2P
SMB3025500YA_2P
12
1000P_0402_50V7K
1000P_0402_50V7K
PL1
1 2
PC2
PC2
100P_0402_50V8J
100P_0402_50V8J
VIN
12
12
PC3
PC3
PC4
PC4
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
1000P_0402_50V7K
VIN
PD1
PD1
LL4148_LL34-2
PD2
PR3
@PR3
@
200_0402_1%
200_0402_1%
1 2
PD2
LL4148_LL34-2
LL4148_LL34-2
PR5
PR5
22K_0402_1%
22K_0402_1%
1 2
+CHGRTC
12
12
PR4
PR4
3.3V
12
PC7
PC7
10U_0603_6.3V6M
10U_0603_6.3V6M
@
@
51ON-2
PC5
PC5
1 2
0.22U_0603_25V7K
0.22U_0603_25V7K
100K_0402_1%
100K_0402_1%
51ON-3
PU1
@PU1
@
APL5156-33DI-TRL_SOT89-3
APL5156-33DI-TRL_SOT89-3
3
VOUT
GND
1
PJ1
PJ1
JUMP_43X39@
JUMP_43X39@
2
112
PQ1
PQ1
TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
2
12
PR9
PR9
200_0603_5%@
200_0603_5%@
2
CHGRTCIN
VIN
12
PC8
PC8
1U_0805_25V6K
1U_0805_25V6K
@
@
C C
+3VLP
PR8
PR8
B B
BATT+
51_ON#<50>
0_0402_5%
0_0402_5%
1 2
LL4148_LL34-2
1 2
51ON-1
12
12
PR2
PR2
PR1
PR1
68_1206_5%
68_1206_5%
68_1206_5%
68_1206_5%
13
12
PC6
PC6
0.1U_0603_25V7K
0.1U_0603_25V7K
VS
JRTC1
JRTC1
- +
MAXEL_ML1220T10@
MAXEL_ML1220T10@
PR6
PR6
560_0603_5%
560_0603_5%
1 2
12
PR7
PR7
560_0603_5%
560_0603_5%
1 2
PD3
PD3
12
+RTCBATT
RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
RB751V-40_SOD323-2
RB751V-40_SOD323-2
PD4
PD4
+CHGRTC
RTC Battery
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
Vin Detector
Vin Detector
Vin Detector
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Y490-LA8691P
1
52 65Tuesday, March 20, 2012
52 65Tuesday, March 20, 2012
52 65Tuesday, March 20, 2012
0.1
0.1
0.1
Page 53
5
4
3
2
1
JBATT1
VMB2
JBATT1
1
1
2
2
3
EC_SMCA
3
4
EC_SMDA
4
5
D D
C C
5
6
6
7
7
8
GND
9
GND
TYCO_1775789-1
TYCO_1775789-1
@
@
12
12
PR10
PR10
PR11
PR11
100_0402_1%
100_0402_1%
100_0402_1%
100_0402_1%
PF2
PF2
12A_65V_451012MRL
12A_65V_451012MRL
1 2
PR12
PR12
6.49K_0402_1%
6.49K_0402_1%
<BOM Structure>
<BOM Structure>
1 2
PR14
PR14
10K_0402_5%
10K_0402_5%
<BOM Structure>
<BOM Structure>
21
VMB
+3VALW
PL2
PL2
SMB3025500YA_2P
SMB3025500YA_2P
1 2
12
PC9
PC9
1000P_0402_50V7K
1000P_0402_50V7K
EC_SMB_CK1 <45,49,62>
EC_SMB_DA1 <45,49,62>
BATT_TEMP <45>
A/D
BATT+
12
PC10
PC10
0.01U_0402_25V7K
0.01U_0402_25V7K
PH1 under CPU botten side :
CPU thermal protection at 92+-3 degree C
Recovery at 56 +-3 degree C
VL
12
PC11
PC11
+3VS
0.1U_0603_25V7K
H_PROCHOT#< 45,6>
PQ3
PQ3
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PROCHOT<45>
0.1U_0603_25V7K
PR18
PR18
1 2
13
D
D
S
S
2
ADP_OCP_1
G
G
PR22
0_0402_5%
0_0402_5%
1 2
100K_0402_1%
100K_0402_1%
@PR22
@
OTP_N_003
0_0402_5%
0_0402_5%
PR23
PR23
PU2
PU2
1
VCC
2
GND
3
OT1
4
OT2
G718TM1U_SOT23-8
G718TM1U_SOT23-8
TMSNS1
RHYST1
TMSNS2
RHYST2
12
ADP_I<45,62>
8
7
OTP_N_002
6
5
ADP_OCP_2
MAINPWON <54>
For KB930 --> Keep PU1 circuit
(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU1 circuit, but keep PR206
PH201, PR205,PR211,PQ201,PR208,PR212
+3VLP
@
@
PR19
PR19
10K_0402_1%
10K_0402_1%
PR21
PR21
1 2
10K_0402_1%
10K_0402_1%
12
PR16
PR16
13.7K_0402_1%
13.7K_0402_1%
12
12
PR17
PR17
21.5K_0402_1%
21.5K_0402_1%
12
PH1
PH1
PR15
PR15
4.42K_0402_1%
4.42K_0402_1%
Turbo_V
1 2
PR20
PR20
57.6K_0402_1%
57.6K_0402_1%
PR210
57.6K:90W
PR205
4.42K:90W
9.1K:120W
16.5K:170W
1 2
82.5K:120W
76.8K:170W
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
B B
VMB2
PR27
PR27
768K_0402_1%
768K_0402_1%
PR29
PR29
10K_0402_1%
10K_0402_1%
1 2
1 2
PR31
PR31
221K_0402_1%
221K_0402_1%
1 2
A A
5
12
P2
PC12
PC12
0.01U_0402_25V7K
0.01U_0402_25V7K
8
3
P
+
2
-
G
4
PR34
@PR34
@
10K_0402_1%
10K_0402_1%
PR36
PR36
10K_0402_1%
10K_0402_1%
PR28
PR28
10M_0402_5%
10M_0402_5%
1 2
1
O
PU3A
PU3A
AS393MTR-E1 SO 8P OP
AS393MTR-E1 SO 8P OP
12
+CHGRTC
12
2VREF_8205
BATT_LEN#<45>
PR24
PR24
1 2
100K_0402_1%
100K_0402_1%
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PR37
PR37
10K_0402_1%
10K_0402_1%
PQ5
PQ5
2
G
G
+3VALW
PR35
PR35
12
PR25
PR25
1 2
+3VALW+3VALW
1 2
100K_0402_1%
100K_0402_1%
13
D
D
S
S
100K_0402_1%
100K_0402_1%
2
G
G
4
PQ7
PQ7
13
D
D
2N7002KW_SOT323-3
2N7002KW_SOT323-3
S
S
BATT_OUT <62>
PQ4
PQ4
TP0610K-T1-E3_SOT23-3
TP0610K-T1-E3_SOT23-3
B+
VL
PR32
PR32
100K_0402_1%
100K_0402_1%
SPOK<54>
PR33
PR33
1 2
1K_0402_1%
1K_0402_1%
1 2
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
22K_0402_1%
22K_0402_1%
13
D
D
2
G
G
S
S
PC15
PC15
1U_0402_6.3V6K
1U_0402_6.3V6K
2010/06/30 2012/12/31
2010/06/30 2012/12/31
2010/06/30 2012/12/31
12
PR26
PR26
PR30
PR30
1 2
PQ6
PQ6
2N7002KW_SOT323-3
2N7002KW_SOT323-3
Compal Secret Data
Compal Secret Data
Compal Secret Data
12
100K_0402_1%
100K_0402_1%
Deciphered Date
Deciphered Date
Deciphered Date
PC13
PC13
0.22U_0603_25V7K
0.22U_0603_25V7K
13
2
2
12
PC14
PC14
0.1U_0603_25V7K
0.1U_0603_25V7K
+VSBP
+VSBP
PJ2
PJ2
JUMP_43X39@
JUMP_43X39@
2
112
Compal Electronics, Inc.
Title
Title
Title
BATTERY CONN/OTP
BATTERY CONN/OTP
BATTERY CONN/OTP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+VSB
Y490-LA8691P
1
0.1
0.1
53 65Tuesday, March 20, 2012
53 65Tuesday, March 20, 2012
53 65Tuesday, March 20, 2012
0.1
Page 54
5
Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO
4
3
2
1
2VREF_8205
+3VALW P + 3VALW
D D
PR38
PR38
13K_040 2_1%
13K_040 2_1%
1 2
PR40
154K_04 02_1%
154K_04 02_1%
BST_3V
UG_3V
LX_3V
LG_3V
PC35
PC35
1U_0603_10V6K
1U_0603_10V6K
PR50
PR50
0_0402_ 5%
0_0402_ 5%
PR52
0_0402_ 5%
0_0402_ 5%
PR54
0_0402_ 5%
0_0402_ 5%
PR40
20K_040 2_1%
20K_040 2_1%
1 2
PR43
PR43
1 2
PU4
PU4
25
P PAD
7
VO2
8
VREG3
9
BOOT2
10
UGATE2
11
PHASE2
12
LGATE2
12
12
@P R52
@
12
@P R54
@
12
3
RT8205_B+
PJ5
B+
PC22
PC22
C C
B B
ACPRN
A A
PJ5
2
112
JUMP_43 X118@
JUMP_43 X118@
12
12
PC17
0.1U_0603_25V7K
0.1U_0603_25V7K
PC17
0.1U_0603_25V7K
0.1U_0603_25V7K
+3VALWP
2012/02/29
change PC29, PC32,
PC34 from
SGA00001E0J to
SGA00002N8J
PR51
PR51
0_0402_ 5%
EC_ON<45 ,50>
PR56
PR56
2
0_0402_ 5%
PR185
@ PR185
@
0_0402_ 5%
0_0402_ 5%
12
5
MAINPW ON<53>
EC_ON
200K_04 02_1%
200K_04 02_1%
12
PC18
PC18
4.7U_0805_25V6-K
4.7U_0805_25V6-K
13
12
PC19
PC19
PC20
PC20
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
+
+
PC29
PC29
2
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
2N7002K DW-2N_SOT3 63-6
2N7002K DW-2N_SOT3 63-6
12
12
2N7002K W_SOT323 -3
2N7002K W_SOT323 -3
13
D
D
2
G
G
S
S
PQ15
PQ15
DTC115E UA_SC70-3
DTC115E UA_SC70-3
12
PQ8
2200P_0402_50V7K
2200P_0402_50V7K
3.3UH +-20 % PCMC063T-3R3M N 6A
3.3UH +-20 % PCMC063T-3R3M N 6A
AO4466L _SO8
AO4466L _SO8
PL3
PL3
1 2
PQ12A
PQ12A
PQ8
PR46
PR46
PC30
PC30
61
VL
PQ14
PQ14
1 2
VS
PR57
PR57
100K_04 02_1%
100K_04 02_1%
12
PR58
PR58
40.2K_0402_1%
40.2K_0402_1%
6
578
4
123
PR53
PR53
PC38
PC38
578
PQ10
PQ10
AO4712_ SO8
AO4712_ SO8
3 6
241
12
13
2
2.2U_0603_10V6K
2.2U_0603_10V6K
4
12
4.7_1206_5%
4.7_1206_5%
12
680P_0603_50V7K
680P_0603_50V7K
ENTRIP1 ENTRIP2
2
100K_04 02_1%
100K_04 02_1%
12
Typ: 175mA
PR55
@ PR55
@
0_0402_ 5%
0_0402_ 5%
+3VL
PQ12B
PQ12B
34
2N7002K DW-2N_SOT3 63-6
2N7002K DW-2N_SOT3 63-6
5
PQ13
PQ13
DTC115E UA_SC70-3
DTC115E UA_SC70-3
+3VLP
12
12
PC24
PC24
4.7U_0805_10V6K
4.7U_0805_10V6K
PR44
PR44
1 2
1 2
2.2_0603 _5%
2.2_0603 _5%
PC27
PC27
0.1U_060 3_25V7K
0.1U_060 3_25V7K
PR48
PR48
499K_04 02_1%
499K_04 02_1%
1 2
B+
12
PR49
PR49
100K_0402_1%
100K_0402_1%
2VREF_8205
VL
+3.3VALWP Imax=7.5A ; Ipeak=9A
1/2 Delta I=1.113A (F=375K Hz)
Vtrip=0.169V
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Ilimit_min=0.169/18m=9.388A
Ilimit_max=0.169/15=11.26A
Iocp=Ilimit+1/2Delta I=10.5A~12.373A
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
PC16
PC16
1U_0603_10V6K
1U_0603_10V6K
PR39
PR39
30K_040 2_1%
30K_040 2_1%
1 2
PR41
PR41
20K_040 2_1%
20K_040 2_1%
1 2
PR42
PR42
88.7K_04 02_1%
88.7K_04 02_1%
ENTRIP2
3
4
5
6
FB2
TONSEL
ENTRIP2
VFB=2.0V
SKIPSEL
EN
14
15
13
RT8205_ B+
12
2010/06/ 30 2012/12/ 31
2010/06/ 30 2012/12/ 31
2010/06/ 30 2012/12/ 31
1 2
ENTRIP1
2
1
FB1
REF
ENTRIP1
24
VO1
23
PGOOD
22
BOOT1
21
UGATE1
20
PHASE1
19
LGATE1
RT8205L ZQW_W QFN24_4X4
RT8205L ZQW_W QFN24_4X4
NC18VREG5
VIN16GND
17
12
PC37
PC37
0.1U_0603_25V7K
0.1U_0603_25V7K
Compal Secret Data
Compal Secret Data
Compal Secret Data
VL
Typ: 175mA
PC36
PC36
4.7U_0805_10V6K
4.7U_0805_10V6K
Deciphered Date
Deciphered Date
Deciphered Date
BST_5V
UG_5V
LX_5V
LG_5V
RT8205_ B+
12
PC23
PC23
PC21
PC21
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
SPOK <53>
PR45
PR45
PC28
2.2_0603 _5%
2.2_0603 _5%
1 2
PC28
0.1U_060 3_25V7K
0.1U_060 3_25V7K
1 2
RT8205
TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP)
(2)SMPS2=375KHZ(+3VALWP)
TPS51125A
TONSEL=VREF (1) SMPS1=245KHZ ( +5VALWP)
(2) SMPS2=305KHZ(+ 3VALWP)
+5VALWP Imax=11.1A ; Ipeak=13.32A
1/2 Delta I=1.33A (F=300K Hz)
Vtrip=0.098V
Rds(on)=7.0m ohm(max) ; Rds(on)=5.1m ohm(typical)
Ilimit_min=0.098/7m=14.03A
Ilimit_max=0.098/5.1m=19.21A
Iocp=Ilimit+1/2Delta I=15.36A ~ 20.54A
2
+5VALW P + 5VALW
12
12
12
PC26
PC26
PC25
PC25
0.1U_0603_25V7K
0.1U_0603_25V7K
2200P_0402_50V7K
2200P_0402_50V7K
AO4456_ SO8
AO4456_ SO8
578
3 6
5
4
Compal Electronics, Inc.
Title
Title
Title
3VALWP/5VALWP
3VALWP/5VALWP
3VALWP/5VALWP
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PJ3
PJ3
2
112
JUMP_43 X118@
JUMP_43 X118@
PJ4
PJ4
2
112
JUMP_43 X118
JUMP_43 X118
@
@
PQ9
PQ9
AO4406A L_SO8
AO4406A L_SO8
241
PL4
12
12
PL4
1 2
PR47
PR47
4.7_1206_5%
4.7_1206_5%
PC33
PC33
680P_0603_50V7K
680P_0603_50V7K
4.7UH_VM PI1004AR-4R7M-Z01 _10A_20%
4.7UH_VM PI1004AR-4R7M-Z01 _10A_20%
786
PQ11
PQ11
123
Y490-LA8691P
1
+5VALWP
1
1
12
PC32
PC32
PC31
PC31
1U_0603_10V6K@
1U_0603_10V6K@
54 65Tuesday, March 20, 2 012
54 65Tuesday, March 20, 2 012
54 65Tuesday, March 20, 2 012
+
+
+
+
PC34
PC34
2
2
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
150U_B2_6.3VM_R35M
0.1
0.1
0.1
Page 55
A
Freq= 266~314KHz , 290KHz(typ)
Iocp=13.58A~23.10A
PR59
PR59
0_0402_5%
0_0402_5%
1 1
2 2
FBVDDQ_PWR_EN
SUSP#
3 3
Freq= 266~314KHz , 290KHz(typ)
Iocp=12.25A~20.77A
4 4
SYSON<45>
1 2
PR67
PR67
0_0402_5%
0_0402_5%
1 2
PR68
PR68
0_0402_5%@
0_0402_5%@
1 2
DGPU_PWROK<19,27,32,58>
A
@PR69
@
PR69
PR60
PR60
47K_0402_5%
47K_0402_5%
47K_0402_5%
47K_0402_5%
1 2
1 2
SUSP#
@
@
12
PC44
PC44
.1U_0402_16V7K
.1U_0402_16V7K
12
PR63
PR63
PR65
PR65
1 2
12
11.5K_0402_1%
11.5K_0402_1%
PR66
PR66
10K_0402_1%
10K_0402_1%
@
@
12
PC54
PC54
.1U_0402_16V7K
.1U_0402_16V7K
12
PR72
PR72
75K_0402_1%
75K_0402_1%
PR74
PR74
1 2
12
11.5K_0402_1%
11.5K_0402_1%
PR76
PR76
10K_0402_1%
10K_0402_1%
PR82
PR82
0_0402_5%
0_0402_5%
1 2
PR83
PR83
0_0402_5%@
0_0402_5%@
1 2
12
PC64
PC64
PR64
PR64
84.5K_0402_1%
84.5K_0402_1%
1 2
PR73
PR73
1 2
+5VALW
12
34
PQ22B
PQ22B
5
1U_0603_10V6K@
1U_0603_10V6K@
1
2
3
4
5
470K_0402_1%
470K_0402_1%
1
PGOOD
2
TRIP
3
EN
4
VFB
5
RF
TPS51212DSCR_SON10_3X 3
TPS51212DSCR_SON10_3X 3
470K_0402_1%
470K_0402_1%
PR78
PR78
10K_0402_1%
10K_0402_1%
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
B
PU5
PU5
PGOOD
TRIP
EN
VFB
RF
TPS51212DSCR_SON10_3X 3
TPS51212DSCR_SON10_3X 3
VFB=0.7V
PU6
PU6
VBST
DRVH
V5IN
DRVL
VBST
DRVH
V5IN
DRVL
SW
TP
10
9
8
SW
7
6
11
TP
10
9
8
7
6
11
VFB=0.7V
+5VALW
PQ22A
PQ22A
2
B
C
578
5
4
5
PQ18
PQ18
4
5
PQ19
PQ19
4
+1.05VS_VGA
1
2
12
3
PC61
PC61
10U_0805_25V6K
10U_0805_25V6K
Compal Secret Data
Compal Secret Data
Compal Secret Data
3 6
1 2
1 2
PC45
PR61
PR61
2.2_0603_5%
2.2_0603_5%
1 2
BST_1.5V
DH_1.5V
LX_1.5V
DL_1.5V
BST_1.5VSP_VGA
DH_1.5VSP_VGA
LX_1.5VSP_VGA
DL_1.5VSP_VGA
12
PR79
PR79
100K_0402_1%
100K_0402_1%
1 2
61
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
12
PR70
PR70
2.2_0603_5%
2.2_0603_5%
1 2
BST_1.5VSP_VGA-1
12
1U_0603_10V6K
1U_0603_10V6K
12
PC60
PC60
10U_0805_25V6K
10U_0805_25V6K
PR81
PR81
100K_0402_1%
100K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
0.22U_0603_16V7K
0.22U_0603_16V7K
BST_1.5V-1
+5VALW
PC47
PC47
1U_0603_10V6K
1U_0603_10V6K
PC55
PC55
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
+5VALW
PC57
PC57
AON6504_POW ERDFN56-8-5
AON6504_POW ERDFN56-8-5
+1.05VS
12
PC63
PC63
0.01u_0603_10V6K
0.01u_0603_10V6K
PC45
1 2
8
PQ20
PQ20
7
6
5
4
AO4456_SO8
AO4456_SO8
SUSP<10,37,51,57>
2010/06/30 2012/12/31
2010/06/30 2012/12/31
2010/06/30 2012/12/31
1.5V_B+
PQ16
PQ16
AO4406AL_SO8
AO4406AL_SO8
241
786
PQ17
PQ17
AO4456_SO8
AO4456_SO8
123
1.5VSP_VGA_B+
MDV1525URH_PDFN33- 8-5
MDV1525URH_PDFN33- 8-5
123
12
12
123
12
PC62
PC62
1U_0603_10V6K
1U_0603_10V6K
PR80
PR80
0_0402_5%@
0_0402_5%@
PR84
PR84
0_0402_5%@
0_0402_5%@
Deciphered Date
Deciphered Date
Deciphered Date
C
2
G
G
12
PC39
PC39
10U_0805_25V6K
10U_0805_25V6K
S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
S COIL 1UH +-20% VMPI0703AR-1R0M-Z01 11A
1 2
12
@PR62
@
PR62
4.7_1206_5%
4.7_1206_5%
@PC48
@
12
PC48
1000P_0603_50V7K
1000P_0603_50V7K
12
PC50
PC50
PC49
PC49
10U_0805_25V6K
10U_0805_25V6K
PL6
PL6
1UH_PCMC063T-1R0M N_11A_20%
1UH_PCMC063T-1R0M N_11A_20%
1 2
@PR71
@
PR71
4.7_1206_5%
4.7_1206_5%
@PC59
@
PC59
1000P_0603_50V7K
1000P_0603_50V7K
PR77
PR77
1 2
470K_0603_5%@
470K_0603_5%@
PQ21
PQ21
13
D
D
2N7002KW_S OT323-3
2N7002KW_S OT323-3
S
S
PJ6
PJ6
2
JUMP_43X118@
12
PC40
PC40
10U_0805_25V6K
10U_0805_25V6K
PL5
PL5
12
12
<BOM Struct ure>
<BOM Struct ure>
PC42
PC42
PC41
PC41
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_50V7K
2200P_0402_50V7K
JUMP_43X118@
12
PC43
PC43
470P_0603_50V7K
470P_0603_50V7K
D
112
B+
+1.5VP
1
+
+
PC46
PC46
2
PJ7
PJ7
220U_B2_6.3VM_R15M
220U_B2_6.3VM_R15M
12
10U_0805_25V6K
10U_0805_25V6K
12
12
PC52
PC52
PC51
PC51
0.1U_0402_25V6
0.1U_0402_25V6
12
<BOM Struct ure>
<BOM Struct ure>
PC53
PC53
2200P_0402_50V7K
2200P_0402_50V7K
+1.5VP
470P_0603_50V7K
470P_0603_50V7K
PJ8
PJ8
2
JUMP_43X118@
JUMP_43X118@
2
112
JUMP_43X118@
JUMP_43X118@
112
B+
+1.5V
+1.5VSP_VGA
1
+
+
PC56
PC56
1 2
2
PC58
PC58
0.1U_0402_10V7K
220U_B2_6.3VM_R15M
220U_B2_6.3VM_R15M
PJ10
PJ10
2
112
JUMP_43X118@
JUMP_43X118@
@
@
0.1U_0402_10V7K
+1.5VSP_VGA
PR75
PR75
0_0402_5%
0_0402_5%
+1.05VS_VGA+1.05VS
Compal Electronics, Inc.
Title
Title
Title
1.5VP/1.5VSP_VGA/1.05VSP_VGA
1.5VP/1.5VSP_VGA/1.05VSP_VGA
1.5VP/1.5VSP_VGA/1.05VSP_VGA
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PJ9
PJ9
2
112
JUMP_43X118@
JUMP_43X118@
12
Y490-LA8691P
D
+1.5VS_VGA
VDDQ_SENSE <25>
55 65Tuesday, March 20, 2012
55 65Tuesday, March 20, 2012
55 65Tuesday, March 20, 2012
0.2
0.2
0.2
Page 56
5
VID [0] VID[1] VCCSA Vout
0 0 0.9V
0 1 0.8V
1 0 0.725V
1 1 0.675V
output voltage adjustable network
D D
1
PC78
PC78
PC77
PC77
1 2
2
2200P_0402_50V7K
2200P_0402_50V7K
0.1U_0603_25V7K
PJ12
PJ12
2
+3VALW
C C
JUMP_43X118@
JUMP_43X118@
+VCCSA_PWR_SRC
112
0.1U_0603_25V7K
2
2
PC80
PC80
PC79
PC79
1
1
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2.2U_0603_10V7K
2.2U_0603_10V7K
+VCCSA_PWR_SRC
4
PC66
PC66
1 2
PC81
PC81
0.22U_0402_10V6K
0.22U_0402_10V6K
SA_PGOOD<45>
+5VALW
12
3300P_0402_50V7K
3300P_0402_50V7K
10_0402_1%
10_0402_1%
19
20
21
22
23
24
PC82
PC82
PR88
PR88
PU7
PU7
12
PGND
PGND
PGND
VIN
VIN
VIN
4.99K_0402_1%
4.99K_0402_1%
+3VS
12
PR86
PR86
100K_0402_5%
100K_0402_5%
SA_PGOOD
PC65
PC65
1 2
1U_0603_10V6K
1U_0603_10V6K
12
18
16
17
V5FILT
V5DRV
PGOOD
TPS51461RGER_QFN24_4X4
TPS51461RGER_QFN24_4X4
COMP
GND
VREF
3
1
2
12
PR94
PR94
PC83
PC83
3
PR85
PR85
1K_0402_1%
1K_0402_1%
12
H_VCCSA_VID1 <10>
12
+VCCSA_BT
+VCCSA_PHASE
PR92
@ PR92
@
33K_0402_5%
33K_0402_5%
H_VCCSA_VID0 <10>
PR89
PR89
0_0402_5%
0_0402_5%
1 2
PR90
PR90
2.2_0603_5%
2.2_0603_5%
1 2
+VCCSA_BT_1
12
PC68
PC68
1000P_0603_50V7K
1000P_0603_50V7K
12
PR91
PR91
4.7_1206_5%
4.7_1206_5%
12
+V1.05S_VCCP_PWRGOOD <51,57>
PC67
PC67
0.22U_0603_16V7K
0.22U_0603_16V7K
1 2
PR87
PR87
1K_0402_1%
1K_0402_1%
H_VCCSA_VID0
H_VCCSA_VID1
15
VID1
SLEW
4
1 2
0.01U_0402_25V7K
0.01U_0402_25V7K
+VCCSA_EN
13
14
EN
VID0
12
BST
11
SW
10
SW
9
SW
8
SW
7
SW
25
TP
VOUT
MODE
5
6
+VCC_SAP
TDC 4.2A
Peak Current 6 A
OCP current 7.2 A
The 1k PD on the VCCSA VIDs are empty.
These should be stuffed to ensure that
VCCSA VID is 00 prior to VCCIO stability.
PL7
PL7
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
0.47UH_FDVE0630-H-R47M=P3_17.7A_20%
1 2
2
+VCCSAP
1 2
PAD-OPEN 4x4m
PAD-OPEN 4x4m
1
PJ11
PJ11
+VCCSA
+VCCSAP
@
@
@
@
@
12
PC70
PC70
PC69
PC69
1 2
1 2
PC71
PC71
0.1U_0402_10V7K
0.1U_0402_10V7K
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PR93
PR93
100_0402_5%
100_0402_5%
PR95
PR95
0_0402_5%
0_0402_5%
PC73
PC73
PC72
PC72
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
12
12
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
@
@
12
PC74
PC74
2200P_0402_50V7K
2200P_0402_50V7K
+VCCSA_SENSE <10>
@
PC75
PC75
PC76
PC76
1 2
1 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
5
4
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Title
Title
Title
VCCSAP/1.05S_VCCPP
VCCSAP/1.05S_VCCPP
VCCSAP/1.05S_VCCPP
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y490-LA8691P
1
56 65Tuesday, March 20, 2012
56 65Tuesday, March 20, 2012
56 65Tuesday, March 20, 2012
0.1
0.1
0.1
Page 57
5
PL8
PL8
HCB1608 KF-121T30_060 3
HCB1608 KF-121T30_060 3
+5VALW
D D
1 2
SUSP#<32,45,51,55,58>
C C
0.75VR_EN#<51>
SUSP<10,37,51,55>
1.8VSP_V IN
12
PC84
PC84
22U_080 5_6.3VAM
22U_080 5_6.3VAM
PR98
PR98
1 2
0_0402_ 5%
0_0402_ 5%
EN_1.8VS P
PR99
PR99
1M_0402 _5%
1M_0402 _5%
PR102
PR102
0_0402_ 5%@
0_0402_ 5%@
1 2
PR103
PR103
47K_040 2_1%
47K_040 2_1%
1 2
2012/02/29
change PR103 from 33k to 47k
PR105
PR105
0_0402_ 5%
0_0402_ 5%
PC100
PC100
0.1U_0402_25V6
0.1U_0402_25V6
1 2
12
PR114
PR114
1 2
10_0402 _1%
10_0402 _1%
12
PR106
PR106
1 2
PR111
PR111
1 2
10.7K_0402_1%
10.7K_0402_1%
PR112
PR112
1 2
1 2
12K_0402_1%
12K_0402_1%
PC109
PC109
1 2
PC97
PC97
10K_0402_1%@
10K_0402_1%@
.1U_0402_16V7K@
.1U_0402_16V7K@
PR108
PR108
0_0402_ 5%
0_0402_ 5%
1 2
PC104
PC104
0.01U_04 02_25V7K
0.01U_04 02_25V7K
@PR116
@
PR116
0_0402_5%
0_0402_5%
1 2
1000P_0402_50V7K
1000P_0402_50V7K
0.01U_04 02_25V7K
0.01U_04 02_25V7K
PC110
PC110
1000P_0 402_50V7K
1000P_0 402_50V7K
1 2
SUSP#
B B
VCCIO_SEN SE<9>
A A
+V1.05S_VCCP_PW RGOOD<51,56>
5
PC96
PC96
1
2
3
4
PC107
PC107
1 2
4
@PC89
@
12
1 2
0.1U_0402_10V7K
0.1U_0402_10V7K
PC89
2
G
G
12
+3VS
PR107
PR107
100K_0402_1%
100K_0402_1%
17
PU10
PU10
PAD
VREF
REFIN
TPS5121 9RTER_QFN16_ 3X3
TPS5121 9RTER_QFN16_ 3X3
GSNS
VSNS
COMP5TRIP6GND
PR117
PR117
1 2
10_0402 _1%
10_0402 _1%
4
PU8 SY8033BDBC_ DFN10_3X3PU8 SY8033BDBC_ DFN10_3X3
4
10
PVIN
9
PVIN
8
SVIN
5
EN
2
LX
PG
3
LX
6
FB
TP
NC
NC
7
1
11
+1.5V
0.1U_0402_10V7K
0.1U_0402_10V7K
13
D
D
PQ23
PQ23
2N7002K W_SOT323 -3
2N7002K W_SOT323 -3
S
S
1 2
PR109
PR109
100K_0402_1%
100K_0402_1%
MODE
7
BST_1.05 VS_VCCP
13
BST
SW
DH
DL
V5
PGND
8
1 2
16
15EN14
PGOOD
12
PR115
PR115
54.9K_0402_1%
54.9K_0402_1%
1.8VSP_LX
FB=0.6Volt
1
PJ15
PJ15
1
JUMP_43 X118
JUMP_43 X118
@
@
2
2
PC90
PC90
4.7U_080 5_6.3V6K
4.7U_080 5_6.3V6K
PR101
PR101
1 2
1K_0402 _1%
1K_0402 _1%
3
PL9
PL9
1UH_PH0 41H-1R0MS_3.8A _20%
1UH_PH0 41H-1R0MS_3.8A _20%
1 2
12
20K_040 2_1%
20K_040 2_1%
PR96
PR96
4.7_1206_5%
4.7_1206_5%
12
PC86
PC86
1.8VSP_F B
680P_0603_50V7K
680P_0603_50V7K
10K_040 2_1%
10K_040 2_1%
12
12
PR104
PR104
12
PC95
PC95
1K_0402_1%
1K_0402_1%
0.1U_0402_16V4Z
0.1U_0402_16V4Z
PR97
PR97
PR100
PR100
PC93
PC93
10U_0603_6.3V6M
10U_0603_6.3V6M
12
12
PU9
PU9
1
VIN
2
GND
3
VREF
4
VOUT
APL5336 KAI-TRL_SOP8P8
APL5336 KAI-TRL_SOP8P8
+0.75VSP
12
12
PC94
PC94
12
PC85
PC85
12
68P_0402_50V8J
68P_0402_50V8J
8
NC
7
NC
6
VCNTL
5
NC
9
TP
10U_0603_6.3V6M
10U_0603_6.3V6M
12
PC87
PC87
22U_0805_6.3VAM
22U_0805_6.3VAM
12
PC88
PC88
22U_0805_6.3VAM
22U_0805_6.3VAM
+3VALW
PC91
PC91
1U_0603 _10V6K
1U_0603 _10V6K
2
+1.8VSP
+1.05VS_VCCPP OCP(min)=22.38A
1.05VS_B +
PL10
PL10
12
12
PC99
PC99
PC102
PC102
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
2200P_0402_50V7K
PC103
PR110
PR110
0_0603_ 5%
0_0603_ 5%
1 2
12
LX_1.05V S_VCCP
11
DH_1.05V S_VCCP
10
9
Security Class ification
Security Class ification
Security Class ification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PC103
0.1U_060 3_25V7K
0.1U_060 3_25V7K
1 2
DL_1.05V S_VCCP
+5VALW
12
PC108
PC108
1U_0603 _10V6K
1U_0603 _10V6K
Compal Secret Data
Compal Secret Data
2010/06/ 30 2012/12/ 31
2010/06/ 30 2012/12/ 31
2010/06/ 30 2012/12/ 31
3
Compal Secret Data
5
4
PQ25
PQ25
5
4
Deciphered Date
Deciphered Date
Deciphered Date
PQ24
PQ24
AON6428 L_DFN8-5
AON6428 L_DFN8-5
123
AON6504 1N DFN
AON6504 1N DFN
123
12
PC101
PC101
0.1U_0402_25V6
0.1U_0402_25V6
1UH_PCM B062D-1R0MS_9 A_20%
1UH_PCM B062D-1R0MS_9 A_20%
1 2
12
PR113
PR113
4.7_1206_5%
4.7_1206_5%
12
PC106
PC106
1000P_0603_50V7K
1000P_0603_50V7K
2
PC98
<BOM Structure>PC98
<BOM Structure>
1
PJ13
PJ13
2
112
JUMP_43 X118
JUMP_43 X118
@
@
PJ14
PJ14
2
112
JUMP_43 X118@
JUMP_43 X118@
PJ16
PJ16
2
112
JUMP_43 X118@
JUMP_43 X118@
PJ17
PJ17
2
112
JUMP_43 X118@
JUMP_43 X118@
PJ18
PJ18
2
112
JUMP_43 X118@
JUMP_43 X118@
12
4.7U_0805_25V6-K
4.7U_0805_25V6-K
B+
+1.8VS+1.8VSP
+0.75VS+0.75VSP
+1.05VS+1.05VS_ VCCPP
+1.05VS_VCCPP
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
PC105
PC105
+
+
2 3
Compal Electronics, Inc.
Title
Title
Title
1.8VSP/0.75VSP/1.05VS_VCCPP
1.8VSP/0.75VSP/1.05VS_VCCPP
1.8VSP/0.75VSP/1.05VS_VCCPP
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Y490-LA8691P
1
57 65Tuesday, March 20, 2 012
57 65Tuesday, March 20, 2 012
57 65Tuesday, March 20, 2 012
0.2
0.2
0.2
Page 58
8
H H
GPU_VID5<23>
GPU_VID4<23>
GPU_VID3<23>
GPU_VID2<23>
GPU_VID1<23>
GPU_VID0<23>
NVDD_PWR_EN<18>
VSSSENSE_VGA<24>
VCCSENSE_VGA<24>
VGA_IMON<45>
27.4_0402_1%
27.4_0402_1%
SUSP#<32,45,51,55,57>
PR157
PR157
5.76K_0402_1%
5.76K_0402_1%
1 2
PC132
PC132
1000P_0402_50V7K
1000P_0402_50V7K
PR169
PR169
0_0402_5%
0_0402_5%
PR176
PR176
@
@
1 2
12
VSS_SEN
12
G G
F F
E E
D D
C C
B B
12
PC131
PC131
PR162
PR162
1.65K_0402_1%
1.65K_0402_1%
VCC_SEN
12
PR170
PR170
0_0402_5%
0_0402_5%
1 2
+VGA_CORE
1 2
PR129 0_0402_5%PR129 0_0402_5%
1 2
DGPU_PWROK<19,27,32, 55>
0.068U_0402_10V6K
0.068U_0402_10V6K
PR177
PR177
27.4_0402_1%
27.4_0402_1%
@
@
PR130
PR156 97.6K_0402_1%@PR156 97.6K_0402_1%@
VCC_SEN_C
1 2
PC133
PC133
12
0_0402_5%
0_0402_5%
@PR130
@
0_0402_5%
0_0402_5%
1 2
1 2
150P_0402_50V8J
150P_0402_50V8J
PC135
PC135
1 2
7
+3VS
12
PR150
PR150
PR152
PR152
12
PC134
PC134
27P_0402_50V8J
27P_0402_50V8J
12
PR163
PR163
150P_0402_50V8J
150P_0402_50V8J
39.2K_0402_1%
39.2K_0402_1%
12
PR174
PR174
1 2
1K_0402_1%
1K_0402_1%
DPRSLPVR_VGA<23>
2012/02/29
change PR164
from 5.49k to
7.87k
3210_EN
3.3K_0402_1%
3.3K_0402_1%
@
@
PR175
PR175
0_0402_5%
0_0402_5%
+VDD33MISC
PU12
PU12
1
EN
2
PWRGD
3
IMON
4
CLKEN#
5
FBRTN
6
FB
7
COMP
8
NC
9
TRDET#
10
DPRSLP
41
AGND
3210_CSCOMP
PR164
PR164
PR180
PR180
80.6K_0402_1%
80.6K_0402_1%
PR138 0_0402_5%PR138 0_0402_5%
PR139 0_0402_5%PR139 0_0402_5%
1 2
1 2
1 2
38
VID139VID040VID5
ILIM11IREF12RPM13RT14RAMP15LLINE
12
7.87K_0402_1%
7.87K_0402_1%
12
PR181
PR181
1000P_0402_50V7K
1000P_0402_50V7K
PR142 0_0402_5%PR142 0_0402_5%
PR141 0_0402_5%PR141 0_0402_5%
PR140 0_0402_5%PR140 0_0402_5%
1 2
1 2
1 2
35
16
@
@
1 2
PR171
PR171
12
59K_0402_1%
59K_0402_1%
6
@
PR119 10K_0402_1%PR119 10K_0402_1%
PR118 10K_0402_1%@PR118 10K_0402_1%
12
12
@
PR127 10K_0402_1% PR127 10K_0402_1%
PR131 10K_0402_1%@PR131 10K_0402_1%
12
12
PR143 0_0402_5%PR143 0_0402_5%
PR144 0_0402_5%PR144 0_0402_5%
+5VS
12
1 2
PSI#
1 2
31NC32
33
VCC
PSI#
VID634VID436VID337VID2
TTSNS
VRTT
DCM#
OD#
PWM1
PWM2
PWM3
SW1
SW2
SW3
CSREF
CSSUM18CSCOMP19GND
ADP3210JCPZ-RL_QFN40_6X6
ADP3210JCPZ-RL_QFN40_6X6
17
20
PR165
PR165
1 2
20K_0402_1%
20K_0402_1%
PC141
PC141
1000P_0402_50V7K
1000P_0402_50V7K
1 2
12
PR183
PR183
PR182
PR182
68.1K_0402_1%
68.1K_0402_1%
357K_0402_1%
357K_0402_1%
PC165
PC165
@
PR120 10K_0402_1%@PR120 10K_0402_1%
12
PR132 10K_0402_1% PR132 10K_0402_1%
12
PR147
PR147
10_0402_1%
10_0402_1%
PR149
PR149
7.32K_0402_1%
7.32K_0402_1%
1 2
PC123
PC123
1U_0603_10V6K
1U_0603_10V6K
30
29
28
27
26
25
24
23
22
21
12
0_0402_5%
0_0402_5%
PC137
PC137
1 2
100P_0402_50V8J
100P_0402_50V8J
3210_CSREF
+VGA_B+
12
1 2
1 2
@
PR122 10K_0402_1%@PR122 10K_0402_1%
PR121 10K_0402_1% PR121 10K_0402_1%
12
12
@
12
PR133 10K_0402_1%@PR133 10K_0402_1%
PR128 10K_0402_1%PR128 10K_0402_1%
12
PSI#
H_PROCHOT#_VGA
DCM#
3210_OD#
A3210_PWM1
A3210_PWM2
PC140
PC140
165K_0402_1%
165K_0402_1%
1200P_0402_50V7K
1200P_0402_50V7K
PR184
PR184
1K_0402_1%
1K_0402_1%
PR123 10K_0402_1%PR123 10K_0402_1%
12
@
12
PR134 10K_0402_1%@PR134 10K_0402_1%
PR137
PR137
1 2
0_0402_5%
0_0402_5%
1 2
PC124
PC124
+5VS
100_0402_1%
100_0402_1%
3210_CSCOMP
PR172
PR172
1 2
PR178
PR178
178K_0603_1%
178K_0603_1%
1 2
PR179
PR179
178K_0603_1%
178K_0603_1%
1 2
5
I_TDC=33.6A
Iccmax= 45A
OCP min=54A
Load line : -1.9 mV/A
FSW=600KHz
PR136
PR136
1K_0402_1%
1K_0402_1%
12
+3VS
DPRSLPVR_VGA
Place PH2 close to hot spot
12
PH2
PH2
100K_0402_5%_TSM0B104J4702RE
100K_0402_5%_TSM0B104J4702RE
0.01U_0402_25V7K
0.01U_0402_25V7K
13
D
D
2
G
G
S
S
PR158
PR158
12
3210_CS_PH1
PR159
PR159
100_0402_1%
100_0402_1%
12
3210_CS_PH2
12
PR168
PR168
73.2K_0402_1%
73.2K_0402_1%
3210_CS_PH1
3210_CS_PH2
PR151100K_0402_5%@PR151100K_0402_5%
12
@
PR153
PR153
12
VGA_AC_DET
@
@
0_0402_5%
0_0402_5%
PQ26
PQ26
@
@
2N7002KW_SOT323-3
2N7002KW_SOT323-3
PH3
PH3
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
1 2
Place PH4 close to
PHASE1 inductor
on the same layer
+3VS
VGA_AC_DET <23,32,45>
4
+VGA_CORE
1
2
12
10
42
VIN
11
VIN
12
VIN
13
VIN
14
VIN
15
VSWH
16
PGND
17
PGND
18
PGND
19
PGND
20
PGND
PGND21PGND22PGND23PGND24PGND25PGND26PGND27PGND28VSWH29VSWH
Near VGA Core
1
12
PC150
PC150
22U_0805_6.3V6M
22U_0805_6.3V6M
12
PC161
PC161
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
12
PC151
PC151
PC152
PC152
2
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
12
12
PC162
PC162
PC163
PC163
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
10
42
VIN
11
VIN
12
VIN
13
VIN
14
VIN
15
VSWH
16
PGND
17
PGND
18
PGND
19
PGND
20
PGND
PGND21PGND22PGND23PGND24PGND25PGND26PGND27PGND28VSWH29VSWH
12
PR154
PR154
PC125
PC125
2_0603_5%
2_0603_5%
0.1U_0603_25V7K
0.1U_0603_25V7K
7
5
8
NC
VIN9VIN
PC160
PC160
PC164
PC164
PHASE
PU13
PU13
NCP5369MNR2G_QFN40_6X6
NCP5369MNR2G_QFN40_6X6
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
CGND
3
PC111
PC111
1 2
7
8
NC
VIN9VIN
PHASE
PU11
PU11
NCP5369MNR2G_QFN40_6X6
NCP5369MNR2G_QFN40_6X6
12
12
2NC3
4GH6
VCIN
BOOT
12
PR124
PR124
2_0603_5%
2_0603_5%
0.1U_0603_25V7K
0.1U_0603_25V7K
4GH6
5
BOOT
CGND
PC126
PC126
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
0_0402_5%
0_0402_5%
1
CGND
PWM
ZCD_EN#
DISB#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
30
43
PR155
PR155
41
40
39
38
37
36
35
34
33
32
31
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
PC112
PC112
PR125
PR125
1 2
1 2
0_0402_5%
0_0402_5%
DCM#
1
2NC3
CGND
VCIN
PWM
ZCD_EN#
DISB#
THWN
CGND
GL
VSWH
VSWH
VSWH
VSWH
VSWH
30
43
12
+5VS
A3210_PWM2
3210_OD#
+5VS
41
40
A3210_PWM1
39
38
37
36
35
34
33
32
31
VSWH
+VGA_CORE
2
+VGA_B+
3210_EN
PC136
PC136
PR173
PR173
12
12
PC113
PC113
PC114
PC114
0.1U_0603_25V7K
0.1U_0603_25V7K
2200P_0402_50V7K
2200P_0402_50V7K
3210_PH1
12
PC119
PC119
12
1000P_0603_50V7K
1000P_0603_50V7K
PR148
PR148
2.2_1206_1%
2.2_1206_1%
PC127
PC127
PR160
PR160
47K_0402_1%
47K_0402_1%
1 2
12
Themal_P
PR161
PR161
0_0402_5%
0_0402_5%
PL13
PL13
.42UH 20% PCME064T-R42MS1R557 20A
.42UH 20% PCME064T-R42MS1R557 20A
1 2
3210_PH2
12
0_0402_5%
0_0402_5%
PR166
PR166
1 2
12
1000P_0603_50V7K
1000P_0603_50V7K
2.2_1206_1%
2.2_1206_1%
3210_CS_PH2
Under VGA Core
12
12
12
12
12
PC142
PC142
PC143
PC143
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC153
PC153
PC154
PC154
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC166
PC166
PC167
PC167
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
FBMA-L11-453215800LMA90T_2P
FBMA-L11-453215800LMA90T_2P
12
12
PC116
PC116
PC115
PC115
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
10U_1206_25VAK
PR126
PR126
47K_0402_1%
47K_0402_1%
1 2
PR135
PR135
0_0402_5%
0_0402_5%
PL12
PL12
.42UH 20% PCME064T-R42MS1R557 20A
.42UH 20% PCME064T-R42MS1R557 20A
1 2
1 2
PR145 0_0402_5%PR145 0_0402_5%
3210_CS_PH1
12
0.1U_0603_25V7K
0.1U_0603_25V7K
+3VS
PR167
PR167
12
PC144
PC144
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC155
PC155
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC168
PC168
0.1U_0402_10V7K
0.1U_0402_10V7K
+3VS
12
Themal_P
1
+
+
2
PR146
PR146
1 2
10_0402_1%
10_0402_1%
3210_CSREF
12
12
PC129
PC129
PC128
PC128
10U_1206_25VAK
10U_1206_25VAK
2200P_0402_50V7K
2200P_0402_50V7K
1
10_0402_1%
10_0402_1%
+
+
1 2
PC138
PC138
2
470U_D2_2VM_R9M
470U_D2_2VM_R9M
3210_CSREF
12
12
PC146
PC146
PC145
PC145
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC157
PC157
PC156
PC156
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
12
PC170
PC170
PC169
PC169
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
PC120
PC120
470U_D2_2VM_R9M
470U_D2_2VM_R9M
PC130
PC130
1
+
+
PC139
PC139
2
PC147
PC147
PC158
PC158
PC171
PC171
+VGA_CORE
1
1 2
PL11
PL11
1
+
+
PC121
PC121
2
470U_D2_2VY_R9M
470U_D2_2VY_R9M
12
10U_1206_25VAK
10U_1206_25VAK
470U_D2_2VM_R9M
470U_D2_2VM_R9M
12
PC148
PC148
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC159
PC159
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
12
PC172
PC172
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
+
+
PC122
PC122
2
12
12
+VGA_CORE
470U_D2_2VY_R9M
470U_D2_2VY_R9M
+VGA_B+
PC149
PC149
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
PC173
PC173
0.1U_0402_10V7K
0.1U_0402_10V7K
B+
A A
8
7
6
5
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
4
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
3
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
2
VGA_COREP
VGA_COREP
VGA_COREP
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
58 65Tuesday, March 20, 2012
58 65Tuesday, March 20, 2012
58 65Tuesday, March 20, 2012
1
0.2
0.2
0.2
Page 59
5
PC174
PR188
PR188
PR247
PR247
1K_0402_1%
1K_0402_1%
CPU2@
CPU2@
0.033u_0402_16V7K
0.033u_0402_16V7K
1 2
FBA3
PC191
PC191
PR216
PR216
54.9_0402_1%
54.9_0402_1%
1 2
PR220
PR220
1 2
1 2
PC174
PC178
PC178
0.033U_0402_16V7K
0.033U_0402_16V7K
12
.1U_0402_16V7K
.1U_0402_16V7K
0_0402_5%
0_0402_5%
PR238
PR238
10_0402_1%
10_0402_1%
8.06K_0402_1%
8.06K_0402_1%
CPU3@ PR247
CPU3@
3P: 806
2P: 1K
GFX@
GFX@
FBA1
12
GFX@
GFX@
VR_RDYA
VR_SVID_DAT1
+3VS
12
PR227
PR227
10K_0402_5%
10K_0402_5%
FB_CPU3
PR241
PR241
1 2
PR247
1 2
806_0402_1%
806_0402_1%
PR189
PR189
1 2
806_0402_1%
806_0402_1%
GFX@
GFX@
+3VS
12
VR_ON<45>
CPU_B+
PR222 1K_0402_1%PR222 1K_0402_1%
PR229
PR229
1 2
0_0402_5%
0_0402_5%
PR232
PR232
1 2
0_0402_5%
0_0402_5%
PC204
PC204
49.9_0402_1%
49.9_0402_1%
1 2
0.033u_0402_16V7K
0.033u_0402_16V7K
FB_CPU2
PC207
PC207
DROOP
PR186
PR186
10_0402_1%
10_0402_1%
1 2
GFX@
D D
TRBSTA#
C C
PC190
PC190
VR_SVID_DAT<9>
VR_SVID_ALRT#<9>
VR_SVID_CLK<9>
GFX@
1 2
8.06K_0402_1%
8.06K_0402_1%
GFX@
GFX@
VCC_AXG_SENSE<10>
VSS_AXG_SENSE<10>
+1.05VS
12
PR215
PR215
.1U_0402_16V7K
.1U_0402_16V7K
130_0402_1%
130_0402_1%
1 2
+1.05VS
12
PC196
@PC196
43P_0402_50V7K
43P_0402_50V7K
75_0402_1%
75_0402_1%
1 2
5
@
VGATE<16>
TRBST#
PR226
PR226
VR_HOT#<45>
VSSSENSE<9>
VCCSENSE<9>
B B
A A
PR193
PR193
1 2
10_0402_1%
10_0402_1%
GFX@
GFX@
PR195
PR195
1 2
1K_0402_1%
1K_0402_1%
GFX@
GFX@
PR210
PR210
10K_0402_1%
10K_0402_1%
+5VS
PR221
PR221
95.3K_0402_1%
95.3K_0402_1%
1 2
1 2
12
PR236
PR236
1 2
1 2
12
0.033u_0402_16V7K
0.033u_0402_16V7K
PC212
PC212
1 2
1000P_0402_50V7K
1000P_0402_50V7K
4
GFX@
GFX@
1 2
FBA2
560P_0402_50V7K
560P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
PR213
PR213
1 2
2_0603_5%
2_0603_5%
PC188
PC188
1 2
2.2U_0603_10V7K
2.2U_0603_10V7K
PR217
PR217
1 2
0_0402_5%
0_0402_5%
PR219
PR219
1 2
10K_0402_1%
10K_0402_1%
12
PC194
PC194
VSN
PC197
PC197
1000P_0402_50V7K
1000P_0402_50V7K
VSP
PR234
PR234
1 2
1K_0402_1%
1K_0402_1%
PC202
PC202
1 2
FB_CPU1
470P_0402_50V7K
470P_0402_50V7K
PR242
PR242
806_0402_1%
806_0402_1%
PR244
PR244
24.9K_0402_1%
24.9K_0402_1%
CPU2@
CPU2@
CSREFCSCOMP
4
PC180
PC180
0.01U_0402_25V7K
0.01U_0402_25V7K
PC184
PC184
6132_VCC
VR_ON_CPU
VBOOT
DIFF_CPU
IMVP_IMON<45>
PR190
PR190
0_0402_1%
0_0402_1%
SLI@
SLI@
2P: 24K
1P: 24.9K
PR196
PR196
1 2
5.11K_0402_1%
5.11K_0402_1%
GFX@
GFX@
2P: 21.5K
1P: 15.8K
1 2
GFX@
GFX@
VR_RDYA
VR_SVID_DAT1
VR_SVID_ALRT#
VR_SVID_CLK
ROSC_CPU
VRMP
VR_HOT#
VGATE
PC200
PC200
10P_0402_50V8J
10P_0402_50V8J
CPU2@
CPU2@
3P: 22p
2P: 10p
CPU3@ PC200
CPU3@
PR237
PR237
12
6.04K_0402_1%
6.04K_0402_1%
3P: 23.7K
2P: 24.9K
PC181
1 2
10P_0402_50V8J
10P_0402_50V8J
COMPA1
PR202
PR202
1 2
0_0402_5%
0_0402_5%
PR207
PR207
1 2
0_0402_5%
0_0402_5%
PU14
PU14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PC200
22P_0402_50V8J
22P_0402_50V8J
COMP_CPU1
CPU3@
CPU3@
PC175
PC175
1 2
.1U_0402_16V7K
.1U_0402_16V7K
1 2
PR190
PR190
GFX@
GFX@
24K_0402_1%
24K_0402_1%
GFX@
GFX@
GFX@PC181
GFX@
GFX@
GFX@
PC182
PC182
1 2
2200P_0402_50V7K
2200P_0402_50V7K
1 2
0_0402_5%
0_0402_5%
PR199
SLI@ PR199
SLI@
SLI@
SLI@
SLI@
SLI@
DIFFA
TRBSTA#
57
59
58
60
61
PAD
VSPA
VSNA
DIFFA
VCC
VDDBP
VRDYA
EN
SDIO
ALERT#
SCLK
VBOOT
NCP6132AMNR2G_QFN60_7X7
NCP6132AMNR2G_QFN60_7X7
ROSC
VRMP
VRHOT#
VRDY
VSN
VSP
DIFF
COMP
TRBST#
18
17
19
16
FB_CPU
TRBST#
COMP_CPU
12
PC203
PC203
12
2200P_0402_50V7K
2200P_0402_50V7K
1 2
PC209
PC209
PR244
PR244
1 2
23.7K_0402_1%
23.7K_0402_1%
PUT COLSE
TO VCORE
Phase 1
Inductor
3
GFX@
GFX@
GFX@
GFX@
1 2
1 2
PC176
PC176
PC177
PC177
1200P_0402_50V7K
1200P_0402_50V7K
330P_0402_50V8J
330P_0402_50V8J
165K_0402_1%
12
PR197
PR197
GFX@PR203
GFX@
CSCOMPA
PR203
1 2
21.5K_0402_1%
21.5K_0402_1%
FBA
DROOPA
ILIMA
COMPA
IMONAIMONA
54
52
56
55
53
51
FBA
ILIMA
IOUTA
COMPA
DROOPA
TRBSTA#
CSCOMP22CSP325CSREF24CSSUM
DROOP21FB
IOUT
ILIM
23
20
DROOP
ILIM_CPU
CPU3@
CPU3@
1 2
PR233 21K_0402_1%
PR233 21K_0402_1%
1 2
CSCOMPCSCOMPCSCOMPCSCOMPCSCOMPCSCOMP
PC969@QC
.1U_0402_16V7K
.1U_0402_16V7K
PR248
PR248
1 2
75K_0402_1%
75K_0402_1%
PH7
PH7
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
165K_0402_1%
PR198
PR198
1 2
GFX@
GFX@
0_0402_5%SLI@
0_0402_5%SLI@
91K_0603_1%
91K_0603_1%
1 2
PR200
PR200
91K_0603_1% GFX@
91K_0603_1% GFX@
PC185
GFX@PC185
GFX@
1000P_0402_50V7K
1000P_0402_50V7K
PR204
PR204
12
1 2
0_0402_5% SLI@
0_0402_5% SLI@
PR205
PR205
0_0402_5% SLI@
0_0402_5% SLI@
PR208
0_0402_5%
0_0402_5%
1 2
CSP1A
CSSUMA
.1U_0402_16V7K
.1U_0402_16V7K
TSENSEA
0_0402_5%
0_0402_5%
46
49
50
48
47
CSP2A
CSP1A
TSNSA
CSREFA
CSSUMA
PWMA
CSCOMPA
BSTA
HGA
SWA
LGA
BST2
HG2
SW2
LG2
PVCC
PGND
LG1
SW1
HG1
BST1
CSP1
DRVEN
CSP2
TSNS
PWM
27
29
26
28
30
TSENSETSENSE CSP2A
PC198
PC198
1 2
CSP1
CSP2
CSP3
3P: 21K
2P: 12.4K
PC205
PC205
1000P_0402_50V7K
1000P_0402_50V7K
CSSUM
PC208
1 2
1500P_0402_50V7K
1500P_0402_50V7K
1 2
1 2
NTC_PH201
12
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
3
GFX@
GFX@
12
GFX@
GFX@
PR191
PR191
75K_0402_1%
75K_0402_1%
1 2
12
NTC_PH203
PR194
PR194
2P: install
SWN2A
1P: @
SWN1A
CSREFA <60>
12
SLI@PR208
SLI@
12
+5VS
GFX@
GFX@
PC187
PC187
1 2
12
PR211
PR211
SLI@
SLI@
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
1 2
.1U_0402_16V7K
.1U_0402_16V7K
CPU3@PC208
CPU3@
PC210
PC210
330P_0402_50V7K
330P_0402_50V7K
PC211
PC211
330P_0402_50V7K
330P_0402_50V7K
1 2
165K_0402_1%
165K_0402_1%
36K_0402_1%
36K_0402_1%
GFX@
GFX@
BSTA1
BST2
6132P_VCCP
BST1
3P: 73.2K
PR228
PR228
73.2K_0402_1%
73.2K_0402_1%
CPU3@
CPU3@
PR233
PR233
12.4K_0402_1%
12.4K_0402_1%
CPU2@
CPU2@
PR249
PR249
2P: 41.2K
6132_PWM <60>
DRVEN <60>
PC208
PC208
1200P_0402_50V7K
1200P_0402_50V7K
CPU2@
CPU2@
CSREF <60>
3P: 1500p
2P: 1200p
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
PUT COLSE
TO GT
PH4
PH4
Inductor
220K_0402_5%_ERTJ0EV224J
220K_0402_5%_ERTJ0EV224J
GFX@
GFX@
CSREFA
PC183
PC183
0.047U_0402_16V7K
0.047U_0402_16V7K
GFX@
GFX@
1 2
CSP1A
CSREFA
PC186
PC186
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
CSP2A
GFX@
GFX@
PR212
PR212
2P: 36K
1P: 26.1K
PR214
PR214
1 2
2.2_0603_5%
2.2_0603_5%
HG1A <60>
GFX@
GFX@
LG1A <60>
1 2
PR218
PR218
4.7_0603_5%
4.7_0603_5%
HG2 <60>
LG2 <60>
1 2
PR223
PR223
0_0402_5%
0_0402_5%
LG1 <60>
HG1 <60>
1 2
PR225
PR225
4.7_0603_5%
4.7_0603_5%
41.2K_0402_1%
41.2K_0402_1%
CPU2@
CPU2@
CSP3
CSP3
PR300
CSREF
21K_0402_1%
21K_0402_1%
@ PR300
@
1 2
CSP2
@PR301
@
PR301
CSREF
21K_0402_1%
21K_0402_1%
1 2
CSP1CSP1
@PR3 02
@
CSREF
PR302
21K_0402_1%
21K_0402_1%
1 2
PR243
PR243
1 2
130K_0603_1%
130K_0603_1%
1 2
PR245
PR245
130K_0603_1%
130K_0603_1%
1 2
PR246
PR246
130K_0603_1%
130K_0603_1%
CPU3@
CPU3@
3P: install
2P: @
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PR201 5.49K_0402_1%
PR201 5.49K_0402_1%
BSTA1_1
BST2_1
BST1_1
PR228
PR228
2
GFX@
GFX@
1 2
1 2
PR209
PR209
5.49K_0402_1%
5.49K_0402_1%
GFX@
GFX@
6132_PWMA <60>
PC189
PC189
12
GFX@
GFX@
0.22U_0603_10V7K
0.22U_0603_10V7K
PC192
PC192
12
0.22U_0603_10V7K
0.22U_0603_10V7K
12
PC193
PC193
2.2U_0603_10V7K
2.2U_0603_10V7K
12
PC195 0.22U_0603_10V7KPC195 0.22U_0603_10V7K
CPU3@
CPU3@
1 2
PR231
PR231
12
6.98K_0402_1%
6.98K_0402_1%
PC199
PC199
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
PR235
PR235
12
6.98K_0402_1%
6.98K_0402_1%
PC201
PC201
0.047U_0402_16V7K
0.047U_0402_16V7K
1 2
PR239
PR239
12
6.98K_0402_1%
6.98K_0402_1%
PC206
PC206
0.047U_0402_16V7K
0.047U_0402_16V7K
SWN1
SWN2
SWN3
2
CSCOMPA
SWN1A <60>
2P: install
1P: @
SWN2A <60>
+5VS
3P: install
2P: @
1 2
1.65K_0402_1%
1.65K_0402_1%
2P: 1.65K
1P: 1K
SW1A <60>
SW2 <60>
SW1 <60>
SWN3 <60>
SWN2 <60>
SWN1 <60>
1
PR192
PR192
0_0402_1%
0_0402_1%
SLI@
SLI@
PR192
PR192
GFX@
GFX@
GFX@
GFX@
PC179
PC179
1 2
1000P_0402_50V7K
1000P_0402_50V7K
TSENSEA
12
PR206
PR206
8.25K_0402_1%
8.25K_0402_1%
GFX@
GFX@
PUT COLSE
TO V_GT
HOT SPOT
CSREFADROOPA
PH5
PH5
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
1 2
GFX@
GFX@
+5VS
0_0402_5%
0_0402_5%
2Phase: @
1Phase: install
Option for
1 phase GFX
CSP2A
12
@PR22 4
@
PR224
+5VS
CSP3
TSENSE
12
PR240
PR240
8.25K_0402_1%
8.25K_0402_1%
PUT COLSE
TO VCORE
HOT SPOT
12
PR230
PR230
CPU2@
CPU2@
1 2
3Phase: @
2Phase: install
0_0402_5%
0_0402_5%
PH6
PH6
100K_0402_1%_TSM0B104F4251RZ
100K_0402_1%_TSM0B104F4251RZ
Compal Electronics, Inc.
CPU_CORE
CPU_CORE
CPU_CORE
Y490-LA8691P
1
Option for
2 phase CPU
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
0.3
0.3
59 65Tuesday, March 20, 2012
59 65Tuesday, March 20, 2012
59 65Tuesday, March 20, 2012
0.3
Page 60
5
4
3
2
1
CPU_B+
5
PQ27
PQ27
BST3_1
9
8
7
6
5
4
4
PC228
PC228
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
CPU3@
CPU3@
HG3
SW3
LG3
123
5
123
AON6504 1N DFN
AON6504 1N DFN
AON6428L_DFN8-5
AON6428L_DFN8-5
PQ29
PQ29
AON6504 1N DFN
AON6504 1N DFN
CPU3@
CPU3@
PQ32
PQ32
CPU3@
CPU3@
4
4
HG1<59>
D D
SW1<59>
LG1<59>
PR254
PR254
1 2
BST3
4.7_0603_5%
4.7_0603_5%
CPU3@
CPU3@
PU15
PU15
1
BST
C C
6132_PWM<59>
DRVEN<59>
+5VS
CPU3@
CPU3@
PR255
PR255
2K_0402_1%
2K_0402_1%
PR256
PR256
12
0_0402_5% CPU3@
0_0402_5% CPU3@
PC233
PC233
2.2U_0603_10V7K
2.2U_0603_10V7K
CPU3@
CPU3@
12
EN_CPU3
12
VCC_CPU3
FLAG
2
PWM
DRVH
3
EN
SW
4
VCC
GND
DRVL
NCP5911MNTBG_DFN8_2X2
NCP5911MNTBG_DFN8_2X2
CPU3@
CPU3@
3Phase: install
2Phase:: @
PC330
PC330
5
123
5
123
12
PC213
PC213
1000P_0402_50V7K
1000P_0402_50V7K
12
PR250
PR250
4.7_1206_5%
4.7_1206_5%
SNUB_CPU1
12
PC226
PC226
680P_0402_50V7K
680P_0402_50V7K
PQ31
PQ31
AON6428L_DFN8-5
AON6428L_DFN8-5
12
10U_0805_25V6K
10U_0805_25V6K
12
SNUB_CPU3
12
12
12
PC214
PC214
10U_0805_25V6K
10U_0805_25V6K
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
PR257
PR257
4.7_1206_5%
4.7_1206_5%
CPU3@
CPU3@
PC234
PC234
680P_0402_50V7K
680P_0402_50V7K
CPU3@
CPU3@
12
PC215
PC215
PC216
PC216
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
PL15
PL15
<BOM Structure>
1
2
<BOM Structure>
4
3
V1N_CPU
12
PC229
PC229
PC230
PC230
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
CPU3@
CPU3@
PL17
PL17
CPU3@
CPU3@
1
2
+VCC_CORE
12
CPU3@
CPU3@
B+
HCB4532KF-800T90_1812
HCB4532KF-800T90_1812
12
PR252
PR252
12
10_0402_1%
10_0402_1%
CPU_B+
12
12
PC232
PC232
PC231
PC231
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
+VCC_CORE
CPU3@
CPU3@
CPU3@
CPU3@
4
3
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
V3N_CPU
PR258
PR258
10_0402_1%
10_0402_1%
CPU3@
CPU3@
PL14
PL14
1 2
PC221
PC221
470P_0603_50V7K
470P_0603_50V7K
CSREF <59>
SWN1 <59>
12
CSREF
1
+
+
2
PC222
PC222
SWN3 <59>
5
PQ28
CPU_B+
1
12
12
+
+
PC224
PC224
PC223
PC223
2
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
1000P_0603_50V7K
1000P_0603_50V7K
HG2<59>
PC225
PC225
470P_0603_50V7K
470P_0603_50V7K
SW2< 59>
LG2<59>
QC 45W CPU
VID1=0.9V
IccMax=94A
Icc_Dyn=66A
Icc_TDC=52A
R_LL=1.9m ohm
OCP~110A
4
4
123
5
123
PQ28
AON6428L_DFN8-5
AON6428L_DFN8-5
PQ30
PQ30
AON6504 1N DFN
AON6504 1N DFN
DC 35W CPU
VID1=1.05V
IccMax=53A
Icc_Dyn=43A
Icc_TDC=36A
R_LL=1.9m ohm
OCP~65A
12
PC440
PC440
1000P_0402_50V7K
1000P_0402_50V7K
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
0.36UH_VMPI1004AR-R36M-Z03_30A_20%
12
PR251
PR251
4.7_1206_5%
4.7_1206_5%
SNUB_CPU2
12
PC227
PC227
680P_0402_50V7K
680P_0402_50V7K
12
PC218
PC218
PC217
PC217
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PL16
PL16
1
2
CPU_B+
12
12
12
PC220
PC220
PC219
PC219
0.1U_0402_25V6
0.1U_0402_25V6
2200P_0402_25V7K
2200P_0402_25V7K
+VCC_CORE
4
3
12
PR253
PR253
10_0402_1%
10_0402_1%
CSREF
SWN2 <59>
V2N_CPU
B B
5
HG1A<59>
SW1A<59>
LG1A<59>
A A
4
GFX@
GFX@
5
4
GFX@
GFX@
5
PQ33
PQ33
AON6428L_DFN8-5
AON6428L_DFN8-5
123
PQ35
PQ35
AON6504 1N DFN
AON6504 1N DFN
123
GFX@
GFX@
12
PC235
PC235
10U_0805_25V6K
10U_0805_25V6K
GFX@
GFX@
12
12
PC236
PC236
10U_0805_25V6K
10U_0805_25V6K
PR261
PR261
PC245
PC245
GFX@
GFX@
12
SNUB_GFX1
12
12
PC237
PC237
PC238
PC238
0.1U_0402_25V6
0.1U_0402_25V6
GFX@
GFX@
2200P_0402_25V7K
2200P_0402_25V7K
0.36UH 20% PDME064T-R36MS1R405 24A
0.36UH 20% PDME064T-R36MS1R405 24A
12
4.7_1206_5%@
4.7_1206_5%@
PR265
PR265
GFX@
GFX@
680P_0402_50V7K@
680P_0402_50V7K@
1 2
0_0402_5%
0_0402_5%
PL18
PL18
GFX@
GFX@
4
+VCC_GFXCORE_AXG
12
PR267
PR267
10_0402_1%
10_0402_1%
GFX@
GFX@
CSREFA <59>
SWN1A <59>
QC 45W GT2
VID1=1.23V
IccMax=46A
Icc_Dyn=37A
Icc_TDC=38A
R_LL=3.9m ohm
OCP~55A
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A
3
2Phase: install
1Phase:: @
1 2
PR259
PR259
2.2_0603_5%
2.2_0603_5%
GFX@
GFX@
BST
FLAG
PWM
DRVH
EN
SW
VCC
GND
DRVL
Deciphered Date
Deciphered Date
Deciphered Date
2
BSTA2_1
9
8
7
6
5
PC240
PC240
0.22U_0603_10V7K
0.22U_0603_10V7K
1 2
GFX@
GFX@
HG2A
SW2A
PQ36
PQ36
AON6504 1N DFN
AON6504 1N DFN
LG2A
GFX@
GFX@
4
4
BSTA2
PU16
PU16
1
6132_PWMA<59>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
+5VS
GFX@
GFX@
DRVEN
PR260
PR260
2K_0402_1%
2K_0402_1%
PR262
PR262
0_0402_5%
0_0402_5%
GFX@
GFX@
12
PC244
PC244
2.2U_0603_10V7K
2.2U_0603_10V7K
GFX@
GFX@
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
12
12
VCC_GFX2
EN_GFX2
2
3
4
NCP5911MNTBG_DFN8_2X2
NCP5911MNTBG_DFN8_2X2
GFX@
GFX@
Compal Secret Data
Compal Secret Data
Compal Secret Data
12
12
PC241
PC241
PC239
5
PQ34
PQ34
AON6428L_DFN8-5
AON6428L_DFN8-5
123
5
GFX@
GFX@
12
PR263
4.7_1206_5%
4.7_1206_5%
123
SNUB_GFX2
12
680P_0402_50V7K
680P_0402_50V7K
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
PC239
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
GFX@
GFX@
GFX@
GFX@
PL19
PL19
0.36UH 20% PDME064T-R36MS1R405 24A
0.36UH 20% PDME064T-R36MS1R405 24A
1 2
GFX@
GFX@
12
@PR263
@
PR264
PR264
0_0402_5%
0_0402_5%
GFX@
GFX@
PC246
@PC246
@
CPU_CORE
CPU_CORE
CPU_CORE
Y490-LA8691P
1
GFX@
GFX@
PC242
PC242
12
0.1U_0402_25V6
0.1U_0402_25V6
12
PC243
PC243
GFX@
GFX@
2200P_0402_25V7K
2200P_0402_25V7K
+VCC_GFXCORE_AXG
PR266
PR266
10_0402_1%
10_0402_1%
GFX@
GFX@
60 65Tuesday, March 20, 2012
60 65Tuesday, March 20, 2012
60 65Tuesday, March 20, 2012
12
CSREFA
SWN2A <59>
0.3
0.3
0.3
CPU_B+CPU_B+
Page 61
5
4
3
2
1
+VCC_CORE
1
PC247
PC247
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
D D
1
PC252
PC252
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC248
PC248
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC253
PC253
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC249
PC249
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC254
PC254
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC250
PC250
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC255
PC255
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
+VCC_CORE
1
PC266
PC266
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC290
PC290
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
C C
1
PC306
PC306
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC267
PC267
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC291
PC291
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC307
PC307
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC268
PC268
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC292
PC292
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC308
PC308
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC269
PC269
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC293
PC293
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC309
PC309
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
+CPU_CORE +VCC_GFXCORE_AXG
1
PC251
PC251
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC256
PC256
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
1
PC270
PC270
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC294
PC294
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC310
PC310
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC257
PC257
10U_080 5_6.3VAM
10U_080 5_6.3VAM
2
+VCC_GFXCORE_AXG
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC260
PC260
1
1
2
2
GFX@
GFX@
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC284
PC284
1
1
2
2
GFX@
GFX@
330U_D2_2VM_R9M
330U_D2_2VM_R9M
1
PC304
PC304
+
+
2 3
GFX@
GFX@
GFX@
GFX@
GFX@
GFX@
GFX@
GFX@
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC258
PC258
PC259
22U_0805_6.3V6M
22U_0805_6.3V6M
GFX@
GFX@
PC282
PC282
GFX@
GFX@
330U_D2_2VM_R9M
330U_D2_2VM_R9M
PC259
1
2
GFX@
GFX@
22U_0805_6.3V6M
22U_0805_6.3V6M
PC283
PC283
1
2
GFX@
GFX@
1
PC303
PC303
+
+
2 3
GFX@
GFX@
1
2
1
2
1
+
+
2 3
PC261
PC261
GFX@
GFX@
PC285
PC285
GFX@
GFX@
330U_D2_2VM_R9M
330U_D2_2VM_R9M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC262
PC262
PC263
22U_0805_6.3V6M
22U_0805_6.3V6M
GFX@
GFX@
PC286
PC286
GFX@
GFX@
PC263
1
2
GFX@
GFX@
22U_0805_6.3V6M
22U_0805_6.3V6M
PC287
PC287
1
2
GFX@
GFX@
1
2
1
2
PC305
PC305
PC59@DC
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC264
PC264
PC265
22U_0805_6.3V6M
22U_0805_6.3V6M
GFX@
GFX@
PC288
PC288
PC265
1
2
22U_0805_6.3V6M
22U_0805_6.3V6M
PC289
PC289
1
2
GFX@
GFX@
1
2
1
2
Below is 458544_CRV_PDDG_0.5 Table 5-8.
5 x 22 µF (0805)
Socket Bottom
5 x (0805) no-stuff
sites
7 x 22 µF (0805)
Socket Top
2 x (0805) no-stuff
sites
+1.05VS
+1.05VS
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC271
PC271
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC272
PC272
2
22U_0805_6.3V6M
1
1
PC273
PC273
PC274
PC274
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC295
PC295
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC275
PC275
2
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC296
PC296
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC276
PC276
PC277
PC277
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
2
PC298
PC298
PC297
PC297
2
22U_0805_6.3V6M
1
1
PC278
PC278
2
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC299
PC299
2
2
1
+
+
2 3
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
1
PC279
PC279
2
1
PC300
PC300
2
330U_D2_2VM_R6M
330U_D2_2VM_R6M
PC311
PC311
PC281
PC281
PC280
PC280
2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1
PC302
PC302
PC301
PC301
2
330U_D2_2VM_R6M
330U_D2_2VM_R6M
1
PC312
PC312
+
+
2 3
PC38,PC39,PC40,PC41
1
PC313
PC313
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC314
PC314
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
1
PC315
PC315
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
+VCC_CORE
1
+
+
PC317
PC317
PC318
B B
PC318
2 3
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
1
+
+
+
+
PC320
PC320
PC319
PC319
2 3
2 3
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
1
+
+
PC321
PC321
2 3
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
+
+
2 3
2
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
1
PC316
PC316
22U_080 5_6.3V6M
22U_080 5_6.3V6M
2
PC8,PC21,PC22,PC63
+
+
PC322
PC322
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
PC38,PC39,PC40,PC41
PC32,PC49,PC54,PC55,PC56
DC:PC73,PC74,PC75,PC76,PC77,PC78(330uF/9m)
QC:PC76,PC78(470uF/4.5m),PC73,PC74,PC75(330uF/9m)
A A
Security Class ification
Security Class ification
Security Class ification
2011/06/ 30 2012/12/ 31
2011/06/ 30 2012/12/ 31
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2011/06/ 30 2012/12/ 31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
CPU_CORE1
CPU_CORE1
CPU_CORE1
Y490-LA8691P
Y490-LA8691P
Y490-LA8691P
61 65Tuesday, March 20, 2 012
61 65Tuesday, March 20, 2 012
61 65Tuesday, March 20, 2 012
1
0.1
0.1
0.1
Page 62
5
4
3
2
1
Charge Option() bit[8]=1
B+
PR268
PR268
4
3
ACN
ACP
PC333
PC333
+3VALWP
1 2
12
PC335
@PR276
@
PR276
100K_0402_1%
100K_0402_1%
PR279
1 2
1 2
12
4.7M_0603_1%
4.7M_0603_1%
5
4
ACOK
CMPIN
PU17
PU17
BQ24737RGRR_VQFN20_ 3P5X3P5
BQ24737RGRR_VQFN20_ 3P5X3P5
SRN12BM
11
12
BM#
6.8_0603_5%
6.8_0603_5%
PC345
PC345
@PR295
@
0.1U_0603_25V7K
0.1U_0603_25V7K
PR295
10K_0402_5%
10K_0402_5%
1 2
12
+3VS
0.1U_0603_25V7K
0.1U_0603_25V7K
PR277
PR277
10K_0603_1%@
10K_0603_1%@
@PR279
@
3
CMPOUT
SRP
12
13
PR294
PR294
PR293
PR293
10_0603_5%
10_0603_5%
12
PC346
PC346
0.1U_0603_25V7K
0.1U_0603_25V7K
PC335
2
14
PL20
PL20
1UH_PCMB061H-1R0M S_7A_20%
1UH_PCMB061H-1R0M S_7A_20%
1 2
SH00000AA00
1 2
PC324
PC324
10U_0805_25V6K@
10U_0805_25V6K@
PC334
PC334
12
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
12
1
ACP
ACN
21
TP
20
VCC
19
PHASE
18
HIDRV
17
GND
BTST
REGN
LODRV
15
47K_0402_1%
47K_0402_1%
ACPRN
PR296
PR296
16
RB751V-40_SOD323-2
RB751V-40_SOD323-2
12
12
1 2
BST_CHG
PD7
PD7
BQ24737_VDD
PC344
PC344
1U_0603_25V6
1U_0603_25V6
5
PC325
PC325
10U_0805_25V6K@
10U_0805_25V6K@
PR282
PR282
10_1206_5%
10_1206_5%
1 2
DH_CHG
12
DL_CHG
BQ24737_VDD
12
PR297
PR297
10K_0402_1%
10K_0402_1%
34
PQ45B
PQ45B
P2
PC339
PC339
1 2
1U_0603_25V6
1U_0603_25V6
PR288
PR288
2.2_0603_5%
2.2_0603_5%
1 2
1 2
LX_CHG
0.047U_0603_16V7K
0.047U_0603_16V7K
PR298
PR298
10K_0402_1%
10K_0402_1%
1 2
PACIN
12
PR299
PR299
12K_0402_1%
12K_0402_1%
1 2
PC331
PC331
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PC340
PC340
1 2
PC332
PC332
PC326
PC326
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
AON7408L_DFN8-5
AON7408L_DFN8-5
12
ACIN <45>
1 2
PQ46
PQ46
CHG_B+
PQ39
PQ39
AO4423L 1P SO8
AO4423L 1P SO8
1
2
3 6
DISCHG_G
PC327
PC327
2200P_0402_50V7K
2200P_0402_50V7K
5
4
123
5
4
123
PR271
PR271
47K_0402_1%
47K_0402_1%
1 2
PR272
PR272
10K_0402_1%
10K_0402_1%
1 2
DISCHG_G-1
PQ42
PQ42
13
DTC115EUA_SC70-3
DTC115EUA_SC70-3
2
SH000005Y80
PL21
12
6251_SN
12
PL21
1 2
PR290
PR290
4.7_1206_5%
4.7_1206_5%
PC343
PC343
680P_0603_50V7K
680P_0603_50V7K
4.7UH_KJ0730-4R7M _5.5A_20%
4.7UH_KJ0730-4R7M _5.5A_20%
PQ48
PQ48
AON7702L_DFN8-5
AON7702L_DFN8-5
ACOFF-1
PD5
PD5
1SS355_SOD323-2
1SS355_SOD323-2
1 2
1 2
CHGCHG
4
1 2
PD6
PD6
1SS355_SOD323-2
1SS355_SOD323-2
12
PC336
PC336
0.1U_0603_25V7K
0.1U_0603_25V7K
PR285
PR285
0.01_1206_1%
0.01_1206_1%
1
2
8
7
5
PR273
PR273
200K_0402_1%
200K_0402_1%
61
PQ45A
PQ45A
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
2
4
3
PC341
PC341
VIN
PACIN
10U_0805_25V6K
10U_0805_25V6K
BATT+
12
12
PC342
PC342
10U_0805_25V6K
10U_0805_25V6K
PQ37
PQ37
AO4423L 1P SO8
AO4423L 1P SO8
DTA144EUA_SC70-3
DTA144EUA_SC70-3
47K_0402_5%
47K_0402_5%
13
2
PQ43A
PQ43A
PQ47
PQ47
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PR286
PR286
1 2
10K_0402_5%
10K_0402_5%
8
7
5
PQ40
PQ40
2
1 3
PQ41
PQ41
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PR281
PR281
47K_0402_1%
47K_0402_1%
1 2
2
ACOFF-1
12
PR291
PR291
0_0402_5%
0_0402_5%
34
PQ44B
PQ44B
5
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
4
VIN
D D
12
PR269
PR269
61
2
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
C C
PACIN
ACOFF<45>
B B
BATT_OUT
1
2
36
12
150K_0402_1%
150K_0402_1%
5
13
P2
1
2
3 6
12
PR270
PR270
PC328
PC328
200K_0402_1%
200K_0402_1%
0.1U_0603_25V7K
0.1U_0603_25V7K
P2-1
12
61
12
PR275
PR275
P2-2
34
PQ43B
PQ43B
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
EC_SMB_DA1<45,49,53>
EC_SMB_CK1<45,49,53>
2012/02/29
Add PC337 0.1uF
PQ38
PQ38
AO4423L 1P SO8
AO4423L 1P SO8
4
5600P_0402_25V7K
5600P_0402_25V7K
0.1U_0603_25V7K
0.1U_0603_25V7K
PR274
PR274
20K_0402_1%
20K_0402_1%
PQ44A
PQ44A
2N7002KDW -2N_SOT363-6
2N7002KDW -2N_SOT363-6
2
PR280
PR280
PR283
PR283
64.9K_0603_1%
64.9K_0603_1%
1 2
PC337 .1U_0603_25V7KPC337 .1U_0603_25V7K
12
8
7
5
PC323
PC323
1 2
1 2
PC329
@PC329
@
VIN
12
390K_0603_1%
390K_0603_1%
PR284
PR284
0_0402_5%
0_0402_5%
1 2
PR287
PR287
0_0402_5%
0_0402_5%
1 2
+3VALWP
P3
BATT_OUT <53>
PR289
PR289
1 2
147K_0402_1%
147K_0402_1%
100K_0402_1%
100K_0402_1%
ADP_I<45,53>
PC338
PC338
1 2
100P_0603_50V8
100P_0603_50V8
PR292
PR292
PR278
39.2K_0402_1%
39.2K_0402_1%
6
7
8
9
10
12
0.01_1206_1%
0.01_1206_1%
1
2
ACPRN<54>
@PR278
@
ACDET
IOUT
SDA
SCL
ILIM
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
3
2N7002KDW-2N_SOT363-6
2N7002KDW-2N_SOT363-6
For disable pre-charge circuit.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2012/12/312010/06/30
2012/12/312010/06/30
2012/12/312010/06/30
2
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
CHARGER
Y490-LA8691P
1
0.2
0.2
62 65Tuesday, March 20, 2012
62 65Tuesday, March 20, 2012
62 65Tuesday, March 20, 2012
0.2
Page 63
5
4
3
2
1
D D
AC
MODE
BATT
MODE
A1
VIN
BATT
B1
V
V
PU2
A3
B4
B5
+3VALW
A5
V
B7 2
V
V
A2
PU3
V
B+
V
B2
B+
PCH_PWR_EN#
2
V
PQ2
EC
VV
A5
A4
ON/OFF
B7
B6
V
V
PBTN_OUT#
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_SLP_A#
V
PM_SLP_SUS#
SYSON
DGPU_PWR_EN
SUSP#,SUSP
B3
51ON#
C C
EC_ON
2
4
PCH_RSMRST#
5
7 SYSON#
(DIS)
8a
8
6
U14,+3VALW_PCH
V
QH4,+5VALW_PCH
+3VALW_PCH
3
+5VALW_PCH
V
PCH
V V
+1.5V
V
PU5
VGA_ON
U49
V
+5VS
V
SYS_PWROK
PM_DRAM_PWRGD
H_CPUPWRGD
PLT_RST#
+3VSDGPU
V
Q6
+1.5VSDGPU
V
13
V
14
CPU
V
15
V
VVVV
11
VGATE
U40
U20
V
+3VS
B B
V
U13
+1.5VS
+1.8VSDGPU
V
U37
+1.0VSDGPU
V
VGA
V
PU28
PU8
VCCPPWRGOOD
V
PU9
+1.05VS_VCCP
VR_ON
9
PU1000
+CPU_CORE
V
VV
+0.75V
PU7
+VCCSA
+VGA_CORE
V
PU998
VGA_PWROK
(DIS)
8b
U47
CK505
V
10
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/07/21 2012/12/31
2011/07/21 2012/12/31
2011/07/21 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Power sequence
Power sequence
Power sequence
LA-8691P
LA-8691P
LA-8691P
0.1
0.1
63 65Tuesday, March 20, 2012
63 65Tuesday, March 20, 2012
1
63 65Tuesday, March 20, 2012
0.1
Page 64
5
4
3
2
1
Version change list (P.I.R. List) Page 1 of 1
for PWR
Reason for change PG# Modify List Date PhaseItem
1
Reserve 0.1uF for Charger IC Reserve PC321
D D
C C
2
EMI Request
3
Combine 1.05V
4
Discharge for +1.05VS_VGA by NV Request 53 Reserve PR528
5
Set VGA_CORE VBOOT voltage
6
For VGA_CORE power saving by NV Request add PR838 0ohm
7
for CPU_CORE load line adjust add PC969
8
to prevent MOS over temperature change PQ702,PQ901,PQ902,PQ905 TPCA806555/58
9
for CPU_CORE test 59 Reserve PC77,PC78
10
11
12
51
change PR322,PR407,PR408,PR503,PR511,PR606,PR804,PR827 to 2.2 ohm
add PC526,PC527,PC970,PC971(470uF)
Remove one power rail +V1.05S_VCCPP
51
Pop PR722,PR712,PR718
unpop PR806
56
change PR813 to 147K ohm
56
57
201109/27
201109/27
201109/27
201109/27
201109/27
201109/27
201109/27
201109/27
201109/27
B test
B test
B test
B test
B test
B test
B test
B test
B test
13
14
B B
15
16
17
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
2011/06/30 2012/12/31
2011/06/30 2012/12/31
2011/06/30 2012/12/31
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
PIR (PWR)
PIR (PWR)
PIR (PWR)
Y490-LA8691P
64 65Tuesday, March 20, 2012
64 65Tuesday, March 20, 2012
64 65Tuesday, March 20, 2012
1
0.1
0.1
0.1
Page 65
5
4
3
2
1
HW PIR (Product Improve Record)
QIQY5 LA-8691P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/03/09
NO DATE PAGE MODIFICATION LIST PURPOSE
D D
---------------------------------------------------------------------------------------------------------------------
01) 03/14 10 R64 Change R64 BOM structure from "@" to "DS3@" For Deep S3 Function
C C
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
3
2011/07/21 2012/12/31
2011/07/21 2012/12/31
2011/07/21 2012/12/31
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
LA-6882P
PIR (HW)
PIR (HW)
PIR (HW)
0.1
0.1
65 65Tuesday, March 20, 2012
65 65Tuesday, March 20, 2012
1
65 65Tuesday, March 20, 2012
0.1
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