CATALYST CAT1320, CAT1321 Service Manual

CAT1320, CAT1321

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Supervisory Circuits with I2C Serial 32K CMOS EEPROM

FEATURES

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■ Precision power supply voltage monitor

— 5V, 3.3V and 3V systems

- +5.0V (+/- 5%, +/- 10%)

- +3.3V (+/- 5%, +/- 10%)

- +3.0V (+/- 10%)

■ Active low reset, CAT1320

■ Active high reset, CAT1321

■ Valid reset guaranteed at V

■ 400kHz I

2

C bus

CC

=1V

DESCRIPTION

The CAT1320 and CAT1321 are complete memory and
supervisory solutions for microcontroller-based systems.
A 32kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I2C bus.

The CAT1320 provides a precision VCC sense circuit
and drives an open drain output, RESET low whenever
VCC falls below the reset threshold voltage.

The CAT1321 provides a precision VCC sense circuit
that drives an open drain output, RESET high whenever
VCC falls below the reset threshold voltage.

The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become

■ 3.0V to 5.5V operation

■ Low power CMOS technology

■ 64-Byte page write buffer

■ 1,000,000 Program/Erase cycles

■ 100 year data retention

■ 8-pin DIP, SOIC, TSSOP and TDFN packages

■ Industrial temperature range

active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the RESET (CAT1320) pin can be used as an
input for push-button manual reset capability.

The CAT1320/21 memory features a 64-byte page. In
addition, hardware data protection is provided by a V
sense circuit that prevents writes to memory whenever V

CC

CC

falls below the reset threshold or until VCC reaches the reset
threshold during power up.

Available packages include an 8-pin DIP, SOIC, TSSOP
and 4.9 x 3mm TDFN.

PIN CONFIGURATION

PDIP (P, L) SOIC (J, W)

1

A0 V

A1

2

CAT1320

A2

3

V

4

SS

1

A0

A1

2

CAT1321

A2

3

V

4

SS

© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice

8

7

6

5

8

7

6

5

CC

RESE

SCL

SDA

V

CC

RESET

SCL

SDA

TSSOP (U, Y)

1

A0 V

A1

2

CAT1320

A2

3

V

4

SS

1

A0

A1

2

CAT1321

A2

3

V

4

SS

1

8

7

6

5

8

V

RESET

7

SCL

6

SDA

5

CC

RESE

SCL

SDA

CC

TDFN PACKAGE: 4.9MM X 3MM

(RD2, ZD2)

1

A0

2

A1

A2

V

SS

A0

A1

A2

V

SS

3

4

1

2

3

4

CAT1320

CAT1321

8

V

CC

7

RESE

6

SCL

5

SDA

8

V

CC

7

RESE

6

SCL

5

SDA

Doc. No. 20585, Rev. 00

CAT1320, CAT1321 Advance Information

L

BLOCK DIAGRAM — CAT1320, CAT1321

EXTERNAL LOAD

SENSE AMPS

SHIFT REGISTERS

COLUMN

DECODERS

32kbit

EEPROM

DATA IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

STATE COUNTERS

SLAVE
ADDRESS
COMPARATORS

V

CC

V

SS

SDA

D

ACK

WORD ADDRESS

BUFFERS

START/STOP

LOGIC

CONTROL

LOGIC

RESET Controller

Precision

Vcc Monitor

OUT

XDEC

Threshold Voltage Options

Part Dash Minimum Maximum
Number Threshold Threshold

-45 4.50 4.75

-42 4.25 4.50

-30 3.00 3.15

-28 2.85 3.00

-25 2.55 2.70

OPERATING TEMPERATURE RANGE

Industrial -40˚C to 85˚C

SC

A0

A1

A2

RESET (CAT1320)
RESET (CAT1321)

PIN FUNCTIONS

Pin Name Function

RESET Active Low Reset Input/Output (CAT1320)

V

SS

SDA Serial Data/Address

SCL Clock Input

RESET Active High Reset Output (CAT1321)

V

CC

Ground

Power Supply

PIN DESCRIPTION

RESET/

These are open-drain pins and RESET can also be used
as a manual reset trigger input. By forcing a reset condition
on the pin the device will initiate and maintain a reset
condition. The RESET pin must be connected through a
pull-down resistor and the RESET pin must be connected
through a pull-up resistor.

SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to trans­fer all data into and out of the device. The SDA pin is an
open drain output and can be wire-ORed with other open
drain or open collector outputs.

RESETRESET

RESET: RESET OUTPUTS

RESETRESET

SCL: SERIAL CLOCK
Serial clock input.

A0, A1, A2: DEVICE ADDRESS INPUTS
When hardwired, up to eight CAT1320/21 devices may
be addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.

Doc. No. 25085, Rev. 00

2

Advance Information CAT1320, CAT1321

ABSOLUTE MAXIMUM RATINGS

Temperature Under Bias .................... -40°C to +85°C

Storage Temperature ........................ -65°C to +105°C

Voltage on any Pin with

Respect to Ground

with Respect to Ground ................ -0.5V to +7.0V

V

CC

(1)

............. -0.5V to +VCC +2.0V

Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.

Note:
(1) Output shorted for no more than one second. No more than

one output shorted at a time.

Package Power Dissipation

Capability (T

= 25°C) ................................... 1.0W

A

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(1)

........................ 100 mA

D.C. OPERATING CHARACTERISTICS

VCC = +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.

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Notes:

1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

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Doc No. 25085, Rev. 00

CAT1320, CAT1321 Advance Information

CAPACITANCE

TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol Test Test Conditions Max Units

(1)

C

C

OUT

(1)

IN

Output Capacitance V

= 0V 8 pF

OUT

Input Capacitance VIN = 0V 6 pF

A.C. CHARACTERISTICS

V

= 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.

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1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.

2. Test Conditions according to “AC Test Conditions” table.

3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.

Doc. No. 25085, Rev. 00

4

Advance Information CAT1320, CAT1321

RESET CIRCUIT A.C. CHARACTERISTICS

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Notes:

1. Test Conditions according to “AC Test Conditions” table.

2. Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

3. Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table

4. VCC Glitch Reference Voltage = V

5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

6. t

PUR

and t

are the delays required from the time VCC is stable until the specified memory operation can be initiated.

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AC TEST CONDITIONS

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RELIABILITY CHARACTERISTICS

Symbol Parameter Reference Test Method Min Max Units

(1)

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END

(1)

T

DR

(1)

V

ZAP

(1)(2)

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LTH

Notes:

1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.

2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.

Endurance MIL-STD-883, Test Method 1033 1,000,000 Cycles/Byte

Data Retention MIL-STD-883, Test Method 1008 100 Years

ESD Susceptibility MIL-STD-883, Test Method 3015 2000 Volts

Latch-Up JEDEC Standard 17 100 mA

5

Doc No. 25085, Rev. 00

CAT1320, CAT1321 Advance Information

DEVICE OPERATION

Reset Controller Description

The CAT1320/21 precision Reset controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open­drain RESET/RESET outputs.

During power-up, the RESET/RESET output remains
active until VCC reaches the VTH threshold and will
continue driving the outputs for approximately 200ms
(t

) after reaching VTH. After the t

PURST

PURST

timeout
interval, the device will cease to drive the reset output.
At this point the reset output will be pulled up or down by
their respective pull up/down resistors.

During power-down, the RESET/RESET output will be
active when V
output will be valid so long as VCC is >1.0V (V

falls below VTH. The RESET/RESET

CC

RVALID

The device is designed to ignore the fast negative going
VCC transient pulses (glitches).

Reset output timing is shown in Figure 1.

Manual Reset Operation

The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.

When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.

Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.

Hardware Data Protection

The CAT1320/21 family has been designed to solve
many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.

).

Whenever the device is in a Reset condition, the embedded
EEPROM is disabled for all operations, including write
operations. If the Reset output is active, in progress
communications to the EEPROM are aborted and no new
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progress internal non-volatile memory write cycle can not
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.

Figure 1. RESET/RESET Output Timing

V

TH

V

RVALID

V

CC

RESET

RESET

Doc. No. 25085, Rev. 00

t

PURST

t

GLITCH

t

6

RPD

t

PURST

t

RPD