Parts List ..................................................................................................................................... 19
SPECIFICATIONS
GENERAL
Number of keys:61
Polyphonic:24-note (12 for some tones)
Preset tones:100, with split/layer functions
Keyboard controls:Touch response: On/Off, Key transpose: 12 steps (F#-C-F)
Auto-rhythms:100, Tempo control: 40 to 255
Auto-accompaniment:Mode: CASIO Chord/Fingered Chord/Full Range Chord
type, Split/Layer settings, Pitch bend range, Basic channel, Local on/off,
Portamento on/off
Song memory:1, Real-time recording, Memory capacity: Approx. 1200 notes in total
Demo tunes:1, including — Mei Wenti (Edward Alstrom)
Tuning control:440Hz ± 50 cents
Built-in speakers:12 cm dia. 2.5 W input rating: 2 pcs.
MIDI:16 multi-channel reception
Terminals:Phone Jack [Output impedance: 110 Ω, Output voltage: 4.2 V(rms)
MAX], Sustain Jack, MIDI Jacks (IN, OUT), AC Adapter Jack (9 V) ,
Foot volume Jack
Auto power off:Approximately 6 minutes after the last operation
Power source:2-way AC or DC source
AC: AC adapter
DC: 6 D size dry batteries
Power consumption:7.7 W
Dimensions (HWD):140 x 997 x 376 mm (5-1/2 x 39-5/16 x 14-13/16 inches)
Weight:5.4 kg (11.9 lbs) without batteries
The power supply circuit generates six voltages as shown in the following table. VDD voltage is always
generated. The others are controlled by APO signal from the CPU.
DVDD+5 VPower jack, Sustain jack, MIDI jack
AVDD+5 VDAC, Filter
LVDD+5 VLED Driver
VCC+9 VPower amplifier, Pilot lamp
VC+9 VPower amplifier
B6A6G6F6E6D6
C7
RESET CIRCUIT
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU. The
CPU then initializes its internal circuit, and clears the working storage RAM.
When the power switch is pressed, the CPU receives a low pulse of POWER signal, then the CPU sends
a reset signal to the DSP.
Battery set
VDD
Reset IC
IC106
RE5VA35AA
POWER
From power switch
RESET
VDD
CPU
LSI101
UPD913GF-3BA
NMI
— 5 —
Reset signal
PLE
HG51B227FB
VDD
DSP
LSI102
CPU (LSI101: UPD913GF-3BA)
The 16-bit CPU contains a 1k-byte RAM, three 8-bit I/O ports, two timers, a keycontroller and serial interfaces.
The CPU detects key velocity by counting the time between first-key input signal FI and second-key SI from
the keyboard. The CPU reads sound data and velocity data from the sound source ROM in accordance with
the selected tone; the CPU can read rhythm data simultaneously when a rhythm pattern is selected. Then the
CPU provides 16-bit serial sound data to the DSP. The CPU also controls MIDI input/output and stores
sequencer data into the working storage RAM.
The following table shows the pin functions of LSI101.
Pin No.TerminalIn/OutFunction
1TXD0Out MIDI signal output
2RXD0In MIDI signal input
3SCK0Out APO (Auto Power Off) signal output
4, 5TXD1, RXD2— Not used. Connected to ground.
6SCK1Out 1 MHz synchronizing pulse output
7AVCCIn +5 V source
8AN0In Pitch bend control voltage input
9AN1In Modulation control voltage input
10AGNDIn Ground (0 V) source
11BCKOut Bit clock output
12SOOut Serial sound data output
13LRCKOut Word clock output
14GNDIn Ground (0 V) source
15, 16XLT0, XLT1In/Out 20 MHz clock input/output
17VCCIn +5 V source
18, 19MD0, MD1In Mode selection terminal
20RSTBIn Reset signal input
21NMIIn Power ON signal input
22INT— Not used. Connected to ground.
23 ~ 30
31 ~ 38KC0 ~ KC7Out Terminal for key input signal
39 ~ 46
47, 48FI8, SI8— Not used
49FI9In Terminal for button input signal
50SI9In Substain signal input
51FI10In Terminal for button input signal
52SI10In Not used
53 ~ 55KI0 ~ KI2In Terminal for button input signal
56MWNBOut Write enable signal output
57 ~ 76MA0 ~ MA17Out Address bus
77MCSB0Out Chip enable signal output for the sound source ROM
78MCSB1Out Not used
79MCSB2Out Chip enable signal output for the DSP
FI0 ~ FI3
SI0 ~ SI3
FI4 ~ FI7
SI4 ~ SI7
In Terminal for key input signal
In Terminal for key input signal
— 6 —
Pin No.TerminalIn/OutFunction
80VCCIn +5 V source
81GNDIn Ground (0 V) source
82MRDBOut Read enable signal output
83 ~ 98MD0 ~ MD15In/Out Data bus
99PLEOut Reset signal output for the DSP
100P17In APO cancellation signal input
CPU Block Diagram
CE
RAM
LSI103
OE
OE
ROM
LSI104
WE
MWEB
MRDB
CE
MD0 ~ MD7
MA0 ~ MA10
MD0 ~ MD15
MA0 ~ MA19
MCSB0
MA0/MA1
RCEB
MRDB
SCK0
P17
WEB
MWNB
NMI
DSP
LSI102
CE1B
MCSB2
CPU
LSI101
RSTB
RESB
PLE
TXDO
RXDO
SCK1
BCK
SO
LRCK
SI9
AN1
AN0
XLT0/XLT1
Sound data and
timing signals
MIDI input/output
KC0 ~ KC7
FI0 ~ FI10, SI0 ~ SI7
KI0 ~ KI2
Sustain signal
Modulation
Pitch bend
APO
APO cancel signal
Power ON signal
Reset ICPG 20MHz
— 7 —
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