Atmel ATPL250A User Manual

Atmel-43106C-ATPL- PANCoordinator-EK Kit User Manual-UserGuide_06-Oct-16

ATPL250A

PANCoordinator-EK Kit User Manual

USER GUIDE

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 Welcome letter introducing the evaluation kit and

its contents.

 Boards:

 One ATPL250ABNv2 board.
 One ATPLCOUP007v2.5 coupling

board (CEN-A frequency band).

 One ATPLCOUP002v2 coupling

board (ARIB frequency band).

 One ATPLCOUP006v2 coupling

board (FCC frequency band).

 Cables:

 One micro A/B-type USB cable.
 One power cord cable IEC320-C8.

 Jumpers:

 One voltage jumper with pitch 5.08

mm.

 One erase jumper with pitch

2.54mm.

Introduction

This PANCoordinator Evaluation Kit (EK) comprises all necessary resources to develop a complete
G3-PLC PANCoordinator. It implements an Atmel® Cortex™-M7 device acting as MCU host, combined with
ATPL250A modem for PLC (Power Line Communication). ATPL250A is a power line communications base
band transceiver, compliant with the PHY layer of G3-PLC specification.

G3-PLC is a mature, consolidated and worldwide accepted standard for OFDM-based power line
communications, with focus on providing Smart Grid services over electricity distribution networks.

This guide describes how to use the kit and get start with it.

Contents

Features

 ATPL250A is a compact and high-efficient device for a wide range of Smart Grid applications such as

Smart Metering (Smart Meters and Data Concentrators), Lighting, Industrial/Home Automation,
Home and Building Energy Management Systems, Solar Energy and Plug-in Hybrid Electric Vehicle
(PHEV) Charging Stations.

 ATPL250A G3-PLC device includes enhanced features such as additional robust modes and

frequency band extension.

 ATPL250A has been conceived to be bundled with an external Atmel MCU. ATPL250ABN PAN

Coordinator board mounts the ATPL250A transceiver and a SAME70 ARM Cortex M7
microcontroller. This development board provides a full featured platform to develop a complete
communications system based on Power Line Communication technology, providing support for:

– PLC band characterization.
– Noise level measurement.
– Sensitivity level measurement.
– Maximum reachable distance.
– Power consumption.
– Check PLC performance in different bands (CENELEC, FCC, ARIB) setting different PLC

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coupling boards (provided with this evaluation kit).

– The EK board can be supplied with universal 115-230 VAC 50-60 Hz power input.
– The EK boards include a JTAG interface for MCU debugging and programming purposes, a

UART for debugging purposes, as well as Ethernet connectivity.

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 Software application examples available based on G3-PLC Stack:

– Atmel provides an Atmel G3-PLC PHY layer library which is used by the external MCU to take

control of ATPL250A PHY layer device. Three G3-PLC PHY layer example projects are
provided with the kit.

– Atmel G3 Stack (ADP + MAC + PHY) for PAN Coordinator with some user applications is

provided with the EK.

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Table of Contents

1. Evaluation Kit Specifications ...................................................................................... 7

1.1 Safety recommendations ....................................................................................................................... 7

1.2 Electrical characteristics ........................................................................................................................ 7

2. Evaluation Kit Overview .............................................................................................. 9

2.1 Design support ...................................................................................................................................... 9

2.2 PANCoordinator-EK contents ................................................................................................................ 9

3. ATPL250ABN Hardware............................................................................................. 13

3.1 Overview ............................................................................................................................................. 13

3.2 Features .............................................................................................................................................. 13

3.3 Block diagram ...................................................................................................................................... 16

3.4 Mechanical and user considerations ................................................................................................... 16

3.5 Hardware description .......................................................................................................................... 17

3.5.1 Power supply .......................................................................................................................... 17

3.5.2 Zero crossing detector ............................................................................................................ 18

3.5.3 SAME70Q21 Flash microcontroller ......................................................................................... 18

3.5.4 ATPL250A PLC Transceiver ................................................................................................... 19

3.5.5 PLC Coupling.......................................................................................................................... 20

3.5.6 Peripherals.............................................................................................................................. 22

3.5.7 Interface Ports ........................................................................................................................ 23

4. ATPLCOUP007 Hardware .......................................................................................... 26

4.1 Overview ............................................................................................................................................. 26

4.2 Features .............................................................................................................................................. 26

4.3 Mechanical and user considerations ................................................................................................... 27

4.4 Hardware description .......................................................................................................................... 27

5. ATPLCOUP002 Hardware .......................................................................................... 28

5.1 Overview ............................................................................................................................................. 28

5.2 Features .............................................................................................................................................. 28

5.3 Mechanical and user considerations ................................................................................................... 29

5.4 Hardware description .......................................................................................................................... 29

6. ATPLCOUP006 Hardware .......................................................................................... 30

6.1 Overview ............................................................................................................................................. 30

6.2 Features .............................................................................................................................................. 30

6.3 Mechanical and user considerations ................................................................................................... 31

6.4 Hardware description .......................................................................................................................... 31

7. PAN Coordinator Evaluation Kit: Getting started .................................................... 32

7.1 Introduction to the embedded system ................................................................................................. 32

7.1.1 IAR Embedded Workbench .................................................................................................... 32

7.1.2 Keil µVision ............................................................................................................................. 32

7.1.3 Atmel Studio 6 ........................................................................................................................ 32

7.1.4 Atmel SAM-ICE JTAG Probe .................................................................................................. 33

7.1.5 J-Link / SAM-ICE JTAG Probe Software & Documentation Pack ........................................... 33

7.1.6 Atmel Software Framework (ASF) .......................................................................................... 35

7.2 PLC application example 1 – PHY Tester ........................................................................................... 36

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7.2.1 Atmel PLC PHY Tester tool Installation .................................................................................. 37

7.2.2 Supplying the boards .............................................................................................................. 39

7.2.3 USB connection ...................................................................................................................... 40

7.2.4 Programming the embedded file ............................................................................................. 41

7.2.5 Running the PLC application example 1 ................................................................................. 43

7.3 PLC application example 2 – PHY TX Test Console ........................................................................... 55

7.3.1 Supplying the boards .............................................................................................................. 56

7.3.2 USB connection ...................................................................................................................... 56

7.3.3 Programming the embedded file ............................................................................................. 56

7.3.4 Running the PLC application example 2 ................................................................................. 57

7.4 PLC application example 3 – PHY Sniffer ........................................................................................... 61

7.4.1 ATPL Multiprotocol Sniffer tool Installation ............................................................................. 62

7.4.2 Supplying the boards .............................................................................................................. 64

7.4.3 USB connection ...................................................................................................................... 64

7.4.4 Programming the embedded files ........................................................................................... 65

7.4.5 Running the PLC application example 3 ................................................................................. 65

7.5 Introduction to G3 Stack ...................................................................................................................... 68

7.5.1 FreeRTOS .............................................................................................................................. 68

7.5.2 ASF Integration ....................................................................................................................... 69

7.5.3 Atmel G3-PLC Stack Structure ............................................................................................... 70

7.6 PLC application 4 – PLC Network ....................................................................................................... 72

7.6.1 Supplying the boards .............................................................................................................. 72

7.6.2 USB connection ...................................................................................................................... 72

7.6.3 Programming the embedded files ........................................................................................... 72

7.6.4 Running the PLC application example 4 ................................................................................. 74

8. References ................................................................................................................. 77

Appendix A Board schemes ......................................................................................... 78

A.1 ATPL250ABNv2 Schemes .................................................................................................................. 78

A.2 ATPLCOUP007v2.5 schemes ............................................................................................................. 85

Revision History ................................................................................................................ 88

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Icon Key Identifiers

Useful Tips and Techniques

Delivers Contextual Information About a Specific Topic

Note to Quality and Performance

Objectives to be Completed

Actions to be Executed Out of the Target

The Expected Result of an Assignment Step

Procedure Which Can Result in Minor Equipment Damage

Procedure With Potential Equipment Damage

Procedure With Imminent Equipment Destruction

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A normal use of ATPL250ABN does not require removing the enclosure
cover. If this action is necessary, it must be performed by qualified staff
after being sure that mains connection has been previously removed.
Be careful it is only for indoor use.

Coupling boards’ kits are shipped in a protective anti-static package.
The boards system must not be subjected to high electrostatic
discharge.

We strongly recommend using a grounding strap or similar ESD
protective device when handling the board in hostile ESD
environments (offices with synthetic carpet, for example) without
enclosure. Avoid touching the component pins or any other metallic
element on the board.

ATMEL does not assume responsibility for the consequences arising
from any improper use of this board.

Parameter

Condition

Min.

Typ.

Max.

Unit

AC mains Voltage Range

100

115/230

250

VAC

Mains Frequency

50/60

Hz

Maximum Input Current

200

(1)

mA

Isolation Voltage

ACDC power supply and PLC coupling transformer

3000

VAC

1. Evaluation Kit Specifications

1.1 Safety recommendations

These development boards must be only used by expert technicians. ATPL250ABN is directly powered
from mains grid, so hazardous voltage (100/230VAC) is present on the board. To avoid user access to
dangerous parts, ATPL250ABN must always be used within its enclosure. All required connectors and
configuration jumpers are easily accessible without electrical shock risk.

This development board does not have any switch on mains connection to switch on or off it. It must always
be connected to an easy accessible mains socket.

Do not connect any probe to high voltage sections if the board is not isolated from the mains supply to avoid
damaging of measurement instruments.

ATPL250ABN is a CE mark product which passes EN60950-1 safety standard, EN50065-1, EN50065-2-3,
EN50065-7 EMC and FCC (as current carrier system) standards. It also satisfies Pb-Free and ROHS
directive.

Boards’ kits are intended for further engineering, development, demonstration, or evaluation purposes only.

It is not a finished product except as may be otherwise noted on the board/kit.

1.2 Electrical characteristics

This section shows the electrical characteristics of the kit’s boards. See the following tables:

Table 1-1. Power Supply Requirements.

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Parameter

Condition

Min.

Typ.

Max.

Unit

TX Power Consumption

FW: PHY TX Test Console Application

Low Impedance Load (PRIME LISN).

Measured on VDD (16V) DCDC output.

3523

(1)

mW

FW: PHY TX Test Console Application

High Impedance Load (CISPR LISN).

Measured on VDD (16V) DCDC output.

2280

(1)

mW

RX Power Consumption

Measured on 3.3V LDO output

664

(1)

mW

Note that the ATPL250ABN can be supplied either with 100VAC or 230VAC by setting the proper jumpers
(pitch = 5.08mm) in the voltage selector, J2, as depicted in the Figure 7-10. By default, voltage jumper is set
for 230VAC. For more information about power supply, see section 3.5.1.

Note: 1. This maximum input current is measured in the worst case situation, so that, when board is supplied with

a minimum input voltage,100VAC, and the worst consumption conditions. That is when it emits against
very low impedance in higher frequency band and it is supplying an extra board through the DC jack J15.

Table 1-2. Power Supply Requirements.

Note: 1. These measurements were taken with a non-optimized FW (the PHY TX Test Console project included in

the kit with a default configuration in TX mode and RX mode) from a power consumption point of view and
they highly depend on the architecture and efficiency of the power supplies. These measurements
correspond to the whole PCBA design and not only to ATPL250A and ATSAME70 devices. All PCB
peripherals are supplied, i.e. ATPLCOUP007 coupling board emitting in CENELEC-A band. Refer to
Atmel ATPL250A and ATSAME70 datasheets for an optimized power consumption measurement result.

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2. Evaluation Kit Overview

ATPL250ABN is the name of the development board included in this PAN Coordinator EK. It implements an
ATPL250A analog front end for PLC, supporting G3-PLC, which has been designed to be controlled by an
external Atmel MCU. In this case, Atmel | Smart SAME70 is the device driving ATPL250A PLC analog front
end.

This document describes how to start working with the Atmel PANCoordinator-EK. A complete description
of PC tools, software examples and hardware are provided in this EK.

2.1 Design support

To make it faster and easier for you to evaluate, prototype, develop and program with Atmel products, we
offer a variety of design resources, including development tools, software, boards, kits and documentation.

For any technical support request, please refer to our Design Support webpage:

http://www.atmel.com/design-support/.

There any user can search the Atmel knowledge base to find tips, help topics, and answers to common
questions. In case that the obtained information is not helpful any user can Open a Support Case indicating
a description of the case, product information, etc.

2.2 PANCoordinator-EK contents

PANCoordinator-EK contents –documentation, software and tools- are available online in

https://secure.atmel.com/. To download this information you need a myAtmel account, please access to
www.atmel.com/myAtmel and create your own account After that, please contact with [e-mail],

specifying your myAtmel user name, your company name and email, and request access to the specific
evaluation kit you have acquired. Please do not hesitate to visit our web site to get the last kit updates.

myAtmel EK contents are:

1. A welcome letter, PANCoordinator-EK_WL, introducing the EK and its contents.

2. PANCoordinator-EK Kit User Manual, doc43106.

3. Hardware folder:
a. ATPL250A datasheet, doc43079.

b. Hardware application notes: PLC coupling reference designs, crystal selection guidelines,

layout recommendations, critical design guidelines, etc.

c. EK schemes, PCB layouts, gerbers and BOM files of ATPL250ABN, ATPLCOUP002,

ATPLCOUP006 and ATPLCOUP007 boards.

4. Software folder:
a. G3_va.b.c folder, contains five projects for several IDE tools, IAR, Atmel Studio and Keil

µVision to work in both frequency bands, CENELEC-A, ARIB and FCC bands, see

g3.workspace.same70q21_atpl250abn_v2.zip file:

 Apps_Phy_Tester_Tool. This application configures G3-PLC PHY layer and its serial

interface to communicate with Atmel PLC PHY Tester Tool to send and receive PLC
messages from/to the PLC line and check the PLC transmission/reception processes
between ATPL250ABN boards. Atmel PLC PHY Tester tool for PC is available in the
PCTools folder.

 Apps_Phy_Tx_Test_Console. This application lets the user to configure a proper set up

to perform both EMC emissions and immunity tests on ATPL250ABN board. These tests
are based on the use of G3 PHY layer with a terminal console firmware that eases the
configuration of several transmission parameters such as modulation, frame data length
and time interval between frames.

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We recommend installing the evaluation kit contents in the root C:\ to avoid problems
with very long paths.

The boards must not be subject to high electrostatic discharge. We recommend using a
grounding strap or similar ESD protective device when handling the board in hostile ESD
environments. Avoid touching the components pins or any other metallic elements on the
board.

 Apps_Phy_Sniffer_Tool. This application configures G3 PHY layer to monitor the PLC

 APPS_DLMS_EMU_COORD_APP. The DLMS Emulator application is an example

 APPS_ADP_MAC_SERIALIZED_APP. The ADP and MAC serialization is an application

b. Common software documentation folder. It contains some user guides as the description of the

Atmel G3 firmware stack, doc43081. Document describes in detail all layers from the Atmel G3
implementation as well as configuration options provided, target platforms, default architecture
and the provided solutions by Atmel.

c. Evaluation License Agreement document.

5. PCTools folder:
a. Atmel PLC PHY Tester, PC tool used to monitor point to point PLC transmissions between

Atmel boards.

b. ATPL Multiprotocol Sniffer, PC tool to monitor data traffic in G3-PLC networks using an Atmel

board as sniffer.

c. SAM-ICE™ Drivers. Users may need to install this driver the first time the SAM-ICE is

connected to the PC.

d. USB Drivers (Silicon USB drivers). Users may need to install these drivers the first time the

ATPL250ABN board is connected to the host PC by means of a serial USB connection.

data traffic on ATPL250ABN board and sends via serial communication this traffic to the
ATPL Multiprotocol Sniffer tool. This tool can be downloaded from the PCTools folder.
Every coupling board is intended to be used in their corresponding frequency bands only.
By default, sniffer project is compiled for ATPLCOUP007 board. This means that only G3
CENELEC band-A is supported.

using the Atmel G3-PLC stack and show how the G3 API should be used. This
application is provided for Coordinator. Application configure the ATPL250ABN board as
G3 Coordinator. A Device node is required, it is configured with DLMS Emulation
capabilities and simulate the data exchange between the G3 Coordinator and the
Device(s). The Device responds dummy DLMS messages after receiving data requests
from the Coordinator.

example that bring you access to the ADP, MAC and Bootstrap API through a serial
connection. This application could be useful for users that want to make intensive test for
the stack or want to run the upper layers in other CPU.

Unpack and inspect the kit carefully. Contact your local Atmel distributor, should you have any issues
concerning the contents of the kit.

The ATPL250ABN board with the ATPLCOUP007 are encapsulated with methacrylate enclosures and
shipped in protective anti-static foam. The two coupling boards, ATPLCOUP002 and ATPLCOUP006, are
shipped in shielded bags.

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Figure 2-1. Packed Atmel PANCoordinator-EK.

Figure 2-2. ATPL250ABN PAN Coordinator board and with ATPLCOUP007.

ATPL250ABN board is provided with an example application preprogrammed, the G3-PLC PHY Tester
project for SAM4E70Q21. After installing the Atmel PLC PHY Tester PC Tool in your PC, users can
interface with the device and start exploring its capabilities, for example, checking the point to point PLC
transmissions between the two Atmel boards. Please refer to chapter 7.2 for further information.

Take into account that the PANCoordinator-EK provides one coupling board for CENELEC-A band, Figure
2-3, set over the ATPL250ABN board. In addition to the ATPLCOUP007 board, evaluation kit adds one
coupling boards for FCC bands, Figure 2-4. And another coupling board for ARIB bands, Figure 2-5.

Depending on the coupling board set in ATPL250ABN board and the PHY configuration parameters
selected in the software project you will send and receive PLC messages in the proper PLC band. So that,
with ATPLCOUP007 board only lets you send and receive PLC messages in CENELEC-A band. And with
ATPLCOUP002 and ATPLCOUP006 board in ARIB or FCC bands respectively.

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Figure 2-3. ATPLCOUP007 Coupling board.

Figure 2-4. ATPLCOUP002 Coupling board.

Figure 2-5. ATPLCOUP006 Coupling board.

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3. ATPL250ABN Hardware

3.1 Overview

This section summarizes the Atmel ATPL250ABN board design. It introduces system-level concepts, such
as power supply, MCU, PLC coupling, memories, peripherals and interface board.

ATPL250ABN is a PAN Coordinator development board based on the ATPL250A, G3-PLC transceiver, and
on the SAME70 ARM Cortex M7 microcontroller. ATPL250ABN PAN Coordinator board provides a platform
to develop a complete communications system over G3-PLC technology.

Figure 3-1. ATPL250ABNv2 PAN Coordinator board.

3.2 Features

The ATPL250ABNv2 board includes the following features:

 Power supply:

 ATPL250A G3-PLC Transceiver:

– Non switched ACDC isolated power supply: 100-230VAC, 50-60Hz.
– 5 volts rail is accessible by means of a DC Jack connector (J15).
– Selectable 12/16 VDD power supply.

– Implements G3 CENELEC-A, FCC and ARIB profiles (ITU-T G.9903, June 2014).
– Power Line Carrier modem for 50 and 60 Hz mains.

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– G3-PLC coherent and continuous amplitude tracking in signal reception.
– Automatic Gain Control (AGC).
– Zero cross detection.
– Embedded PLC Analog Front End (AFE), requires only external discrete high efficient Class D

Line Driver for signal injection.

 Support to G3-PLC coupling boards ATPLCOUPxxx.
 Mains zero-crossing detector circuit.
 SAME70Q21 MCU ARM Cortex-M7:

– Core

 ARM Cortex-M7 at up to 300 MHz.
 16 Kbytes of ICache and 16 Kbytes of DCache with Error Code Correction (ECC).
 Memory Protection Unit (MPU) with 16 zones.
 Simple- and double-precision HW Floating Point Unit (FPU).
 DSP Instructions, Thumb®-2 Instruction Set.
 Embedded Trace Module (ETM) with instruction trace stream, including Trace Port

Interface Unit (TPIU).

– Memories

 2048 Kbytes Embedded Flash.
 384 Kbytes Embedded SRAM.
 Tightly Coupled Memory (TCM) interface with four configurations (disabled, 2 x 32

Kbytes, 2 x 64 Kbytes, and 2 x 128 Kbytes).

 16 Kbytes ROM with embedded Boot Loader routines (UART0, USB) and IAP routines.
 16-bit Static Memory Controller (SMC) with support for SRAM, PSRAM, NOR and NAND

Flash.

 16-bit SDRAM Controller.

– Cryptography

 True Random Number Generator (TRNG).
 AES: 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB-197 Specifications.
 Integrity Check Monitor (ICM). Supports Secure Hash Algorithm SHA1, SHA224 and

SHA256.

 External Memories:

– 4Mx16-bit SDRAM.
– 32-Mbit SPI Data Flash.
– TWI EEPROM (do not populate).
– microSD card connector.

 Peripherals:

– MCU 24 MHz crystal oscillator.
– MCU 32.768 kHz crystal oscillator.
– VDD and 5V Voltage monitor.
– Reset button.
– User’s LEDs.
– Chip erase.

 Interface:

– JTAG debugging port.
– Embedded Trace Module (ETM).

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– High Speed USB 2.0 Device.
– Xplained PRO Master/Slave Interface.
– UARTs over USB and CMOS levels.
– Ethernet 10/100 Mbps.
– Poly-phase Base Node extension header.
– Data Concentrator extension header.
– GPIOs extension header.

Figure 3-2. ATPL250ABNv2 PAN Coordinator board overview.

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A normal use of the ATPL250ABN does not require removing the enclosure cover. If this
action is necessary, it must be performed by qualified staff being sure that mains
connection has been previously removed.

ATSAME70Q21

115/230 VAC

DC/DC

ATPLCOUPxxx Board

MAINS

PLC

RECTIFIER

Zero Crossing

VDD

3V3

2Kb EEPROM

TWI0

SPI + INT

ATPL250A

3V3

User LED’s

Timer Counter Input

PP Exp Header

USART1

USB 2.0 Device

UDP

JTAG / TRACE

JTAG & SWD & TRACE

UARTs CMOS

UART0 & UART1

32Mb SPI

DataFlash

SPI (USART0)

B Micro USB Port

UART

To

USB

24MHz Crystal

RESET

Slow Clock Crystal

12MHz Crystal

Voltage Monitor

10MHz CLK

GPIOs

4Mx16 bit

SDRAM

EBI

AFE

Ethernet

MAC MII

micro SD

Connector

HSMCI

DC Exp Header

UART1

GPIOs Exp Header

GPIOs

3.3 Block diagram

Figure 3-3. ATPL250ABNv2 Block diagram.

3.4 Mechanical and user considerations

This development board is directly powered from mains grid, so hazardous voltage is present on the board.
To avoid user access to dangerous parts, ATPL250ABN must always be used in its enclosure. All required
connectors and configuration jumpers are easily accessible without removing the enclosure cover.

ATPL250ABN is a CE mark product which passes EN60950-1 safety standard and EN50065-1,
EN50065-2-3, EN50065-7 EMC and FCC (as current carrier system) standards. It also satisfies Pb-Free
and ROHS directive.

ATPL250ABN supply voltage is taken from mains grid (100/230VAC, 50-60Hz), J1 connector.
ATPL250ABN dimensions are 178mm x 124mm x 30mm (LxWxH) and the enclosure dimensions are

191mm x 140mm x 48mm (LxWxH).
The operating temperature range is about -10 to 85ºC.

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By default, the voltage jumpers’ configuration is for 230VAC. See Figure 7-10.

3.5 Hardware description

In this section the modules of the ATPL250ABNv2 board are described. Take into account that the board’s
BOM; is not a final design, so they include devices that could be no necessary in the customer designs once
the design has been optimized.

Hardware files are contained in the Hardware folder: “.\Hardware\HW_SCH&PCB\ATPL250ABNv2”.

3.5.1 Power supply

ATPL250ABN board can be powered either with 100VAC or 230VAC by setting the proper jumpers in the
voltage selector (J2, Figure A-2). J1 IEC-320-C8 connector allows cable connection to mains grid. This
design uses an encapsulated transformer (T1, Figure A-2) plus a full bridge rectifier (D1, Figure A-2) to
obtain a DC voltage without increasing noise in PLC frequency bands (42 to 472 kHz), as may occur with
switched ACDC power supplies. F1 and VR1 are used as protective devices in the equipment input and F2
protects the transformer output against over current situations.

The maximum transformer output power of 14VA is oversized compared to the maximum current
consumption of ATPL250ABN when it is used as a G3-PLC PAN Coordinator. However, this design is
intended to power up other development kits which may have considerable power consumption if they
include components such TFT displays.

The “V
to generate the regulated DC voltage “VDD”, which is used to power the class D amplifier of the PLC coupling

circuit. The output level of the buck converter is selectable between 12V and 16V by means of jumper J16.

Refer to the application note “PLC Coupling Reference Designs” doc43052 to know how the jumper J16

must be configured depending on the PLC coupling board which is being used.
A second buck converter (U12, Figure A-2) also with switching frequency above the highest PLC frequency

band is used to generate a regulated 5V voltage rail. Despite 5V is not used by any device on ATPL250ABN
board, it may be useful to power other Atmel evaluation kits to form more complex PLC reference designs,
such as data concentrators. The DC Jack connector J15 (J15, Figure A-10) can be used to connect other
board to 5V.

Finally on the power supply chain scheme, a low dropout (LDO) regulator (U13, Figure A-2) is used to
generate the 3V3 voltage rail required by ATPL250A and the MCU. The current consumption from 3V3
voltage rail can be measured connecting an ammeter in the placeholder of jumper J17.

” voltage rail is used as input power of a high switching frequency buck converter (U11, Figure A-2)

DC

Other 1.2V voltage levels are generated by the embedded LDOs on ATPL250A and ATSAME70Q21
respectively. For a more detailed information about these LDOs, refer to ATPL250A and ATSAME70Q21
datasheets.

Figure 3-4. Power supply diagram.

Switching frequency of DCDC buck converters used in this evaluation kit has been chosen to be higher than
maximum PLC frequency band supported by ATPL250A device.

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We recommend characterizing the potential impact of the selected SMPS for customer
designs on the G3-PLC frequency band transmission.

Be careful with the VDD voltage selected, because the PLC coupling driver board
ATPLCOUPXXX could be damaged. Please check the features of these boards to select
the operation voltage.

Jumper

configuration

VDD could be two different voltages, 16 volts or 12 volts, depending on the jumper position. If the jumper is
not placed, the voltage VDD is 16 volts. If the jumper is placed in J16, VDD is 12 volts. By default, the board
has a jumper, so board provides 12 volts. These different voltages are used to supply the PLC coupling
driver board.

Figure 3-5. VDD selection in ATPL250ABN board.

The following test points and LEDs allow to check that these power supplies are operating properly (see
Figure A-2):

 VDD: TP6 and green LED D17.
 5V: TP5 and green LED D3.
 3V3: TP13 and green LED D13.
 GND: TP3 & TP4.

3.5.2 Zero crossing detector

Phase identification is an important feature of devices that are connected to a smart grid network, such as
smart meters. A typical implementation is based on measuring the time difference between a specific PLC
frame reception and the last zero crossing event of the mains single-phase to which the device is
connected.

Figure A-2 shows the zero crossing detection circuit, U10, used in ATPL250ABN board, which allows
discerning between rising and falling edges of the mains voltage. The output signal of the detection circuit
“VNR” is connected to a specific input of the ATPL250A and a synchronization algorithm is applied in order
to obtain an accurate measurement of the time between PLC frame reception and zero crossing events.

The “VNR” signal is also connected to a timer counter input pin of the ATSAME70Q21 in order to have also

information about zero crossing events on the microcontroller side.
It is important to note that in products that do not require galvanic isolation between primary and secondary

circuits and the digital reference ground is connected to either line or neutral, a simple zenner diode with
proper current limiting resistors, which considerably reduce the BOM cost, can be used instead of the circuit
mounted in ATPL250ABN.

3.5.3 SAME70Q21 Flash microcontroller

3.5.3.1 SAME70Q21 Overview

The Atmel SAME70Q21 Flash microcontroller is based on the high-performance 32-bit ARM Cortex-M7
RISC processor and includes a floating point unit (FPU). It operates at a maximum speed of 300 MHz and

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features 2048 Kbytes of Flash and 384 Kbytes of multiport SRAM, which guarantees a minimum access
latency. The on-chip SRAM can be configured as Tightly Coupled Memory (TCM) or system memory.

The SAME70 offers a rich set of advanced connectivity peripherals including a 10/100 Mbps Ethernet MAC
supporting IEEE 1588, 802.1Qbb, 802.3az, 802.1AS and 802.1Qav. With a simple- and double-precision
HW FPU, advanced analog features, as well as a full set of timing and control functions, the SAME70 is the
ideal solution for industrial automation, home and building control, machine-to-machine communications,
automotive aftermarket and energy management applications.

Furthermore, the peripheral set of SAME70 includes a high-speed USB device port with embedded
transceiver, a high-speed MCI for SDIO/SD/MMC, 16-bit SDRAM interface, 16-bit external bus interface
featuring a static memory controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and
NAND Flash, 12-bit ITU-R BT.601/656 Image Sensor Interface (ISI), hardware acceleration for AES256,
three USARTs, five UARTs, three TWIs, three SPIs, as well as two 4-channel PWM, four three-channel
16-bit Timers with quadrature decoder logic support, one RTC, Analog Front End interfaces (12-bit ADC,
DAC, MUX and PGA), one 12-bit DAC (2-ch) and an analog comparator.

3.5.3.2 SAME70Q21 Clocking

Besides the embedded RC oscillators of ATSAME70Q21, two crystal oscillators are assembled on
ATPL250ABN board to obtain a more precise and stable system clock reference, Y1 of 12 MHz and Y2,
(Figure A-3). Furthermore, a 24MHz clock signal generated by the PLC transceiver ATPL250A is used by
default as clock input by configuring the high frequency oscillator of ATSAME70Q21 in bypass mode. This
configuration allows reducing the overall BOM cost (12MHz crystal oscillator is not required) while keeping a
stable clock input signal.

A slow clock crystal oscillator of 32.768 kHz (Y2, Figure A-3) is used as SAME70 can be used as calendar
and time base counter.

3.5.4 ATPL250A PLC Transceiver

3.5.4.1 ATPL250A Overview

Atmel ATPL250A (U1, Figure A-7) is a power line communications modem, compliant with the PHY layer of
G3-PLC specification. G3-PLC is an open standard technology used for Smart Grid applications like Smart
Metering, Industrial Lighting and Automation, Home Automation, Street Lighting, Solar Energy and PHEV
Charging Stations.

ATPL250A G3-PLC device includes enhanced features such as additional robust modes and frequency
band extension. ATPL250A is able to operate in independently selectable transmission bands up to 472
kHz.

ATPL250A has been conceived to be bundled with an ATMEL MCU running the Physical Layer API and
being controlled by means of a serial synchronous communication interface (SPI).

Please refer to ATPL250A datasheet on the Atmel website or in doc43079 for a detailed description.

3.5.4.2 ATPL250A Clocking

ATPL250A requires a 24MHz crystal oscillator (Y3, Figure A-7). And SAME70Q21 requires a 12 MHz
crystal oscillator (Y1, Figure A-7).

The 24MHz clock signal could be used as internal reference time of the PLC modem, ATPL250A, and also
to generate a 12MHz. So, it could be connected the output clock signal (CLKOUT) of ATPL250A like an
input clock (CLKIN) of SAME70Q21 when ATPL250A is configured in bypass mode. In this way, only one
high frequency crystal oscillator is required. For this option that is mounted by default in the board, R85 is
soldered but R67 and R68 are not populated, and remember that ATPL250A must be configured properly.

Clocking item is widely detailed in the datasheet, doc43079.

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3.5.5 PLC Coupling

Atmel PLC technology is purely digital and does not require external DAC/ADC, thus simplifying the external
required circuitry. Generally Atmel PLC coupling reference designs make use of few passive components
plus a Class D amplification stage for transmission.

Figure A-8 and Figure A-9 show external components required by ATPL250A for PLC reception and
transmission respectively.

PLC coupling reference design is composed by the same sub-circuits:

 Coupling Stage.
 Reception Stage.
 Transmission Stage.
 Filtering Stage.

Figure 3-6. PLC Coupling example.

3.5.5.1 Coupling stage

The coupling stage blocks the DC component of the line to/from which the signal is injected / received (i.e.:
50/60 Hz of the mains). This is carried out by a high voltage capacitor (C26, Figure A-8). Coupling stage
could also voltage isolate the coupling circuitry from the external world by means of a 1:1 PLC transformer.
Capacitor is laying out in ATPL250ABN. The optional PLC transformer is included in ATPLCOUP007 board
(voltage isolated), see section 4.

Footprint of BNC connector (J11, Figure A-8) is included in the board, but is not mounted by default.
Removing the R12 and R13 and soldering R88 and R89 resistors, the PLC coupling signal can be isolated
from the mains grid and that connector allows performing measurements of transmitted and received PLC
signal without side effects (noise) coming from the grid.

3.5.5.2 Reception stage

The reception stage adapts the received analog signal to be properly captured by the internal reception
chain. Reception circuit is independent of the PLC frequency band which is being used. It basically consists
on:

 Single-pole low pass filter (RC Filter), R49 & C43, Figure A-9.

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 Automatic Gain Control (AGC) circuit. The AGC circuit avoids distortion (set of resistors used to

attenuate the incoming PLC signal) on the received signal that may arise when the input signal is high
enough to polarize the protective diodes in direct region (D10, Figure A-9).

 Driver of the internal ADC. The driver to the internal ADC comprises a couple of resistors (DC biasing

resistors, R59 and R60) and a couple of capacitors (DC decoupling capacitors, C45 and C46). This
driver provides a DC component and adapts the received signal to be properly converted by the
internal reception chain.

3.5.5.3 Transmission stage

The transmission stage adapts the EMIT signals and amplifies them if required (Figure A-8). It can be
composed by:

 Driver: A group of resistors which adapt the EMIT signals to either control the Class-D amplifier or to

be filtered by the next stage.

 Amplifier: If required, a Class-D amplifier which generates a square waveform from 0 to VDD is

included.

 Bias and protection: A couple of resistors and a couple of Schottky barrier diodes provide a DC

component and provide protection from received disturbances.

Transmission stage shall be always followed by a filtering stage.

3.5.5.4 Filtering stage

The filtering stage is composed by band-pass filters which have been designed to achieve high
performance in field deployments complying at the same time with the proper normative and standards.

The in-band flat response filtering stage does not distort the injected signal, reduces spurious emission to
the limits set by the corresponding regulation and blocks potential interferences from other transmission
frequency bands.

The filtering stage has three aims:

 Band-pass filtering of high frequency components of the square waveform generated by the

transmission stage.

 Adapt Input/Output impedances for optimal reception/transmissions. This is controlled by TXRX

signals.

 And, in some cases, Band-pass filtering for received signals.

When the system is intended to be connected to a physical frequency band with high voltage or which is not
electrically referenced to the same point then the filtering stage must be always followed by a coupling
stage.

These components are not implemented on ATPL250ABN board because are dependent on the application
parameters such frequency band transmission. A set of boards known as ATPLCOUPxxx have been design
by to support multiple transmission options supported by ATPL250A. PANCoordinator-EK includes
ATPLCOUP007, ATPLCOUP002 and ATPLCOUP006 boards which are described in chapters 4, 5 and 6
respectively. Other coupling boards have been designed. The Application Note, doc43052, provides a
complete description of Atmel PLC Coupling Reference Designs available.

3.5.5.5 ATPLCOUP boards

Table 3-1 summarizes the main characteristics of currently available PLC coupling reference designs.
Please refer to Atmel doc43052 for a complete description of ATPLCOUP boards.

This technology only allows one frequency band active at a time.

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Board Name

Frequency Band

Branch

Electrical

Isolation

CENELEC

Band

ARIB

FCC

ATPLCOUP002

152-405 kHz

Double

Yes

- X -

ATPLCOUP006

152-489 kHz

Double

Yes - - X ATPLCOUP007

35-91 kHz

Single

Yes A - - ATPLCOUP008

35-91 kHz

Single

No A -

-

Table 3-1. ATPLCOUP boards.

Figure 3-7. FCC & ARIB bands.

3.5.6 Peripherals

These peripherals are not necessary to implement a G3-PLC design, they are included to show some
features of the ATPL250A for a customer designs.

3.5.6.1 SDRAM

The amount of data to be managed by a PAN Coordinator device typically exceeds the embedded SRAM
density of ATSAME70Q21 (384kB). To overcome this limitation, an external SDRAM with 4Mx16-bit density
is used in ATPL250ABN to support a big quantity of connected devices.

3.5.6.2 Data Flash

A 4MB SPI serial DataFlash is used to extend the non-volatile memory capability of ATSAME70Q21 (1MB).
Two different packages (U3 and U12, Figure A-4) are used in ATPL250ABN board to support the pinout of

both the Adesto (former Atmel) family of DataFlash memories and standard serial flash products. Since both
packages use the same chip select signal, only one device can be assembled simultaneously.

3.5.6.3 EEPROM

ATPL250ABN board includes the possibility to mount a serial EEPROM memory connected by Two Wires
Interface, TWI, (U2, Figure A-4) with the SAME70. This device is not assembled by default. Please refer to
AT24Cxx datasheet for a further description on Atmel’s website.

3.5.6.4 microSD card connector

The high speed multimedia card interface (HSMCI) peripheral of ATSAME70Q21 supports the SD memory
card specification V2.0. A microSD card connector with card detection switch is used in ATPL250ABN
board. The card detection feature can be implemented by means of a GPIO with interrupt capability.

3.5.6.5 Voltage Monitor

Two ports (PB2 and PD30) of the ATSAME70Q21 analog front end module are used to monitor the VDD and
5V voltage rails through external voltage divisors, as shown in Figure A-3.

The voltage monitor circuit allows the implementation of multiple applications such as:

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 Detection of fault conditions.
 Detection of low power mode entering conditions.
 Detection of wake-up situations.
 Measuring of PLC power amplifier voltage value.

The selected ports for the voltage monitor circuit can also be used as input of the analog comparator in
ATSAME70Q21.

3.5.6.6 Reset

Besides the reset conditions managed by the reset controller peripheral of the ATSAME70Q21, such as
power-on-reset and brown-out monitor, two other reset sources are added at PCB level in ATPL250ABN:

 User controller reset switch button (SW1).
 The “NRST_CONC” signal on the data concentrator expansion connector, which allows resetting the

The input/output “NRST” pin of ATSAME70Q21 is connected to the “PLL_INIT” input reset pin of the

ATPL250A. Therefore, all reset conditions commented above, generate also a complete reset of the PLC
transceiver. It is important to note that a reset event on “PLL_INIT” disables the “CLKOUT” output pin and, in
case the ATSAME70Q21 is using this clock signal as the external clock input in bypass mode, a reset
condition may lead to a loss of master clock on the microcontroller if a proper configuration is not applied by
firmware. The firmware releases provided by Atmel for the base node reference design take this condition
into account.

base node reference design when it is used in data concentrator topologies.

In addition to the complete reset of the PLC transceiver generated by an assertion of the “PLL_INIT” input,

the “ARST” and “SRST” input reset signals allow also resetting the ATPL250A but in each of these cases

without disabling the external clock on “CLKOUT” pin. Therefore, no special configurations have to be

considered on the microcontroller side related to the clock system configuration. “ARST” and “SRST” are
managed by the GPIOs PE1 and PE2 respectively in ATPL250ABN board.

3.5.6.7 Chip Erase

The 1x2 right angle pin-header J14 marked as “ERASE” (see Figure A-3) is connected to the SAME70 chip
erase pin (PB12) and 3V3. This header can be used to erase the ATSAME70Q21 flash memory by placing
a jumper on the header and pressing the reset switch button. After a while, the erase jumper should be
removed and the PCBA must be turn off and turn on by disconnecting and connecting it again to the mains
grid (flash erasing takes only 200ms).

3.5.6.8 User LEDs

The board incorporates two user LEDs (LED0 & LED1), green and red (D5 & D6, Figure A-3), connected to
GPIOs PA21 and PA22 respectively of the SAME70Q21.

3.5.7 Interface Ports

3.5.7.1 ATSAME70Q21 JTAG/SWD Debug Port

The ATSAME70Q21 JTAG/SWD interface is available in a standard 20 pins male right angle header for
debugging and programming purposes.

Please, refer to ATSAME70Q21 datasheet for a more detailed description of the debug port. It is important
to note that JTAG is only available for boundary scan manufacturing test purposes.

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3.5.7.2 Embedded Trace Module (ETM)

The Embedded Trace Macrocell (ETM) is a real-time trace module which delivers unrivalled instruction
trace capture in an area far smaller than traditional trace units, enabling the SAME70 MCU to implement full
instruction trace.

The ETM depends on the Trace Port Interface Unit (TPIU) to export data out of the system. The TPIU
features the following pins:

 TRACECLK is the data stream synchronization signal
 TRACED0-TRACED3

ATPL250ABN implements a CoreSight™ 20, 20-pin, 50-mil keyed connector (pin seven is removed).
Besides the TPIU signals, the CoreSight connector features also a Serial Wire Debug (SWD) interface.

Considering that the TPIU signals of the ATSAME70Q21 are multiplexed with the GMAC Ethernet RMII
interface, it is not possible to use the ETM if the Ethernet port is enabled. Furthermore, if ETM is used, it is
important to keep the Ethernet PHY IC in reset mode (GPIO PD31 must be asserted low) to avoid signal
collisions.

3.5.7.3 High-speed USB Device 2.0

The ATPL250ABN has a micro-USB receptacle connected to the high-speed USB device 2.0 module of
ATSAME70Q21. To be able to detect when a USB host is attached to ATPL250ABN board, a GPIO (PC17)
is used to detect the VBUS voltage on the connector. The 5V voltage rail provided by the USB host is not
used in ATPL250ABN rather than for detection purpose.

3.5.7.4 Debug UART

The UART0 of ATSAME70Q21 is connected to a CP2105 UART to USB 2.0 bridge to ease PC connectivity
for debugging purposes. The firmware projects provided by Atmel to ease the evaluation of the G3
PHY-layer performance are based on serial interface through UART0.

As shown in Figure A-5, the UART to USB bridge CP2105 is powered from the 3.3V LDO on ATPL250ABN
rather than from the 5V voltage rail of the USB connection. Therefore, ATPL250ABN board has to be
connected to mains if the debugging UART is going to be used.

UART0 signals in CMOS levels are also available in the 3-pins right angle header J5.

3.5.7.5 Ethernet

The ATSAME70Q21 has a built in 10/100 Mbps Ethernet IEEE® 802.3 MAC with a RMII interface that
connects to a Micrel KSZ8081RNA PHY-layer transceiver. The Ethernet input and output differential pairs of
the PHY-layer transceiver are directly connected to a RJ45 Ethernet connector with embedded isolating
signal transformers.

Refer to Figure A-6 for a complete view of the Ethernet PHY-layer transceiver design.

3.5.7.6 Poly-Phase Expansion Header

The 10-pin dual row male header J8 contains the USART transmission and reception signals of
ATSAME70Q21 USART1 and two extra GPIOs. This expansion header is intended to cover poly-phase
PLC base node reference designs in combination with other Atmel evaluation boards.

3.5.7.7 Data Concentrator Expansion Header

The 10-pin dual row male header J4 contains the UART transmission and reception signals of
ATSAME70Q21 UART1 and two extra GPIOs. Furthermore, as commented in section 3.5.6.6, a reset input
of ATPL250ABN board is available as well. This expansion header is intended to cover data concentrator
reference designs in combination with other Atmel evaluation boards.

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3.5.7.8 GPIOs Expansion Header

The 2.54mm pitch right-angle header J12 offers access to the I/O ports of the microcontroller that are not
used within the ATPL250ABN board. Refer to ATSAME70Q21 datasheet for a description of the peripheral
functionality available of each GPIO.

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PLC transformer provides

the voltage isolation from

mains.

Test point.

TX led indication.

Test point.

Test point.

Test point.

4. ATPLCOUP007 Hardware

4.1 Overview

ATPLCOUP007 is a PLC coupling board designed to communicate in CENELEC-A band, especially in
G3-PLC band, from 35 to 91 kHz. ATPLCOUP007 mounts a single branch with voltage isolation from mains
to the PLC coupling driver board. The goal of this design is provided to the customers with a cost optimized
performance transmission board in CENELEC-A band for G3-PLC. This board is set by default in the
ATPL250ABN board of the PANCoordinator-EK.

Figure 4-1. CENELEC bands.

4.2 Features

The ATPLCOUP007v2.5 board includes the following features:

 Specially designed to communicate in CENELEC-A frequency band (35 – 91 kHz).
 Voltage Isolation from mains with a transformer, MSR EXL-165S-LT, soldered in top layer board.
 Single branch:

– Low impedance optimized.

Figure 4-2. ATPLCOUP007v2.5 PLC Coupling board (top view).

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Jumper

configuration

4.3 Mechanical and user considerations

ATPLCOUP007 is delivered with the PANCoordinator-EK. Board-to-board SMD connectors, J1 and J2, are
used to connect the ATPLCOUP007 into connectors J6 and J7 of ATPL250ABN board (Figure A-8). These
J1 and J2 connectors are in bottom layer of ATPLCOUP007 and they have the following part numbers:

 J1: SAMTEC FTR-130-54-L-S.
 J2: SAMTEC FTR-124-54-L-S.

The ATPLCOUP007 board is directly powered from mains grid, so hazardous voltage is present on the
board. To avoid user access to dangerous parts, ATPLCOUP007 must always be used in its enclosure.

ATPLCOUP007 is a CE mark product that passes EN 50065-1, EN 50065-2-3 and EN 50065-7 EMC
standards. It also satisfies Pb-Free and ROHS directive.

ATPLCOUP007 dimensions are 51.5mm x 39.5mm x 18mm (LxWxH).
The operating temperature range is about -40 to 85ºC.

4.4 Hardware description

Hardware files are contained in the Hardware folder: “.\Hardware\HW_SCH&PCB\ATPLCOUP007v2.5”.
ATPLCOUP007 is an isolated reference design which provides a full performance PLC coupling reference

design in terms of output signal level over a wide range of load impedance values while complying with
EN50065-1, EN50065-2-3 and EN50065-7 normative. It supports the frequency band between 35 and 91
kHz of CENELEC-A band.

ATPLCOUP007 is composed of only one transmission branch (single branch) which filtering stage has a flat
band pass response with typical field impedances. It involves a cost optimization in the BOM. For more
information, see PLC coupling reference designs document, doc43052.

Take into account that, when ATPLCOUP007 is connected to ATPL250ABN, VDD voltage must be 12 volts
to avoid damaging the coupling board, so jumper in J16 must be set (see section 3.5.1 and Figure A-2). By
default, the jumper is placed in J16.

Figure 4-3. VDD selection in ATPL250ABN board.

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