Atmel ATmega8U2, ATmega16U2, ATmega32U2 Datasheet

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 125 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz

• Non-volatile Program and Data Memories

– 8K/16K/32K Bytes of In-System Self-Programmable Flash – 512/512/1024 EEPROM – 512/512/1024 Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 25°C

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by on-chip Boot Program hardware-activated after reset True Read-While-Write Operation

– Programming Lock for Software Security

• USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification REV 2.0 – 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s – Fully independant 176 bytes USB DPRAM for endpoint memory allocation – Endpoint 0 for Control Transfers: from 8 up to 64-bytes – 4 Programmable Endpoints:

IN or Out Directions Bulk, Interrupt and IsochronousTransfers Programmable maximum packet size from 8 to 64 bytes

Programmable single or double buffer – Suspend/Resume Interrupts – Microcontroller reset on USB Bus Reset without detach – USB Bus Disconnection on Microcontroller Request

• Peripheral Features

– One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit

PWM channels)

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode

(three 8-bit PWM channels) – USART with SPI master only mode and hardware flow control (RTS/CTS) – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• On Chip Debug Interface (debugWIRE)

• Special Microcontroller Features

– Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 22 Programmable I/O Lines – QFN32 (5x5mm) / TQFP32 packages

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range

Note: 1. See “Data Retention” on page 6 for details.

8-Bit Microcontroller

(1)

8-bit Microcontroller with 8/16/32K Bytes of ISP Flash and USB Controller

ATmega8U2 ATmega16U2 ATmega32U2

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1. Pin Configurations

UVCC

QFN32

(PCINT11 / AIN2 ) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5/ AIN3) PD4

(TXD1 / INT3) PD3

(XCK / AIN4 / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

282726 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D-

D+

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / AIN5 / INT6) PD6

(CTS

/ HWB / AIN6 / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVCC

UVCC

VQFP32

(PCINT11 /AIN2 ) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5/ AIN3) PD4

(TXD1 / INT3) PD3

(XCK AIN4 / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

282726 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D-

D+

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / AIN5 / INT6) PD6

/ HWB

/ AIN6 / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVCC

Figure 1-1. Pinout

ATmega8U2/16U2/32U2

1.1 Disclaimer

Note: The large center pad underneath the QFN package should be soldered to ground on the board to

ensure good mechanical stability.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

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ATmega8U2/16U2/32U2

PROGRAM COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

INTERRUPT

UNIT

EEPROM

USART1

STATUS

ALU

PORTC DRIVERS

PORTD DRIVERS

PORTB DRIVERS

PC7 - PC0 PD7 - PD0

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PB7 - PB0

D+/SCK D-/SDATA

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB

PS/2

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

ON-CHIP DEBUG

Debug-Wire

PROGRAMMING

LOGIC

DATA DIR.

REG. PORTD

DATA REGISTER

PORTD

POR - BOD

RESET

PLL

SPI

ON-CHIP

3.3V

REGULATOR

UVcc

UCap

1uF

2. Overview

The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting

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ATmega8U2/16U2/32U2

architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega8U2/16U2/32U2 provides the following features: 8K/16K/32K Bytes of In-System Programmable Flash with Read-While-Write capabilities, 512/512/1024 Bytes EEPROM, 512/512/1024 SRAM, 22 general purpose I/O lines , 32 general purpose work ing registers, two flexible Timer/Counters with compare modes and PWM, one USART, a prog rammable Watchdog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system and programmi n g and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, the main Oscillator continues to run.

The device is manufactured using Atmel’s high -dens ity no nvola tile memo ry tec hnol ogy. The onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega8U2/16U2/32U2 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega8U2/16U2/32U2 are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 AVCC

AVCC is the supply voltage pin (input) for all analog features (Analog Comparator, PLL). It should be externally connected to VCC through a low-pass filter.

2.2.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

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Port B also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on

page 74.

2.2.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of various special features of the ATmega8U2/16U2/32U2 as listed on page 77.

2.2.6 Port D (PD7..PD0)

Port D serves as analog inputs to the analog comparator. Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-

cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.2.7 D-

USB Full Speed Negative Data Upstream Port

ATmega8U2/16U2/32U2

2.2.8 D+

2.2.9 UGND

2.2.10 UVCC

2.2.11 UCAP

2.2.12 RESET/PC1/dW

2.2.13 XTAL1

USB Full Speed Positive Data Upstream Port

USB Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System Control and

Reset” on page 47. Shorter pulses are not guaranteed to generate a reset. This pin alternatively

serves as debugWire channel or as generic I/O. The configuration depen ds on the fuses RSTDISBL and DWEN.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.14 XTAL2/PC0

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Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

4. Code Examples

This documentation contains simple code examples that briefly sh ow how to use vari ous parts of the device. Be aware that not all C compiler vendors include bit def initions in the header files and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumentation for more details.

These code examples assume that the part spe cific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBI C", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega8U2/16U2/32U2

7799D–AVR–11/10

6. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

6.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

6.2 Architectural Overview

Figure 6-1. Block Diagram of the AVR Architecture

ATmega8U2/16U2/32U2

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipe lining. While one instruc tion is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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ATmega8U2/16U2/32U2

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega8U2/16U2/32U2 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU opera tions are divided into three main categories – arithmetic, logical, and bit-functions. See the “Instruction Set” section for a detailed description.

6.4 Status Register

7799D–AVR–11/10

The Status Register contains information about the r esult of th e most recen tly executed arith metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in man y case s re move th e need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be ha nd le d by software.

6.4.1 SREG – Status Register

Bit 76543210 0x3F (0x5F) ITHSVNZCSREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

ATmega8U2/16U2/32U2

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

7799D–AVR–11/10

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

6.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11

ATmega8U2/16U2/32U2

70Addr. R0 0x00

R1 0x01 R2 0x02 … R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

6.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some a dded functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.

7799D–AVR–11/10

6.6 Stack Pointer

ATmega8U2/16U2/32U2

Figure 6-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed d isplacem ent, automatic increment, and automatic decrement (see the instruction set reference fo r details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure

7-2 on page 18.

See Table 6-1 for Stack Pointer details.

Table 6-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALL ICALL RCALL

POP Incremented by 1 Data is popped from the stack

RET RETI

Decremented by 2

Incremented by 2 Return address is popped from the stack with return from

Return address is pushed onto the stack with a subroutine call or interrupt

subroutine or return from interrupt

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

7799D–AVR–11/10

6.6.1 SPH and SPL – Stack Pointer High and Low Register

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

Bit 1514131211109 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

11111111

6.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast- access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

, directly generated from the selected clock source for the

CPU

ATmega8U2/16U2/32U2

Figure 6-4. The Parallel Instruction Fetches and Instruction Executions

Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 6-5. Single Cycle ALU Operation

7799D–AVR–11/10

6.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with th e Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 246 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 64. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 64 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 246.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

ATmega8U2/16U2/32U2

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap pears befo re the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

7799D–AVR–11/10

ATmega8U2/16U2/32U2

CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

7799D–AVR–11/10

Assembly Code Example

sei ; set Global Interrupt Enable sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending ; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

6.8.1 Interrupt Response Time

The interrupt execution response for all the enabl ed AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling ro utine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

ATmega8U2/16U2/32U2

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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7. AVR Memories

This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

7.1 In-System Reprogrammable Flash Program Memory

The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable Flash memory for program storage . Since all AVR instructio ns are 16 or 32 bits wide, the Flas h is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The ATmega8U2/16U2/32U2 Program Counter (PC) is 16 bits wide, thus addressing the 8K/16K/32K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Memory Programming” on page

246. “Memory Programming” on page 246 contains a detailed description on Flash data serial

downloading using the SPI pins or the debugWIRE interface. Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description and ELPM - Ex tended Load Program Me mory instruction description).

ATmega8U2/16U2/32U2

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

7799D–AVR–11/10

Figure 7-1. Program Memory Map

0x00000

0x1FFF (8KBytes)

0x3FFF (16KBytes)

Program Memory

Application Flash Section

Boot Flash Section

0x7FFF (32KBytes)

ATmega8U2/16U2/32U2

7.2 SRAM Data Memory

Figure 7-2 shows how the ATmega8U2/16U2/32U2 SRAM Memory is organized.

The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 768 Data Memory locations address the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory, and the 512 locations of internal data SRAM.The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Postincrement. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base addres s given

by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

7799D–AVR–11/10

The 32 general purpose working registers, 64 I/O registers, and the 512/512/1024bytes of inter-

32 Registers

64 I/O Registers

Internal SRAM

(512/512/1024 x 8)

$0000 - $001F $0020 - $005F

$2FF/$2FF/$4FF (8U2/16U2/32U2)

$0060 - $00FF

Data Memory

160 Ext I/O Reg.

$0100

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

nal data SRAM in the ATmega8U2/16U2/32U2 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

Figure 7-2. Data Memory Map

7.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

ATmega8U2/16U2/32U2

cycles as described in Figure 7-3.

CPU

7.3 EEPROM Data Memory

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Figure 7-3. On-chip Data SRAM Access Cycles

The ATmega8U2/16U2/32U2 contains 512/512/1024 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/er ase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 259, page 244, and page 250 respectively.

7.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 7-2 on page 22. A self-timing function,

however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be take n. In heavily filtered power supplies, V some period of time to run at a voltage lower th an sp ecified as min imum for the clo ck freq uency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.3.2 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

ATmega8U2/16U2/32U2

is likely to rise or fall slowly on power-up/down. This causes the device for

the EEPROM data can be corrupted because the supply voltage is

CC,

7.4 I/O Memory

An EEPROM data corruption can be caused by two situ at ion s wh en the vo lt age is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-ou t Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V

reset Protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the ATmega8U2/16U2/32U2 is shown in “Register Summary” on

page 288.

All ATmega8U2/16U2/32U2 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega8U2/16U2/32U2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Op code for the IN and OUT instructions. For the

7799D–AVR–11/10

Extended I/O space from 0x60 - 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

7.4.1 General Purpose I/O Registers

The ATmega8U2/16U2/32U2 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

7.5 Register Description

ATmega8U2/16U2/32U2

7.5.1 EEARH and EEARL – The EEPROM Address Register

Bit 1514131211 10 9 8 0x22 (0x42) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 210

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

XXXXX XXX

• Bits 15:12 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 11:0 – EEAR[8:0]: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

7.5.2 EEDR – The EEPROM Data Register

Bit 76543210 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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• Bits 7:0 – EEDR[7:0]: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.5.3 EECR – The EEPROM Control Register

Bit 76543210 0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for th e differen t modes are shown in Table 7- 1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

ATmega8U2/16U2/32U2

Table 7-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Time Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

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ATmega8U2/16U2/32U2

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Me mory Pr o-

gramming” on page 246 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a log ic one to trig ger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-2 lists the typic al programming time for EEPROM access from the CPU.

Table 7-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

26,368 3.3 ms

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ATmega8U2/16U2/32U2

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData) {

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

; /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

(1)

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Note: 1. See “Code Examples” on page 6.

ATmega8U2/16U2/32U2

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

(1)

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR ret

C Code Example

(1)

unsigned char EEPROM_read(unsigned int uiAddress) {

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

Note: 1. See “Code Examples” on page 6.

7.5.4 GPIOR2 – General Purpose I/O Register 2

Bit 76543210 0x2B (0x4B) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

7.5.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210 0x2A (0x4A) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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7.5.6 GPIOR0 – General Purpose I/O Register 0

Bit 76543210 0x1E (0x3E) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

ATmega8U2/16U2/32U2

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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 42. The clock systems are detailed below.

Figure 8-1. Clock Distribution

ATmega8U2/16U2/32U2

8.1.1 CPU Clock – clk

CPU

USB

clk

USB PLL

clk

PLL Clock Prescaler

clk

USB (48MHz)

Pllin (8MHz)

XTAL (2-16 MHz)

Crystal

Oscillator

General I/O

Modules

clk

CPU Core RAM

I/O

AVR Clock

Control Unit

Source clock

System Clock

Prescaler

Clock

Multiplexer

External

Clock

clk

CPU

clk

FLASH

Watchdog TimerReset Logic

Watchdog clock

Watchdog Oscillator

Flash and EEPROM

Calibrated RC

Oscillator

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

8.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

8.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

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FLASH

ATmega8U2/16U2/32U2

USB

CPU Clock

External Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

3ms

resume

Resume from Host

Watchdog wake-up from power-down

8.1.4 USB Clock – clk

8.2 Clock Switch

8.2.1 Exemple of use

USB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48 MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8 MHz clock on the PLL input.

In the ATmega8U2/16U2/32U2 product, the Clock Multiplexer and the System Clock Presca ler can be modified by software.

The modification can occur when the device enters in USB Suspend mode. It th en switches from External Clock to Calibrated RC Oscillator in order to reduce consumption. In such a configuration, the External Clock is disabled.

The firmware can use the watchdog timer to be woken-up from power-down in order to check if there is an event on the application.

If an event occurs on the application or if the USB controller signals a non-idle state on the USB line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC Oscillator to the External Clock.

Figure 8-2. Example of clock switching with wake-up from USB Host

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Figure 8-3. Example of clock switching with wake-up from Device

USB

CPU Clock

External Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

3ms

upstream-resume

Upstream Resume from device

Watchdog wake-up from power-down

8.2.2 Clock switch Algorythm

8.2.2.1 Swith from external clock to RC clock

if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1) { Usb_ack_suspend(); // UDINT.SUSPI = 0; Usb_freeze_clock(); // USBCON.FRZCLK = 1; Disable_pll(); // PLLCSR.PLLE = 0; Enable_RC_clock(); // CLKSEL0.RCE = 1; while (!RC_clock_ready()); // while (CLKSTA.RCON != 1); Select_RC_clock(); // CLKSEL0.CLKS = 0; Disable_external_clock(); // CLKSEL0.EXTE = 0; }

ATmega8U2/16U2/32U2

8.2.2.2 Switch from RC clock to external clock

if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1) { Usb_ack_wake_up(); // UDINT.WAKEUPI = 0; Enable_external_clock(); // CKSEL0.EXTE = 1; while (!External_clock_ready()); // while (CLKSTA.EXTON != 1); Select_external_clock(); // CLKSEL0.CLKS = 1; Enable_pll(); // PLLCSR.PLLE = 1; Disable_RC_clock(); // CLKSEL0.RCE = 0; while (!Pll_ready()); // while (PLLCSR.PLOCK != 1); Usb_unfreeze_clock(); // USBCON.FRZCLK = 0; }

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8.3 Clock Sources

ATmega8U2/16U2/32U2

The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 8-1. Device Clocking Options Select

Device Clocking Option CKSEL3:0

Low Power Crystal Oscillator 1111 - 1000 Full Swing Crystal Oscillator 0111 - 0110 Reserved 0101 - 0100 Reserved 0011 Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0001

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.3.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0 MHz and with the fuse CKDIV8 programmed, resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting u sing a ny available prog ramming inter face.

8.3.2 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.

(1)

to start oscillating and a minimum number of oscillating

To ensure sufficient V

, the device issues an internal reset with a time-out delay (t

TOUT

) after the device reset is released by all other reset sources. “On-chip Debug System” on page 45 describes the start conditions for the internal reset. The delay (t

) is timed from the Watchdog

TOUT

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “Typical Characteristics” on page 273.

Table 8-2. Number of Watchdog Oscillator Cycles

Ty p Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

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The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-

XTAL2

XTAL1

GND

ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.

8.4 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-4. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power con sumption, bu t is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

ATmega8U2/16U2/32U2

Figure 8-4. Crystal Oscillator Connections

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.

Table 8-3. Low Power Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1

Frequency Range

0.4 - 0.9 100

0.9 - 3.0 101 12 - 22

3.0 - 8.0 110 12 - 22

8.0 - 16.0 111 12 - 22

(1)

(MHz) CKSEL3..1

(2)

(3)

and C2 (pF)

–

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Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

ATmega8U2/16U2/32U2

3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Start-up Time from

Power-down and

Power-save

258 CK 14CK + 4.1 ms

258 CK 14CK + 65 ms

1K CK 14CK

1K CK 14CK + 4.1 ms

1K CK 14CK + 65 ms

16K CK 14CK 1 01

16K CK 14CK + 4.1 ms 1 10

16K CK 14CK + 65 ms 1 11

Additional Delay

from Reset

= 5.0V) CKSEL0 SUT1..0

(1)

(2)

000

001

010

011

100

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

7799D–AVR–11/10

Table 8-5. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

Power Conditions

down and Power-save

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms

Reserved 1 1

Note: 1.

The device is shipped with this option selected.

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

8.5 Full Swing Crystal Oscillator

This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current consumption is higher than the “Low Power Crystal Oscillator” on page 30. Note that the Full Swing Crystal Oscillator will only operate for V

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 1. For ceramic resonators, the capacitor values given by the manufacturer should be used.

= 2.7 - 5.5 volts.

ATmega8U2/16U2/32U2

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Table 1. Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Start-up Time from Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

Power-down and

Power-save

258 CK 14CK + 4.1 ms

258 CK 14CK + 65 ms

1K CK 14CK

1K CK 14CK + 4.1 ms

1K CK 14CK + 65 ms

16K CK 14CK

16K CK 14CK + 4.1 ms

16K CK 14CK + 65 ms

Additional Delay

from Reset

= 5.0V) CKSEL0 SUT1..0

(1)

(2)

000

001

010

011

100

8.6 Calibrated Internal RC Oscillator

By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See Table

26-1 on page 266 for more details. The device is shipped with the CKDIV8 Fuse programmed.

See “System Clock Prescaler” on page 35 for more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 8-6. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in

Table 26-1 on page 266.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 38, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 26-1 on page 266.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 249.

Table 8-6. Internal Calibrated RC Oscillator Operating Modes

Frequency Range

(3)

(2)

(MHz) CKSEL3..0

7.3 - 8.1 0010

(1)

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-5 on page 31.

Table 8-7. Start-up times for the internal calibrated RC Oscillator clock selection

), the CKDIV8

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14 CK 00 Fast rising power 6 CK 14 CK + 4.1 ms 01 Slowly rising power 6 CK 14 CK + 65 ms

Note: 1. The device is shipped with this option selected.

down and Power-save

Reserved 1 1

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

7799D–AVR–11/10

8.7 External Clock

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

ATmega8U2/16U2/32U2

The device can utilize a external clock source as shown in Figure 8-5. To run the device on an external clock, the CKSEL Fuses must be programmed as shown in Table 8-1.

Figure 8-5. External Clock Drive Configuration

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-8.

Table 8-8. Start-up Times for the External Clock Selection

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

35 for details.

8.8 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to d rive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

Start-up Time from Power-

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

8.9 System Clock Prescaler

7799D–AVR–11/10

The ATmega8U2/16U2/32U2 has a system clock prescaler, an d the system clock can be divided by setting the “CLKPR – Clock Prescale Register” on page 39. This feature can be used to

ATmega8U2/16U2/32U2

decrease the system clock frequency and the powe r consump t ion when the r equ ire ment for pr ocessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk a factor as shown in Table 8-9 on page 40.

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to th e pr eviou s setting, nor the clock frequency co rresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write proce dure is not interrupted.

I/O

, clk

CPU

, and clk

are divided by

FLASH

8.10 PLL

The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1).

8.10.1 Internal PLL for USB interface

The internal PLL in ATmega8U2/16U2/32U2 generates a clock frequency that is 6x multiplied from nominally 8 MHz input. The source of the 8 MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 8 MHz.

7799D–AVR–11/10

Figure 8-6. PLL Clocking System

8 MHz

RC OSCILLATOR

XTAL1 XTAL2

XTAL

OSCILLATOR

PLL

PLLE

Lock

Detector

Tclk

Timer1

To S y stem Clock Prescaler

clk

8MHz

PLL clock Prescaler

PINDIV

PDIV3..0

clk

USB

/48

PLLITM

PLLUSB

CKSEL3:0

PLOCK

8.1 1 Register Description

8.11.1 CLKSEL0 – Clock Selection Register 0

Bit 76543210 (0xD0) RCSUT1 RCSUT0 EXSUT1 EXSU T0 RCE EXTE - CLKS CLKSEL0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 See Bit Description

ATmega8U2/16U2/32U2

7799D–AVR–11/10

• Bit 7:6 – RCSUT[1:0]: SUT for RC oscillator

These 2 bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits. A firmware change will not have any effect because this additionnal start-up time is only used after a reset and not after a clock switch.

• Bit 5:4 – EXSUT[1:0]: SUT for External Oscillator / Low Power Oscillator

These 2 bits are the SUT value for the External Oscillator / Low Power Oscillator. If the External oscillator / Low Power Oscillator is selected by fuse bits, the SUT fuse are copyed into these bits. The firmware can modify these bits by writing a new value. This value will be used at the next start of the External Oscillator / Low Power Oscillator.

• Bit 3 – RCE: Enable RC Oscillator

The RCE bit must be written to logic one to enable the RC Oscillator. The RCE bit must be written to logic zero to disable the RC Oscillator.

• Bit 2 – EXTE: Enable External Oscillator / Low Power Oscillator

The OSCE bit must be written to logic one to enable External Oscillator / Low Power Oscillator. The OSCE bit must be written to logic zero to disable the External Oscillator / Low Power Oscillator.

• Bit 0 – CLKS: Clock Selector

The CLKS bit must be written to logic one to select the External Oscillator / Low Power Oscillator as CPU clock. The CLKS bit must be written to logic zero to select the RC Oscillator as CPU clock. After a reset, the CLKS bit is set by hardware if the External Oscillator / Low Power Oscil-

lator is selected by the fuse bits configuration. The firmware has to check if the clock is correctly started before selected it.

8.11.2 CLKSEL1 – Clock Selection Register 1

Bit 76543210 (0xD1) RCCKSEL3RCCKSEL2RCCKSEL1RCCKSEL0EXCKSEL3EXCKSEL2EXCKSEL1EXCKSEL0CLKSEL1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 1 0 0 0 0 0

• Bit 7:4 – RCCKSEL[3:0]: CKSEL for RC oscillator

Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the 0010b value that corresponds to the RC oscillator. Modifying this value by firmware before switching to RC oscillator is prohibited because the RC clock will not start.

• Bit 3:0 – EXCKSEL[3:0]: CKSEL for External oscillator / Low Power Oscillator

Clock configuration for the External Oscillator / Low Power Oscillator. After a reset, if the External oscillator / Low Power Oscillator is selected by fuse bits, this part of the register is loaded with the fuse configuration. Firmware can modify it to change the start-up time after the clock switch.

ATmega8U2/16U2/32U2

8.11.3 CLKSTA – Clock Status Register

Bit 76543210 (0xD2) - - - - - - RCON EXTON CLKSTA Read/Write RRRRRRRR Initial Value 0 0 0 0 See Bit Description

• Bit 7:2 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 1 – RCON: RC Oscillator On

This bit is set by hardware to one if the RC Oscillator is running. This bit is set by hardware to zero if the RC Oscillator is stoped.

• Bit 0 – EXTON: External Oscillator / Low Power Oscillator On

This bit is set by hardware to one if the External Oscillator / Low Power Oscillator is running. This bit is set by hardware to zero if the External Oscillator / Low Power Oscillator is stoped.

8.11.4 OSCCAL – Oscillator Calibration Register

Bit 76543210 (0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

7799D–AVR–11/10

• Bits 7:0 – CAL[7:0]: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 26-1 on page 266. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 26-

1 on page 266. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL[6:0] bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range.

8.11.5 CLKPR – Clock Prescale Register

Bit 76543210 (0x61) CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description

ATmega8U2/16U2/32U2

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bit 6:4 - Reserved bits

These bits are reserved and will always read as zero.

• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 8-9.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software m ust ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Table 8-9. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0 1 1 1 128 1 0 0 0 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

8.11.6 PLLCSR – PLL Control and Status Register

Bit 76543210 0x29 (0x49) – – – DIV5 DIV3 PINDIV PLLE PLOCK PLLCSR Read/WriteRRRR/WRRR/WR Initial Value 0 0 0 0 0 0 0 0

• Bit 7:5 – Res: Reserved Bits

These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero .

• Bit 4 – DIV5 PLL Input Prescaler (1:5)

• Bit 3 – DIV3 PLL Input Prescaler (1:3)

• Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2)

These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the PLL from either a 8 or 16 MHz input.

When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1). When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).

7799D–AVR–11/10

• Bit 3:2 – Res: Reserved Bits

These bits are reserved and always read as zero.

ATmega8U2/16U2/32U2

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started. Note that the Calibrated 8 MHz Internal RC oscillator is automatically enabled when the PLLE bit is set and with PINMUX (see PLLFRQ register) is set. The PLL must be disabled before entering Power down mode in order to stop Internal RC Oscillator and avoid extra-consumption.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. After the PLL is enabled, it takes about several ms for the PLL to lock. To clear PLOCK, clear PLLE.

7799D–AVR–11/10

9. Power Management and Sleep Modes

9.1 Overview

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the po wer consumption to the application’s requirements.

9.2 Sleep Modes

Figure 8-1 on page 26 presents the different clock systems in the ATmega8U2/16U2/32U2, and

their distribution. The figure is helpful in selecting an appropriate sleep mode. shows the different sleep modes and their wake up sources.

Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock

Domains Oscillators Wake-up Sources

ATmega8U2/16U2/32U2

(3)

Sleep Mode

CPU

clk

FLASH

clk

Main Clock

Source

Enabled

INT[7:0] and

PCINT12-0

SPM/

EEPROM Ready

WDT Interrupt

Other I/O

USB Synchronous

Interrupts

USB Asynchonous

Interrupts

Idle X X XXXXXX Power-down X Power-save X Standby Extended

Standby

(1)

(2)

XX XX XX

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. For INT[7:4], only level interrupt.

3. Asynchronous USB interrupt is WAKEUPI only.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, Power-down, Power-save, Standby or Extended standby) will be activated by the SLEEP instruction. See Table 9-2 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a r eset occurs duri ng sle ep mod e, the MCU wakes up and executes from the Reset Vector.

9.3 Idle Mode

7799D–AVR–11/10

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, Timer/Counters,

Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

CPU

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow, USART Transmit Complete or some USB interrupts (like SOFI, WAKEUPI...). If wake-up from the Analog Comparator interrupt is not required, the Ana log Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode.

9.4 Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on INT7:4, an external interrupt on INT3:0, a pin change interrupt or an asynchronous USB interrupt source (WAKEUPI only), can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 84 for details.

and clk

, while allowing the other clocks to run.

FLASH

ATmega8U2/16U2/32U2

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page 29.

9.5 Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down. This mode has been conserved for compatibility purpose with higher-end products.

9.6 Standby Mode

When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

9.7 Extended Standby Mode

When the SM2:0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. So Extended Standby Mode is equivalent to Standy Mode, but is also conserved for compatib ility purpose. From Extended Standby mode, the device wakes up in six clock cycle.

9.8 Power Reduction Register

The Power Reduction Registers (PRR0 and PRR1), provides a method to stop the clock to individual peripherals to reduce power consumption. See “PRR0 – Power Reduction Register 0” and

“PRR1 – Power Reduction Register 1” on page 46 for details. The current state of the peripheral

is frozen and the I/O registers can not be read or written. Resources used by the peripheral

7799D–AVR–11/10

when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption.

9.9 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

9.9.1 Analog Comparator

When entering Idle mode, the Analog Comp arat or sho uld b e disa bled if not us ed. In ot her sle ep modes, the Analog Comparator is automatically disabled. However, if the Ana log C omp arat or is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 223 for details on how to configure the Analog Comparator.

ATmega8U2/16U2/32U2

9.9.2 Brown-out Detector

If the Brown-out Detector is not needed by the a pplication, this modu le should be turned off . If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 50 for details on how to configure the Brown-out Detector.

9.9.3 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, or the Analog Comparator. If these modules are disabled as described in the sections abo ve, the inte rnal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on

page 51 for details on the start-u p time.

9.9.4 Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 64 for details on how to configure the Watchdog Timer.

9.9.5 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where the I/O clock (clk power is consumed by the input logic when not needed. In some cases, the input logic is nee ded for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input

Enable and Sleep Modes” on page 71 for details on which pins are enabled. If the input buffer is

I/O

) is stopped, the input buffers of the device will be disabled. This ensures that no

7799D–AVR–11/10

enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V

/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1). Refer to

“DIDR1 – Digital Input Disable Register 1” on page 225 for details.

9.9.6 On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

9.10 Register Description

9.10.1 SMCR – Sleep Mode Control Register

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210 0x33 (0x53) ––––SM2SM1SM0SESMCR Read/Write RRRRR/WR/WR/WR/W Initial Value00000000

ATmega8U2/16U2/32U2

• Bit 7:4 - Reserved bits

These bits are reserved and will always read as zero.

• Bits 3:1 – SM[2:0]: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Table 9-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle 001Reserved 010Power-down 011Power-save 100Reserved 101Reserved 1 1 0 Standby 1 1 1 Extended Standby

Note: 1. Standby modes are only recommended for use with external crystals or resonators.

(1)

• Bit 0– SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enab le (SE) bit to one just before the exec ution of the SLEEP instruction and to clear it immediately after waking up.

7799D–AVR–11/10

9.10.2 PRR0 – Power Reduction Register 0

Bit 7 6 5 4 3 2 1 0 (0x64) - - PRTIM0 – PRTIM1 PRSPI - - PRR0 Read/Write R/W R/W R/W R R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7:6 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

ATmega8U2/16U2/32U2

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.

• Bit 1 - Res: Reserved bit

These bits are reserved and will always read as zero.

• Bit 0 - Res: Reserved bit

These bits are reserved and will always read as zero.

9.10.3 PRR1 – Power Reduction Register 1

Bit 7 654 3 21 0 (0x65) PRUSB – – – - – – PRUSART1 PRR1 Read/Write R/W R R R R/W R R R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 - PRUSB: Power Reduction USB

Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re initialized to ensure proper operation.

• Bit 6:1 - Res: Reserved bits

These bits are reserved and will always read as zero.

7799D–AVR–11/10

• Bit 0 - PRUSART1: Power Reduction USART1

Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation.

10. System Control and Reset

10.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 10-1 shows the reset logic. “System and Reset Characteristics” on page 267 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 29.

ATmega8U2/16U2/32U2

10.2 Reset Sources

The ATmega8U2/16U2/32U2 has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V

Reset threshold (V

• USB Reset. The MCU is reset when the USB macro is enabled and detects a USB Reset.

Note that with this reset the USB macro remains enabled so that the device stays attached to the bus.

POT

) and the Brown-out Detector is enabled.

BOT

pin for longer

is below the Brown-out

7799D–AVR–11/10

Figure 10-1. Reset Logic

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

USBRF

USB Device

Reset Detection

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

ATmega8U2/16U2/32U2

10.2.1 Power-on Reset

7799D–AVR–11/10

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in “System and Reset Characteristics” on page 267. The POR is activated whenever V

is below the detection level. The POR circuit can be used to trigger the start-up Reset, as

well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V

Figure 10-2. MCU Start-up, RESET

decreases below the detection level.

rise. The RESET signal is activated again, without any delay,

Tied to V

10.2.2 External Reset

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

ATmega8U2/16U2/32U2

Figure 10-3. MCU Start-up, RESET Extended Externally

An External Reset is generated by a low level on the RESET minimum pulse width (see “System and Reset Characteristics ” on page 267) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V delay counter starts the MCU after the Time-out period – t

pin. Reset pulses longer than the

– on its positive edge, the

RST

has expired.

TOUT –

Figure 10-4. External Reset During Operation

7799D–AVR–11/10

10.2.3 Brown-out Detection

RESET

TIME-OUT

INTERNAL

RESET

BOT-

BOT+

TOUT

ATmega8U2/16U2/32U2 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V

level during operation by comparing it to a fixed trigger level. The trigger level for the BOD

can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V V

BOT

value below the trigger level (V vated. When V starts the MCU after the Time-out period t

The BOD circuit will only detect a drop in V ger than t

Figure 10-5. Brown-out Reset During Operation

+ V

ATmega8U2/16U2/32U2

/2 and V

HYST

increases above the trigger level (V

given in “System and Reset Characteristics” on page 267.

BOD

BOT-

= V

BOT

- V

BOT-

/2. When the BOD is enabled, and VCC decreases to a

HYST

in Figure 10-5), the Brown-out Reset is immediately acti-

in Figure 10-5), the delay counter

BOT+

has expired.

TOUT

if the voltage stays below the trigger level for lon-

BOT+

10.2.4 Watchdog Reset

10.2.5 USB Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

“Watchdog Timer” on page 51 for details on operation of the Watchdog Timer.

Figure 10-6. Watchdog Reset During Operation

When the USB macro is enabled and configured with the USB reset MCU feature enabled, and if a valid USB Reset signalling is detected, the microc ontroller is reset unless the USB macro

7799D–AVR–11/10

that remains enabled. This allows the device to stay attached to the bus during and after the

USB Traffic

(USB Lines)

USBRSTMIN

End of Reset

reset, while enhancing firmware reliability.

Figure 10-7. USB Reset During Operation

10.3 Internal Voltage Reference

ATmega8U2/16U2/32U2 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator.

ATmega8U2/16U2/32U2

10.3.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in “System and Reset Characteristics” on page 267. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Co mparator (by setting the

ACBG bit in ACSR).

Thus, when the BOD is not enabled, aft er setting the ACBG bit, the user must always allow the reference to start up before the output from the Analog Comparator is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

10.4 Watchdog Timer

10.4.1 Features

Clocked from separate On-chip Oscillator

•

• 3 Operating modes

–Interrupt – System Reset – Interrupt and System ResetSelectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

• Early warning after one Time-Out period reached, programmable Reset (see operating modes)

after 2 Time-Out periods reached.

10.4.2 Overview

7799D–AVR–11/10

ATmega8U2/16U2/32U2 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives a early warning interrupt

ATmega8U2/16U2/32U2

128kHz

OSCILLATOR

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0 WDP1 WDP2 WDP3

WATCHDOG RESET

WDE

WDIF

WDIE

WDEWIE

MCU RESET

INTERRUPT

EARLY WARNING INTERRUPT

CLOCK DIVIDER

WCLKD0

WCLKD1

OSC/1 OSC/3 OSC/5

OSC/7

when the counter reaches a given time-out value. The WDT gives an interrupt or a system reset when the counter reaches two times the given time-out value . In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

Figure 10-8. Watchdog Timer

In Interrupt mode, the WDT gives an interrupt when the timer expires two times. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. On e example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected.

In System Reset mode, the WDT gives a reset when the timer expires two times. This is typically used to prevent system hang-up in case of runaway code.

The third mode, Interrupt and System Reset mode, com bines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

In addition to these modes, the early warning interrupt can be enabled in order to generate an interrupt when the WDT counter expires the first time.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE or changing time-out configuration is as follows:

1. In the same operation, write a logic one to the Watchdog change enable bits WDCE

and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit and even if it will be cleared after the operation.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also includes a clock divider that directly acts on the clock source. This divider handles odd division factors (3, 5, 7). In combination with the prescaler, a large number of time-out values can be obtained.

The divider factor change is also ruled by the secure timed sequence : first the WDE and WDCE bits must be set, and then four cycles are available to load the new divider value into the WDTCKD register. Be aware that after this operation WDE will still be set. So keep in mind the importance of order of operations. When setting up the WDT in Interrupt mode with specific values of prescaler and divider, the divider register must be loaded before the prescaler register :

1. Set WDCE and WDE

2. Load the divider factor into WDTCKD

3. Wait WDCE being automatically cleared (just wait 2 more cycles)

4. Set again WDCE and WDE

5. Clear WDE, set WDIE and load the prescaler factor into WDTCSR in a same operation

6. Now the system is properly configured for Interrupt only mode. Inverting the two opera-

tions would have been resulted into “Reset and Interrupt mode” and needed a third operation to clear WDE.

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR andi r16, (0xff & (0<<WDRF)) out MCUSR, r16

; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out

in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE) out WDTCSR, r16

; Turn on global interrupt

sei ret

C Code Example

(1)

void WDT_off(void) {

__disable_interrupt(); __watchdog_reset(); /* Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt();

}

Note: 1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is n ot set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Assembly Code Example

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in r16, WDTCSR ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16

; -- Got four cycles to set the new values from here ; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) out WDTCSR, r16

; -- Finished setting new values, used 2 cycles ; Turn on global interrupt

sei ret

C Code Example

void WDT_Prescaler_Change(void) {

__disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt();

}

(1)

Note: 1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

10.5 Register Description

10.5.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210 0x34 (0x54) Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

• Bit 7:6 – Res: Reserved Bit

These bits are reserved and will always read as zero.

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– –USBRF– WDRF BORF EXTRF PORF MCUSR

ATmega8U2/16U2/32U2

• Bit 5 – USBRF: USB Reset Flag

This bit is set if a USB Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 4 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

10.5.2 WDTCSR – Watchdog Timer Control Register

Bit 76543210 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value0000X000

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs twice in the Watchdog Timer and if the Watchdog Timer is configured for interrupt. WDIF is automatically cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. Two consecutives times-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware : the Watchdog goes to System Reset Mode. This is useful for keeping the Watchdog Timer security while using the interrupt. To reinitialize the Interrupt and System Reset Mode, WDIE must be set after each interrupt. This shou ld however not be done within the interrupt service routine itself, as this might compromise the safety-

7799D–AVR–11/10

ATmega8U2/16U2/32U2

function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 10-1. Watchdog Timer Configuration

WDTON (Fuse) WDE WDIE Mode Action on 2x Time-out

1 (unprogrammed) 0 0 Stopped None 1 (unprogrammed) 0 1 Interrupt Mode Interrupt 1 (unprogrammed) 1 0 System Reset Mode Reset

1 (unprogrammed) 1 1

0 (programmed) x x System Reset Mode Reset

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur ing conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in

Table on page 58.

10.5.3 WDTCKD – Watchdog Timer Clock Divider Register

Bit 76543210 (0x62) --WDE-

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

WIFCM

Interrupt and System Reset Mode

WCLKD2 WD EWIF WDEWIE WCLKD1 WCLKD0 WDTCKD

Interrupt, then go to System Reset Mode

7799D–AVR–11/10

• Bit 7:6 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 5 - WDEWIFCL: Watchdog Early Warning Flag Clear Mode

When this bit has been set by software, the WDEWIF interrupt flag is not cleared by hardware when entering the Watchdog Interrupt subroutine (it has to be clear ed by software by writing a logic one to the flag).

When cleared, the WDEWIF is cleared by hardware when executing the corresponding interrupt handling vector.

• Bit 4 - WCLKD2 bit: Watchdog Timer Clock Divider

See “Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider” on page 58.

ATmega8U2/16U2/32U2

• Bit 3 - WDEWIF: Watchdog Early Warning Interrupt Flag

This bit is set when a first time-out occurs in the Watchdog Timer and if the WDEWIE bit is enabled. WDEWIF is automatically cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF can be cleared by writing a logic one to the flag. When the I-bit in SREG and WDEWIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 2 - WDEWIE: Watchdog Early Warning Interrupt Enable

When this bit has been set by software, an interrupt will be generated on the watchdog interrupt vector when the Early warning flag is set to one by hardware.

• Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider

Table 10-2. Watchdog Timer Clock Divider Configuration

WCLKD2 WCLKD1 WCLKD0 Mode

000 001Clk 010Clk 011Clk 100Clk 101Clk 110Clk 111Clk

Clk

WDT WDT WDT WDT WDT WDT WDT WDT

= Clk = Clk = Clk = Clk = Clk = Clk = Clk = Clk

128k 128k 128k 128k 128k 128k 128k 128k

/ 3 / 5 / 7 / 9 / 11 / 13 / 15

Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1)

Watchdog Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 16 ms 32 ms 0001 4K (4096) cycles 32 ms 64 ms 0010 8K (8192) cycles 64 ms 128 ms 0011 16K (16384) cycles 0.125 s 0.250 s 0100 32K (32768) cycles 0.25 s 0.5 s 0101 64K (65536) cycles 0.5 s 1.0 s 0110 128K (131072) cycles 1.0 s 2.0 s 0111 256K (262144) cycles 2.0 s 4.0 s 1000 512K (524288) cycles 4.0 s 8.0 s 10011024K (1048576) cycles 8.0 s 16.0 s

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

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ATmega8U2/16U2/32U2

Table 10-3. Watchdog Timer Prescale Select, DIV = 0 (CLKwdt = CLK128 / 1) (Continued)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

1010 1011 1100 1101 1110 1111

(Early warning)

Table 10-4. Watchdog Timer Prescale Select, DIV = 1 (CLKwdt = CLK128 / 3)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reserved

Early warning Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

0000 2K (2048) cycles 48 ms 96 ms 0001 4K (4096) cycles 96 ms 192 ms 0010 8K (8192) cycles 192 ms 384 ms 0011 16K (16384) cycles 0.375 s 0.75 s 0100 32K (32768) cycles 0.75 s 1.5 s 0101 64K (65536) cycles 1.5 s 3 s 0110 128K (131072) cycles 3 s 6 s 0111 256K (262144) cycles 6 s 12 s 1000 512K (524288) cycles 12 s 24 s 10011024K (1048576) cycles 24 s 48 s 1010 1011 1100 1101 1110 1111

Reserved

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ATmega8U2/16U2/32U2

Table 10-5. Watchdog Timer Prescale Select, DIV = 2 (CLKwdt = CLK128 / 5)

Watchdog Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 80 ms 160 ms 0001 4K (4096) cycles 160 ms 320 ms 0010 8K (8192) cycles 320 ms 640 ms 0011 16K (16384) cycles 0.625 s 1.25 s 0100 32K (32768) cycles 1.25 s 2.5 s 0101 64K (65536) cycles 2.5 s 5 s 0110 128K (131072) cycles 5 s 10 s 0111 256K (262144) cycles 10 s 20 s 1000 512K (524288) cycles 20 s 40 s 10011024K (1048576) cycles 40 s 80 s 1010

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

1011 1100 1101 1110 1111

Reserved

Table 10-6. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7)

Watchdog Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 112 ms 224 ms 0001 4K (4096) cycles 224 ms 448 ms 0010 8K (8192) cycles 448 ms 896 ms 0011 16K (16384) cycles 0.875 s 1.75 s 0100 32K (32768) cycles 1.75 s 3.5 s 0101 64K (65536) cycles 3.5 s 7 s 0110 128K (131072) cycles 7 s 14 s 0111 256K (262144) cycles 14 s 28 s

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

1000 512K (524288) cycles 28 s 56 s 10011024K (1048576) cycles 56 s 112 s

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ATmega8U2/16U2/32U2

Table 10-6. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7) (Continued)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

1010 1011 1100 1101 1110 1111

(Early warning)

Table 10-7. Watchdog Timer Prescale Select, DIV = 4 (CLKwdt = CLK128 / 9)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reserved

Early warning Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

0000 2K (2048) cycles 72ms 144 ms 0001 4K (4096) cycles 144 ms 288 ms 0010 8K (8192) cycles 288 ms 576 ms 0011 16K (16384) cycles 576 s 1.15 s 0100 32K (32768) cycles 1.1 s 2.3 s 0101 64K (65536) cycles 2.3 s 4.6 s 0110 128K (131072) cycles 4.6 s 9.2 s 0111 256K (262144) cycles 9.2 s 18.4s 1000 512K (524288) cycles 18.4 s 36.8 s 10011024K (1048576) cycles 36.8 s 73 s 1010 1011 1100 1101 1110 1111

Reserved

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Table 10-8. Watchdog Timer Prescale Select, DIV = 5 (CLKwdt = CLK128 / 11)

Watchdog Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 88 ms 176 ms 0001 4K (4096) cycles 176 ms 352 ms 0010 8K (8192) cycles 352 ms 704 ms 0011 16K (16384) cycles 704 ms 1.4 s 0100 32K (32768) cycles 1.4 s 2.8 s 0101 64K (65536) cycles 2.8 s 5.6 s 0110 128K (131072) cycles 5.6 s 11.2 s 0111 256K (262144) cycles 11.2 s 22.5 s 1000 512K (524288) cycles 22.5 s 45 s 10011024K (1048576) cycles 45s 90 s 1010

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

1011 1100 1101 1110 1111

Reserved

Table 10-9. Watchdog Timer Prescale Select, DIV = 6(CLKwdt = CLK128 / 13)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 104 ms 208 ms 0001 4K (4096) cycles 208 ms 416 ms 0010 8K (8192) cycles 416 ms 832 ms 0011 16K (16384) cycles 832 ms 1.64 s 0100 32K (32768) cycles 1.6 s 3.3 s 0101 64K (65536) cycles 3.3 s 6.6 s 0110 128K (131072) cycles 6.6 s 13.3 s 0111 256K (262144) cycles 13.3 s 26.6 s

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reset/Interrupt Typical

Watchdog

Time-out at

VCC = 5.0V

1000 512K (524288) cycles 26.6 s 53.2 s 10011024K (1048576) cycles 53.2 s 106.4 s

7799D–AVR–11/10

ATmega8U2/16U2/32U2

Table 10-9. Watchdog Timer Prescale Select, DIV = 6(CLKwdt = CLK128 / 13) (Continued)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

1010 1011 1100 1101 1110 1111

(Early warning)

Table 10-10. Watchdog Timer Prescale Select, DIV = 7 (CLKwdt = CLK128 / 15)

Number of WDT Oscillator Cycles before 1st time-out

WDP3 WDP2 WDP1 WDP0

(Early warning)

Early warning Typical

Time-out at

VCC = 5.0V

Reserved

Early warning Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

Watchdog

Reset/Interrupt Typical

Time-out at

VCC = 5.0V

0000 2K (2048) cycles 120 ms 240 ms 0001 4K (4096) cycles 240 ms 480 ms 0010 8K (8192) cycles 480 ms 960 ms 0011 16K (16384) cycles 0.960 s 1.9 s 0100 32K (32768) cycles 1.92 s 3.8 s 0101 64K (65536) cycles 3.8 s 7.6 s 0110 128K (131072) cycles 7.6 s 15.3 s 0111 256K (262144) cycles 15.3 s 30.7 s 1000 512K (524288) cycles 30.7 s 61.4 s 10011024K (1048576) cycles 61.4 s 122 s 1010 1011 1100 1101 1110 1111

Reserved

7799D–AVR–11/10

11. Interrupts

11.1 Overview

This section describes the specifics of the interrupt handling as performed in ATmega8U2/16U2/32U2. For a general explanation of the AVR interrupt handling, refer to

“Reset and Interrupt Handling” on page 13.

1 1.2 Interrupt Vectors in ATmega8U2/16U2/32U2

Table 11-1. Reset and Interrupt Vectors

ATmega8U2/16U2/32U2

Vector

No.

1 $0000

2 $0002 INT0 External Interrupt Request 0 3 $0004 INT1 External Interrupt Request 1 4 $0006 INT2 External Interrupt Request 2 5 $0008 INT3 External Interrupt Request 3 6 $000A INT4 External Interrupt Request 4 7 $000C INT5 External Interrupt Request 5 8 $000E INT6 External Interrupt Request 6

9 $0010 INT7 External Interrupt Request 7 10 $0012 PCINT0 Pin Change Interrupt Request 0 1 1 $0014 PCINT1 Pin Change Interrupt Request 1 12 $0016 USB General USB General Interrupt request 13 $0018 USB Endpoint USB Endpoint Interrupt request 14 $001A WDT Watchdog Time-out Interrupt 15 $001C TIMER1 CAPT Timer/Counter1 Capture Event

Program

Address

(2)

Source Interrupt Definition

(1)

RESET

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, USB Reset and debugWIRE AVR Reset

7799D–AVR–11/10

16 $001E TIMER1 COMPA Timer/Counter1 Compare Match A 17 $0020 TIMER1 COMPB Timer/Counter1 Compare Match B 18 $0022 TIMER1 COMPC Timer/Counter1 Compare Match C 19 $0024 TIMER1 OVF Timer/Counter1 Overflow 20 $0026 TIMER0 COMPA Timer/Counter0 Compare Match A 21 $0028 TIMER0 COMPB Timer/Counter0 Compare match B 22 $002A TIMER0 OVF Timer/Counter0 Overflow 23 $002C SPI, STC SPI Serial Transfer Complete 24 $002E USART1 RX USART1 Rx Complete 25 $0030 USART1 UDRE USART1 Data Register Empty 26 $0032 USART1TX USART1 Tx Complete

ATmega8U2/16U2/32U2

Table 11-1. Reset and Interrupt Vectors (Continued)

Vector

No.

27 $0034 ANALOG COMP Analog Comparator 28 $0036 EE READY EEPROM Ready 29 $0038 SPM READY Store Program Memory Ready

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

Program

Address

reset, see “Memory Programming” on page 246.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. Moreover, contrary to other 8K/16K devices, the interrupt vectors spacing remains identical (2 words) for both 8KB and 16KB versions.

(2)

Source Interrupt Definition

Table 11-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these lo cations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 11-2. Reset and Interrupt Vectors Placement

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002

(1)

0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 23-8 on page 239. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

11.2.1 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

1 1.3 Register Description

11.3.1 MCUCR – MCU Control Register

Bit 76543210 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value00000000

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on p age 246 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedur e must be followed to change the IVSEL bit:

JTD – – PUD – – IVSEL IVCE MCUCR

7799D–AVR–11/10

ATmega8U2/16U2/32U2

a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section

Programming” on page 246

for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below .

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE) out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL) out MCUCR, r16 ret

“Memory

C Code Example

void Move_interrupts(void) {

/* Enable change of Interrupt Vectors */ MCUCR = (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = (1<<IVSEL);

}

7799D–AVR–11/10

12. I/O-Ports

Logic

See Figure

"General Digital I/O" for

Details

Pxn

12.1 Overview

ATmega8U2/16U2/32U2

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if con figured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

acteristics” on page 264 for a complete list of parameters.

Figure 12-1. I/O Pin Equivalent Schematic

and Ground as indicated in Figure 12-1. Refer to “Electrical Char-

7799D–AVR–11/10

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented ge nerally a s PORTxn . The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 82.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Da ta Dir ec tion Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

68. Most port pins are multiplexed with alternate func tions for the peripheral feat ures on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 72. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

12.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a func- tional description of one I/O-port pin, here generically called Pxn.

ATmega8U2/16U2/32U2

Figure 12-2. General Digital I/O

Pxn

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk

: I/O CLOCK

I/O

(1)

SLEEP

SYNCHRONIZER

DLQ

PINxn

PUD

DDxn

CLR

RESET

PORTxn

CLR

RESET

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

RRx

WDx

RDx

RPx

clk

I/O

WRx

DATA BUS

WPx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

12.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 82, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The por t pins are tri-stated when reset condition becomes active, even if no clocks are running.

7799D–AVR–11/10

SLEEP, and PUD are common to all ports.

I/O

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

12.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

12.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to dis able all pullups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 12-1 summarizes the control signals for the pin value.

Table 12-1. Port Pin Configurations

ATmega8U2/16U2/32U2

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source)

12.2.4 Reading the Pin Value

Independent of the setting of Data Direction b it DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 12-2, the PINxn Register bit a nd th e precedin g latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 12- 3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are deno te d t

PUD

(in MCUCR) I/O Pull-up Comment

pd,max

and t

respectively.

pd,min

7799D–AVR–11/10

ATmega8U2/16U2/32U2

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

Figure 12-3. Synchronization when Reading an Externally Applied Pin value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

7799D–AVR–11/10

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 12-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 12-4. Synchronization when Reading a Software Assigned Pin Value

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

ATmega8U2/16U2/32U2

Assembly Code Example

...

; Define pull-ups and set outputs high ; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB ...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation(); /* Read port pins */ i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

12.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 12-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standb y mode to avoid high power consu mption if some input signals are left floating, or have an analog signal level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 72.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

/2.

7799D–AVR–11/10

12.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins h ave a de fined level. Even though most of the digital inputs are disabled in the deep sleep modes as descri bed above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an extern al pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output.

12.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 12-5 shows how the port pin control signals from th e simplified Figure 12-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

ATmega8U2/16U2/32U2

or GND is not recommended, since this may cause exce ssive curr ents if the pin is

Figure 12-5. Alternate Port Functions

Pxn

(1)

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

SYNCHRONIZER

SET

DLQ

CLR

PINxn

CLR

PORTxn

CLR

RESET

DDxn

PUD

CLR

WDx

RDx

RRx

RPx

clk

I/O

WRx

PTOExn

WPx

DATA BUS

7799D–AVR–11/10

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

DIxn

AIOxn

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

ATmega8U2/16U2/32U2

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

I/O

Table 12-2 summarizes the function of the overriding signals. The pin and por t indexes from Fig- ure 12-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 12-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

Pull-up Override Enable

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

Port Value Override Value

Port Toggle Override Enable

Digital Input

DIEOE

DIEOV

DI Digital Input

AIO

Enable Override Enable

Digital Input Enable Override Value

Analog Input/Output

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

7799D–AVR–11/10

12.3.1 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 12-3.

Table 12-3. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

PB6 PCINT6 (Pin Change Interrupt 6) PB5 PCINT5 (Pin Change Interrupt 5) PB4 T1/PCINT4 (Timer/Counter1 Clock Input or Pin Change Interrupt 4)

PB3

OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)

PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave Output or Pin Change Interrupt 3)

ATmega8U2/16U2/32U2

PB2

PB1 SCLK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1) PB0 SS

PDI/MOSI/PCINT2 (Programming Data Input or SPI Bus Master Output/Slave Input or Pin Change Interrupt 2)

/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

The alternate pin configuration is as follows:

• OC0A/OC1C/PCINT7, Bit 7

OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configur ed as a n o utput ( DDB7 set “ one ”) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.

• PCINT6, Bit 6

PCINT6, Pin Change Interrupt source 6: The PB6 pin can serve as an external interrupt source.

• PCINT5, Bit 5

PCINT5, Pin Change Interrupt source 5: The PB5 pin can serve as an external interrupt source.

7799D–AVR–11/10

• T1/PCINT4, Bit 4

T1, Timer/Counter1 counter source. PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source.

• PDO/MISO/PCINT3 – Port B, Bit 3

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90USB82/162.

MISO: Master Data input, Slave Data outp ut pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlle d by DDB3. When the pin is forc ed to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT3, Pin Change Interrupt source 3: The PB3 pin can serve as an external interrupt source.

ATmega8U2/16U2/32U2

• PDI/MOSI/PCINT2 – Port B, Bit 2

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is use d as data input line for the AT90USB82/162.

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT2, Pin Change Interrupt source 2: The PB2 pin can serve as an external interrupt source.

• SCK/PCINT1 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. This pin also serves as Clock for the Serial Programming interface.

PCINT1, Pin Change Interrupt source 1: The PB1 pin can serve as an external interrupt source.

•SS

/PCINT0 – Port B, Bit 0

: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source.

Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

PCINT0, Pin Change Interrupt source 0: The PB0 pin can serve as an external interrupt source

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ATmega8U2/16U2/32U2

.Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals shown in Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT..

Table 12-4. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name

PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC0A/OC1C ENABLE 0 0 0 PVOV OC0A/OC1C 0 0 0 DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0 DIEOV 1 1 1 1

DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT

AIO – – – –

PB7/OC0A/OC1C/ PCINT7 PB6/PCINT6 PB5/PCINT5 PB4/T1/PCINT4

PCINT4 INPUT T1 INPUT

Table 12-5. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name

PUOE SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PB3/MISO/PCINT3/ PDO

PB2/MOSI/PCINT2/ PDI

PB1/SCK/ PCINT1 PB0/SS/PCINT0

SPE • MSTR SPE • MSTR

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DDOV 0 0 0 0 PVOE SPE • MSTR PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0 DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0 DIEOV 1 1 1 1

AIO – – – –

SPI MSTR INPUT PCINT3 INPUT

SPE • MSTR SPE • MSTR 0

SPI SLAVE INPUT PCINT2 INPUT

SCK INPUT PCINT1 INPUT

SPI SS PCINT0 INPUT

12.3.2 Alternate Functions of Port C

The Port C alternate function is as follows:

Table 12-6. Port C Pins Alternate Functions

Port Pin Alternate Function

The alternate pin configuration is as follows:

• ICP1/INT4/CLK0, Bit 7

ICP1, Input Capture pin 1 :The PC7 pin can act as an input capture for Timer/Counter1.

PC7 ICP1/INT4/CLKO PC6 PCINT8/OC1A PC5 PCINT9/OC1B PC4 PCINT10

-PC2 PCINT11 PC1 Reset PC0 XTAL2

, dW

ATmega8U2/16U2/32U2

INT4, External Interrupt source 4 : The PC7 pin can serve as an external interrupt source to the MCU.

CLK0, Clock Output : The PC7 pin can serve as oscillator clock ouput if the feature is enabled by fuse.

• PCINT8/OC1A, Bit 6

PCINT8, Pin Change Interrupt source 8 : The PC6 pin can serve as an external inte rrupt sour ce. OC1A, Output Compare Match A output: The PC6 pin can serve as an external output for the

Timer/Counter1 Output Compare. The pin has to be configur ed as an ou tput (DDC6 set “one ”) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

• PCINT9/OC1B, Bit 5

PCINT9, Pin Change Interrupt source 9: The PC5 pin can serve as an external interrupt source. OC1B, Output Compare Match B output: The PC5 pin can serve as an external output for the

Timer/Counter1 Output Compare. The pin has to be configur ed as an ou tput (DDC5 set “one ”) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

• PCINT10, Bit 4

PCINT10, Pin Change Interrupt source 10 : The PC4 pin can serve as an external interrupt source.

• PCINT11, Bit 2

PCINT11, Pin Change Interrupt source 11 : The PC2 pin can serve as an external interrupt source.

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• Reset

/dW, Bit 1

ATmega8U2/16U2/32U2

Reset, Reset input. External Reset input is active low and enabled by unprogramming ("1") the RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated whe n the pin is used as the RESET pin.

dW, debugWire channel. When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed, the debugWIRE system within the target device is activated. The RESET port pin is configured as a wired -AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between the target and the emulator.

•XTAL2

, Bit 0

XTAL2, Oscillator. The PC0 pin can serve as Inverting Output for internal Oscillator amplifier.

Table 12-7 and Table 12-8 relate the alternate functions of Port C to the overriding signals

shown in Figure 12-5 on page 72.

Table 12-7. Overriding Signals for Alternate Functions in PC7..PC4

Signal Name PC7/ICP1/INT4/CLK0

PUOE0 000 PUOV0 000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 OC1A ENABLE OC1B ENABLE 0 PVOV 0 OC1A OC1B 0 DIEOE INT4 ENABLE PCINT8 ENABLE PCINT9 ENABLE PCINT10 ENABLE DIEOV1 111 DI INT4 INPUT PCINT8 INPUT PCINT9 INPUT PCINT10 INPUT

PC6/PCINT8/ OC1A

PC5/PCINT9/ OC1B PC4/PCINT10

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AIO– –––

Table 12-8. Overriding Signals for Alternate Functions in PC2..PC0

Signal Name PC2/PCINT11 PC1/RESET/dW PC0/XTAL2

PUOE 0 0 0 PUOV 0 0 0 DDOE 0 0 0 DDOV 0 0 0 PVOE 0 0 0 PVOV 0 0 0 DIEOE PCINT11 ENABLE 0 0 DIEOV 1 0 0 DI PCINT11 INPUT – – AIO – – –

12.3.3 Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 12-9.

Table 12-9. Port D Pins Alternate Functions

Port Pin Alternate Function

PD7 HWB PD6 INT6/RTS PD5 XCK1/PCINT12 (USART1 External Clock Input/Output) PD4 INT5 PD3 INT3/TXD1 (External Interrupt3 Input or USART1 Transmit Pin) PD2 INT2 PD1 INT1

ATmega8U2/16U2/32U2

/TO/INT7/CTS

/AIN1/RXD1(External Interrupt2 Input or USART1 Receive Pin) /AIN0 (External Interrupt1 Input)

PD0 INT0

/OC0B (External Interrupt0 Input)

The alternate pin configuration is as follows:

•

HWB/TO/INT7/CTS, Bit 7

HWB

, Hardware Boot : The PD7 pin can serve as TO, Timer/Counter0 counter source. INT7, External Interrupt source 7: The PD7 pin can serve as an external interrupt source to the

MCU. CTS

, USART1 Transmitter Flow Control. This pin ca n control the transmitter in function of its

state.

•

INT6/RTS,Bit 6

INT6, External Interrupt source 6: The PD6 pin can serve as an external interrupt source to the MCU.

RTS

, USART1 Receiver Flow Control. This pin can control the receiver in function of its state.

•

XCK1/PCINT12, Bit 5

XCK1, USART1 External Clock : The data direction register DDRD5 controls whether the clock is output (DDRD5 set) or input (DDRD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous Mode.

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PCINT12, Pin Change Interrupt source 12: The PD5 pin can serve as an external interrupt source.

•

INT5, Bit 4

INT5, External Interrupt source 5: The PD4 pin can serve as an external interrupt source to the MCU.

•

INT3/TXD1, Bit 3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU.

ATmega8U2/16U2/32U2

TXD1, USART1 Transmit Data : When the USART1 Transmitter is enabled, this pin is configured as an ouput regardless of DDRD3.

•

INT2/AIN1/RXD1, Bit 2

INT2, External Interrupt source 2: The PD2 pin can serve as an external interrupt source to the MCU.

AIN1, Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator.

RXD1, USART1 Receive Data : When the USART1 Receiver is enabled, this pin is configured as an input regardless of DDRD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

•

INT1/AIN0, Bit 1

INT1, External Interrupt source 1: The PD1 pin can serve as an external interrupt source to the MCU.

AIN0, Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator.

•

INT0/OC0B, Bit 0

INT0, External Interrupt source 0: The PD0 pin can serve as an external interrupt source to the MCU.

OC0B, Output Compare Match B output: The PD0 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configur ed as an ou tput (DDD0 set “one ”) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.

Table 12-10 and Table 12-11 relates the alternate functions of Port D to the overriding sign als

shown in Figure 12-5 on page 72.

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ATmega8U2/16U2/32U2

Table 12-10. Overriding Signals for Alternate Functions PD7..PD4

PD7/T0/INT7/

Signal Name

PUOE CTS RTS 0 0

PUOV

DDOE CTS RTS 0 0 DDOV 0 1 0 0

PVOE 0

PVOV 0

DIEOE

DIEOV 1 1 1 1

AIO – – – –

HBW/CTS

PORTD7 • PUD

INT7/CTS ENABLE

T0 INPUT INT7 INPUT

INPUT

CTS

Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0

PD6/INT6/ RTS PD5/XCK/PCINT12 PD4/INT5

00 0

RTS OUTPUT ENABLE

RTS OUTPUT

INT6 ENABLE

INT6 INPUT

XCK OUTPUT ENABLE 0

XCK1 OUTPUT 0

PCINT12 ENABLE

XCK INPUT PCINT12 INPUT

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INT5 ENABLE

INT5 INPUT

PD2/INT2/RXD1/

Signal Name PD3/INT3/TXD1

PUOE TXEN1 RXEN1 0 0 PUOV 0 PORTD2 • PUD 00 DDOE TXEN1 RXEN1 0 0 DDOV 1 0 0 0 PVOE TXEN1 0 0 OC0B ENABLE PVOV TXD1 0 0 OC0B

DIEOE INT3 ENABLE

DIEOV 1 AIN1 ENABLE AIN0 ENABLE 1 DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT AIO – AIN1 INPUT AIN0 INPUT –

Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0

and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure.

AIN1 PD1/INT1/AIN0 PD0/INT0/OC0B

INT2 ENABLE AIN1 ENABLE

INT1 ENABLE AIN0 ENABLE

INT0 ENABLE

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12.4 Register Description for I/O-Ports

12.4.1 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 68 for more details about this feature.

12.4.2 PORTB – Port B Data Register

Bit 76543210 0x05 (0x25) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

12.4.3 DDRB – Port B Data Direction Register

Bit 76543210 0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

JTD – –PUD– – IVSEL IVCE MCUCR

ATmega8U2/16U2/32U2

12.4.4 PINB – Port B Input Pins Address

Bit 76543210 0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

12.4.5 PORTC – Port C Data Register

Bit 76543210 0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4 - PORTC2 PORTC1 PORTC0 PORTC Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value00000000

12.4.6 DDRC – Port C Data Direction Register

Bit 76543210 0x07 (0x27) DDC7 DDC6 DDC5 DDC4 - DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value00000000

12.4.7 PINC – Port C Input Pins Address

Bit 76543210 0x06 (0x26) PINC7 PINC6 PINC5 PINC4 - PINC2 PINC1 PINC0 PINC Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

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12.4.8 PORTD – Port D Data Register

Bit 76543210 0x0B (0x2B) PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

12.4.9 DDRD – Port D Data Direction Register

Bit 76543210 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

12.4.10 PIND – Port D Input Pins Address

Bit 76543210 0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega8U2/16U2/32U2

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13. External Interrupts

13.1 Overview

The External Interrupts are triggered by the INT[7:0] pin or any of the PCINT[12:0] pins. Observe that, if enabled, the interrupts will trigger even if the INT[7:0] or PCINT[12:0] pins are configured as outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI0 will trigger if any enabled PCINT[7:0] pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. The Pin change interrupt PCI1 will trigger if any enabled PCINT[12:8] pin toggles. PCMSK1 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT[12:0] are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT[3:0]) and EICRB (INT[7:4]). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT[7:4] requires the presence of an I/O clock, described in “System

Clock and Clock Options” on page 26. Low level interrupts and the edge interr upt on INT[3:0] are

detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

ATmega8U2/16U2/32U2

Note that if a level triggered interrupt is used for wake-up from Power -down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 26.

13.2 Register Description

13.2.1 EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210 (0x69) ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3:0 Sense Control Bits

The External Interrupts 3:0 are activated by the external pins INT[3:0] if the SREG I-flag and the corresponding interrupt mask in the EI MS K is set. Th e leve l and edg es on the e xtern al pins that activate the interrupts are defined in Table 13-1. Edges on INT[3:0] are registered asynchronously. Pulses on INT[3:0] pins wider than the minimum pulse width given in “External Interrupts

Characteristics” on page 268 will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enab led, a level trigger ed interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Fina lly, th e INTn

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ATmega8U2/16U2/32U2

interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.

Table 13-1. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn ge nerates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchron ously an interrupt request.

Note: 1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

13.2.2 EICRB – External Interrupt Control Register B

Bit 76543210 (0x6A) ISC71ISC70ISC61ISC60ISC51ISC50ISC41ISC40EICRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7:4 Sense Control Bits

The External Interrupts [7:4] are activated by the external pins INT[7:4] if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 13-2. The value on the INT[7:4] pins are sam pled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

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7799D–AVR–11/10

Table 13-2. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge between two samples of INTn generates an interrupt request. 1 1 The rising edge between two samples of INTn generates an interrupt request.

Note: 1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

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13.2.3 EIMSK – External Interrupt Mask Register

Bit 76543210 0x1D (0x3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – INT[7:0]: External Interrupt Request 7:0 Enable

When an INT[7:0] bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EIC RB – defines whethe r the external interr upt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

13.2.4 EIFR – External Interrupt Flag Register

Bit 76543210 0x1C (0x3C) INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 EIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

ATmega8U2/16U2/32U2

• Bits 7:0 – INTF[7:0]: External Interrupt Flags 7:0

When an edge or logic change on the INT[7:0] pin triggers an interrupt request, INTF[7:0] becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT[7:0] in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical o ne to it. These flags are always cleared when INT[7:0] are configured as level interrupt. Note that when entering sleep mode with the INT[3:0] interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF[3:0] flags. See “Digital Input Enable and Sleep Modes” on page 71 for more information.

13.2.5 PCICR – Pin Change Interrupt Control Register

Bit 76543210 (0x68) Read/Write RRRRRRR/WR/W Initial Value00000000

- - – – – – PCIE1 PCIE0 PCICR

• Bit 1:0 – PCIE[1:0]: Pin Change Interrupt Enable 1:0

When the PCIE1/0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), Pin Change interrupt 1/0 is enabled. Any change on any enabled PCINT[12:8]/[7:0] pin will cause an interrupt. The corresponding inte rrupt of Pin Change Interrup t Request is executed from the PCI1/0 Interrupt Vector. PCINT[12:8]/[7:0] pins are enabled individually by the PCMSK1/0 Register.

13.2.6 PCIFR – Pin Change Interrupt Flag Register

Bit 76543210 0x1B (0x3B) Read/Write RRRRRRR/WR/W Initial Value00000000

7799D–AVR–11/10

- - – – – – PCIF1 PCIF0 PCIFR

• Bit 1:0 – PCIF[1:0]: Pin Change Interrupt Flag 1:0

When a logic change on any PCINT[12:8]/[7:0] pin triggers an interrupt request, PCIF1/0 becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

13.2.7 PCMSK0 – Pin Change Mask Register 0

Bit 76543210 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0

Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O pin is disabled.

13.2.8 PCMSK1 – Pin Change Mask Register 1

Bit 76543210 (0x6C) Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

- - - PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

ATmega8U2/16U2/32U2

• Bit 4:0 – PCINT[12:8]: Pin Change Enable Mask 12: 8

Each PCINT[12:8] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[12:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[12:8] is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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14. Timer/Counter0 and Timer/Counter1 Prescalers

Tn_sync

(To Clock Select Logic)

Edge DetectorSynchronization

DQDQ

clk

I/O

14.1 Overview

Timer/Counter0 and 1 share the same prescaler module , but the Timer/Counters ca n have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0 or 1.

14.2 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f as a clock source. The prescaled clock has a frequency of either f f

14.3 Prescaler Reset

The prescaler is free running, i.e., operates independently o f the Clock Select logic of the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn[2:0] > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

CLK_I/O

/256, or f

CLK_I/O

/1024.

). Alternatively, one of four taps from the prescaler can be used

CLK_I/O

ATmega8U2/16U2/32U2

CLK_I/O

/8, f

CLK_I/O

/64,

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.

14.4 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detecto r. Figure 14- 1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock ( high period of the internal system clock.

The edge detector generates one clk = 6) edge it detects.

Figure 14-1. Tn/T0 Pin Sampling

clk

). The latch is transparent in the

I/O

pulse for each positive (CSn2:0 = 7) or ne gative (CSn2 :0

7799D–AVR–11/10

ATmega8U2/16U2/32U2

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (f sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f

An external clock source can not be prescaled.

Figure 14-2. Prescaler for synchronous Timer/Counters

ExtClk

< f

/2) given a 50/50% duty cycle. Since the edge detec tor uses

clk_I/O

/2.5.

14.5 Register Description

14.5.1 GTCCR – General Timer/Counter Control Register

Bit 7 6 5 4 3 2 1 0 0x23 (0x43) TSM Read/Write R/W R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0

7799D–AVR–11/10

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared by hardware, and the Timer/Counters start counting simultaneously.

– – – – – - PSRSYNC GTCCR

ATmega8U2/16U2/32U2

• Bits 6:1 – Res: Reserved

These bits are reserved and will always read as zero.

• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Co un ter4 and Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter0 and Timer/Counter1 share the same prescaler and a reset of this prescaler will affect all timers.

7799D–AVR–11/10

15. 8-bit Timer/Counter0 with PWM

15.1 Features

• T wo In depen dent Outpu t Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

15.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (e vent management) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 15-1. For the actual placement of I/O pins, refer to “Pinout” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “Register Description” on page 102.

ATmega8U2/16U2/32U2

15.2.1 Registers

Figure 15-1. 8-bit Timer/Counter Block Diagram

Count

Clear

Control Logic

Direction

TOP BOTTO M

Timer/Counter

TCNTn

OCRnA

DATA BUS

OCRnB

TCCRnA TCCRnB

clk

Fixed

TOP

Val ue

TOVn

(Int.Req.)

Clock Select

Edge

Detector

( From Prescaler )

OCnA

(Int.Req.)

Wavefor m

Generation

OCnB

(Int.Req.)

Wavefor m

Generation

OCnA

OCnB

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A an d OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Inte rrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

7799D–AVR–11/10

The Timer/Counter can be clocked internally, via the pre scaler, or by an exter nal clock so urce on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

15.2.2 Definitions

DATA B U S

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clk

bottom

direction

clear

ATmega8U2/16U2/32U2

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See “Output Compare Unit” on page 93. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compa re interrupt request.

Many register and bit references in this section are written in genera l form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 15-1 are also used extensively throughout the document. Table 15-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00.

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Re gister. The assignment is dependent on the mode of operation.

15.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For de tails on clock sour ces and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 88.

15.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

15-2 shows a block diagram of the counter and its surroundings.

Figure 15-2. Counter Unit Block Diagram

7799D–AVR–11/10

Signal description (internal signals):

ATmega8U2/16U2/32U2

count Increment or dec re m en t TC NT 0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2:0] = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 96.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM0[2:0] bits. TOV0 can be used for generating a CPU interrupt.

15.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is aut omatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM0[2:0] bits and Compare O utput mode (COM0x[1:0]) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Operation” on page 96).

is present or not. A CPU write overrides (has priority over) all counter clear or

Timer/Counter clock, referred to as clkT0 in the following.

). clkT0 can be generated from an external or internal clock source,

7799D–AVR–11/10

Figure 15-3 shows a block diagram of the Output Compare unit.

ATmega8U2/16U2/32U2

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA B U S

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnX1:0

bottom

Figure 15-3. Output Compare Unit, Block Diagram

The OCR0x Registers are double buffered when using any o f the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare ( CTC) modes of op eration, the double buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.

15.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

15.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an inte rrupt when the Timer/Counter clo ck is enabled.

15.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

7799D–AVR–11/10

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

PORT

DDR

OCnx

Waveform Generator

COMnx1

COMnx0

DATA BU S

FOCn

clk

I/O

down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when changing between Waveform Generation modes.

Be aware that the COM0x[1:0] bits are not double buffered together with the compare value. Changing the COM0x[1:0] bits will take effect immediately.

15.6 Compare Match Output Unit

The Compare Output mode (COM0x[1:0]) bits have two functions. The Waveform Generator uses the COM0x[1:0] bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x[1:0] bits control the OC0x pin output source. Figure 15-4 shows a sim- plified schematic of the logic affecte d by the COM0x[1:0] bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Po rt Control Registers (DDR and PORT) that are affected by the COM0x[1:0] bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

ATmega8U2/16U2/32U2

Figure 15-4. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independent of the Waveform Generation mode .

The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 102.

7799D–AVR–11/10

15.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x[1:0] bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x[1:0] = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 15-2 on page 102. For fast PWM mode, refer to

Table 15-3 on page 102, and for phase correct PWM refer to Table 15-4 on page 103.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

15.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM0[2:0]) and Compare Output mode (COM0x[1:0]) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0x[1:0] bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For nonPWM modes the COM0x[1:0] bits control whether the output should be set, cleared, or toggled at a Compare Match (See “Compare Match Output Unit” on page 95.).

For detailed timing information see “Timer/Counter Timing Diagrams” on page 100.

ATmega8U2/16U2/32U2

15.7.1 Normal Mode

The simplest mode of operation is the Normal mode (WGM0 [2:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

15.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mo de (WGM0[2:0] = 2), th e OCR0A Register is used t o manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting exte rn al ev en ts.

The timing diagram for the CTC mode is shown in Figure 15-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

7799D–AVR–11/10

ATmega8U2/16U2/32U2

TCNTn

OCn (Toggle)

OCnx Interrupt Flag Set

1 4

Period

2 3

(COMnx1:0 = 1)

OCnx

clk_I/O

2 N 1 OCRnx+()⋅⋅

------------------------------------------------- -=

Figure 15-5. CTC Mode, Timing Diagram

An interrupt can be generated ea ch time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap arou nd starting at 0x00 before the Co mpare Match can occur.

15.7.3 Fast PWM Mode

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A[1:0] = 1). The OC0A value will not be visible on the port pin unless the data dir ection for the pin is set to output. The waveform generated will have a maximum frequency of f f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

clk_I/O

OC0

equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

The fast Pulse Width Modulation or fast PWM mode (WGM0[2:0] = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM0[2:0] = 3, and OCR0A when WGM0[2:0] = 7. In noninverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mo de can be twice as high as the phas e correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

7799D–AVR–11/10

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

ATmega8U2/16U2/32U2

TCNTn

OCRnx Update and TOVn Interrupt Flag Set

Period

2 3

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

4 5 6 7

OCnxPWM

clk_I/O

N 256⋅

----------------- -=

PWM mode is shown in Figure 15-6. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

Figure 15-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x[1:0] bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A[1:0] bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. Th is option is not available for the OC0B pin (See Table 15-3 on page 102). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Regis ter repre sents specia l cases when generat ing a PW M

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x[1:0] = 1). The waveform generated will have a maximum frequency of f

OC0

= f

/2 when OCR0A is set to zero. This

clk_I/O

7799D–AVR–11/10

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Update

put Compare unit is enabled in the fast PWM mode.

15.7.4 Phase Correct PWM Mode

The phase correct PWM mode (WGM0[2:0] = 1 or 5) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT TOM. TOP is defined as 0xFF when WGM0[2:0] = 1, and OCR0A when WGM0[2:0] = 5. In noninverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inve rted. The dual- slope o peration has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications.

In phase correct PWM mode the counter is increme nted until the counter value m atches TOP. When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 15-7 . The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

ATmega8U2/16U2/32U2

Figure 15-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM . The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value.

7799D–AVR–11/10

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inve rted PWM output can be generated by setting the COM0x[1:0] to three: Setting the COM0A0 bit to

ATmega8U2/16U2/32U2

OCnxPCPWM

clk_I/O

N 510⋅

----------------- -=

clk

(clk

I/O

/1)

TOVn

clk

I/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See Table 15-4 on page 103). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Compare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 15-7 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match.

• OCR0A changes its value from MAX, like in Figure 15-7. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an upcounting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up.

15.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a clock enable signal in the following figures. The fig ures include information on whe n Interrupt Flags are set. Figure 15-8 contains timing data fo r basic Timer/Counter operation. The figur e shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 15-8. Timer/Counter Timing Diagram, no Prescaling

7799D–AVR–11/10

Figure 15-9 shows the same timing data, but with the prescaler enabled.

100

Atmel ATmega8U2, ATmega16U2, ATmega32U2 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Disclaimer

2. Overview

2.1 Block Diagram

2.2 Pin Descriptions

2.2.1 VCC

2.2.2 GND

2.2.3 AVCC

2.2.4 Port B (PB7..PB0)

2.2.5 Port C (PC7..PC0)

2.2.6 Port D (PD7..PD0)

2.2.7 D-

2.2.8 D+

2.2.9 UGND

2.2.10 UVCC

2.2.11 UCAP

2.2.12 RESET/PC1/dW

2.2.13 XTAL1

2.2.14 XTAL2/PC0

3. Resources

4. Code Examples

5. Data Retention

6. AVR CPU Core

6.1 Introduction

6.2 Architectural Overview

6.3 ALU – Arithmetic Logic Unit

6.4 Status Register

6.4.1 SREG – Status Register

6.5 General Purpose Register File

6.5.1 The X-register, Y-register, and Z-register

6.6 Stack Pointer

6.6.1 SPH and SPL – Stack Pointer High and Low Register

6.7 Instruction Execution Timing

6.8 Reset and Interrupt Handling

6.8.1 Interrupt Response Time

7. AVR Memories

7.1 In-System Reprogrammable Flash Program Memory

7.2 SRAM Data Memory

7.2.1 Data Memory Access Times

7.3 EEPROM Data Memory

7.3.1 EEPROM Read/Write Access

7.3.2 Preventing EEPROM Corruption

7.4 I/O Memory

7.4.1 General Purpose I/O Registers

7.5 Register Description

7.5.1 EEARH and EEARL – The EEPROM Address Register

7.5.2 EEDR – The EEPROM Data Register

7.5.3 EECR – The EEPROM Control Register

7.5.4 GPIOR2 – General Purpose I/O Register 2

7.5.5 GPIOR1 – General Purpose I/O Register 1

7.5.6 GPIOR0 – General Purpose I/O Register 0

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

8.2 Clock Switch

8.2.1 Exemple of use

8.2.2 Clock switch Algorythm

8.2.2.1 Swith from external clock to RC clock

8.2.2.2 Switch from RC clock to external clock

8.3 Clock Sources

8.3.1 Default Clock Source

8.3.2 Clock Startup Sequence

8.4 Low Power Crystal Oscillator

8.5 Full Swing Crystal Oscillator

8.6 Calibrated Internal RC Oscillator

8.7 External Clock

8.8 Clock Output Buffer

8.9 System Clock Prescaler

8.10 PLL

8.10.1 Internal PLL for USB interface

8.1 1 Register Description

8.11.1 CLKSEL0 – Clock Selection Register 0

8.11.2 CLKSEL1 – Clock Selection Register 1

8.11.3 CLKSTA – Clock Status Register

8.11.4 OSCCAL – Oscillator Calibration Register

8.11.5 CLKPR – Clock Prescale Register