– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 4 MIPS Throughput at 4 MHz
• High Endurance Non-volatile Memorie segments
– 8K/16K Bytes of In-System Self-Programmable Flash Program
Memory(A Tmega8HVA/16HVA)
– 256 Bytes EEPROM
– 512 Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 years at 85°C /100 years at 25°C
– Programming Lock for Software Security
• Battery Management Features
– One or Two Cells in Series
– Over-current Protection (Charge and Discharge)
– Short-circuit Protection (Discharge)
– High Voltage Outputs to Drive N-Channel Charge/Discharge FETs
• Peripheral Features
– Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input
Capture (IC), Compare Mode and CTC
– SPI - Serial Programmable Interface
– 12-bit Voltage ADC, Four External and One Internal ADC Inputs
– High Resolution Coulomb Counter ADC for Current Measurements
– Programmable Watchdog Timer
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI ports
– Power-on Reset
– On-chip Voltage Regulator with Short-circuit Monitoring Interface
– External and Internal Interrupt Sources
– Sleep Modes:
Idle, ADC Noise Reduction, Power-save, and Power-off
• Additional Secure Authentication Features available only under ND A
• Packages
– 36-pad LGA
– 28-lead TSOP
• Operating Voltage: 1.8 - 9V
• Maximum Withstand Voltage (High-voltage pins): 28V
• Temperature Range: - 20°C to 85°C
• Speed Grade: 1-4 MHz
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 8K/16K
Bytes In-System
Programmable
Flash
Digital supply voltage. Normally connected to VREG.
1.3.3VREG
Output from the internal voltage regulator.
1.3.4CF1P/CF1N/CF2P/CF2N
CF1P/CF1N/CF2P/CF2N are the connection pins for connecting external fly capacito rs to the
step-up regulator.
1.3.5VREF
Internal Voltage Reference for external decoupling.
1.3.6VREFGND
Ground for decoupling of Internal Voltage Reference. Do not conn ect t o GND or SGND on PCB.
8024AS–AVR–04/08
3
ATmega8HVA/16HVA
1.3.7GND
Ground
1.3.8Port A (PA1..PA0)
Port A serves as a low-voltage 2-bit bi-d irectional I/ O port with internal pull-up resisto rs (selected
for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega8HVA/16HVA as
listed in ”Alternate Functions of Port A” on page 70.
1.3.9Port B (PB3..PB0)
Port B is a low-voltage 4-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8HVA/16HVA as
listed in ”Alternate Functions of Port B” on page 71.
1.3.10PC0
Port C serves the functions of various special features of the ATmega8HVA/16HVA as listed in
”Alternate Functions of Port C” on page 61.
1.3.11OC
1.3.12OD
1.3.13NI
1.3.14PI
1.3.15NV/PV1/PV2
1.3.16BATT
1.3.17RESET
/dw
High voltage output to drive Charge FET.
High voltage output to drive Discharge FET.
NI is the filtered negative input from the current sense resistor.
PI is the filtered positive input from the current sense resistor.
NV, PV1, and PV2 are the inputs for battery cells 1 and 2.
Input for detecting when a charger is connected.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page
38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE
communication pin.
4
8024AS–AVR–04/08
2.Overview
R
D
PB3..0
CF1P CF2P
PC0
The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion applications with focus on high security/authentication, accurate monitoring, low cost and high
utilization of the cell energy. The device contains secur e authentication features as well as
autonomous battery protection during charging and discharging. The chip allows very accurate
accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV. The feature set makes the ATmega8HVA/16HVA a key component in any system focusing on high
security, battery protection, accurate monitoring, high system utilization and low cost.
Figure 2-1.Block Diagram
ATmega8HVA/16HVA
PB0
ESET/dW
BATT
VFET
VREG
Oscillator
Circuits /
Clock
Generation
Watchdog
Oscillator
VCC
GND
CF1N CF2N
Watchdog
Timer
Power
Supervision
POR &
RESET
Charger
Detect
Voltage
Regulator
Oscillator
Sampling
Interface
Program
Logic
debugWIRE
Voltage Regulator
Monitor Interface
PORTB (4)
SPI
SRAMFlash
CPU
DATA BUS
8/16-bit T/C0
8/16-bit T/C1
PORTA (2)
PA1..0
PORTC (1)
EEPROM
Security
Module
Protection
Reference
Counter ADC
PA1..0
FET
Control
Battery
Voltage
ADC
Voltage
Coulumb
VPTAT
OC
OD
PV2
PV1
NV
VREF
VREFGN
PI
NI
A combined step-up and linear voltage regulator ensures that the chip can operate with supply
voltages as low as 1.8V for 1-cell applications. The regulator automatically switches to linear
mode when the input voltage is sufficiently high, thereby ensuring a minimum power consumption at all times. For 2-cell applications, only linear regulation is enabled. The regulator
capabilities, combined with an extremely low power consumption in the power saving modes,
greatly enhances the cell energy utilization compared to existing solutions.
The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports
pre-charging of deeply discharged ba tt er y cells without using a separate Pre-charge FET.
5
8024AS–AVR–04/08
ATmega8HVA/16HVA
The ATmega8HVA/16HVA contains a 12-bit ADC that can be used to measure the voltage of
each cell individually. The ADC can also be used to monitor temperature, either on-chip temperature using the built-in temperature sensor, external t emper ature using thermi stors conne cted to
dedicated ADC inputs. The ATmega8HVA/16HVA contains a high-voltage tolerant, open-drain
IO pin that supports serial communication. Programming can be done in-system using the 4
General Purpose IO ports that support SPI programming.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The MCU includes 8K/16K bytes of In-System Programmable Flash with Re ad-While-Write
capabilities, 256 bytes EEPROM, 512 bytes SRAM, 32 general purpose working registers, 6
general purpose I/O lines, debugWIRE for On-chip debugging and SPI for In-system Programming, two flexible Timer/Counters with Input Capture and compare modes, internal and external
interrupts, a 12-bit Sigma Delta ADC for voltage and temperature measurements, a high resolution Sigma Delta ADC for Coulomb Counting and instantan eous current measurements,
Additional Secure Authentication Features, an authonomou s Battery Protection module, a pro grammable Watchdog Timer with wake-up capabilities, and software selectable power saving
modes.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two indepdent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The device is manufactured using Atmel’s high voltage high density non-volatile memo ry technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System,
through an SPI serial interface, by a conven tional no n-volatile memory progr ammer or by a n Onchip Boot program running on the AVR core. By com bining an 8-bit RISC CPU with In-System
Self-Programmable Flash, fuel gauging ADCs, dedicated battery protection circuitry, and a voltage regulator on a monolithic chip, the ATmega8HVA/16HVA is a powerful microcontroller that
provides a highly flexible and cost effective solution for Li-ion Smart Battery applications.
The ATmega8HVA/16HVA AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Onchip Debugger.
The ATmega8HVA/16HVA is a low-power CMOS 8-bit microcontroller based on the AVR architecture. It is part of the AVR Smart Battery family that provides secure authentication, highly
accurate monitoring and autonomous protection for Lithium-ion battery cells.
6
8024AS–AVR–04/08
2.1Comparison Between ATmega8HVA and ATmega16HVA
The ATmega8HVA and ATmega16HVA differ only in memory size and interrupt vector size.
Table 2-1 summarizes the different configuration for the two devices.
Table 2-1.Configuration summary
DeviceFlashInterrupt vector size
ATmega8HVA8K1 Word
ATmega16HVA16K2 Word
3.Disclaimer
All Min, Typ and Max values contained in this datasheet are preliminary estimat es based on simulations and characterization of other AVR microcontrollers manufactured on the same process
technology. Final values will be available after the device is characterized.
4.Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
ATmega8HVA/16HVA
5.Data Retention
Note:1.
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
Notes:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F on ly.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega8HVA/16HVA is a
complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the
IN and OUT instructions. For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
––––ICF1OCF1BOCF1ATOV193
––––ICF0OCF0BOCF0ATOV093
––––––––
––––––––
8024AS–AVR–04/08
11
ATmega8HVA/16HVA
7.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd − 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2
MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2
MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2
FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSRd, RrFractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSURd, RrFractional Multiply Signed with UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
(1)
JMP
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
(1)
CALL
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Reg i ster with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs , kBranch if Sta tus Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/ 2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1N one1/2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
kDirect JumpPC ← kNone3
kDirect Subroutine Call PC ← kNone4
12
8024AS–AVR–04/08
ATmega8HVA/16HVA
7.Instruction Set Summary (Continued)
MnemonicsOperandsDescriptionOperationFlags#Clocks
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
BIT AND BIT-TEST INSTRUCTIONS
SBIP,bSet Bit in I/O RegisterI/O(P,b) ← 1None2
CBIP,bClear Bit in I/O RegisterI/O(P,b) ← 0None2
LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1
LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1
ROLRdRotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)Z,C,N,V1
RORRdRotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1
ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n=0..6Z,C,N,V1
SWAPRdSwap NibblesRd(3..0)← Rd(7..4),Rd(7..4)←Rd(3..0)None1
BSETsFlag SetSREG(s) ← 1SREG(s)1
BCLRsFlag ClearSREG(s) ← 0 SREG(s)1
BSTRr, bBit Store from Register to TT ← Rr(b)T1
BLDRd, bBit load from T to RegisterRd(b) ← TNone1
SECSet CarryC ← 1C1
CLCClear CarryC ← 0 C1
SENSet Negative FlagN ← 1N1
CLNClear Negative FlagN ← 0 N1
SEZSet Zero FlagZ ← 1Z1
CLZClear Zero FlagZ ← 0 Z1
SEIGlo ba l Interru pt Ena bleI ← 1I1
CLIGlobal Interrupt DisableI ← 0 I1
SESSet Signed Test FlagS ← 1S1
CLSClear Signed Test FlagS ← 0 S1
SEVSet Twos Complement Overflow.V ← 1V1
CLVClear Twos Complement OverflowV ← 0 V1
SETSet T in SREGT ← 1T1
CLTClear T in SREGT ← 0 T1
SEHSet Half Carry Flag in SREGH ← 1H1
CLHClear Half Carry Flag in SREGH ← 0 H1
DATA TRANSFER INSTRUCTIONS
MOVRd, RrMove Between RegistersRd ← RrNone1
MOVWRd, RrCopy Register Word
LDIRd, KLoad ImmediateRd ← KNone1
LDRd, XLoad IndirectRd ← (X)None2
LDRd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2
LDRd, - XLoad Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None2
LDRd, YLoad IndirectRd ← (Y)None2
LDRd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2
LDRd, - YLoad Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None2
LDDRd,Y+qLoad Indirect with DisplacementRd ← (Y + q)None2
LDRd, ZLoad Indirect Rd ← (Z)None2
LDRd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2
LDRd, -ZLoad Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2
LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None2
LDSRd, kLoad Direct from SRAMRd ← (k)None2
STX, RrStore Indirect(X) ← RrNone2
STX+, RrStore Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2
ST- X, RrStore Indirect and Pre-Dec.X ← X - 1, (X) ← RrNone2
STY, RrStore Indirect(Y) ← RrNo ne2
STY+, RrStore Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2
ST- Y, RrStore Indirect and Pre-Dec.Y ← Y - 1, (Y) ← RrNone2
STDY+q,RrStore Indirect with Displacement(Y + q) ← RrNone2
STZ, RrStore Indirect(Z) ← RrNone2
STZ+, RrStore Indirect and Post-Inc.(Z) ← Rr, Z ←
ST-Z, RrStore Indirect and Pre-Dec.Z ← Z - 1, (Z) ← RrNone2
STDZ+q,RrStore Indirect with Displacement(Z + q) ← RrNone2
STSk, RrStore Direct to SRAM(k) ← RrNone2
LPMLoad Program MemoryR0 ← (Z)None3
LPMRd, ZLoad Program MemoryRd ← (Z)None3
LPMRd, Z+Load Program Memo ry and Post-IncRd ← (Z), Z ← Z+1None3
SPMStore Program Memory(Z) ← R1:R0NoneINRd, PIn PortRd ← PNone1
Rd+1:Rd ← Rr+1:Rr
Z + 1None2
None1
8024AS–AVR–04/08
13
ATmega8HVA/16HVA
7.Instruction Set Summary (Continued)
MnemonicsOperandsDescriptionOperationFlags#Clocks
OUTP, RrOut PortP ← RrNone1
PUSHRrPush Register on StackSTACK ← RrNone2
POPRdPop Register from StackRd ← STACKNone2
MCU CONTROL INSTRUCTIONS
NOPNo OperationNone1
SLEEPSleep(see specific descr. for Sleep function)None1
WDRWatchdog Reset(see specific descr. for WDR/timer)None1
BREAKBreakFor On-chip Debug OnlyNoneN/A
Note:1. These instructions are only available in ATmega16HVA.
14
8024AS–AVR–04/08
8.Ordering Information
8.1ATmega8HVA
ATmega8HVA/16HVA
36CK1
28T
(1)
Operation Range
-20 to +85°C
Speed (MHz)Power SupplyOrdering CodePackage
1 - 41.8 - 9.0V
Notes:1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
ATmega8HVA-4CKU
ATmega8HVA-4TU
Package Type
36CK136-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package.
28T28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP)
8024AS–AVR–04/08
15
ATmega8HVA/16HVA
8.2ATmega16HVA
36CK1
28T
(1)
Operation Range
-20 to +85°C
Speed (MHz)Power SupplyOrdering CodePackage
1 - 41.8 - 9.0V
Notes:1. Pb-free packaging, complies with the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
ATmega16HVA-4CKU
ATmega16HVA-4TU
36CK136-pad, (6.50 x 3.50 x 0.85 mm Body, 0.60 mm Pitch), Land Grid Array (LGA) Package.
28T28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP)
16
Package Type
8024AS–AVR–04/08
9.Packaging Information
9.136CK1
Marked A1 ID
Top View
ATmega8HVA/16HVA
D
E
A1 (Substrate)
A (Total PKG HGT)
0.08
A1 BALL PAD CORNER
8
6
7
5
3
4
e
e2
e1
L1
e
Øb
Bottom View
Notes: 1. This drawing is for general information only.
2. Metal pad dimensions.
3. = > Dummy pad.
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
36CK1, 36-Pad, 6.50 x 3.50 x 0.73 mm Body,
0.60 mm Pitch, Land Grid Array (LGA) Package
Side View
2
1
A
B
C
D
E
b
L
SYMBOL
D 6.40 6.50 6.60
E 3.40 3.50 3.60
A 0.59 0.66 0.73
A1 0.17 0.21 0.25
L 0.70 REF 2
L1 0.35 REF
b 0.35 REF 2
Øb 0.32 0.35 0.38 2
e 0.60 TYP
e1 0.80 REF
e2 0.55 REF
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
3/15/07
DRAWING NO.
36CK1
REV.
D
8024AS–AVR–04/08
17
ATmega8HVA/16HVA
9.228T
PIN 1
Pin 1 Identifier Area
D1
D
e
E
b
A2
A
A1
Notes:1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
0º ~ 5º
SEATING PLANE
SYMBOL
c
L
L1
GAGE PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A––1.20
A10.05–0.15
A20.901.001.05
D13.2013.4013.60
D111.7011.8011.90Note 2
E7.908.008.10Note 2
L0.500.600.70
L10.25 BASIC
b0.170.220.27
c0.10– 0.21
e0.55 BASIC
NOM
MAX
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
18
TITLE
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
28T
8024AS–AVR–04/08
12/06/02
REV.
C
10. Errata
10.1ATmega8HVA
10.1.1Rev. A
10.2ATmega16HVA
10.2.1Rev. A
ATmega8HVA/16HVA
No known errata.
No known errata.
8024AS–AVR–04/08
19
ATmega8HVA/16HVA
11. Datasheet Revision History
11.1Rev. 8024A – 04/08
1.Initial revision
20
8024AS–AVR–04/08
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