Features
• High-performance, Low-power AVR
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
– 8K Bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-W ri te Operation
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– 1K Byte Internal SRAM
– Programming Lock for Software Security
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and MLF package
Six Channels 10-bit Accuracy
Two Channels 8-bit Accuracy
– 6-channel ADC in PDIP package
Four Channels 10-bit Accuracy
Two Channels 8-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Progr ammable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power -on Rese t and Programmable Brown- out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF
• Operating Voltages
– 2.7 - 5.5V (ATmega8L)
– 4.5 - 5.5V (ATmega8)
• Speed Grades
– 0 - 8 MHz (ATmega8L)
– 0 - 16 MHz (ATmega8)
• Power Consumpti o n at 4 Mhz, 3V, 25°C
– Active: 3.6 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 0.5 µA
®
8-bit Microcontroller
8-bit
with 8K Bytes
In-System
Programmable
Flash
ATmega8
ATmega8L
2486M–AVR–12/03
Rev. 2486M–AVR–12/03
Pin Configurations
PDIP
(RESET) PC6
(XCK/T0) PD4
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(INT1) PD3
(XCK/T0) PD4
GND
VCC
GND
VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3
VCC
GND
(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0
TQFP Top View
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PD2 (INT0)
PD1 (TXD)
32313029282726
9101112131415
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)
PC3 (ADC3)
PC2 (ADC2)
25
24
PC1 (ADC1)
23
PC0 (ADC0)
22
ADC7
21
GND
20
AREF
19
ADC6
18
AVCC
17
PB5 (SCK)
16
(T1) PD5
(ICP1) PB0
(AIN0) PD6
(AIN1) PD7
(MISO) PB4
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
MLF Top View
PD2 (INT0)
PD1 (TXD)
PD0 (RXD)
PC6 (RESET)
PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
32313029282726
(INT1) PD3
(XCK/T0) PD4
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7
2
ATmega8(L)
GND
VCC
GND
VCC
1
2
3
4
5
6
7
8
9101112131415
(T1) PD5
(AIN0) PD6
(ICP1) PB0
(AIN1) PD7
25
16
(MISO) PB4
(OC1A) PB1
(SS/OC1B) PB2
(MOSI/OC2) PB3
24
23
22
21
20
19
18
17
PC1 (ADC1)
PC0 (ADC0)
ADC7
GND
AREF
ADC6
AVCC
PB5 (SCK)
2486M–AVR–12/03
ATmega8(L)
Overview The ATmega8 is a low-p ower CM OS 8-bit microcontro ller based on the A VR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega8
achieves throug hputs a pproac hing 1 MIPS pe r MHz, all owing the syst em de signer to
optimize power consumption versus processing speed.
Block Diagram Figure 1. Block Diagram
XTAL1
RESET
VCC
PC0 - PC6 PB0 - PB7
XTAL2
GND
AGND
AREF
PORTC DRIVERS/BUFFERS
PORTC DIGITAL INTERFACE
MUX &
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
AVR CPU
ADC
INTERFACE
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
PORTB DRIVERS/BUFFERS
PORTB DIGITAL INTERFACE
TWI
TIMERS/
COUNTERS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CTRL.
& TIMING
INTERRUPT
UNIT
EEPROM
OSCILLATOR
OSCILLATOR
2486M–AVR–12/03
PROGRAMMING
LOGIC
+
-
SPI
COMP.
INTERFACE
USART
PORTD DIGITAL INTERFACE
PORTD DRIVERS/BUFFERS
PD0 - PD7
3
The AVR core combines a ric h instr uctio n set wit h 32 general purpose worki ng regi sters .
All the 32 regi sters are dire ctly conn ected to the Arithm etic Logic U nit (A LU), all owing
two independent regist ers t o be acces sed i n one sing le inst ructi on execut ed in one clo ck
cycle. The resulting arc hitect ur e is more code eff icient whil e achievi ng throug hput s up to
ten times faster than conventional CISC microcontrollers.
The ATmega8 provides the following features: 8K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23
general purpose I/O lines, 32 general purpose working registers, three flexible
Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, a 6-channel ADC (eight
channels in TQFP and MLF packages) where four (six) chann els have 10-bit accuracy
and two channels have 8-bi t accurac y, a programmabl e Wa tchdog Tim er with Internal
Oscillator, an SPI serial port, and five software selec table power savi ng modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt
system to continue functioning. The Power-down mode saves the register contents but
freezes the Oscillator, disabling all other chip functions until the next Interrupt or Hardware Reset. In Power-save mode, the asynch ronou s time r conti nues to run, all owing the
user to mainta in a tim er bas e wh ile the re st of t he d evice i s slee ping . T he AD C N oise
Reduction mode stops the CPU and all I/O modules except asynchronous timer and
ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillato r is running while the rest of the device is sleeping . This allows
very fast start-u p combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology.
The Flash Program memory can be reprogrammed In-System through an SPI serial
interface, by a con ventio nal no n-volat ile me mory pro gramme r, or by an On-c hip boot
program running on the AVR core. The boot program can use any interface to download
the application program in the Application Flash memory. Software in the Boot Flash
Section will continue to run while the Application Flash Section is updated, providing
true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-ef fective solution to many embed ded
control applications.
The ATmega8 A VR i s supp orted with a f ull su ite of program and sys tem de velopm ent
tools, including C co mpilers , macro assem blers, p rogram debugg er/simu lators, In-Circuit Emulators, and evaluation kits.
Disclaimer Typical values contained i n this dat asheet are based on simulatio ns and ch aracteriza-
tion of other AVR microcontrollers manufactured on the same process technology. Min
and Max values will be available after the device is characterized.
4
ATmega8(L)
2486M–AVR–12/03
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
ATmega8(L)
Port B (PB7..PB0) XTAL1/ XTAL2/TOSC1/TOSC2
Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each
PC6/RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electri-
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buf fers have symmetrical drive char acteristics with both hi gh sink
and source capability. As inputs, Por t B pins that are externally p ulled low w ill source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplif ier and input to the internal clock oper ating circuit.
Depending on the clock selection fuse settings, PB7 can be used as output from the
inverting Oscillator amplifier.
If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is u sed as
TOSC2..1 input for the Asynchronous Timer/Counte r2 if the AS2 bit in ASSR is set.
The various special features of Port B are elaborated in “Alternate Functions of Port B”
on page 56 and “System Clock and Clock Options” on page 23.
bit). The Port C output buffers have symmetri cal drive characterist ics with both high sink
and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
cal characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on
this pin for longer than the minimum pulse length will generate a Reset, even if the clock
is not running. T he minimu m pulse len gth is give n in Tabl e 15 on pa ge 36. Shorter
pulses are not guaranteed to generate a Reset.
The various special features of Port C are elaborated on page 59.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers have symmetri cal drive characterist ics with both high sink
and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port D also serves the functions of vari ous special features of the ATmega8 as listed on
page 61.
RESET Reset input. A low level on this pin for longer than the minimum pulse length will gener-
ate a reset, even if the clock is not running. The minimum pulse length is given in Table
15 on page 36. Shorter pulses are not guara nteed to generate a reset.
2486M–AVR–12/03
5
AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It
should be externally connected to V
it should be connected to VCC through a low-pass filter. Not e that Port C (5..4) use digi tal
supply voltage, V
AREF AREF is the analog reference pin for the A/D Convert e r.
CC
.
, even if the ADC is not used. If the ADC is used,
CC
ADC7..6 (TQFP and MLF Package Only)
About Code Examples
In the TQFP and MLF p ackag e, ADC7 ..6 serve as anal og inputs to the A/D conver ter.
These pins are powered from the analog supply and serve as 10-bi t ADC channels.
This datasheet contains simple code examples that briefly show how to use various
parts of the device. These cod e example s assume tha t the part speci fic header file is
included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please
confirm with the C compiler documentation for more details.
6
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
AVR CPU Core
Introduction This section discusses the AV R core architecture in general. The main function of the
CPU core is to e nsu re corre ct program exec ution. The CP U mu st there fore b e abl e to
access memories, perform cal culations, control peripherals, and handle interrupts.
Architectural Overview Figure 2. Block Diagram of the AVR MCU Architecture
Data Bus 8-bit
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Control Lines
Program
Counter
Direct Addressing
Status
and Control
32 x 8
General
Purpose
Registrers
ALU
Indirect Addressing
Data
SRAM
EEPROM
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
i/O Module1
i/O Module 2
i/O Module n
2486M–AVR–12/03
I/O Lines
In order to maximize per formance and parallelism, the AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the Program
memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept
enables in struc tions to be exec uted in ever y clock cy cle. Th e Progr am mem ory is I nSystem Reprogrammable Flash memory.
The fast-access Regist er File contains 32 x 8-bit general purpose working registers with
a single clock cycle a ccess time. This a llows single -cycle Arithmetic Logic Unit (ALU)
operation. In a typical AL U operation, two operands are out put from the Registe r File,
the operation is executed, and the result is stored back in the Register File – in one
clock cycle.
7
Six of the 32 registers can be used as three 16-bit indirect address register pointers for
Data Space addressing – enabling efficient address calculations. One of the these
address pointers can also be use d as an address pointer for look up tables in Flash Program memory. These adde d function registers are the 1 6-bit X-, Y-, and Z-register,
described later in t his section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After
an arithmetic operation, the St atus Regist er is updat ed to reflect i nformation a bout the
result of the operation.
The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole ad dress space. Most AVR instructions h ave a
single 16-bit word format. Every Program me mory address contains a 16- or 32-bit
instruction.
Program Flash memory space is divided in two sections, the Boot program section and
the Application program secti on. Both sections have dedicated Lock Bits for write and
read/write protect ion. The SPM instruction that writes into the Application Flash memory
section must reside in the Boot program section.
During interrupts and subroutine cal ls, the return address Program Counter (PC) is
stored on the Stack . Th e Stac k is effectiv ely al locat ed in t he general data SRAM , a nd
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible inte rrupt modu le has its con trol regist ers in the I/O space with an additio nal
global interrupt enable bit in the Status Register. All interrupts have a separate Interrupt
Vector in the Interrupt Vector table. The interrupts have priority in accordance with their
Interrupt Vector pos ition. The lower the Interrupt Vect or address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control
Registers, SPI, and other I/O functions. The I/O Memory can be accessed dir ectl y, or as
the Data Space locations follow ing t hose of t he Register File, 0x20 - 0x5F.
8
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
Arithmetic Logic Unit – ALU
The high-performance AVR ALU operates in direct connection with all the 32 general
purpose worki ng register s. Withi n a single cl ock cycle, arithmet ic operat ions betw een
general purp ose regis ters or be tween a re giste r and an imme diate ar e ex ecuted . T he
ALU operations are divided i nto three main categories – arithmetic, logical, and bit- functions. Some implementations of the architecture also provide a powerful multiplier
supporting both signed/unsi gned m ultiplic ation and fractio nal format. See the “Ins truction Set” section for a detailed description.
Status Register The Status Register contains information about the result of the most recently executed
arithmetic instruction. This information can be used for altering program flow in order to
perform conditi onal opera tions. Note that the Stat us Registe r is update d after all AL U
operations, as specified in the Instruction Set Reference. This will in many cases
remove the need for using the dedicated compare instructions, resulting in faster and
more compact code.
The Status Register is not a utomaticall y stored wh en ent ering an i nterrupt routine and
restored when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit 7 6 5 4 3 2 1 0
I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Valu e 0 0 0 0 0 0 0 0
• Bit 7 – I: Glob a l In te r ru p t En a b le
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global
Interrupt Enable Register is cleared, none of the interrupts are enabled independent of
the individual interrupt enable sett ings. The I-bit is cl eared by hardwar e after an in terrup t
has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as
described in the Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as sour ce or
destination for the operated bit. A bit from a register in the Reg ister File can be copied
into T by the BST instruction, and a bit i n T can be copied into a b it in a reg ister in the
Register File by the BLD instruct ion.
• Bit 5 – H: Half Car ry F la g
The Half Carry Fl ag H indicates a Hal f Carry in some arithmetic operations. Half Carry is
useful in BCD arithmetic. See the “Instru cti on Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusiv e or between t he Negative Flag N and the Two’ s Complement Overflow Flag V. See the “Instruction Set Descr iption” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s C omplem ent O verflow Fla g V s upports two’s compl eme nt a rithmet ics. S ee
the “Instruction Set Descr iption” for detailed informati on.
• Bit 2 – N: Negative Flag
2486M–AVR–12/03
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See
the “Instruction Set Descr iption” for detailed informati on.
• Bit 1 – Z: Zero Flag
9
The Zero Flag Z indicates a zero result i n an arith metic or logic operation. S ee the
“Instruction Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.
General Purpose Register File
The Register F ile is optim ized f or the A VR E nhanc ed RIS C in struction set. I n orde r to
achieve the required performance and flexibility, the following input/output schemes are
supported by the Register File:
• One 8-bit output operand and one 8-bit result input.
• Two 8-bit output operands and one 8-bit result input.
• Two 8-bit output operands and one 16-bit result input.
• One 16-bit output operand and one 16-bit result input.
Figure 3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
10
Most of the instruction s operati ng on the Regist er File have di rec t access to al l regi sters ,
and most of them are single cycle instructions.
As shown in Figure 3, each register is also assigned a Data memory address, mapping
them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, t his memory organizati on provides great
flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to
index any register in the file.
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
The X-register, Y-register and Z-register
The registers R26..R31 have some added functions to their general purpose usage.
These registers are 16-bit address pointers for i ndirect addressing of the Data Sp ace.
The three indirect address registers X, Y and Z are defined as described in Figure 4.
Figure 4. The X-, Y- and Z-Registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressi ng mode s these ad dress registe rs have f unctions as f ixed di splacement, automatic increm ent, and autom atic decremen t (see the Inst ruction Set
Reference for details).
Stack Pointer The Stack is mainly used for storing temp orary data, for storing l ocal variables and for
storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing
from higher memory locati ons to lower mem ory locations. This implies that a Stack
PUSH command decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the
program before any subroutine calls are executed or interrupts are enabled. The Stack
Pointer must be set to point a bove 0x60. The Stack Poi nter is decremented by one
when data is pushed ont o the Stack with the PUSH inst ruction, and it is decremented by
two when the return address is pushed onto the Stack with subroutine call or interrupt.
The Stack Pointer is incremented by one when dat a is popped f rom the Stack with the
POP instruction, and it is incremented by two when address is popped from the Stack
with return from subroutine RET or return fr om inte rrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I /O space. The number of bits actually used i s implementation dependent. Note that t he data space in some
implementations of the AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present.
Bit 15 14 13 12 11 10 9 8
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
7 6 5 4 3 2 1 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Valu e 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
2486M–AVR–12/03
11
Instruction Execution Timing
This section describes the gener al access timing conc epts for i nstruct ion execut ion. The
AVR CPU is driven by the CPU clock clk
, directly generated from the selected clock
CPU
source for the chip. No internal clock division is used.
Figure 5 shows the parallel instructi on fetches and instruc tion exec utions enab led by the
Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept t o obtain up t o 1 M IPS p er MH z with t he co rrespondin g u nique res ults for
functions per cost, functions per clocks, and functions per power-unit.
Figure 5. The Parallel Instruc ti on Fetches and Instruction Executions
T1 T2 T3 T4
clk
CPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 6 shows the internal timing concept for the Register File. In a single clock cycle
an ALU operation using two register operands is executed, and the result is stored back
to the destination regis ter.
Reset and Interrupt Handling
Figure 6. Single Cycle ALU Operation
T1 T2 T3 T4
clk
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
The AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All
interrupts are assigned indi vidual en able bits w hich must b e wr itten logic one together
with the Global Interru pt Ena ble bit i n the Stat us Reg ister in orde r to enabl e the i nterr upt.
Depending on the Program Counter value, interrupts may be automatically disabled
when Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves software
security. See the section “Memor y Programming” on page 219 for details.
The lowest addresse s in the Program memory spa ce are by default define d as the
Reset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on
page 44. The list also determines the priority levels of the different interrupts. The lower
the address the higher is the priority l evel. RESET ha s the highe st priority, and next is
INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start
12
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
of the boot Flash section by settin g the Interrup t Vector Select (IVSEL) bit in t he General
Interrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information.
The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write SelfProgramming” on page 206.
When an interrupt occurs, the Global In terrupt Enab le I-bit is cleared and al l interrupts
are disabled. The user softw are ca n wri te logi c on e to the I-bit t o en able n este d int errupts. All enabled interrupts can then i nterrupt the current interrupt routine. The I-bit is
automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basicall y two types of inter rupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bi t posi tion( s) to be c leared. If an i nterr upt condi tion oc cur s while the
corresponding interrupt enable bit is cleared, the Interrupt Fl ag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or
more interrupt conditions occur while the global interrupt enable bit is cleared, the cor responding Interrupt Flag(s) will be set and remembered until the globa l interrupt enable
bit is set, and will then be executed by order of pri ority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the i nterrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will alway s return to the main program and execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt wil l be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to
avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMWE ; start EEPROM write
sbi EECR, EEWE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMWE); /* start EEPROM write */
EECR |= (1<<EEWE);
SREG = cSREG; /* restore SREG value (I-bit) */
2486M–AVR–12/03
13
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending inter rupt s, as shown in the following example.
Assembly Code Example
sei ; set global interrupt enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI(); /* set global interrupt enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles
minimum. After four clock cycles, the Program Vector address for the actual interrupt
handling routine is exe cuted. D uring th is 4-cloc k cycle p eriod, th e P rogram Counter is
pushed onto the Stack. Th e Vector is n ormally a jum p to the interrupt routine, and this
jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt
occurs when the MCU is in sleep mode, the interrupt execution response time is
increased by four clock cycles. This increase comes in additio n to the st art-up time from
the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four
clock cycles, the Program C ounter (2 byt es) is popped back from the St ack, the St ack
Pointer is incremented by 2, and the I-bit in SREG is set.
14
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
AVR ATmega8 Memories
In-System Reprogrammable Flash Program Memory
This section de scribes the di fferent mem ories in the A Tmega8. The AVR archit ecture
has two main memory spaces, the Data memory and the Program Memory space. In
addition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.
The ATmega8 contains 8K bytes On-c hip In-Sys tem Repro gramma ble Flash memory
for program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is
organized as 4K x 16 bits. F or sof tware se curity, the Fla sh Prog ram m emory spac e is
divided into two sections, Boot Program section and Application Program secti on.
The Flash me mory has an endurance of at least 10 ,000 write/erase cycles. The
ATmega8 Program Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock Bits for
software protection are described in detail in “Boot Loader Support – Read-While-Write
Self-Programming” on page 206. “Memory Programming” on page 219 contains a
detailed description on Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be all ocated within the entire Program memory addr ess space (see
the LPM – Load Program memory instruction description) .
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 12.
Figure 7. Program Memory Map
Application Flash Section
Boot Flash Section
$000
$FFF
2486M–AVR–12/03
15
SRAM Data Memory Figure 8 shows how the ATmega8 SRAM Memory is organized.
The lower 1120 Data memory locations address the Register File, the I/O Memory, and
the internal data SRAM. The first 96 locations ad dress the R egister File and I /O Memory, and the next 1024 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with
Displacement, Indirect , Indi rect with Pre- decr ement, and Indir ect wit h Post-i ncre ment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing rea ches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base
address given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address regis ters X, Y and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Register s, and the 1024 bytes of inter-
nal data SRAM in the ATmega8 are all accessible through all these addressing modes.
The Register File is described in “General Purpose Register File” on page 10.
Figure 8. Data Memory Map
Register File
Data Address Space
R0
R1
R2
...
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
$0000
$0001
$0002
...
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
Internal SRAM
$0060
$0061
...
$045E
$045F
16
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
Data Memory Access Times
This section describes the general access timing concepts for internal memory access.
The internal data SRAM access is performed in two clk
cycles as described in Figure
CPU
9.
Figure 9. On-chip Data SRAM Access Cycles
T1 T2 T3
clk
CPU
Address
Data
WR
Data
RD
Compute Address
Memory Vccess Instruction
Address Valid
Write
Read
Next Instruction
EEPROM Data Memory The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a sepa-
rate data sp ace, in w hich si ngle b ytes can be re ad and writte n. Th e E EPRO M has an
enduranc e of at lea st 100, 000 write /erase cycle s. The acc ess be tween th e EEPR OM
and the CPU is described bellow, specifying the EEPROM Address Registers, the
EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 219 contains a detailed description on EEPROM Programming in SPI- or Parallel Programming mode.
EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 1 on page 19. A self-timing
function, however, lets the user software detect when the next byte can be written. If the
user code contains instructions that w rite the EEPROM , some precautions m ust be
taken. In heavily filtered power supplies, V
is likely to rise or fall slowly on Power-
CC
up/down. This causes the device for some period of time to run at a voltage lower than
specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 21. for details on how to avoid probl ems in these situations.
In order to prevent unintenti onal EEPROM writes, a specific wr ite pro cedure must be f ollowed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU i s halted for four clock cycles before the next
instruction is execut ed. Wh en the E EPRO M is w ritten, the CPU is h alted fo r two cl ock
cycles before the next instr u ction is executed.
2486M–AVR–12/03
17
The EEPROM Address Register – EEARH and EEARL
Bit 15 14 13 12 11 10 9 8
– – – – – – – EEAR8 EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
7 6 5 4 3 2 1 0
Read/Write R R R R R R R R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Valu e 0 0 0 0 0 0 0 X
X X X X X X X X
• Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in t he ATmega8 and will alway s read as zero.
• Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Ad dress Registers – EEAR H and EEARL – speci fy the EEPROM
address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The ini tial val ue o f EEAR is undefi ned. A proper value must be
written before the EEPROM may be accessed.
The EEPROM Data Register – EEDR
The EEPROM Control Register – EECR
Bit 7 6 5 4 3 2 1 0
MSB LSB EEDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Valu e 0 0 0 0 0 0 0 0
• Bits 7..0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to
the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by
EEAR.
Bit 7 6 5 4 3 2 1 0
– – – – EERIE EEMWE EEWE EERE EECR
Read/Write R R R R R/W R/W R/W R/W
Initial Valu e 0 0 0 0 0 0 X 0
• Bits 7..4 – Res: Reserved Bits
These bits are reserved bits in t he ATmega8 and will alway s read as zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a
constant interrupt when EEWE is cleared.
• Bit 2 – EEMWE: EEPROM Master Write Enable
18
The EEMWE bit determines wh ether setting E EWE to one causes the EEP ROM to be
written. When EEMWE is set, setting EEWE within four clock cyc les will write data to the
EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.
When EEMWE has been written to one by software, hardware cl ears the bit to zero after
four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
• Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When
address and data are correctly set up, the EEWE bit must be written to one to write the
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
value into the EEPROM. The EEMWE bit must be written to one before a logical one is
written to EEWE, otherwise no EEPROM write takes place. The following procedure
should be followed when writing the EEPROM (the order of steps 3 and 4 is not
essential):
1. Wait until EEWE becomes zero.
2. Wait until SPMEN in SPMCR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6. Within four clock cycles afte r setting EEMWE, write a logical one to EEWE.
The EEPROM can not be progra mmed du ring a CPU write to the Flash me mory. The
software must check that the Flash programming is completed before initiating a new
EEPROM writ e. St ep 2 is o nly rel evant i f the s oftwa re c ontain s a b oot loader al lowing
the CPU to program the F lash. If the F lash is never being u pdated by the CPU, st ep 2
can be omitted. See “Boot Loa der Suppo rt – Read-While-Writ e Self-Programmin g” on
page 206 for details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the
EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be
modified, causing th e inte rrupted E EPROM acce ss to fa il. It is recom mended to ha ve
the Global Interrupt Flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEWE bit is cleared by hardware. The
user software can poll this bit and wait for a zero before writing the next byte. When
EEWE has been set, the CPU is halted for two cycles before the n ext instruction is
executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to a logic
one to trigger the EEPROM read. The EEPROM read access takes one instruction, and
the requested data is available immediately. When the EEPROM is read, the CPU is
halted for four cycles before the next instruction is executed.
The user should poll the EEWE bit be fore st artin g the read oper ation. If a wri te opera tion
is in progress, it is neither pos sible to read the EEPRO M, nor to change the EEAR
Register.
The calibrated Oscil lator is used to ti me the EEPROM accesses. Table 1 li sts the typical
programming time for EEPROM access from the CPU.
Table 1. EEPROM Programming Time
Number of Calibrated RC
Symbol
EEPROM Write (from CPU) 8448 8.5 ms
Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.
Oscillator Cycles
(1)
Typ Programming Time
2486M–AVR–12/03
19
The following code examples show one assembly and on e C function for writing to the
EEPROM. The examples assume that i nterrupts are controlled (for example by disabling interrupts glob ally) so that no interrupts will occur during execution of these
functions. The exam ples also assume t hat no Flash boo t loader is present in the software. If such code is present, the EEPROM write function must also wait for any
ongoing SPM command to finish.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_write
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Write data (r16) to data register
out EEDR,r16
; Write logical one to EEMWE
sbi EECR,EEMWE
; Start eeprom write by setting EEWE
sbi EECR,EEWE
ret
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address and data registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMWE */
EECR |= (1<<EEMWE);
/* Start eeprom write by setting EEWE */
EECR |= (1<<EEWE);
}
20
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interru pts are controlled so that no interrupts will occur during
execution of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEWE
rjmp EEPROM_read
; Set up address (r18:r17) in address register
out EEARH, r18
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEWE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
EEPROM Write during Powerdown Sleep Mode
Preventing EEPROM Corruption
2486M–AVR–12/03
When entering Power-down sleep mode whi le an EEPROM write opera tion i s activ e, the
EEPROM write operation will continue, and will complete before the Write Access time
has passed. However, when the write operation is completed, the Oscillator conti nues
running, and as a consequence, the device does not enter Power-down entirely. It is
therefore recommended to verify that the EEPROM write operation is completed before
entering Power-down.
During periods of low V
the EEPROM data can be corrupted because the supply volt-
CC,
age is too low for the CPU and the EEPROM to operate properly. These issues are the
same as for board level systems using EEPROM, and the same design solutions should
be applied.
An EEPROM data corruption can be caused by two situations wh en the voltage is too
low. First, a regular write sequence to t he EEPROM requires a minimum volt age to
operate correctly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM da ta corruption can easily be avoided by fol lowing this design
recommendation:
21
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the
detection level of the intern al BOD does no t match the needed det ection l evel, an
external low V
operation is in progress, the write operation will be completed provided that the
power supply voltage is suffici ent.
Reset Protection circuit can be used. If a reset occurs while a write
CC
I/O Memory The I/O space definition of the ATmega8 is shown in “” on page 282.
All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are
accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 0x1F are directly bit-acces sible using the SBI and CB I instructions. In these re gisters,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer
to the instruction set sec ti on for more details. When using the I/O specific commands IN
and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers
as data space using LD and ST instructions, 0x20 must be added to t hese addresses.
For compatibility wit h future devices, rese rved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writi ng a logical one to them. Note that the CBI
and SBI instructions will operate on all bits in the I/O Register, writing a one back into
any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
22
ATmega8(L)
2486M–AVR–12/03
System Clock and Clock Options
ATmega8(L)
Clock Systems and their Distribution
Figure 10 presen ts the princip al clo ck system s in the AV R and the ir distributi on. All of
the clocks need not be active at a given time. In order to redu ce power consump tion, the
clocks to modules not being used can be halted by using different sleep modes, as
described in “Power Management and Sleep Modes” on page 31. The clock systems
are detailed Figure 10.
Figure 10. Clock Distribution
Asynchronous
Timer/Counter
General I/O
Modules
clk
clk
ASY
ADC CPU Core RAM
clk
ADC
I/O
AVR Clock
Control Unit
Source Clock
Clock
Multiplexer
clk
CPU
clk
FLASH
Reset Logic
Watchdog Timer
Watchdog Clock
Watchdog
Oscillator
Flash and
EEPROM
CPU Clock – clk
I/O Clock – clk
I/O
Flash Clock – clk
2486M–AVR–12/03
CPU
FLASH
Timer/Counter
Oscillator
External RC
Oscillator
External Clock
Crystal
Oscillator
Low-Frequency
Crystal Oscillator
Calibrated RC
Oscillator
The CPU clock is routed to parts of the system concerned with operation of the AVR
core. Examples of such module s are the General Purpose Reg ister File, the Stat us Register and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the
core from performing general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and
USART. The I/O clock is also used by the External Interrupt module, but note that some
external inter rupts are d etected by as ynchrono us logic, al lowing suc h interrup ts to be
detected even if the I/O cloc k is halted. Also note that address recogniti on in the TWI
module is carried out async hronousl y when clk
is halted, enabling TWI address recep -
I/O
tion in all sleep modes.
The Flash clock controls operation of the Flash interface. The Flash clock is usually
active simultaneously with th e CPU clock.
23
Asynchronous Timer Clock –
clk
ASY
The Asynchronous Timer cl ock allo ws the A synchronous Tim er/Counter t o be c locked
directly from an external 32 kHz clock crystal. The dedicated clock domain allows using
this Timer/Counter as a real-time counte r even when the device is i n sleep mod e. The
Asynchronous Timer/Counter uses the same XTAL pins as the CPU m ain clock but
requires a CPU main clock frequency of more than four times the Oscillator frequency.
Thus, asynchronous operation is only available while the chip is clocked on the Internal
Oscillator.
ADC Clock – clk
ADC
The ADC is provid ed with a ded icated clock do main. Thi s allows ha lting the C PU and
I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.
Clock Sources The device has the following clock source options, selectable by Flash Fuse Bits as
shown below. The clock from the selected source is input to the A VR cl ock gene rator,
and routed to the appropriate module s.
Table 2. Device Clocking Options Select
Device Clocking Option CKSEL3..0
External Crystal/Ceramic Resonator 1111 - 1010
External Low-frequency Crystal 1001
External RC Oscillator 1000 - 0101
Calibrated Internal RC Oscillator 0100 - 0001
External Clock 0000
Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocki ng optio n is given i n the followi ng secti ons. When the
CPU wakes u p from P ower-dow n or Po wer-sa ve, the sel ected cl ock so urce is used to
time the start-up, ens uring st able Osci llat or op erati on before i nstruc tion exe cuti on star ts.
When the CPU starts from reset, t here is as an add itional delay allowin g th e powe r to
reach a stable level before com mencing norm al operation. The Wat chdog Oscil lator is
used for timing this real-tim e part of the start-u p time. The numb er of WDT Oscilla tor
cycles used for each time-o ut is shown in Table 3. The frequ ency of the Wa tchdog
Oscillator is voltage dependent as shown in “ATmega8 Typical Characteristics”. The
device is shipped with CKSEL = “0001” and SUT = “10” (1 MHz I nternal RC Oscillator,
slowly rising power) .
(1)
24
Table 3. Number of Watchdog Oscillator Cycles
Typical Tim e- ou t (VCC = 5.0V) Typical Ti me-out (VCC = 3.0V) Number of Cycles
4.1 ms 4.3 ms 4K (4,096)
65 ms 69 ms 64K (65,536)
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can
be configured for use as an On-chip Osc illator, as shown i n F igure 11. Either a quartz
crystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator output
will oscillate a full rail-to-rail swing on the output. This mode is suitable when operating
in a very noisy environ ment or when the outpu t from XTAL2 drive s a second clock
buffer. This mode has a wide frequency range. When CKOPT is unprogrammed, the
Oscillator has a smaller output swing. T his reduces power consumption conside rably.
This mode has a limited frequency range and it cannot be used to drive other clock
buffers.
For resonators, the maximum frequency is 8 MHz with CK OPT unpro grammed and
16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals
and resonators. The optimal value of the capacitors depends on the cryst al or resonator
in use, the amount of stray capacitance, an d the electromagn etic noise of the environment. Some initial gu ideline s for choosing capa citors for use with c rystals are g iven in
Table 4. For ceramic resonators, the capac itor values given by the manufacturer should
be used.
Figure 11. Crystal Oscillator Connections
C2
C1
XTAL2
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in
Table 4.
Table 4. Crystal Oscillator Operating Modes
Frequency
CKOPT CKSEL3..1
1 101
1 110 0.9 - 3.0 12 - 22
1 111 3.0 - 8.0 12 - 22
0 101, 110, 111 1.0 ≤ 12 - 22
Note: 1. This option should not be used with crystals, only with ceramic resonators.
(1)
Range(MHz)
0.4 - 0.9 –
Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)
2486M–AVR–12/03
The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown
in Table 5.
25
Table 5. Start-up Times for the Crystal Oscillator Clock Selection
Start-up Time
from Power-down
CKSEL0 SUT1..0
0 00 258 CK
0 01 258 CK
0 10 1K CK
0 11 1K CK
1 00 1K CK
1 01 16K CK –
1 10 16K CK 4.1 ms
1 11 16K CK 65 ms
Notes: 1. These options should only be used when not operating close to the maximum fre-
quency of the device, and only if frequency stability at start-up is not important for the
application. These options are not suitable for crystals.
2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating
close to the maximum frequency of the device, and if frequency stability at start-up is
not important for the application.
and Power-save
(1)
(1)
(2)
(2)
(2)
Addition al Delay
from Reset
(VCC = 5.0V) Recommended Us age
4.1 ms
65 ms
–
4.1 ms
65 ms
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Ceramic resonator , BOD
enabled
Ceramic resonator, fast
rising power
Ceramic resonator, slowly
rising power
Crystal Oscillator, BOD
enabled
Crystal Oscillator, fast
rising power
Crystal Oscillator, slowly
rising power
Low-frequency Crystal Oscillator
To use a 32.7 68 kHz w atch crystal as the clo ck source for the device , the Low-f requency Crystal Oscillator must be selected by setting the CKSEL Fuses to “1001”. The
crystal should be connected as shown in Figure 11. By programming the CKOPT Fuse,
the user can enable internal capacitors on XTAL1 and XTAL2, thereby removing the
need for external capacitors. The internal capacitors have a nominal value of 36 pF.
When this Oscilla tor is sele cted, sta rt-up times are determ ined by the SUT Fuse s as
shown in Table 6.
Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection
Start-up Time from
Power-down and
SUT1..0
00 1K CK
01 1K CK
10 32K CK 65 ms Stable frequency at start-up
11 Reserved
Note: 1. These options should o nly be u sed if frequency stability a t sta rt-up is not imp ortant fo r
Power-save
(1)
(1)
the application.
Additional Delay
from Reset
(VCC = 5.0V) Recommended Usage
4.1 ms Fast rising power or BOD enabled
65 ms Slowly rising power
26
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
External RC Oscillator For timing insensitive applications, the external RC configuration shown in Figure 12
can be used. The frequency is roughly estimated by the equation f = 1/(3RC). C should
be at least 22 pF. By programming the CKOPT Fuse, the user can enable an inter nal 36
pF capacitor bet ween XTAL1 a nd GND, thereby rem oving the need for an external
capacitor. For more information on Oscillator operation and details on how to choose R
and C, refer to the External RC Oscillator application note.
Figure 12. External RC Configuration
V
CC
R
NC
XTAL2
XTAL1
C
GND
The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..0 as shown in
Table 7.
Table 7. External RC Oscillator Operating Modes
CKSEL3..0 Frequency Range (MHz)
0101 ≤ 0.9
0110 0.9 - 3.0
0111 3.0 - 8.0
1000 8.0 - 12.0
When this Oscilla tor is sele cted, sta rt-up times are determ ined by the SUT Fuse s as
shown in Table 8.
2486M–AVR–12/03
Table 8. Start-up Times for the External RC Oscillator Clock Selection
Start-up Time from
Power-down and
SUT1..0
00 18 CK – BOD enabled
01 18 CK 4.1 ms Fast rising power
10 18 CK 65 ms Slowly rising power
11 6 CK
Note: 1. This option should not be used when operating close to the maximum frequency of
Power-save
(1)
the device.
Additional Delay
from Reset
= 5.0V) Recommended Usage
(V
CC
4.1 ms Fast rising power or BOD enabled
27
Calibrated Internal RC Oscillator
The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All
frequencies are nominal values at 5V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 9. If selected, it will
operate with no external components. The CKOPT Fuse should always be unprogrammed when using this clo ck optio n. Durin g reset, hardwa re loads t he cali brati on byte
into the OSCCAL Register and ther eby automat ically cal ibra tes the RC Osci llat or. At 5V,
25°C and 1.0 MHz O scillator frequen cy selected, thi s calibration gi ves a freq uency
within ± 3% of the nominal frequency. Using run-time calibration methods as described
in application notes availab le at www.atmel.com/avr it is possible to achieve ± 1% accuracy at any given V
and Temperature. When this Oscillator is used as the chip clock,
CC
the Watchdog Oscillator will still be used for the Watchdog T imer and for the Reset
Time-out. For more information on the pre-programmed ca libration value, see the section “Calibration Byte” on page 221.
Table 9. Internal Calibrated RC Oscillator Operati ng Mo des
CKSEL3..0 Nominal Frequency (MHz)
(1)
0001
0010 2.0
0011 4.0
0100 8.0
Note: 1. The device is shipped with this option selected.
1.0
When this Oscilla tor is sele cted, sta rt-up times are determ ined by the SUT Fuse s as
shown in Table 10. PB6 (XTAL1/TOS C1) and PB7(XT AL2/TOSC2) can be used a s
either general I/O pins or Timer Oscillator pins ..
Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
Start-up Time fro m
Power-down and
SUT1..0
00 6 CK – BOD enabled
01 6 CK 4.1 ms Fast rising power
(1)
10
11 Reserved
Note: 1. The device is shipped with this option selected.
Power-save
6 CK 65 ms Slowly rising power
Additional Del ay
from Reset
(V
= 5.0V) Recommended Usage
CC
28
ATmega8(L)
2486M–AVR–12/03
ATmega8(L)
Oscillator Calibrat ion Register – OSCCAL
Bit 7 6 5 4 3 2 1 0
CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Valu e Device Specific Calibration Value
• Bits 7..0 – CAL7..0: Oscillator Calibration Value
Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency. During Reset, the 1 MHz calibration value
which is located in the signa ture row H igh byte (add ress 0x00) is automatically loaded
into the OSCCAL Register. If th e inter nal RC is us ed at o ther frequen cie s, the cali bra tion
values must be loaded manually. This can be done by first reading the signature row by
a programmer, and then store the calibration values in the Flash or EEPROM. Then the
value can be read by software an d lo aded into the OSCCAL Regi ste r. When OSCCAL is
zero, the lowest available frequency is chosen. Writing non-zero va lues to this register
will increase the frequency of the Internal O scillator. Wr iting 0xFF to the register gi ves
the highest available frequency. The calibrated Oscillator is used to time EEPROM and
Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above
the nominal fre quency. Otherw ise, the EEP ROM or F lash write m ay fai l. No te that the
Oscillator is intend ed fo r cali bration t o 1. 0, 2.0, 4.0, or 8. 0 MHz. Tuning to other values is
not guaranteed, as indicated i n Table 11.
Table 11. Internal RC Oscillator Frequency Range
OSCCAL Value
Min Frequency in Percentage of
Nominal Frequency (%)
Max Frequency in P er cent ag e o f
Nominal Freque ncy (%)
0x00 50 100
0x7F 75 150
0xFF 100 200
2486M–AVR–12/03
29
External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in
Figure 13. To run the de vice on an exte rnal clock, the CK SEL Fuses must be programmed to “0000”. By programming the CKOPT Fuse, the user can enable an internal
36 pF capacitor between XTAL1 and GND.
Figure 13. External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
When this clock source is selected, start-up times are determined by the SUT Fuses as
shown in Table 12.
Table 12. Start-up Times for the External Clock Selection
Start-up Time fro m
Power-down and
SUT1..0
00 6 CK – BOD enabled
01 6 CK 4.1 ms Fast rising power
10 6 CK 65 ms Slowly rising power
11 Reserved
Power-save
Additional Del ay
from Reset
(VCC = 5.0V) Recommended Usage
When applying an external clock, it is required to avoid sudden changes in the applied
clock frequency to ensure stable operation of the MCU. A vari ation in frequency of more
than 2% from one clock cycle to the next can lead to unpredictable behavior. It is
required to ensu re that th e MCU is kept in Reset during such changes in the clock
frequency.
Timer/Counter Oscillator For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), the
crystal is connected directly betwe en the p ins. B y pro gramming the CK OPT Fuse, the
user can enable internal capacito rs on XTAL1 and XTAL 2, thereby rem oving the need
for external capacit ors. The Osci llat or is opt imized f or use wit h a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended.
30
ATmega8(L)
2486M–AVR–12/03
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