ATMEL ATmega8, ATmega8L User Manual

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory segments

– 8K Bytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1K Byte Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package

Eight Channels 10-bit Accuracy

– 6-channel ADC in PDIP package

Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF

• Operating Voltages

– 2.7 - 5.5V (ATmega8L)
– 4.5 - 5.5V (ATmega8)

• Speed Grades

– 0 - 8 MHz (ATmega8L)
– 0 - 16 MHz (ATmega8)

• Power Consumption at 4 Mhz, 3V, 25°C

– Active: 3.6 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 0.5 µA

®

8-bit Microcontroller

(1)

8-bit
with 8K Bytes
In-System
Programmable
Flash

ATmega8
ATmega8L

Pin Configurations

(RESET) PC6

(XCK/T0) PD4

(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(INT1) PD3

(XCK/T0) PD4

GND
VCC
GND

VCC
(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

(RXD) PD0
(TXD) PD1
(INT0) PD2
(INT1) PD3

VCC
GND

(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP1) PB0

TQFP Top View

1
2
3
4
5
6
7
8

PDIP

1
2
3
4
5
6
7
8
9
10
11
12
13
14

PD2 (INT0)

PD1 (TXD)

32313029282726

9101112131415

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

28
27
26
25
24
23
22
21
20
19
18
17
16
15

PC4 (ADC4/SDA)

PC5 (ADC5/SCL)
PC4 (ADC4/SDA)
PC3 (ADC3)
PC2 (ADC2)
PC1 (ADC1)
PC0 (ADC0)
GND
AREF
AVCC
PB5 (SCK)
PB4 (MISO)
PB3 (MOSI/OC2)
PB2 (SS/OC1B)
PB1 (OC1A)

PC3 (ADC3)

PC2 (ADC2)

25

24

PC1 (ADC1)

23

PC0 (ADC0)

22

ADC7

21

GND

20

AREF

19

ADC6

18

AVCC

17

PB5 (SCK)

16

(T1) PD5

(ICP1) PB0

(AIN0) PD6

(AIN1) PD7

(MISO) PB4

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

MLF Top View

PD2 (INT0)

PD1 (TXD)

PD0 (RXD)

PC6 (RESET)

PC5 (ADC5/SCL)

PC4 (ADC4/SDA)

PC3 (ADC3)

PC2 (ADC2)

32313029282726

(INT1) PD3

(XCK/T0) PD4

(XTAL1/TOSC1) PB6
(XTAL2/TOSC2) PB7

2

ATmega8(L)

GND
VCC
GND
VCC

1
2
3
4
5
6
7
8

9101112131415

(T1) PD5

(AIN0) PD6

(ICP1) PB0

(AIN1) PD7

25

16

(MISO) PB4

(OC1A) PB1

(SS/OC1B) PB2

(MOSI/OC2) PB3

PC1 (ADC1)

24

PC0 (ADC0)

23

ADC7

22

GND

21

AREF

20

ADC6

19

AVCC

18

PB5 (SCK)

17

NOTE:
The large center pad underneath the MLF
packages is made of metal and internally
connected to GND. It should be soldered
or glued to the PCB to ensure good
mechanical stability. If the center pad is
left unconneted, the package might
loosen from the PCB.

2486S–AVR–08/07

ATmega8(L)

Overview The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture.

By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs
approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption ver­sus processing speed.

Block Diagram Figure 1. Block Diagram

XTAL1

RESET

VCC

PC0 - PC6 PB0 - PB7

XTAL2

GND

AGND

AREF

PORTC DRIVERS/BUFFERS

PORTC DIGITAL INTERFACE

MUX &

ADC

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

ADC

INTERFACE

STACK

POINTER

SRAM

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PORTB DRIVERS/BUFFERS

PORTB DIGITAL INTERFACE

TWI

TIMERS/

COUNTERS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

EEPROM

OSCILLATOR

OSCILLATOR

2486S–AVR–08/07

PROGRAMMING

LOGIC

+

-

SPI

COMP.

INTERFACE

USART

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7

3

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega8 provides the following features: 8K bytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes of EEPROM, 1K byte of SRAM, 23 general purpose
I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte oriented Two­wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with
10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power­down mode saves the register contents but freezes the Oscillator, disabling all other chip func­tions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleep­ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution
to many embedded control applications.

The ATmega8 AVR is supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.

Disclaimer Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.

4

ATmega8(L)

2486S–AVR–08/07

Pin Descriptions

VCC Digital supply voltage.

GND Ground.

ATmega8(L)

Port B (PB7..PB0) XTAL1/XTAL2/TOSC1/ TOSC2

Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC6/RESET

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil­lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1
input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in “Alternate Functions of Port B” on page

58 and “System Clock and Clock Options” on page 25.

Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char­acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 15 on page 38. Shorter pulses are not guaranteed to
generate a Reset.

The various special features of Port C are elaborated on page 61.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega8 as listed on page

63.

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page

38. Shorter pulses are not guaranteed to generate a reset.

2486S–AVR–08/07

5

AV

CC

AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). It should be
externally connected to V
nected to V

through a low-pass filter. Note that Port C (5..4) use digital supply voltage, VCC.

CC

, even if the ADC is not used. If the ADC is used, it should be con-

CC

AREF AREF is the analog reference pin for the A/D Converter.

ADC7..6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the A/D converter.
These pins are powered from the analog supply and serve as 10-bit ADC channels.

6

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

Resources A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note: 1.

Data Retention Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

2486S–AVR–08/07

7

About Code Examples

This datasheet contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compi­lation. Be aware that not all C compiler vendors include bit definitions in the header files and
interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation
for more details.

8

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

AVR CPU Core

Introduction This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.

Architectural Overview

Figure 2. Block Diagram of the AVR MCU Architecture

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Indirect Addressing

Data Bus 8-bit

Status

and Control

32 x 8

General

Purpose

Registrers

ALU

Data

SRAM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

i/O Module1

i/O Module 2

2486S–AVR–08/07

i/O Module n

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc­tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ­ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers

9

can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic opera­tion, the Status Register is updated to reflect information about the result of the operation.

The Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word for­mat. Every Program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot program section and the
Application program section. Both sections have dedicated Lock Bits for write and read/write
protection. The SPM instruction that writes into the Application Flash memory section must
reside in the Boot program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack
Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global
interrupt enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi­tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis­ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.

10

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

Arithmetic Logic
Unit – ALU

The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.

Status Register The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 76543210

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter­rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the Instruction Set Reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti­nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.

⊕ V

2486S–AVR–08/07

11

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a Carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:

• One 8-bit output operand and one 8-bit result input.

• Two 8-bit output operands and one 8-bit result input.

• Two 8-bit output operands and one 16-bit result input.

• One 16-bit output operand and one 16-bit result input.

Figure 3 shows the structure of the 32 general purpose working registers in the CPU.

Figure 3. AVR CPU General Purpose Working Registers

7 0 Addr.

R0 0x00
R1 0x01
R2 0x02

…

R13 0x0D

General R14 0x0E
Purpose R15 0x0F
Working R16 0x10

Registers R17 0x11

…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte

12

Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.

As shown in Figure 3, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple­mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

The X-register, Y­register and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg­isters are 16-bit address pointers for indirect addressing of the Data Space. The three indirect
address registers X, Y and Z are defined as described in Figure 4.

Figure 4. The X-, Y- and Z-Registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the Instruction Set Reference for details).

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca­tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.

Instruction Execution Timing

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when address is
popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa­tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

00000000

This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk

, directly generated from the selected clock source for the

CPU

chip. No internal clock division is used.

2486S–AVR–08/07

13

Figure 5 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.

Figure 5. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina­tion register.

Figure 6. Single Cycle ALU Operation

Reset and Interrupt Handling

T1 T2 T3 T4

clk

CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate Program Vector in the Program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock Bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 222 for details.

The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” on page 46. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the boot Flash section by setting the Inter­rupt Vector Select (IVSEL) bit in the General Interrupt Control Register (GICR). Refer to

“Interrupts” on page 46 for more information. The Reset Vector can also be moved to the start of

the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-

While-Write Self-Programming” on page 209.

14

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis­abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec­tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the global interrupt
enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
global interrupt enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

2486S–AVR–08/07

15

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe­cuted before any pending interrupts, as shown in the following example.

Assembly Code Example

sei ; set global interrupt enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini­mum. After four clock cycles, the Program Vector address for the actual interrupt handling
routine is executed. During this 4-clock cycle period, the Program Counter is pushed onto the
Stack. The Vector is normally a jump to the interrupt routine, and this jump takes three clock
cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is com­pleted before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the
interrupt execution response time is increased by four clock cycles. This increase comes in addi­tion to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incre­mented by 2, and the I-bit in SREG is set.

16

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

AVR ATmega8 Memories

In-System Reprogrammable Flash Program Memory

This section describes the different memories in the ATmega8. The AVR architecture has two
main memory spaces, the Data memory and the Program Memory space. In addition, the
ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.

The ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memory for pro­gram storage. Since all AVR instructions are 16- or 32-bits wide, the Flash is organized as 4K x
16 bits. For software security, the Flash Program memory space is divided into two sections,
Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega8 Pro­gram Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The
operation of Boot Program section and associated Boot Lock Bits for software protection are
described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page

209. “Memory Programming” on page 222 contains a detailed description on Flash Program-

ming in SPI- or Parallel Programming mode.

Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 13.

Figure 7. Program Memory Map

Application Flash Section

Boot Flash Section

$000

$FFF

2486S–AVR–08/07

17

SRAM Data Memory

Figure 8 shows how the ATmega8 SRAM Memory is organized.

The lower 1120 Data memory locations address the Register File, the I/O Memory, and the inter­nal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next
1024 locations address the internal data SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace­ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre­ment, the address registers X, Y and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data
SRAM in the ATmega8 are all accessible through all these addressing modes. The Register File
is described in “General Purpose Register File” on page 12.

Figure 8. Data Memory Map

Register File

Data Address Space

R0
R1
R2

...

R29
R30
R31

I/O Registers

$00
$01
$02

...

$3D
$3E
$3F

$0000
$0001
$0002

...

$001D
$001E

$001F

$0020
$0021
$0022

...

$005D
$005E
$005F

Internal SRAM

$0060
$0061

...

$045E
$045F

18

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

Data Memory Access Times

EEPROM Data Memory

This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk

cycles as described in Figure 9.

CPU

Figure 9. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Data

WR

Data

RD

Compute Address

Memory Vccess Instruction

Address Valid

Write

Read

Next Instruction

The ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
bellow, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.

EEPROM Read/Write Access

“Memory Programming” on page 222 contains a detailed description on EEPROM Programming

in SPI- or Parallel Programming mode.

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1 on page 21. A self-timing function,
however, lets the user software detect when the next byte can be written. If the user code con­tains instructions that write the EEPROM, some precautions must be taken. In heavily filtered
power supplies, V

is likely to rise or fall slowly on Power-up/down. This causes the device for

CC

some period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See “Preventing EEPROM Corruption” on page 23. for details on how to avoid problems in
these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.

2486S–AVR–08/07

19

The EEPROM Address
Register – EEARH and
EEARL

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/WriteRRRRRRRR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

XXXXXXXX

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bits in the ATmega8 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.

The EEPROM Data
Register – EEDR

The EEPROM Control
Register – EECR

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000

• Bits 7..0 – EEDR7..0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 X 0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATmega8 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter­rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

20

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.
When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at
the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has
been written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEWE bit must be written to one to write the value into the
EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

erwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write.
Step 2 is only relevant if the software contains a boot loader allowing the CPU to program the
Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-Programming” on page 209 for details about boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft­ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,
the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typical pro­gramming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

Number of Calibrated RC

Symbol

EEPROM Write (from CPU) 8448 8.5 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

Oscillator Cycles

(1)

Typ Programming Time

2486S–AVR–08/07

21

The following code examples show one assembly and one C function for writing to the
EEPROM. The examples assume that interrupts are controlled (for example by disabling inter­rupts globally) so that no interrupts will occur during execution of these functions. The examples
also assume that no Flash boot loader is present in the software. If such code is present, the
EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

22

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

The next code examples show assembly and C functions for reading the EEPROM. The exam­ples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

EEPROM Write during Power-down Sleep Mode

Preventing EEPROM Corruption

2486S–AVR–08/07

When entering Power-down sleep mode while an EEPROM write operation is active, the
EEPROM write operation will continue, and will complete before the Write Access time has
passed. However, when the write operation is completed, the Oscillator continues running, and
as a consequence, the device does not enter Power-down entirely. It is therefore recommended
to verify that the EEPROM write operation is completed before entering Power-down.

During periods of low V

the EEPROM data can be corrupted because the supply voltage is

CC,

too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec­ond, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This
can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the
internal BOD does not match the needed detection level, an external low V

Reset Protec-

CC

23

tion circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.

I/O Memory The I/O space definition of the ATmega8 is shown in “” on page 287.

All ATmega8 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed
by the IN and OUT instructions, transferring data between the 32 general purpose working regis­ters and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit­accessible using the SBI and CBI instructions. In these registers, the value of single bits can be
checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more
details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F
must be used. When addressing I/O Registers as data space using LD and ST instructions,
0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will operate on all bits in the I/O Register, writing a one back into any flag read as
set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

24

ATmega8(L)

2486S–AVR–08/07

System Clock and Clock Options

ATmega8(L)

Clock Systems and their Distribution

Figure 10 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 33. The clock systems are detailed Figure 10.

Figure 10. Clock Distribution

Asynchronous
Timer/Counter

General I/O

Modules

clk

clk

ASY

ADC CPU Core RAM

clk

ADC

I/O

AVR Clock

Control Unit

Source Clock

Clock

Multiplexer

clk

CPU

clk

FLASH

Reset Logic

Watchdog Timer

Watchdog Clock

Watchdog

Oscillator

Flash and
EEPROM

CPU Clock – clk

I/O Clock – clk

I/O

Flash Clock – clk

2486S–AVR–08/07

CPU

FLASH

Timer/Counter

Oscillator

External RC

Oscillator

External Clock

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

Calibrated RC

Oscillator

The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter­rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that address recognition in the TWI module is carried out asynchro­nously when clk

is halted, enabling TWI address reception in all sleep modes.

I/O

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul­taneously with the CPU clock.

25

Asynchronous Timer
Clock – clk

ASY

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly
from an external 32 kHz clock crystal. The dedicated clock domain allows using this
Timer/Counter as a real-time counter even when the device is in sleep mode. The Asynchronous
Timer/Counter uses the same XTAL pins as the CPU main clock but requires a CPU main clock
frequency of more than four times the Oscillator frequency. Thus, asynchronous operation is
only available while the chip is clocked on the Internal Oscillator.

ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.

Clock Sources The device has the following clock source options, selectable by Flash Fuse Bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.

Table 2. Device Clocking Options Select

Device Clocking Option CKSEL3..0

External Crystal/Ceramic Resonator 1111 - 1010

External Low-frequency Crystal 1001

External RC Oscillator 1000 - 0101

Calibrated Internal RC Oscillator 0100 - 0001

External Clock 0000

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the start­up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts
from reset, there is as an additional delay allowing the power to reach a stable level before com­mencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the
start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3.
The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8 Typical
Characteristics”. The device is shipped with CKSEL = “0001” and SUT = “10” (1 MHz Internal
RC Oscillator, slowly rising power).

(1)

26

Table 3. Number of Watchdog Oscillator Cycles

Typical Time-out (VCC = 5.0V) Typical Time-out (VCC = 3.0V) Number of Cycles

4.1 ms 4.3 ms 4K (4,096)

65 ms 69 ms 64K (65,536)

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 11. Either a quartz crystal or a
ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator
amplifier modes. When CKOPT is programmed, the Oscillator output will oscillate a full rail-to­rail swing on the output. This mode is suitable when operating in a very noisy environment or
when the output from XTAL2 drives a second clock buffer. This mode has a wide frequency
range. When CKOPT is unprogrammed, the Oscillator has a smaller output swing. This reduces
power consumption considerably. This mode has a limited frequency range and it cannot be
used to drive other clock buffers.

For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and 16 MHz with
CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The
optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray
capacitance, and the electromagnetic noise of the environment. Some initial guidelines for
choosing capacitors for use with crystals are given in Table 4. For ceramic resonators, the
capacitor values given by the manufacturer should be used.

Figure 11. Crystal Oscillator Connections

C2

C1

XTAL2

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4.

Table 4. Crystal Oscillator Operating Modes

Frequency

CKOPT CKSEL3..1

1 101

1 110 0.9 - 3.0 12 - 22

1 111 3.0 - 8.0 12 - 22

0 101, 110, 111 1.0 ≤ 12 - 22

Note: 1. This option should not be used with crystals, only with ceramic resonators.

(1)

Range(MHz)

0.4 - 0.9 –

Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

5.

2486S–AVR–08/07

27

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time

from Power-down

CKSEL0 SUT1..0

0 00 258 CK

0 01 258 CK

010 1K CK

011 1K CK

100 1K CK

101 16K CK –

1 10 16K CK 4.1 ms

1 11 16K CK 65 ms

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These
options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability
at start-up. They can also be used with crystals when not operating close to the maximum fre­quency of the device, and if frequency stability at start-up is not important for the application.

and Power-save

(1)

(1)

(2)

(2)

(2)

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

4.1 ms

65 ms

–

4.1 ms

65 ms

Ceramic resonator, fast
rising power

Ceramic resonator, slowly
rising power

Ceramic resonator, BOD
enabled

Ceramic resonator, fast
rising power

Ceramic resonator, slowly
rising power

Crystal Oscillator, BOD
enabled

Crystal Oscillator, fast
rising power

Crystal Oscillator, slowly
rising power

Low-frequency Crystal Oscillator

External RC Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the Low-frequency Crystal
Oscillator must be selected by setting the CKSEL Fuses to “1001”. The crystal should be con­nected as shown in Figure 11. By programming the CKOPT Fuse, the user can enable internal
capacitors on XTAL1 and XTAL2, thereby removing the need for external capacitors. The inter­nal capacitors have a nominal value of 36 pF.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6.

Table 6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

SUT1..0

00 1K CK

01 1K CK

10 32K CK 65 ms Stable frequency at start-up

11 Reserved

Note: 1. These options should only be used if frequency stability at start-up is not important for the

Power-save

(1)

(1)

application.

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

4.1 ms Fast rising power or BOD enabled

65 ms Slowly rising power

For timing insensitive applications, the external RC configuration shown in Figure 12 can be
used. The frequency is roughly estimated by the equation f = 1/(3RC). C should be at least 22

28

ATmega8(L)

2486S–AVR–08/07

ATmega8(L)

pF. By programming the CKOPT Fuse, the user can enable an internal 36 pF capacitor between
XTAL1 and GND, thereby removing the need for an external capacitor.

Figure 12. External RC Configuration

CC

V

R

NC

XTAL2

XTAL1

C

GND

The Oscillator can operate in four different modes, each optimized for a specific frequency
range. The operating mode is selected by the fuses CKSEL3..0 as shown in Table 7.

Table 7. External RC Oscillator Operating Modes

CKSEL3..0 Frequency Range (MHz)

0101 0.1 - 0.9

0110 0.9 - 3.0

0111 3.0 - 8.0

1000 8.0 - 12.0

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8.

Table 8. Start-up Times for the External RC Oscillator Clock Selection

2486S–AVR–08/07

Start-up Time from

Power-down and

SUT1..0

00 18 CK – BOD enabled

01 18 CK 4.1 ms Fast rising power

10 18 CK 65 ms Slowly rising power

11 6 CK

Note: 1. This option should not be used when operating close to the maximum frequency of the device.

Power-save

(1)

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

4.1 ms Fast rising power or BOD enabled

29

Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator provides a fixed 1.0, 2.0, 4.0, or 8.0 MHz clock. All frequen­cies are nominal values at 5V and 25°C. This clock may be selected as the system clock by
programming the CKSEL Fuses as shown in Table 9. If selected, it will operate with no external
components. The CKOPT Fuse should always be unprogrammed when using this clock option.
During reset, hardware loads the 1 MHz calibration byte into the OSCCAL Register and thereby
automatically calibrates the RC Oscillator. At 5V, 25°C and 1.0 MHz Oscillator frequency
selected, this calibration gives a frequency within ± 3% of the nominal frequency. Using run-time
calibration methods as described in application notes available at www.atmel.com/avr it is possi­ble to achieve ± 1% accuracy at any given V

and Temperature. When this Oscillator is used

CC

as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the
Reset Time-out. For more information on the pre-programmed calibration value, see the section

“Calibration Byte” on page 225.

Table 9. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0 Nominal Frequency (MHz)

(1)

0001

0010 2.0

0011 4.0

0100 8.0

Note: 1. The device is shipped with this option selected.

1.0

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 10. PB6 (XTAL1/TOSC1) and PB7(XTAL2/TOSC2) can be used as either general I/O pins

or Timer Oscillator pins..

Table 10. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

Start-up Time from

Power-down and

SUT1..0

00 6 CK – BOD enabled

01 6 CK 4.1 ms Fast rising power

(1)

10

11 Reserved

Note: 1. The device is shipped with this option selected.

Power-save

6 CK 65 ms Slowly rising power

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

30

ATmega8(L)

2486S–AVR–08/07