BDTIC www.bdtic.com/ATMEL
Features
• High-performance, Low-power AVR
• Advanced RISC Architecture
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 64K Bytes of In-System Reprogrammable Flash program memory
– 2K Bytes EEPROM
– 4K Bytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 1 to 16 Bits
– 8-channel, 10-bit ADC
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain (1x, 10x, 200x)
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby
and Extended Standby
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
• I/O and Packages
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V for ATmega64L
– 4.5 - 5.5V for ATmega64
• Speed Grades
– 0 - 8 MHz for ATmega64L
– 0 - 16 MHz for ATmega64
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 64K Bytes
In-System
Programmable
Flash
ATmega64
ATmega64L
Summary
Pin
Figure 1. Pinout ATmega64
Configuration
PEN
RXD0/(PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/INT7) PE7
(SS) PB0
(SCK) PB1
(MOSI) PB2
(MISO) PB3
(OC0) PB4
(OC1A) PB5
(OC1B) PB6
TQFP/MLF
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
646362616059585756555453525150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
171819202122232425262728293031
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2(ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10
PC1 (A9)
PC0 (A8)
PG1(RD)
PG0(WR)
VCC
GND
XTAL2
RESET
TOSC2/PG3
TOSC1/PG4
(OC2/OC1C) PB7
Note: The bottom pad under the QFN/MLF package should be soldered to ground.
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(T1) PD6
(ICP1) PD4
(TXD1/INT3) PD3
(T2) PD7
(XCK1) PD5
Disclaimer Typical values contained in this data sheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
Overview
The ATmega64 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing
powerful instructions in a single clock cycle, the ATmega64 achieves throughputs approaching 1 MIPS per MHz, allowing
the system designer to optimize power consumption versus processing speed.
Block Diagram
Figure 2. Block Diagram
VCC
GND
AVC C
PORTF DRIVERS
DATAREGISTER
PORTF
DATADIR.
REG. PORTF
DATAREGISTER
PORTA
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATADIR.
REG. PORTA
DATAREGISTER
PORTC DRIVERS
PORTC
PC0 - PC7
DATADIR.
REG. PORTC
8-BIT DATA BUS
AREF
PEN
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
DATAREGISTER
+
-
ANALOG
COMPARATOR
USART0
PORTE
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
REG. PORTE
PORTE DRIVERS
DATADIR.
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
DATAREGISTER
PORTB
REG. PORTB
PORTB DRIVERS
INTERNAL
OSCILLATOR
WATCHDOG
MCU CONTROL
REGISTER
COUNTERS
INTERRUPT
EEPROM
DATADIR.
TIMER
TIMER/
UNIT
SPI
CALIB. OSC
OSCILLATOR
OSCILLATOR
TIMING AND
CONTROL
USART1
DATAREGISTER
PORTD
PORTD DRIVERS
2-WIRE SERIAL
INTERFACE
DATADIR.
REG. PORTD
DATAREG.
PORTG
PORTG DRIVERS
DATADIR.
REG. PORTG
XTAL1
XTAL2
RESET
PB0 - PB7PE0 - PE7
PD0 - PD7
PG0 - PG4
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
2490NS–AVR–05/08
3
The ATmega64 provides the following features: 64K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible
Timer/Counters with compare modes and PWM, two USARTs, a byte oriented Two-wire Serial
Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable
gain, programmable Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std.
1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and
programming, and six software selectable power saving modes. The Idle mode stops the CPU
while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all
other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the
device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby
mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode,
both the main Oscillator and the asynchronous timer continue to run.
The device is manufactured using Atmel’s high-density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot Program can use any interface to download the
Application Program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega64 is a powerful microcontroller that provides a highly-flexible
and cost-effective solution to many embedded control applications.
ATmega103 and ATmega64 Compatibility
The ATmega64 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, In-Circuit Emulators,
and evaluation kits.
The ATmega64 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility
with the ATmega103, all I/O locations present in ATmega103 have the same location in
ATmega64. Most additional I/O locations are added in an Extended I/O space starting from 0x60
to 0xFF (i.e., in the ATmega103 internal RAM space). These location can be reached by using
LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the
increased number of Interrupt Vectors might be a problem if the code uses absolute addresses.
To solve these problems, an ATmega103 compatibility mode can be selected by programming
the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the
internal RAM is located as in ATmega103. Also, the extended Interrupt Vectors are removed.
The ATmega64 is 100% pin compatible with ATmega103, and can replace the ATmega103 on
current printed circuit boards. The application notes “Replacing ATmega103 by ATmega128”
and “Migration between ATmega64 and ATmega128” describes what the user should be aware
of replacing the ATmega103 by an ATmega128 or ATmega64.
4
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
ATmega103 Compatibility Mode
By programming the M103C Fuse, the ATmega64 will be compatible with the ATmega103
regards to RAM, I/O pins and Interrupt Vectors as described above. However, some new features in ATmega64 are not available in this compatibility mode, these features are listed below:
• One USART instead of two, asynchronous mode only. Only the eight least significant bits of
the Baud Rate Register is available.
• One 16 bits Timer/Counter with two compare registers instead of two 16 bits Timer/Counters
with three compare registers.
• Two-wire serial interface is not supported.
• Port G serves alternate functions only (not a general I/O port).
• Port F serves as digital input only in addition to analog input to the ADC.
• Boot Loader capabilities is not supported.
• It is not possible to adjust the frequency of the internal calibrated RC Oscillator.
• The External Memory Interface can not release any Address pins for general I/O, neither
configure different wait states to different External Memory Address sections.
• Only EXTRF and PORF exist in the MCUCSR Register.
• No timed sequence is required for Watchdog Timeout change.
• Only low-level external interrupts can be used on four of the eight External Interrupt sources.
• Port C is output only.
• USART has no FIFO buffer, so Data OverRun comes earlier.
• The user must have set unused I/O bits to 0 in ATmega103 programs.
Pin Descriptions
VCC Digital supply voltage.
GND Ground.
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega64 as listed on page
73.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega64 as listed on page
74.
2490NS–AVR–05/08
5
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega64 as listed on page 77. In
ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated
when a reset condition becomes active.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega64 as listed on page
78.
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega64 as listed on page
81.
Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will
be activated even if a reset occurs.
The TDO pin is tri-stated unless TAP states that shift out data are entered.
Port F also serves the functions of the JTAG interface.
In ATmega103 compatibility mode, Port F is an input port only.
Port G (PG4..PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features.
In ATmega103 compatibility mode, these pins only serves as strobes signals to the external
memory as well as input to the 32 kHz Oscillator, and the pins are initialized to PG0 = 1,
PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock
is not running. PG3 and PG4 are Oscillator pins.
6
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page
52. Shorter pulses are not guaranteed to generate a reset.
XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting Oscillator amplifier.
AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to V
through a low-pass filter.
AREF AREF is the analog reference pin for the A/D Converter.
PEN This is a programming enable pin for the SPI Serial Programming mode. By holding this pin low
during a Power-on Reset, the device will enter the SPI Serial Programming mode. PEN
function during normal operation.
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
CC
has no
2490NS–AVR–05/08
7
Resources A comprehensive set of development tools, application notes and datasheetsare available for
download on http://www.atmel.com/avr.
Note: 1.
Data Retention Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
8
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) Reserved – – – – – – – –
.. Reserved – – – – – – – –
(0x9E)
(0x9D) UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 191
(0x9C) UDR1 USART1 I/O Data Register 188
(0x9B) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 189
(0x9A) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 190
(0x99) UBRR1L USART1 Baud Rate Register Low 193
(0x98) UBRR1H – – – – USART1 Baud Rate Register High 193
(0x97)
(0x96)
(0x95) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 191
(0x94)
(0x93)
(0x92)
(0x91)
(0x90) UBRR0H – – – – USART0 Baud Rate Register High 193
(0x8F)
(0x8E)
(0x8D) Reserved – – – – – – – –
(0x8C) TCCR3C FOC3A FOC3B FOC3C – – – – – 138
(0x8B) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 132
(0x8A) TCCR3B ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 136
(0x89) TCNT3H Timer/Counter3 – Counter Register High Byte 138
(0x88) TCNT3L Timer/Counter3 – Counter Register Low Byte 13 8
(0x87) OCR3AH Timer/Counter3 – Output Compare Register A High Byte 139
(0x86) OCR3AL Timer/Counter3 – Output Compare Register A Low Byte 139
(0x85) OCR3BH Timer/Counter3 – Output Compare Register B High Byte 139
(0x84) OCR3BL Timer/Counter3 – Output Compare Register B Low Byte 139
(0x83) OCR3CH Timer/Counter3 – Output Compare Register C High Byte 139
(0x82) OCR3CL Timer/Counter3 – Output Compare Register C Low Byte 139
(0x81) ICR3H Timer/Counter3 – Input Capture Register High Byte 140
(0x80) ICR3L Timer/Counter3 – Input Capture Register Low Byte 140
(0x7F)
(0x7E)
(0x7D) ETIMSK – – TICIE3 OCIE3A OCIE3B TOIE3 OCIE3C OCIE1C 141
(0x7C) ETIFR – – ICF3 OCF3A OCF3B TOV3 OCF3C OCF1C 142
(0x7B)
(0x7A)
(0x79) OCR1CH Timer/Counter1 – Output Compare Register C High Byte 139
(0x78) OCR1CL Timer/Counter1 – Output Compare Register C Low Byte 139
(0x77)
(0x76)
(0x75)
(0x74) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN
(0x73) TWDR Two-wire Serial Interface Data Register 208
(0x72) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 208
(0x71) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 207
(0x70) TWBR Two-wire Serial Interface Bit Rate Register 206
(0x6F) OSCCAL Oscillator Calibration Register 43
(0x6E)
(0x6D)
(0x6C)
(0x6B)
(0x6A) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 90
(0x69)
(0x68)
(0x67)
(0x66)
(0x65)
(0x64)
(0x63)
(0x62) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 88
(0x61) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89
Reserved – – – – – – – –
Reserved – – – – – – – –
Reserved – – – – – – – –
Reserved – – – – – – – –
Reserved – – – – – – – –
Reserved
Reserved
Reserved
ADCSRB
Reserved – – – – – – – –
Reserved – – – – – – – –
Reserved – – – – – – – –
TCCR1C FOC1A FOC1B FOC1C – – – – – 137
Reserved
Reserved
Reserved – – – – – – – –
Reserved – – – – – – – –
XMCRA
XMCRB XMBK
Reserved – – – – – – – –
Reserved – – – – – – – –
SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 281
Reserved
Reserved – – – – – – – –
PORTG
DDRG
PING – – – PING4 PING3 PING2 PING1 P ING0 89
– – – – – – – –
– – – – – – – –
– – – – – – – –
– – – – – ADTS2 ADTS1 ADTS0 247
– – – – – – – –
– – – – – – – –
– TWIE 206
– SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 32
– – – – XMM2 XMM1 XMM0 34
– – – – – – – –
– – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89
– – – DDG4 DDG3 DDG2 DDG1 DDG0 89
2490NS–AVR–05/08
9
Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x60) Reserved – – – – – – – –
0x3F (0x5F) SREG I T H S V N Z C 12
0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 14
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 14
0x3C (0x5C) XDIV XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 39
0x3B (0x5B) Reserved – – – – – – – –
0x3A (0x5A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 91
0x39 (0x59) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 92
0x38 (0x58) EIFR INTF7 INTF6 INTF5 INTF4 INTF3 INTF INTF1 INTF0 92
0x37 (0x57) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 109, 140, 160
0x36 (0x56) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 109, 142, 160
0x35 (0x55) MCUCR SRE SRW10 SE SM1 SM0 SM2 IVSEL IVCE 32, 46, 64
0x34 (0x54) MCUCSR JTD – – JTRF WDRF BORF EXTRF PORF 55, 256
0x33 (0x53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 104
0x32 (0x52) TCNT0 Timer/Counter0 (8 Bit) 106
0x31 (0x51) OCR0 Timer/Counter0 Output Compare Register 106
0x30 (0x50) ASSR
0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 132
0x2E (0x4E) TCCR1B ICNC1 ICES1
0x2D (0x4D) TCNT1H Timer/Counter1 – Counter Register High Byte 138
0x2C (0x4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 138
0x2B (0x4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 139
0x2A (0x4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 139
0x29 (0x49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 139
0x28 (0x48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 139
0x27 (0x47) ICR1H Timer/Counter1 – Input Capture Register High Byte 140
0x26 (0x46) ICR1L Timer/Counter1 – Input Capture Register Low Byte 140
0x25 (0x45) TCCR2 FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 157
0x24 (0x44) TCNT2 Timer/Counter2 (8 Bit) 159
0x23 (0x43) OCR2 Timer/Counter2 Output Compare Register 160
0x22 (0x42) OCDR
0x21 (0x41) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 57
0x20 (0x40) SFIOR TSM – – – ACME PUD PSR0 PSR321 72, 111, 145, 227
0x1F (0x3F) EEARH – – – – – EEPROM Address Register High Byte 22
0x1E (0x3E) EEARL EEPROM Address Register Low Byte 22
0x1D (0x3D) EEDR EEPROM Data Register 22
0x1C (0x3C) EECR – – – – EERIE EEMWE EEWE EERE 22
0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 87
0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 87
0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87
0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87
0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87
0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87
0x15 (0x35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 87
0x14 (0x34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 87
0x13 (0x33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88
0x12 (0x32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88
0x11 (0x31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88
0x10 (0x30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88
0x0F (0x2F) SPDR SPI Data Register 169
0x0E (0x2E) SPSR SPIF WCOL – – – – – SPI2X 169
0x0D (0x2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 167
0x0C (0x2C) UDR0 USART0 I/O Data Register 188
0x0B (0x2B) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 189
0x0A (0x2A) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 190
0x09 (0x29) UBRR0L USART0 Baud Rate Register Low 193
0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 228
0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 243
0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 245
0x05 (0x25) ADCH ADC Data Register High Byte 246
0x04 (0x24) ADCL ADC Data Register Low byte 246
0x03 (0x23) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 88
0x02 (0x22) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88
0x01 (0x21) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 88
– – – – AS0 TCN0UB OCR0UB TCR0UB 107
– WGM13 WGM12 CS12 CS11 CS10 136
IDRD/
OCDR7
OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 253
10
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x00 (0x20) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
2490NS–AVR–05/08
11
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rd l,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N ,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsi gned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ¨ (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ¨ (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multip ly Signed with Unsigned R1:R0 ¨ (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
JMP k Direct Jump PC ← kNone3
RCALL k Relative Subrou tine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← ZNone3
CALL k Direct Subroutine Call PC ← kNone4
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Co mpare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) the n PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
12
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
Instruction Set Summary (Continued)
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word
LDI Rd, K Load Immediate Rd ← KNone1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1 :R0 None IN Rd, P In Port Rd ← PNone1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3.. 0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← TNone1
SEC Set Carry C ← 1C1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1N1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1Z1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1I1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1S1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1V1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1T1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1H1
Rd+1:Rd ← Rr+1:Rr
None 1
2490NS–AVR–05/08
13
Instruction Set Summary (Continued)
CLH Clear Half Carry Flag in SREG H ← 0 H 1
MCU CONTROL INSTRUCTIONS
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
14
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
Ordering Information
Speed (MHz) Power Supply Ordering Code
8 2.7 - 5.5
16 4.5 - 5.5
Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
ATmega64L-8AU
ATmega64L-8MU
ATmega64-16AU
ATmega64-16MU
(2)
Package
64A
64M1
64A
64M1
(1)
Operation Range
Industrial
°C to 85°C)
(-40
Package Type
64A 64-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
64M1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
2490NS–AVR–05/08
15
Packaging Information
64A
PIN 1
B
PIN 1 IDENTIFIER
e
E1 E
D1
D
C
0°~7°
L
Notes:
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A1
A2 A
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
SYMBOL
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
NOM
MAX
NOTE
16
2325 Orchard Parkway
R
San Jose, CA 95131
ATmega64(L)
TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
10/5/2001
DRAWING NO.
64A
REV.
B
2490NS–AVR–05/08
64M1
D
Marked Pin# 1 ID
ATmega64(L)
E
SEATING PLANE
C
TOP VIEW
A1
A
K
L
D2
E2
K
b
e
BOTTOM VIEW
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
Note:
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Pin #1 Corner
1
2
3
Option A
Option B
Option C
Pin #1
Triangle
Pin #1
Chamfer
(C 0.30)
Pin #1
Notch
(0.20 R)
SIDE VIEW
SYMBOL
A 0.80 0.90 1.00
A1 – 0.02 0.05
b 0.18 0.25 0.30
D
D2 5.20 5.40 5.60
E
E2 5.20 5.40 5.60
e 0.50 BSC
L0.35 0.40 0.45
K 1.25 1.40 1.55
0.08
C
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
8.90 9.00 9.10
8.90 9.00 9.10
NOM
MAX
NOTE
2490NS–AVR–05/08
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
64M1
5/25/06
REV.
G
17
Errata The revision letter in this section refers to the revision of the ATmega64 device.
ATmega64, rev. A to C
• First Analog Comparator conversion may be delayed
• Interrupts may be lost when writing the timer registers in the asynchronous timer
• Stabilizing time needed when changing XDIV Register
• Stabilizing time needed when changing OSCCAL Register
• IDCODE masks data from TDI input
• Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request
1. First Analog Comparator conversion may be delayed
If the device is powered by a slow rising V
, the first Analog Comparator conversion will
CC
take longer than expected on some devices.
Problem Fix/Workaround
When the device has been powered or reset, disable then enable theAnalog Comparator
before the first conversion.
2. Interrupts may be lost when writing the timer registers in the asynchronous timer
If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.
Problem Fix/Workaround
Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF
before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2
3. Stabilizing time needed when changing XDIV Register
After increasing the source clock frequency more than 2% with settings in the XDIV register,
the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The NOP instruction will always be executed correctly also right after a frequency change.
Thus, the next 8 instructions after the change should be NOP instructions. To ensure this,
follow this procedure:
1.Clear the I bit in the SREG Register.
2.Set the new pre-scaling factor in XDIV register.
3.Execute 8 NOP instructions
4.Set the I bit in SREG
This will ensure that all subsequent instructions will execute correctly.
Assembly Code Example:
CLI ; clear global interrupt enable
OUT XDIV, temp ; set new prescale value
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
NOP ; no operation
SEI ; clear global interrupt enable
18
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
4. Stabilizing time needed when changing OSCCAL Register
After increasing the source clock frequency more than 2% with settings in the OSCCAL register, the device may execute some of the subsequent instructions incorrectly.
Problem Fix / Workaround
The behavior follows errata number 3., and the same Fix / Workaround is applicable on this
errata.
5. IDCODE masks data from TDI input
The JTAG instruction IDCODE is not working correctly. Data to succeeding devices are
replaced by all-ones during Update-DR.
Problem Fix / Workaround
– If ATmega64 is the only device in the scan chain, the problem is not visible.
– Select the Device ID Register of the ATmega64 by issuing the IDCODE instruction or
by entering the Test-Logic-Reset state of the TAP controller to read out the contents
of its Device ID Register and possibly data from succeeding devices of the scan
chain. Issue the BYPASS instruction to the ATmega64 while reading the Device ID
Registers of preceding devices of the boundary scan chain.
– If the Device IDs of all devices in the boundary scan chain must be captured
simultaneously, the ATmega64 must be the first device in the chain.
6. Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt
request.
Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR register triggers an unexpected EEPROM interrupt request.
Problem Fix / Workaround
Always use OUT or SBI to set EERE in EECR.
2490NS–AVR–05/08
19
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
Changes from Rev. 2490M-08/07 to Rev. 2490N-05/08
Changes from Rev. 2490L-10/06 to Rev. 2490M-08/07
Changes from Rev. 2490K-04/06 to Rev. 2490L-10/06
1. Updated “PEN” on page 7.
2. Updated “Ordering Information” on page 376.
1. Updated “Features” on page 1.
2. Added “Data Retention” on page 8.
3. Updated “Errata” on page 18.
4. Updated “Assembly Code Example(1)” on page 177.
5. Updated “Slave Mode” on page 167.
1. Added note to “Timer/Counter Oscillator” on page 45.
2. Updated “Fast PWM Mode” on page 125.
3. Updated Table 52 on page 104, Table 54 on page 105, Table 59 on page 134, Table 61
on page 136, Table 64 on page 158, and Table 66 on page 158.
4. Updated “Errata” on page 18.
Changes from Rev. 2490J-03/05 to Rev. 2490K-04/06
Changes from Rev. 2490I-10/04 to Rev. 2490J-03/05
20
ATmega64(L)
1. Updated Figure 2 on page 3.
2. Added “Resources” on page 8.
3. Added Addresses in Register Descriptions.
4. Updated “SPI – Serial Peripheral Interface” on page 163.
5. Updated Register- and bit names in “USART” on page 171.
6. Updated note in “Bit Rate Generator Unit” on page 204.
7. Updated Features in “Analog to Digital Converter” on page 230.
1. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package
QFN/MLF”.
2. Updated “Electrical Characteristics” on page 325
3. Updated “Ordering Information” on page 15
2490NS–AVR–05/08
ATmega64(L)
Changes from Rev. 2490H-10/04 to Rev. 2490I-11/04
Changes from Rev. 2490G-03/04 to Rev. 2490H-10/04
1. Removed “Preliminary” and TBD’s.
2. Updated Table 8 on page 40, Table 11 on page 42, Table 19 on page 52, Table 132 on
page 327, Table 134 on page 330.
3. Updated features in “Analog to Digital Converter” on page 230.
4. Updated “Electrical Characteristics” on page 325.
1. Removed references to Analog Ground, IC1/IC3 changed to ICP1/ICP3, Input Capture
Trigger changed to Input Capture Pin.
2. Updated “ATmega103 and ATmega64 Compatibility” on page 4.
3. Updated “External Memory Interface” on page 27
4. Updated “XDIV – XTAL Divide Control Register” to “Clock Sources” on page 38.
5. Updated code example in “WDTCR – Watchdog Timer Control Register” on page 57.
6. Added section “Unconnected Pins” on page 70.
7. Updated Table 19 on page 52, Table 20 on page 56, Table 95 on page 236, and
Table 60 on page 135.
Changes from Rev. 2490F-12/03 to Rev. 2490G-03/04
Changes from Rev. 2490E-09/03 to Rev. 2490F-12/03
Changes from Rev. 2490D-02/03 to Rev. 2490E-09/03
8. Updated Figure 116 on page 239.
9. Updated “Version” on page 255.
10. Updated “DC Characteristics” on page 325.
11. Updated “Typical Characteristics” on page 340.
12. Updated features in“Analog to Digital Converter” on page 230 and Table 136 on page
333.
13. Updated “Ordering Information” on page 15.
1. Updated “Errata” on page 18.
1. Updated “Calibrated Internal RC Oscillator” on page 43.
1. Updated note in “XDIV – XTAL Divide Control Register” on page 39.
2. Updated “JTAG Interface and On-chip Debug System” on page 50.
2490NS–AVR–05/08
3. Updated “TAP – Test Access Port” on page 248 regarding JTAGEN.
21
4. Updated description for the JTD bit on page 258.
5. Added a note regarding JTAGEN fuse to Table 118 on page 292.
Changes from Rev. 2490C-09/02 to Rev. 2490D-02/03
6. Updated R
7. Updated “ADC Characteristics” on page 332.
8. Added a proposal for solving problems regarding the JTAG instruction
IDCODE in “Errata” on page 18.
1. Added reference to Table 124 on page 296 from both SPI Serial Programming
and Self Programming to inform about the Flash page size.
2. Added Chip Erase as a first step under “Programming the Flash” on page 322
and “Programming the EEPROM” on page 323.
3. Corrected OCn waveforms in Figure 52 on page 126.
4. Various minor Timer1 corrections.
5. Improved the description in “Phase Correct PWM Mode” on page 101 and on
page 153.
6. Various minor TWI corrections.
7. Added note under "Filling the Temporary Buffer (Page Loading)" about writing to the EEPROM during an SPM page load.
values in “DC Characteristics” on page 325.
PU
Changes from Rev. 2490B-09/02 to Rev. 2490C-09/02
Changes from Rev. 2490A-10/01 to Rev. 2490B-09/02
8. Removed ADHSM completely.
9. Added note about masking out unused bits when reading the Program
Counter in “Stack Pointer” on page 14.
10. Added section “EEPROM Write During Power-down Sleep Mode” on page 25.
11. Changed V
12. Added information about conversion time for Differential mode with Auto
Triggering on page 234.
13. Added t
14. Updated “Packaging Information” on page 16.
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad QFN/MLF Package and updated “Ordering Information” on
page 15.
WD_FUSE
value to 120 in Table 19 on page 52.
HYST
in Table 128 on page 308.
22
ATmega64(L)
2490NS–AVR–05/08
ATmega64(L)
2. Added the section “Using all Locations of External Memory Smaller than 64 KB” on
page 35.
3. Added the section “Default Clock Source” on page 39.
4. Renamed SPMCR to SPMCSR in entire document.
5. Added Some Preliminary Test Limits and Characterization Data
Removed some of the TBD's and corrected data in the following tables and pages:
Table 2 on page 24, Table 7 on page 38, Table 9 on page 41, Table 10 on page 41, Table
12 on page 42, Table 14 on page 43, Table 16 on page 44, Table 19 on page 52, Table 20
on page 56, Table 22 on page 58, “DC Characteristics” on page 325, Table 131 on page
327, Table 134 on page 330, Table 136 on page 333, and Table 137 - Table 144.
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
See “Leaving Programming Mode” on page 321.
7. Improved description on how to do a polarity check of the ADC diff results in “ADC
Conversion Result” on page 242.
8. Updated Programming Figures:
Figure 138 on page 294 and Figure 147 on page 306 are updated to also reflect that AVCC
must be connected during Programming mode. Figure 142 on page 301 added to illustrate
how to program the fuses.
9. Added a note regarding usage of the “PROG_PAGELOAD (0x6)” and
“PROG_PAGEREAD (0x7)” instructions on page 313.
10. Updated “TWI – Two-wire Serial Interface” on page 198.
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the “Bit
Rate Generator Unit” on page 204. Added the description at the end of “Address Match Unit”
on page 205.
11. Updated Description of OSCCAL Calibration Byte.
In the data sheet, it was not explained how to take advantage of the calibration bytes for 2,
4, and 8 MHz Oscillator selections. This is now added in the following sections:
Improved description of “OSCCAL – Oscillator Calibration Register(1)” on page 43 and “Cal-
ibration Byte” on page 293.
12. When using external clock there are some limitations regards to change of frequency.
This is descried in “External Clock” on page 44 and Table 131 on page 327.
13. Added a sub section regarding OCD-system and power consumption in the section
“Minimizing Power Consumption” on page 49.
14. Corrected typo (WGM-bit setting) for:
– “Fast PWM Mode” on page 99 (Timer/Counter0).
–
“Phase Correct PWM Mode” on page 101 (Timer/Counter0).
– “Fast PWM Mode” on page 152 (Timer/Counter2).
– “Phase Correct PWM Mode” on page 153 (Timer/Counter2).
2490NS–AVR–05/08
23
15. Corrected Table 81 on page 192 (USART).
16. Corrected Table 102 on page 262 (Boundary-Scan)
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2490NS–AVR–05/08
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