ATMEL ATmega6490 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powe rful Instructions – Most Single Clock Cy cle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– In-System Self-programmable Flash Program Memory

• 32K Bytes (ATmega329/ATmega3290)

• 64K Bytes (ATmega649/ATmega6490)

– EEPROM

• 1K bytes (ATmega329/ATmega3290)

• 2K bytes (ATmega649/ATmega6490)

– Internal SRAM

• 2K bytes (ATmega329/ATmega3290)

• 4K bytes (ATmega649/ATmega6490) – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation – Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver (ATmega329/ATmega649) – 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490) – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator –Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Pac kages

– 53/68 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V: – 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V – ATmega329/3290/649/6490: – 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

• 1 MHz, 1.8V: 350 µA

• 32 kHz, 1.8V: 20 µA (including Oscillator)

• 32 kHz, 1.8V: 40 µA (including Oscillator and LCD)

– Power-down Mode:

• 100 nA at 1.8V

8-Bit Microcontroller

(1)

8-bit

Microcontroller with In-System Programmable Flash

ATmega329/V ATmega3290/V ATmega649/V ATmega6490/V

Preliminary Summary

ATmega329/3290/649/6490

1. Pin Configurations

Figure 1-1. Pinout ATmega3290/6490

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23/SEG36)

PH6 (PCINT22/SEG37)

PH5 (PCINT21/SEG38)

PH4 (PCINT20/SEG39)

DNC

GND

9998979695949392919089888786858483828180797877

100

INDEX CORNER

ATmega3290/6490

26272829303132333435363738394041424344454647484950

VCC

DNC

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

DNC

RESET/PG5

(T1/SEG33) PG3

(T0/SEG32) PG4

(OC2A/PCINT15) PB7

VCC

GND

DNC

(TOSC2) XTAL2

(TOSC1) XTAL1

(PCINT26/SEG31) PJ2

(PCINT27/SEG30) PJ3

DNC

(PCINT28/SEG29) PJ4

(ICP1/SEG26) PD0

(PCINT29/SEG28) PJ5

(PCINT30/SEG27) PJ6

(SEG24) PD2

(SEG23) PD3

(SEG22) PD4

(INT0/SEG25) PD1

(SEG21) PD5

(SEG20) PD6

(SEG19) PD7

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Figure 1-2. Pinout ATmega329/649

AREF

GND

AVCC

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

INDEX CORNER

PF0 (ADC0)

PF1 (ADC1)

6018592058

ATmega329/3290/649/6490

VCC

GND

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

57225623552454255326522751

ATmega329/649

PF7 (ADC7/TDI)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

PC5 (SEG7)

PC4 (SEG8)

PC3 (SEG9)

PC2 (SEG10)

PC1 (SEG11)

PC0 (SEG12)

PG1 (SEG13)

PG0 (SEG14)

VCC

GND

RESET/PG5

(T0/SEG23) PG4

(T1/SEG24) PG3

(OC2A/PCINT15) PB7

(TOSC1) XTAL1

(TOSC2) XTAL2

(ICP1/SEG22) PD0

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(SEG16) PD6

(SEG17) PD5

(SEG15) PD7

Note: The large center pad underneath the QFN/MLF pa ckages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

2. Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es will be available after the device is characterized.

3. Overview

The ATmega329/3290/649/6490 is a low-power CMOS 8-bit micr ocontroller based on the AVR e nhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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ATmega329/3290/649/6490

3.1 Block Diagram

Figure 3-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF DRIVERS

PORTF

AVR CPU

DATA DIR.

REG. PORTF

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

ALU

STATUS

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

CONTROLLER/

LCD

DRIVER

XTAL1

XTAL2

RESET

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

COMPARATOR

DATA REGISTER

USART

PORTE

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

DATA REGISTER

PORTB

PORTB DRIVERS

PB0 - PB7PE0 - PE7

DATA DIR.

REG. PORTB

SPI

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

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ATmega329/3290/649/6490

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugg ing support and program ming, a complete On-chip L CD controller with internal contrast control, three flexible Time r/Counters wit h compa re modes, in ternal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Bo ot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a powerful microcontroller that provides a highly flexible and cost effective solut ion to many embed ded control applications.

The ATmega329/3290/649/6490 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

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ATmega329/3290/649/6490

3.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes, pin count and pinout. Table 3-1 on page 6 summarizes the different configurations for the four devices.

Table 3-1. Configuration Summary

Device Flash EEPROM RAM

ATmega329 32K bytes 1K bytes 2K bytes 4 x 25 54 ATmega3290 32K bytes 1K bytes 2K bytes 4 x 40 69 ATmega649 64K bytes 2K bytes 4K bytes 4 x 25 54 ATmega6490 64K bytes 2K bytes 4K bytes 4 x 40 69

3.3 Pin Descriptions

The following section describes the I/O-pin special funct ion s.

3.3.1 V

3.3.2 GND

3.3.3 Port A (PA7..PA0)

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

LCD Segments

General Purpose I/O Pins

Port A also serves the function s of various special features of the ATmega329/3290/649/6490 as listed on page 67.

3.3.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports. Port B also serves the function s of various special features of the ATmega329/3290/649/6490

as listed on page 68.

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3.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed on page 71.

3.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega329/3290/649/6490 as listed on page 73.

ATmega329/3290/649/6490

3.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port E also serves the function s of various special features of the ATmega329/3290/649/6490 as listed on page 75.

3.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

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ATmega329/3290/649/6490

3.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves the functions of various specia l features of the ATmega3 29/3290/649/6490 as listed on page 75.

3.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290/6490 as listed on page 75.

3.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up re sistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

3.3.12 RESET

3.3.13 XTAL1

3.3.14 XTAL2

3.3.15 AVCC

3.3.16 AREF

Port J also serves the functions of various special features of the ATmega3290/64 90 as listed on

page 75.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset

Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

through a low-pass filter.

This is the analog reference pin for the A/D Converter.

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3.3.17 LCDCAP

4. Resources

5. Data Retention

ATmega329/3290/649/6490

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 24-2. This capacitor acts as a reservoir for LCD power (V

ripple on V

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

Note: 1.

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

but increases the time until V

LCD

reaches its target value.

LCD

). A large capacitance reduces

LCD

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ATmega329/3290/649/6490

6. Register Summary

Note: Registers with bold type only available in ATmega3290/6490.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4)

LCDDR19 SEG339 SEG338 SEG337 SEG336 SEG335 SEG334 SEG333 SEG332 244 LCDDR18 SEG331 SEG330 SEG329 SEG328 SEG327 SEG326 SEG325 SEG324 244 LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 244 LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 244 LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 244 LCDDR14 SEG239 SEG238 SEG237 SEG236 SEG235 SEG234 SEG233 SEG232 244 LCDDR13 SEG231 SEG230 SEG229 SEG228 SEG227 SEG226 SEG225 SEG224 244 LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 244 LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 244 LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 244 LCDDR09 SEG139 SEG138 SEG137 SEG136 SEG135 SEG134 SEG133 SEG132 244 LCDDR08 SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 244 LCDDR07 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 244 LCDDR06 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 244 LCDDR05 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 244 LCDDR04 SEG039 SEG038 SEG037 SEG036 SEG035 SEG034 SEG033 SEG032 244 LCDDR03 SEG031 SEG030 SEG029 SEG028 SEG027 SEG026 SEG025 SEG024 244 LCDDR02 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 244 LCDDR01 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG009 SEG008 244 LCDDR00 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 244

Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - LCDCCR LCDDC2 LCDDC1 LCDDC0 - LCDCC3 LCDCC2 LCDCC1 LCDCC0 243

LCDFRR - LCDPS2 LCDPS1 LCDPS0 - LCDCD2 LCDCD1 LCDCD0 241 LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 LCDPM3 LCDPM2 LCDPM1 LCDPM0 239 LCDCRA LCDEN LCDAB - LCDIF LCDIE - -LCDBL239 Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - -

PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 90

DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 90

PINJ - PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 90

PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 89

DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 90

PINH PINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 90

Reserved Reserved Reserved Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved

UDR0 USART0 Data Register 190

UBRR0H

UBRR0L USART0 Baud Rate Register Low 194

- - - - - - - -

USART0 Baud Rate Register High 194

2552JS–AVR–08/07

ATmega329/3290/649/6490

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xC3) (0xC2) (0xC1) (0xC0) (0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B)

(0x8A)

(0x89) (0x88) (0x87) (0x86) (0x85)

Reserved - - - - - - - UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 192

UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191

UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 190 Reserved - - - - - - - Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - -

USIDR USI Data Register 203

USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 203

USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 204

Reserved - - - - - - - -

ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB 155 Reserved - - - - - - - Reserved - - - - - - - -

OCR2A Timer/Counter 2 Output Compare Register A 155 TCNT2 Timer/Counter2 155

Reserved - - - - - - - -

TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 153 Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved Reserved Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved Reserved - - - - - - - Reserved Reserved - - - - - - - OCR1BH Timer/Counter1 Output Compare Register B High 136

OCR1BL Timer/Counter1 Output Compare Register B Low 136 OCR1AH Timer/Counter1 Output Compare Register A High 136

OCR1AL Timer/Counter1 Output Compare Register A Low 136

ICR1H Timer/Counter1 Input Capture Register High 137 ICR1L Timer/Counter1 Input Capture Register Low 137

TCNT1H Timer/Counter1 High 136

- - - - - - - -

2552JS–AVR–08/07

ATmega329/3290/649/6490

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0x84) (0x83) (0x82) (0x81) (0x80) (0x7F)

(0x7E) (0x7D) (0x7C)

(0x7B)

(0x7A)

(0x79)

(0x78)

(0x77)

(0x76)

(0x75)

(0x74)

(0x73)

(0x72)

(0x71)

(0x70)

(0x6F)

(0x6E) (0x6D) (0x6C)

(0x6B)

(0x6A)

(0x69)

(0x68)

(0x67)

(0x66)

(0x65)

(0x64)

(0x63)

(0x62)

(0x61)

(0x60)

0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

TCNT1L Timer/Counter1 Low 136

Reserved - - - - - - - -

TCCR1C FOC1A FOC1B - - - - - -135 TCCR1B ICNC1 ICES1 - WGM13WGM12CS12CS11CS10 134 TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - -WGM11WGM10132

DIDR1 - - - - - - AIN1D AIN0D 210 DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 227

Reserved - - - - - - - -

ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 223 ADCSRB -ACME- - - ADTS2 ADTS1 ADTS0 209/227 ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 225

ADCH ADC Data Register High 226

ADCL ADC Data Register Low 226 Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - PCMSK3 - PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 57 Reserved - - - - - - - Reserved - - - - - - - -

TIMSK2 - - - - - - OCIE2A TOIE2 156 TIMSK1 - -ICIE1- - OCIE1B OCIE1A TOIE1 137

TIMSK0 - - - - - - OCIE0A TOIE0 106 PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 57 PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 58 PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 58 Reserved - - - - - - - -

EICRA - - - - - -ISC01ISC0055 Reserved - - - - - - - Reserved - - - - - - - OSCCAL Oscillator Calibration Register [CAL7..0] 32 Reserved - - - - - - - -

PRR - - - PRLCD PRTIM1 PRSPI PSUSART0 PRADC 40 Reserved - - - - - - - Reserved - - - - - - - -

CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 33

WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 48

SREG I T H S V N Z C 12

SPH Stack Pointer High 14

SPL Stac k Pointer Low 14 Reserved - - - - - - - Reserved Reserved - - - - - - - Reserved Reserved SPMCSR SPMIE RWWSB Reserved

MCUCR JTD - -PUD- - IVSEL IVCE 52/87/254 MCUSR

SMCR

Reserved - - - - - - - -

OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 250

ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 209

Reserved - - - - - - - -

SPDR SPI Data Register 167 SPSR SPIF WCOL

SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 165 GPIOR2 General Purpose I/O Register 25 GPIOR1 General Purpose I/O Register 25

Reserved Reserved - - - - - - - -

OCR0A Timer/Counter0 Output Compare A 105 TCNT0 Timer/Counter0 105

- - - - - - - -

- RWWSRE BLBSET PGWRT PGERS SPMEN 291

- - - JTRF WDRF BORF EXTRF PORF 47

- - - - SM2 SM1 SM0 SE 39

- - - - - SPI2X 167

- - - - - - - -

2552JS–AVR–08/07

ATmega329/3290/649/6490

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40)

0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

Reserved - - - - - - - -

TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 103

GTCCR TSM - - - - - PSR2 PSR10 108/157 EEARH - - - - - EEPROM Address Register High 22

EEARL EEPROM Address Register Low 22

EEDR EEPROM Data Register 22 EECR

GPIOR0 General Purpose I/O Register 25

EIMSK PCIE3 PCIE2 PCIE1 PCIE0

EIFR PCIF3 PCIF2 PCIF1 PCIF0 - - - INTF0 56 Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - Reserved - - - - - - - -

TIFR2 - - - - - -OCF2ATOV2157 TIFR1 - -ICF1- -OCF1BOCF1ATOV1138 TIFR0 - - - - - -OCF0ATOV0106

PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89

DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 89

PING - - PING5 PING4 PING3 PING2 PING1 PING0 89

PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 89

DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89

PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89

PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 88

DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88

PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 89

PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88

DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88

PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88

PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 88

DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 88

PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88

PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 87

DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87

PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87

PORTA PORTA7 PORTA6 PORTA5 PO RTA4 PORTA3 PORTA2 PORTA 1 P ORTA 0 87

DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 87

PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87

- - - - EERIE EEMWE EEWE EERE 22

- - -INT055

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

2552JS–AVR–08/07

ATmega329/3290/649/6490

7. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← kNone3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← ZNone3 CALL k Direct Subroutine Call PC ← kNone4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 /2

2552JS–AVR–08/07

ATmega329/3290/649/6490

Mnemonics Operands Description Operation Flags #Clocks

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← TNone1 SEC Set Carry C ← 1C1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1N1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1Z1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1I1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1S1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1V1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1T1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← KNone1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) Non e 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None -

Rd+1:Rd ← Rr+1:Rr

None 1

2552JS–AVR–08/07

ATmega329/3290/649/6490

Mnemonics Operands Description Operation Flags #Clocks

IN Rd, P In Port Rd ← PNone1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A

2552JS–AVR–08/07

ATmega329/3290/649/6490

8. Ordering Information

8.1 ATmega329

Speed (MHz)

(3)

Power Supply Ordering Code Package Type

8 1.8 - 5.5V

16 2.7 - 5.5V

ATmega329V -8AI ATmega329V-8AU ATmega329V -8MI ATmega329V -8MU

ATmega329-16AI ATmega329-16AU ATmega329-16MI ATmega329-16MU

(2)

64A 64A 64M1 64M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For Speed vs. V

see Figure 29-1 on page 328 and Figure 29-2 on page 328.

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

0°C to 85°C)

(-4

Package Type

64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Pack age (QFN/MLF) 100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

2552JS–AVR–08/07

ATmega329/3290/649/6490

8.2 ATmega3290

Speed (MHz)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

3. For Speed vs. VCC see Figure 29-1 on page 328 and Figure 29-2 on page 328.

(3)

8 1.8 - 5.5V

16 2.7 - 5.5V

and minimum quantities.

tive). Also Halide free and fully Green.

Power Supply Ordering Code Package Type

ATmega3290V -8AI ATmega3290V-8AU

ATmega3290-16AI ATmega3290-16AU

(2)

100A 100A

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

(-4

0°C to 85°C)

Package Type

2552JS–AVR–08/07

ATmega329/3290/649/6490

8.3 ATmega649

Speed (MHz)

(3)

Power Supply Ordering Code Package Type

8 1.8 - 5.5V

16 2.7 - 5.5V

ATmega649V -8AI ATmega649V-8AU ATmega649V -8MI ATmega649V -8MU

ATmega649-16AI ATmega649-16AU ATmega649-16MI ATmega649-16MU

(2)

64A 64A 64M1 64M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

3. For Speed vs. V

see Figure 29-1 on page 328 and Figure 29-2 on page 328.

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

(-40°C to 85°C)

Package Type

2552JS–AVR–08/07

ATmega329/3290/649/6490

8.4 ATmega6490

Speed (MHz)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

3. For Speed Grades see Figure 29-1 on page 328 and Figure 29-2 on page 328.

(3)

8 1.8 - 5.5V

16 2.7 - 5.5V

and minimum quantities.

tive). Also Halide free and fully Green.

Power Supply Ordering Code Package Type

ATmega6490V -8AI ATmega6490V-8AU

ATmega6490-16AI ATmega6490-16AU

(2)

100A 100A

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

(-4

0°C to 85°C)

Package Type

2552JS–AVR–08/07

9. Packaging Information

9.1 64A

PIN 1

PIN 1 IDENTIFIER

ATmega329/3290/649/6490

E1 E

0°~7°

Notes:

1.This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

MIN

NOM

MAX

NOTE

2552JS–AVR–08/07

2325 Orchard Parkway

San Jose, CA 95131

TITLE

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

64A

REV.

ATmega329/3290/649/6490

9.2 64M1

Marked Pin# 1 ID

SEATING PLANE

TOP VIEW

BOTTOM VIEW

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

Note:

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Pin #1 Corner

1 2 3

Option A

Option B

Option C

Pin #1 Triangle

Pin #1 Chamfer (C 0.30)

Pin #1 Notch (0.20 R)

SIDE VIEW

SYMBOL

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D2 5.20 5.40 5.60

E2 5.20 5.40 5.60

e 0.50 BSC

L 0.35 0.40 0.45

K 1.25 1.40 1.55

0.08

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

8.90 9.00 9.10

NOM

MAX

NOTE

2325 Orchard Parkway

San Jose, CA 95131

TITLE

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

5/25/06

DRAWING NO.

64M1

REV.

2552JS–AVR–08/07

9.3 100A

ATmega329/3290/649/6490

PIN 1

PIN 1 IDENTIFIER

E1 E

0˚~7˚

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.08 mm maximum.

A2 A

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.17 – 0.27

C 0.09 – 0.20

L 0.45 – 0.75

e 0.50 TYP

MIN

NOM

MAX

NOTE

2552JS–AVR–08/07

2325 Orchard Parkway

San Jose, CA 95131

TITLE

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

100A

REV.

ATmega329/3290/649/6490

10. Errata

10.1 ATmega329

10.1.1 ATmega329 rev. C

•

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

10.1.2 ATmega329 rev. B

Not sampled.

10.1.3 ATmega329 rev. A

•

• Interrupts may be lost when writing the timer registers in the asynchronous timer

1. LCD contrast voltage too high

Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

LCD contrast volta ge too high

When the LCD is active and using low power wavefor m, the LCD contrast volt age can b e too high. This occurs when V

Problem Fix/Workaround

There are several possible workarounds:

- Use normal waveform instead of low power waveform

- Use drivetime of 375 µs or longer

is higher than V

, and when using low LCD drivetime.

LCD

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

2552JS–AVR–08/07

10.2 ATmega3290

10.2.1 ATmega3290 rev. C

•

Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

10.2.2 ATmega3290 rev. B

Not sampled.

10.2.3 ATmega3290 rev. A

•

LCD contrast volta ge too high

• Interrupts may be lost when writing the timer registers in the asynchronous timer

ATmega329/3290/649/6490

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

1. LCD contrast voltage too high

When the LCD is active and using low power wavefor m, the LCD contrast volt age can b e too high. This occurs when V

is higher than V

, and when using low LCD drivetime.

LCD

Problem Fix/Workaround

There are several possible workarounds:

- Use normal waveform instead of low power waveform

- Use drivetime of 375 µs or longer

2. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

2552JS–AVR–08/07

ATmega329/3290/649/6490

10.3 ATmega649

10.3.1 ATmega649 rev. A

•

Interrupts may be lost when writing the timer registers in the asynchronous timer

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

10.4 ATmega6490

10.4.1 ATmega6490 rev. A

Interrupts may be lost when writing the timer registers in the asynchronous timer

•

1. Interrupts may be lost when writing the timer registers in the asynchronous timer

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Wortkaround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

2552JS–AVR–08/07

11. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision.

11.1 Rev. 2552J – 08/07

1. Updated “Features” on page 1.

2. Added “Data Retention” on page 9.

3. Updated “Serial Programming Algorithm” on page 309.

4. Updated “Speed Grades” on page 328.

5. Updated “System and Reset Characteristics” on page 330.

6. Moved Register Descriptions to the end of each chapter.

11.2 Rev. 2552I – 04/07

ATmega329/3290/649/6490

1. Updated date in backpage

2. Updated column in Table 29-5 on page 330.

11.3 Rev. 2552H – 11/06

1. Updated Table 29-7 on page 333.

2. Updated note in Table 29-7 on page 333 and Table 29-2 on page 329.

11.4 Rev. 2552G – 07/06

1. Updated Table 15-2 on page 104, Table 15-4 on page 104, Table 17-3 on

2. Updated “Fast PWM Mode” on page 124.

3. Updated Features in “USI – Universal Serial Interface” on page 195.

4. Added “Clock speed considerations.” on page 202.

5. “Errata” on page 24.

11.5 Rev. 2552F – 06/06

page 133, Table 17-5 on page 134, Table 17-5 on page 134, Table 18-2 on page 153 and Table 18-4 on page 154.

2552JS–AVR–08/07

1. Updated “Calibrated Internal RC Oscillator” on page 29.

2. Updated “OSCCAL – Oscillator Calibration Register” on page 32

3. Added Table 29-2 on page 329.

ATmega329/3290/649/6490

11.6 Rev. 2552E – 04/06

1. Updated “Calibrated Internal RC Oscillator” on page 29.

11.7 Rev. 2552D – 03/06

1. Updated “Errata” on page 24.

11.8 Rev. 2552C – 03/06

1. Added “Resources” on page 9.

2. Added Addresses in Registers.

3. Updated number of General Purpose I/O pins.

4. Updated code example in “Bit 0 – IVCE: Interrupt Vector Change Enable”

5. Updated Introduction in “I/O-Ports” on page 59.

6. Updated “SPI – Serial Peripheral Interface” on page 158.

7. Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page

8. Updated Features in “Analog to Digital Converter” on page 211.

9. Updated “Prescaling and Conversion Timing” on page 214.

10. Updated features in “LCD Controller” on page 228.

11. Updated “ATmega329/3290/649/6490 Boot Loader Parameters” on page

12. Updated “DC Characteristics” on page 310.

13. Updated “LCD Controller Characteristics – Preliminary Data – TBD” on

on page 53.

209.

290.

page 334.

11.9 Rev. 2552B – 05/05

1. MLF-package alternative changed to “Q uad Flat No-Lead/Micro Lead

2. Added “Pin Change Interrupt Timing” on page 54.

3. Updated Table 24-6 on page 242, Table 24-7 on page 243 and Table 28-15

4. Added Figure 28-12 on page 312.

5. Updated Figure 23-9 on page 219 and Figure 28-5 on page 304.

6. Updated algorithm “Enter Programming Mode” on page 299.

7. Added “Supply Current of I/O modules” on page 340.

8. Updated “Ordering Information” on page 17.

11.10 Rev. 2552A –11/04

1. Initial version.

Frame Package QFN/MLF”.

on page 310.

2552JS–AVR–08/07

ATMEL ATmega6490 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

2. Disclaimer

3. Overview

3.1 Block Diagram

3.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

3.3 Pin Descriptions

3.3.2 GND

3.3.3 Port A (PA7..PA0)

3.3.4 Port B (PB7..PB0)

3.3.5 Port C (PC7..PC0)

3.3.6 Port D (PD7..PD0)

3.3.7 Port E (PE7..PE0)

3.3.8 Port F (PF7..PF0)

3.3.9 Port G (PG5..PG0)

3.3.10 Port H (PH7..PH0)

3.3.11 Port J (PJ6..PJ0)

3.3.12 RESET

3.3.13 XTAL1

3.3.14 XTAL2

3.3.15 AVCC

3.3.16 AREF

3.3.17 LCDCAP

4. Resources

5. Data Retention

6. Register Summary

7. Instruction Set Summary

8. Ordering Information

8.1 ATmega329

8.2 ATmega3290

8.3 ATmega649

8.4 ATmega6490

9. Packaging Information

9.1 64A

9.2 64M1

9.3 100A

10. Errata

10.1 ATmega329

10.1.1 ATmega329 rev. C

10.1.2 ATmega329 rev. B

10.1.3 ATmega329 rev. A

10.2 ATmega3290

10.2.1 ATmega3290 rev. C

10.2.2 ATmega3290 rev. B

10.2.3 ATmega3290 rev. A

10.3 ATmega649

10.3.1 ATmega649 rev. A

10.4 ATmega6490

10.4.1 ATmega6490 rev. A

11. Datasheet Revision History