ATMEL ATmega6490 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powe rful Instructions – Most Single Clock Cy cle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– In-System Self-programmable Flash Program Memory

• 32K Bytes (ATmega329/ATmega3290)

• 64K Bytes (ATmega649/ATmega6490)

– EEPROM

• 1K bytes (ATmega329/ATmega3290)

• 2K bytes (ATmega649/ATmega6490)

– Internal SRAM

• 2K bytes (ATmega329/ATmega3290)

• 4K bytes (ATmega649/ATmega6490)
– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program

• True Read-While-Write Operation
– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver (ATmega329/ATmega649)
– 4 x 40 Segment LCD Driver (ATmega3290/ATmega6490)
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Pac kages

– 53/68 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega329V/ATmega3290V/ATmega649V/ATmega6490V:
– 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega329/3290/649/6490:
– 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

• 1 MHz, 1.8V: 350 µA

• 32 kHz, 1.8V: 20 µA (including Oscillator)

• 32 kHz, 1.8V: 40 µA (including Oscillator and LCD)

– Power-down Mode:

• 100 nA at 1.8V

®

8-Bit Microcontroller

(1)

8-bit

Microcontroller
with In-System
Programmable
Flash

ATmega329/V
ATmega3290/V
ATmega649/V
ATmega6490/V

Preliminary
Summary

ATmega329/3290/649/6490

1. Pin Configurations

Figure 1-1. Pinout ATmega3290/6490

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24/SEG35) PJ0

(PCINT25/SEG34) PJ1

DNC

DNC

DNC

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

DNC

PH7 (PCINT23/SEG36)

PH6 (PCINT22/SEG37)

PH5 (PCINT21/SEG38)

PH4 (PCINT20/SEG39)

DNC

DNC

GND

9998979695949392919089888786858483828180797877

100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

INDEX CORNER

ATmega3290/6490

26272829303132333435363738394041424344454647484950

VCC

DNC

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PA3 (COM3)

PA4 (SEG0)

PA5 (SEG1)

PA6 (SEG2)

PA7 (SEG3)

PG2 (SEG4)

PC7 (SEG5)

PC6 (SEG6)

DNC

PH3 (PCINT19/SEG7)

PH2 (PCINT18/SEG8)

PH1 (PCINT17/SEG9)

PH0 (PCINT16/SEG10)

DNC

DNC

DNC

DNC

PC5 (SEG11)

PC4 (SEG12)

PC3 (SEG13)

PC2 (SEG14)

PC1 (SEG15)

PC0 (SEG16)

PG1 (SEG17)

PG0 (SEG18)

DNC

RESET/PG5

(T1/SEG33) PG3

(T0/SEG32) PG4

(OC2A/PCINT15) PB7

VCC

GND

DNC

DNC

(TOSC2) XTAL2

(TOSC1) XTAL1

(PCINT26/SEG31) PJ2

(PCINT27/SEG30) PJ3

DNC

(PCINT28/SEG29) PJ4

(ICP1/SEG26) PD0

(PCINT29/SEG28) PJ5

(PCINT30/SEG27) PJ6

(SEG24) PD2

(SEG23) PD3

(SEG22) PD4

(INT0/SEG25) PD1

(SEG21) PD5

(SEG20) PD6

(SEG19) PD7

2

2552JS–AVR–08/07

Figure 1-2. Pinout ATmega329/649

AREF

GND

AVCC

64

63

62

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

INDEX CORNER

19

PF0 (ADC0)

PF1 (ADC1)

61

6018592058

21

ATmega329/3290/649/6490

VCC

GND

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

57225623552454255326522751

ATmega329/649

PF7 (ADC7/TDI)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PA0 (COM0)

PA1 (COM1)

PA2 (COM2)

50

49

PA3 (COM3)

48

PA4 (SEG0)

47

PA5 (SEG1)

46

PA6 (SEG2)

45

PA7 (SEG3)

44

43

PG2 (SEG4)

42

PC7 (SEG5)

41

PC6 (SEG6)

40

PC5 (SEG7)

PC4 (SEG8)

39

PC3 (SEG9)

38

PC2 (SEG10)

37

PC1 (SEG11)

36

PC0 (SEG12)

35

34

PG1 (SEG13)

33

PG0 (SEG14)

29

28

32

31

30

VCC

GND

RESET/PG5

(T0/SEG23) PG4

(T1/SEG24) PG3

(OC2A/PCINT15) PB7

(TOSC1) XTAL1

(TOSC2) XTAL2

(ICP1/SEG22) PD0

(SEG18) PD4

(SEG19) PD3

(SEG20) PD2

(INT0/SEG21) PD1

(SEG16) PD6

(SEG17) PD5

(SEG15) PD7

Note: The large center pad underneath the QFN/MLF pa ckages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.

2. Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.

3. Overview

The ATmega329/3290/649/6490 is a low-power CMOS 8-bit micr ocontroller based on the AVR e nhanced RISC architec­ture. By executing powerful instructions in a single clock cycle, the ATmega329/3290/649/6490 achieves throughputs
approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2552JS–AVR–08/07

3

ATmega329/3290/649/6490

3.1 Block Diagram

Figure 3-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF DRIVERS

PORTF

AVR CPU

DATA DIR.

REG. PORTF

ADC

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

REGISTER

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

CONTROLLER/

LCD

DRIVER

XTAL1

XTAL2

RESET

4

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

COMPARATOR

DATA REGISTER

+

-

USART

PORTE

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

DATA REGISTER

PORTB

PORTB DRIVERS

PB0 - PB7PE0 - PE7

DATA DIR.

REG. PORTB

SPI

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

2552JS–AVR–08/07

ATmega329/3290/649/6490

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega329/3290/649/6490 provides the following features: 32/64K bytes of In-System
Programmable Flash with Read-While-Write capabilities, 1/2K bytes EEPROM, 2/4K byte
SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface
for Boundary-scan, On-chip Debugg ing support and program ming, a complete On-chip L CD
controller with internal contrast control, three flexible Time r/Counters wit h compa re modes, in ter­nal and external interrupts, a serial programmable USART, Universal Serial Interface with Start
Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal
Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to con­tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator,
disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode,
the asynchronous timer and the LCD controller continues to run, allowing the user to maintain a
timer base and operate the LCD display while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except asynchronous timer, LCD controller
and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crys­tal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast
start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip In-System re-Programmable (ISP) Flash allows the program memory to be repro­grammed In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip Boot program running on the AVR core. The Bo ot program can
use any interface to download the application program in the Application Flash memory. Soft­ware in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega329/3290/649/6490 is a pow­erful microcontroller that provides a highly flexible and cost effective solut ion to many embed ded
control applications.

The ATmega329/3290/649/6490 AVR is supported with a full suite of program and system
development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators,
In-Circuit Emulators, and Evaluation kits.

2552JS–AVR–08/07

5

ATmega329/3290/649/6490

3.2 Comparison between ATmega329, ATmega3290, ATmega649 and ATmega6490

The ATmega329, ATmega3290, ATmega649, and ATmega6490 differs only in memory sizes,
pin count and pinout. Table 3-1 on page 6 summarizes the different configurations for the four
devices.

Table 3-1. Configuration Summary

Device Flash EEPROM RAM

ATmega329 32K bytes 1K bytes 2K bytes 4 x 25 54
ATmega3290 32K bytes 1K bytes 2K bytes 4 x 40 69
ATmega649 64K bytes 2K bytes 4K bytes 4 x 25 54
ATmega6490 64K bytes 2K bytes 4K bytes 4 x 40 69

3.3 Pin Descriptions

The following section describes the I/O-pin special funct ion s.

3.3.1 V

3.3.2 GND

3.3.3 Port A (PA7..PA0)

CC

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

LCD
Segments

General Purpose
I/O Pins

Port A also serves the function s of various special features of the ATmega329/3290/649/6490
as listed on page 67.

3.3.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port B has better driving capabilities than the other ports.
Port B also serves the function s of various special features of the ATmega329/3290/649/6490

as listed on page 68.

6

2552JS–AVR–08/07

3.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port C also serves the functions of special features of the ATmega329/3290/649/6490 as listed
on page 71.

3.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega329/3290/649/6490
as listed on page 73.

ATmega329/3290/649/6490

3.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port E also serves the function s of various special features of the ATmega329/3290/649/6490
as listed on page 75.

3.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve sym­metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2552JS–AVR–08/07

7

ATmega329/3290/649/6490

3.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port G also serves the functions of various specia l features of the ATmega3 29/3290/649/6490
as listed on page 75.

3.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3290/6490 as listed
on page 75.

3.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up re sistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capa­bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

3.3.12 RESET

3.3.13 XTAL1

3.3.14 XTAL2

3.3.15 AVCC

3.3.16 AREF

Port J also serves the functions of various special features of the ATmega3290/64 90 as listed on

page 75.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in “System and Reset

Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con­nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

CC

through a low-pass filter.

This is the analog reference pin for the A/D Converter.

8

2552JS–AVR–08/07

3.3.17 LCDCAP

4. Resources

5. Data Retention

ATmega329/3290/649/6490

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 24-2. This capacitor acts as a reservoir for LCD power (V

ripple on V

A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.

Note: 1.

Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.

but increases the time until V

LCD

reaches its target value.

LCD

). A large capacitance reduces

LCD

2552JS–AVR–08/07

9