Introduction
ATmega164P/V/324P/V/644P/V
megaAVR® Data Sheet
The ATmega164P/V/324P/V/644P/V is a low power, CMOS 8-bit microcontrollers based on the AVR
enhanced RISC architecture. The ATmega164P/V/324P/V/644P/V is a 40/44-pins device ranging from
16 KB to 64 KB Flash, with 1 KB to 4 KB SRAM, 512 Bytes to 2 KB EEPROM. By executing instructions in
a single clock cycle, the devices achieve CPU throughput approaching one million instructions per second
(MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing
speed.
Features
High-performance, Low-power AVR
Advanced RISC Architecture
131 Powerful Instructions – Most Single-clock Cycle Execution
32 × 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20 MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory segments
16K/32K/64K Bytes of In-System Self-programmable Flash program memory
512B/1K/2K Bytes EEPROM
1K/2K/4K Bytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
®
8-bit Microcontroller
(1)
®
True Read-While-Write Operation
Programming Lock for Software Security
JTAG (IEEE std. 1149.1 Compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
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Six PWM Channels
8-channel, 10-bit ADC
Differential mode with selectable gain at 1×, 10× or 200×
Byte-oriented Two-wire Serial Interface
Two Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby
I/O and Packages
32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF (ATmega164P/324P/644P)
44-pad DRQFN (ATmega164P)
Operating Voltages
1.8V - 5.5V for ATmega164PV/324PV/644PV
2.7V - 5.5V for ATmega164P/324P/644P
Speed Grades
ATmega164PV/324PV/644PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 10 MHz @ 2.7V - 5.5V
ATmega164P/324P/644P: 0 - 10 MHz @ 2.7V - 5.5V, 0 - 20 MHz @ 4.5V - 5.5V
Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164PV/324PV/644PV
Active: 0.4 mA
Power-down Mode: 0.1 µA
Power-save Mode: 0.6 µA (Including 32 kHz RTC)
Note: 1. See “Data Retention” on page 16.
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Table of Contents
1 Pin Configurations .............................................................................................................. 11
1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF ............................................................ 11
2Overview .................................................................................................................................... 12
2.1 Block Diagram ................................................................................................. 12
2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P ......... 13
2.3 Pin Descriptions............................................................................................... 14
3 About ........................................................................................................................................... 16
3.1 Resources ....................................................................................................... 16
3.2 About Code Examples..................................................................................... 16
3.3 Data Retention................................................................................................. 16
4 AVR CPU Core ....................................................................................................................... 17
4.1 Overview.......................................................................................................... 17
4.2 ALU – Arithmetic Logic Unit............................................................................. 18
4.3 Status Register ................................................................................................ 18
4.4 General Purpose Register File ........................................................................ 19
4.5 Stack Pointer ................................................................................................... 21
4.6 Instruction Execution Timing ........................................................................... 22
4.7 Reset and Interrupt Handling........................................................................... 23
5 AVR Memories ....................................................................................................................... 26
5.1 Overview.......................................................................................................... 26
5.2 In-System Reprogrammable Flash Program Memory ..................................... 26
5.3 SRAM Data Memory........................................................................................ 27
5.4 EEPROM Data Memory .................................................................................. 29
5.5 I/O Memory...................................................................................................... 30
5.6 Register Description ........................................................................................ 31
6 System Clock and Clock Options .............................................................................. 36
6.1 Clock Systems and their Distribution............................................................... 36
6.2 Clock Sources ................................................................................................. 37
6.3 Low Power Crystal Oscillator........................................................................... 39
6.4 Full Swing Crystal Oscillator ............................................................................ 40
6.5 Low Frequency Crystal Oscillator .................................................................... 41
6.6 Calibrated Internal RC Oscillator ..................................................................... 43
6.7 128 kHz Internal Oscillator .............................................................................. 44
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6.8 External Clock ................................................................................................. 44
6.9 Timer/Counter Oscillator.................................................................................. 45
6.10 Clock Output Buffer ......................................................................................... 45
6.11 System Clock Prescaler .................................................................................. 45
6.12 Register Description ........................................................................................ 47
7 Power Management and Sleep Modes ................................................................... 49
7.1 Overview.......................................................................................................... 49
7.2 Sleep Modes.................................................................................................... 49
7.3 BOD Disable.................................................................................................... 50
7.4 Idle Mode......................................................................................................... 50
7.5 ADC Noise Reduction Mode............................................................................ 50
7.6 Power-down Mode........................................................................................... 51
7.7 Power-save Mode............................................................................................ 51
7.8 Standby Mode ................................................................................................. 51
7.9 Extended Standby Mode ................................................................................. 51
7.10 Power Reduction Register ............................................................................... 52
7.11 Minimizing Power Consumption ...................................................................... 52
7.12 Register Description ........................................................................................ 54
8 System Control and Reset ............................................................................................. 57
8.1 Resetting the AVR ........................................................................................... 57
8.2 Reset Sources ................................................................................................. 57
8.3 Power-on Reset............................................................................................... 58
8.4 External Reset ................................................................................................. 59
8.5 Brown-out Detection ........................................................................................ 60
8.6 Watchdog Reset .............................................................................................. 60
8.7 Internal Voltage Reference.............................................................................. 61
8.8 Watchdog Timer .............................................................................................. 62
8.9 Register Description ........................................................................................ 65
9 Interrupts ................................................................................................................................... 68
9.1 Overview.......................................................................................................... 68
9.2 Interrupt Vectors in ATmega164P/324P/644P ................................................ 68
9.3 Register Description ........................................................................................ 72
10 External Interrupts .............................................................................................................. 74
10.1 Overview.......................................................................................................... 74
10.2 Register Description ........................................................................................ 74
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11 I/O-Ports ..................................................................................................................................... 79
11.1 Overview.......................................................................................................... 79
11.2 Ports as General Digital I/O ............................................................................. 80
11.3 Alternate Port Functions .................................................................................. 85
11.4 Register Description ........................................................................................ 98
12 8-bit Timer/Counter0 with PWM ................................................................................ 100
12.1 Features ........................................................................................................ 100
12.2 Overview........................................................................................................ 100
12.3 Timer/Counter Clock Sources ....................................................................... 101
12.4 Counter Unit .................................................................................................. 101
12.5 Output Compare Unit..................................................................................... 102
12.6 Compare Match Output Unit .......................................................................... 103
12.7 Modes of Operation ....................................................................................... 104
12.8 Timer/Counter Timing Diagrams ................................................................... 108
12.9 Register Description ...................................................................................... 110
13 16-bit Timer/Counter1 with PWM ............................................................................. 117
13.1 Features ........................................................................................................ 117
13.2 Overview........................................................................................................ 117
13.3 Accessing 16-bit Registers ............................................................................ 119
13.4 Timer/Counter Clock Sources ....................................................................... 122
13.5 Counter Unit .................................................................................................. 122
13.6 Input Capture Unit ......................................................................................... 123
13.7 Output Compare Units ................................................................................... 125
13.8 Compare Match Output Unit .......................................................................... 128
13.9 Modes of Operation ....................................................................................... 129
13.10 Timer/Counter Timing Diagrams ................................................................... 136
13.11 Register Description ...................................................................................... 137
14 8-bit Timer/Counter2 with PWM and Asynchronous Operation ........... 145
14.1 Features ........................................................................................................ 145
14.2 Overview........................................................................................................ 145
14.3 Timer/Counter Clock Sources ....................................................................... 146
14.4 Counter Unit .................................................................................................. 147
14.5 Output Compare Unit..................................................................................... 147
14.6 Compare Match Output Unit .......................................................................... 149
14.7 Modes of Operation ....................................................................................... 150
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14.8 Timer/Counter Timing Diagrams ................................................................... 154
14.9 Asynchronous Operation of Timer/Counter2 ................................................. 155
14.10 Timer/Counter Prescaler ............................................................................... 157
14.11 Register Description ...................................................................................... 157
15 SPI – Serial Peripheral Interface ............................................................................... 165
15.1 Features ........................................................................................................ 165
15.2 Overview........................................................................................................ 165
15.3 SS Pin Functionality ...................................................................................... 169
15.4 Data Modes ................................................................................................... 169
15.5 Register Description ...................................................................................... 171
16 USART ...................................................................................................................................... 174
16.1 Features ........................................................................................................ 174
16.2 USART1 and USART0 .................................................................................. 174
16.3 Overview........................................................................................................ 174
16.4 Clock Generation........................................................................................... 175
16.5 Frame Formats .............................................................................................. 178
16.6 USART Initialization....................................................................................... 179
16.7 Data Transmission – The USART Transmitter .............................................. 180
16.8 Data Reception – The USART Receiver ....................................................... 183
16.9 Asynchronous Data Reception ...................................................................... 187
16.10 Multi-processor Communication Mode .......................................................... 190
16.11 Register Description ...................................................................................... 192
16.12 Examples of Baud Rate Setting..................................................................... 197
17 USART in SPI Mode .......................................................................................................... 201
17.1 Features ........................................................................................................ 201
17.2 Overview........................................................................................................ 201
17.3 Clock Generation........................................................................................... 201
17.4 SPI Data Modes and Timing.......................................................................... 202
17.5 Frame Formats .............................................................................................. 202
17.6 Data Transfer................................................................................................. 204
17.7 AVR USART MSPIM vs. AVR SPI ................................................................ 206
17.8 Register Description ...................................................................................... 207
18 2-wire Serial Interface ..................................................................................................... 210
18.1 Features ........................................................................................................ 210
18.2 2-wire Serial Interface Bus Definition ............................................................ 210
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18.3 Data Transfer and Frame Format .................................................................. 211
18.4 Multi-master Bus Systems, Arbitration and Synchronization ......................... 213
18.5 Overview of the TWI Module ......................................................................... 216
18.6 Using the TWI................................................................................................ 218
18.7 Transmission Modes ..................................................................................... 221
18.8 Multi-master Systems and Arbitration............................................................ 233
18.9 Register Description ...................................................................................... 234
19 AC - Analog Comparator ............................................................................................... 238
19.1 Overview........................................................................................................ 238
19.2 Analog Comparator Multiplexed Input ........................................................... 238
19.3 Register Description ...................................................................................... 239
20 ADC - Analog-to-digital Converter .......................................................................... 241
20.1 Features ........................................................................................................ 241
20.2 Overview........................................................................................................ 241
20.3 Operation....................................................................................................... 242
20.4 Starting a Conversion .................................................................................... 243
20.5 Prescaling and Conversion Timing................................................................ 244
20.6 Changing Channel or Reference Selection ................................................... 247
20.7 ADC Noise Canceler ..................................................................................... 248
20.8 ADC Conversion Result................................................................................. 253
20.9 Register Description ...................................................................................... 255
21 JTAG Interface and On-chip Debug System ..................................................... 260
21.1 Features ........................................................................................................ 260
21.2 Overview........................................................................................................ 260
21.3 TAP – Test Access Port ................................................................................ 260
21.4 TAP Controller ............................................................................................... 262
21.5 Using the Boundary-scan Chain .................................................................... 263
21.6 Using the On-chip Debug System ................................................................. 263
21.7 On-chip Debug Specific JTAG Instructions ................................................... 264
21.8 Using the JTAG Programming Capabilities ................................................... 264
21.9 Bibliography................................................................................................... 265
21.10 Register Description ...................................................................................... 265
22 IEEE 1149.1 (JTAG) Boundary-scan ...................................................................... 266
22.1 Features ........................................................................................................ 266
22.2 Overview........................................................................................................ 266
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22.3 Data Registers ............................................................................................... 267
22.4 Boundary-scan Specific JTAG Instructions ................................................... 268
22.5 Boundary-scan Chain .................................................................................... 269
22.6 ATmega164P/324P/644P Boundary-scan Order .......................................... 272
22.7 Boundary-scan Description Language Files .................................................. 273
22.8 Register Description ...................................................................................... 274
23 Boot Loader Support – Read-While-Write Self-Programming ............... 275
23.1 Features ........................................................................................................ 275
23.2 Overview........................................................................................................ 275
23.3 Application and Boot Loader Flash Sections ................................................. 275
23.4 Read-While-Write and No Read-While-Write Flash Sections........................ 276
23.5 Boot Loader Lock Bits ................................................................................... 278
23.6 Entering the Boot Loader Program................................................................ 279
23.7 Addressing the Flash During Self-Programming ........................................... 280
23.8 Self-Programming the Flash.......................................................................... 280
23.9 Register Description ...................................................................................... 290
24 Memory Programming .................................................................................................... 292
24.1 Program And Data Memory Lock Bits ........................................................... 292
24.2 Fuse Bits........................................................................................................ 293
24.3 Signature Bytes ............................................................................................. 295
24.4 Calibration Byte ............................................................................................. 295
24.5 Page Size ...................................................................................................... 295
24.6 Parallel Programming Parameters, Pin Mapping, and Commands ............... 295
24.7 Parallel Programming .................................................................................... 298
24.8 Serial Downloading........................................................................................ 306
24.9 Serial Programming Instruction set ............................................................... 308
24.10 Programming via the JTAG Interface ............................................................ 310
25 Electrical Characteristics – TA = -40°C to 85°C .............................................. 322
25.1 DC Characteristics......................................................................................... 322
25.2 Speed Grades ............................................................................................... 326
25.3 Clock Characteristics ..................................................................................... 327
25.4 System and Reset Characteristics ................................................................ 328
25.5 External Interrupts Characteristics ................................................................ 328
25.6 SPI Timing Characteristics ............................................................................ 329
25.7 2-wire Serial Interface Characteristics ........................................................... 330
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25.8 ADC Characteristics ...................................................................................... 332
26 Electrical Characteristics – TA = -40°C to 105°C ............................................ 335
26.1 DC Characteristics......................................................................................... 335
27 Typical Characteristics – TA = -40°C to 85°C ................................................... 338
27.1 ATmega164P Typical Characterization ......................................................... 338
27.2 ATmega324P Typical Characteristics ........................................................... 363
27.3 ATmega644P Typical Characteristic ............................................................. 388
28 Typical Characteristics – TA = -40°C to 105°C ................................................ 413
28.1 ATmega164P Typical Characteristics ........................................................... 413
28.2 ATmega324P Typical Characteristics ........................................................... 434
28.3 ATmega644P Typical Characteristics ........................................................... 455
29 Register Summary ............................................................................................................. 476
30 Instruction Set Summary .............................................................................................. 480
31 Ordering Information ....................................................................................................... 483
31.1 ATmega164P................................................................................................. 483
31.2 ATmega324P................................................................................................. 484
31.3 ATmega644P................................................................................................. 485
32 Packaging Information ................................................................................................... 486
32.1 44A ................................................................................................................ 486
32.2 40P6 .............................................................................................................. 487
32.3 44M1.............................................................................................................. 488
33 Errata ......................................................................................................................................... 489
33.1 ATmega164P................................................................................................. 489
33.2 ATmega324P................................................................................................. 489
33.3 ATmega644P................................................................................................. 489
34 Datasheet Revision History ......................................................................................... 490
34.1 Rev. A - 10/2018............................................................................................ 490
34.2 Rev. 8011R - 09/2015 ................................................................................... 490
34.3 Rev. 8011Q - 02/2013 ................................................................................... 490
34.4 Rev. 8011O - 07/10 ....................................................................................... 490
34.5 Rev. 8011N - 10/09 ....................................................................................... 490
34.6 Rev. 8011M - 08/09 ....................................................................................... 491
34.7 Rev. 8011L - 02/09 ........................................................................................ 491
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34.8 Rev. 8011K - 09/08........................................................................................ 491
34.9 Rev. 8011J - 09/08 ........................................................................................ 491
34.10 Rev. 8011I - 05/08 ......................................................................................... 491
34.11 Rev. 8011H - 04/08 ....................................................................................... 492
34.12 Rev. 8011G - 08/07 ....................................................................................... 492
34.13 Rev. 8011F - 04/07........................................................................................ 493
34.14 Rev. 8011E - 04/07........................................................................................ 493
34.15 Rev. 8011D - 02/07 ....................................................................................... 493
34.16 Rev. 8011C - 10/06 ....................................................................................... 493
34.17 Rev. 8011B - 09/06........................................................................................ 493
34.18 Rev. 8011A - 08/06........................................................................................ 493
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1. Pin Configurations
1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF
Figure 1-1. Pinout ATmega164P/324P/644P
ATmega164P/V/324P/V/644P/V
PDIP
(PCINT8/XCK0/T0) PB0
(PCINT9/CLKO/T1) PB1
(PCINT10/INT2/AIN0) PB2
(PCINT11/OC0A/AIN1) PB3
(PCINT12/OC0B/SS) PB4
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT29/OC1A) PD5
(PCINT30/OC2B/ICP) PD6
TQFP/VQFN/QFN/MLF
PB4 (SS/OC0B/PCINT12)
PB3 (AIN1/OC0A/PCINT11)
PB2 (AIN0/INT2/PCINT10)
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
GND
VCC
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVC C
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
PC3 (TMS/PCINT19)
PC2 (TCK/PCINT18)
PC1 (SDA/PCINT17)
PC0 (SCL/PCINT16)
PD7 (OC2A/PCINT31)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
VCC
GND
XTAL2
XTAL1
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
VCC
GND
(PCINT16/SCL) PC0
(PCINT29/OC1A) PD5
(PCINT31/OC2A) PD7
(PCINT30/OC2B/ICP) PD6
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT17/SDA) PC1
(PCINT18/TCK) PC2
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
GND
AVC C
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
(PCINT19/TMS) PC3
Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on the board to
ensure good mechanical stability.
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2. Overview
CPU
GND
VCC
RESET
Power
Supervision
POR / BOD &
RESET
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
XTAL1
XTAL2
PORT A (8)
PORT D (8)
PD7..0
PORT C (8)
PC5..0
TWI
SPI
EEPROM
JTAG/OCD
16 bit T/C 1
8 bit T/C 2
8 bit T/C 0
SRAMFLASH
USART 0
Internal
Bandgap reference
Analog
Comparator
A/D
Converter
PA7..0
PORT B (8)
PB7..0
USART 1
TOSC1/PC6TOSC2/PC7
The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus
processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
ATmega164P/V/324P/V/644P/V
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega164P/324P/644P provides the following features: 16K/32K/64K bytes of In-System Programmable
Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1K/2K/4K bytes SRAM, 32 general
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purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible
Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog
Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for
accessing the On-chip Debug system and programming and six software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue
functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other
chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC
Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize
switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the
rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using high-density nonvolatile memory technology. The On-chip ISP Flash allows
the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional
nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program
can use any interface to download the application program in the application Flash memory. Software in the
Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible and
cost effective solution to many embedded control applications.
The ATmega164P/324P/644P AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation
kits.
2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P
Table 2-1. Differences between ATmega164P and ATmega644P
Device Flash EEPROM RAM
ATmega164P 16 Kbyte 512 Bytes 1 Kbyte
ATmega324P 32 Kbyte 1 Kbyte 2 Kbyte
ATmega644P 64 Kbyte 2 Kbyte 4 Kbyte
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2.3 Pin Descriptions
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7:PA0)
Port A serves as analog inputs to the Analog-to-digital Converter.
Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs,
Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins
are tri-stated when a reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATmega164P/324P/644P as listed on page
87.
ATmega164P/V/324P/V/644P/V
2.3.4 Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tristated when a reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATmega164P/324P/644P as listed on page
88.
2.3.5 Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tristated when a reset condition becomes active, even if the clock is not running.
Port C also serves the functions of the JTAG interface, along with special features of the
ATmega164P/324P/644P as listed on page 91.
2.3.6 Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output
buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
2.3.7
Port D also serves the functions of various special features of the ATmega164P/324P/644P as listed on page
94.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running. The minimum pulse length is given in ”System and Reset Characteristics” on page 328.
Shorter pulses are not ensured to generate a reset.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 14
2.3.8 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.9 XTAL2
Output from the inverting Oscillator amplifier.
2.3.10 AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally connected
to V
CC
2.3.11 AREF
This is the analog reference pin for the Analog-to-digital Converter.
ATmega164P/V/324P/V/644P/V
, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 15
3. About
3.1 Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
www.microchip.com.
3.2 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the device. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is
compiler dependent. Refer to the C compiler documentation for more details.
The code examples assume that the part specific header file is included before compilation. For I/O registers
located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with
instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC",
"SBR", and "CBR".
3.3 Data Retention
ATmega164P/V/324P/V/644P/V
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over
20 years at 85°C or 100 years at 25°C.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 16
4. AVR CPU Core
Flash
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registrers
ALU
Status
and Control
I/O Lines
EEPROM
Data Bus 8-bit
Data
SRAM
Direct Addressing
Indirect Addressing
Interrupt
Unit
SPI
Unit
Watchdog
Timer
Analog
Comparator
I/O Module 2
I/O Module1
I/O Module n
4.1 Overview
This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure
correct program execution. The CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
Figure 4-1. Block Diagram of the AVR Architecture
ATmega164P/V/324P/V/644P/V
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate
memories and buses for program and data. Instructions in the program memory are executed with a single level
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory.
This concept enables instructions to be executed in every clock cycle. The program memory is In-System
Reprogrammable Flash memory.
The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 17
ATmega164P/V/324P/V/644P/V
operands are output from the Register File, the operation is executed, and the result is stored back in the
Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing
– enabling efficient address calculations. One of the these address pointers can also be used as an address
pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Zregister, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register.
Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is
updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the
whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address
contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the Application Program
section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that
writes into the Application Flash memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The
Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine
(before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space.
The data SRAM can easily be accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit
in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts
have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the
higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the
Register File, 0x20 - 0x5F. In addition, the ATmega164P/324P/644P has Extended I/O space from 0x60 - 0xFF
in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.
4.2 ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and
an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and
bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.
4.3 Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction.
This information can be used for altering program flow in order to perform conditional operations. Note that the
Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in
many cases remove the need for using the dedicated compare instructions, resulting in faster and more
compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 18
ATmega164P/V/324P/V/644P/V
4.3.1 SREG – Status Register
The AVR Status Register – SREG – is defined as:
Bit 76543210
0x3F (0x5F) I T H S V N Z C SREG
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable
control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of
the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by
hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the
Instruction Set Manual on www.microchip.com.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the
operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T
can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD
arithmetic.
(1)
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation.
Note: 1. Refer to the Instruction Set Manual on www.microchip.com for more details.
4.4 General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required
performance and flexibility, the following input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 19
ATmega164P/V/324P/V/644P/V
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2. AVR CPU General Purpose Working Registers
7 0 Addr.
R0 0x00
R1 0x01
R2 0x02
…
R13 0x0D
General R14 0x0E
Purpose R15 0x0F
Working R16 0x10
Registers R17 0x11
…
R26 0x1A X-register Low Byte
R27 0x1B X-register High Byte
R28 0x1C Y-register Low Byte
R29 0x1D Y-register High Byte
R30 0x1E Z-register Low Byte
R31 0x1F Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and most of them are
single cycle instructions.
As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the
first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this
memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers
can be set to index any register in the file.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 20
4.4.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit
address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are
defined as described in Figure 4-3.
Figure 4-3. The X-, Y-, and Z-registers
15 XH XL 0
X-register 7 0 7 0
R27 (0x1B) R26 (0x1A)
15 YH YL 0
Y-register 7 0 7 0
R29 (0x1D) R28 (0x1C)
15 ZH ZL 0
Z-register 7 0 7 0
R31 (0x1F) R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic
increment, and automatic decrement (see the instruction set reference for details).
ATmega164P/V/324P/V/644P/V
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses
after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower
memory locations. The Stack Pointer Register always points to the top of the Stack. The Stack Pointer points to
the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. A Stack PUSH command will
decrease the Stack Pointer.
The Stack in the data SRAM must be defined by the program before any subroutine calls are executed or
interrupts are enabled. Initial Stack Pointer value equals the last address of the internal SRAM and the Stack
Pointer must be set to point above start of the SRAM, see Figure 5-2 on page 28.
See Table 4-1 for Stack Pointer details.
Table 4-1. Stack Pointer instructions
Instruction Stack Pointer Description
PUSH Decremented by 1 Data is pushed onto the stack
CALL
ICALL
RCALL
POP Incremented by 1 Data is popped from the stack
RET
RETI
Decremented by 2 Return address is pushed onto the stack with a subroutine call or
Incremented by 2 Return address is popped from the stack with return from
interrupt
subroutine or return from interrupt
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used
is implementation dependent, see Table 4-2 on page 22. Note that the data space in some implementations of
the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 21
ATmega164P/V/324P/V/644P/V
4.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low
Bit 151413121110 9 8
0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH
0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL
76543210
Read/Write R R R R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0/0/1
11111111
Note: 1. Initial values respectively for the ATmega164P/324P/644P.
Table 4-2. Stack Pointer size
Device Stack Pointer size
ATmega164P SP[10:0]
ATmega324P SP[11:0]
ATmega644P SP[12:0]
(1)
0/1/0
(1)
1/0/0
(1)
00
4.5.2 RAMPZ – Extended Z-pointer Register for ELPM/SPM
Bit 765432 1 0
0x3B (0x5B)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0
For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4.
Note that LPM is not affected by the RAMPZ setting.
Figure 4-4. The Z-pointer used by ELPM and SPM
Bit (Individually) 7 0 7 0 7 0
RAMPZ ZH ZL
Bit (Z-pointer) 23 16 15 8 7 0
The actual number of bits is implementation dependent. Unused bits in an implementation will always read as
zero. For compatibility with future devices, be sure to write these bits to zero.
4.6 Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by
the CPU clock clk
used.
Figure 4-5 on page 23 shows the parallel instruction fetches and instruction executions enabled by the Harvard
architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to
1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions
per power-unit.
, directly generated from the selected clock source for the chip. No internal clock division is
CPU
RAMPZ
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 22
ATmega164P/V/324P/V/644P/V
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1 T2 T3 T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1 T2 T3 T4
clk
CPU
Figure 4-5. The Parallel Instruction Fetches and Instruction Executions
Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using
two register operands is executed, and the result is stored back to the destination register.
Figure 4-6. Single Cycle ALU Operation
4.7 Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each
have a separate program vector in the program memory space. All interrupts are assigned individual enable bits
which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to
enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when
Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section
”Memory Programming” on page 292 for details.
The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.
The complete list of vectors is shown in ”Interrupts” on page 68. The list also determines the priority levels of the
different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and
next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot
Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 68
for more information. The Reset Vector can also be moved to the start of the Boot Flash section by
programming the BOOTRST Fuse, see ”Memory Programming” on page 292.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user
software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the
current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is
executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For
these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt
handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by
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ATmega164P/V/324P/V/644P/V
writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the
corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global
Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not
necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the
interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one more
instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when
returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will
be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following
example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG
value
cli ; disable interrupts during timed
sequence
sbi EECR, EEMPE ; start
EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore
SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store
SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any
pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep ; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 24
4.7.1 Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock
cycles the program vector address for the actual interrupt handling routine is executed. During these five clock
cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt
routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle
instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in
sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in
addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program
Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in
SREG is set.
ATmega164P/V/324P/V/644P/V
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 25
ATmega164P/V/324P/V/644P/V
5. AVR Memories
5.1 Overview
This section describes the different memories in the ATmega164P/324P/644P. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATmega164P/324P/644P features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
5.2 In-System Reprogrammable Flash Program Memory
The ATmega164P/324P/644P contains 16K/32K/64K bytes On-chip In-System Reprogrammable Flash memory
for program storage. Since all AVR instructions are 16 bits or 32 bits wide, the Flash is organized as 32/64 x 16.
For software security, the Flash Program memory space is divided into two sections, Boot Program section and
Application Program section.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega164P/324P/644P
Program Counter (PC) is 15/16 bits wide, thus addressing the 32/64K program memory locations. The operation
of Boot Program section and associated Boot Lock bits for software protection are described in detail in
”Memory Programming” on page 292. ”Memory Programming” on page 292 contains a detailed description on
Flash data serial downloading using the SPI pins or the JTAG interface.
Constant tables can be allocated within the entire program memory address space (see the LPM – Load
Program Memory instruction description.
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Timing” on page 22.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 26
Figure 5-1. Program Memory Map
ATmega164P/V/324P/V/644P/V
Program Memory
0x0000
Application Flash Section
5.3 SRAM Data Memory
Figure 5-2 shows how the ATmega164P/324P/644P SRAM Memory is organized.
The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported
within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from
$060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
The first 4,352 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory,
and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard
I/O Memory, then 160 locations of Extended I/O memory and the next 4,096 locations address the internal data
SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect,
Indirect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature
the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Zregister.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address
registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the
1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all
these addressing modes. The Register File is described in ”General Purpose Register File” on page 19.
Boot Flash Section
0x1FFF
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 27
ATmega164P/V/324P/V/644P/V
F
Data Memory
clk
WR
RD
Data
Data
Address
Address valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction
Figure 5-2. Data Memory Map for ATmega164P/324P/644P
5.3.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM
access is performed in two clk
Figure 5-3. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
160 Ext I/O Reg.
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
Internal SRAM
(1024/2048/4096 x 8)
0x04FF/0x08FF/0x10F
cycles as described in Figure 5-3.
CPU
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 28
5.4 EEPROM Data Memory
The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following,
specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see page 306, page
310, and page 295 respectively.
5.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space. See ”Register Description” on page 31 for
details.
The write access time for the EEPROM is given in Table 5-2 on page 33. A self-timing function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as
minimum for the clock frequency used. See Section “5.4.2” on page 29. for details on how to avoid problems in
these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.
When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
ATmega164P/V/324P/V/644P/V
is likely to rise or fall slowly
CC
5.4.2 Preventing EEPROM Corruption
During periods of low V
the EEPROM data can be corrupted because the supply voltage is too low for the
CC,
CPU and the EEPROM to operate properly. These issues are the same as for board level systems using
EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can
execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by following this design recommendation:
Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by
enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the
needed detection level, an external low V
operation is in progress, the write operation will be completed provided that the power supply voltage is
sufficient.
reset Protection circuit can be used. If a reset occurs while a write
CC
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 29
5.5 I/O Memory
The I/O space definition of the ATmega164P/324P/644P is shown in ”Register Summary” on page 476.
All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose
working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bitaccessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by
using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O
specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers
as data space using LD and ST instructions, 0x20 must be added to these addresses. The
ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within
the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory
addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the
CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing
such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
ATmega164P/V/324P/V/644P/V
The ATmega164P/324P/644P contains three General Purpose I/O Registers, see ”Register Description” on
page 31. These registers can be used for storing any information, and they are particularly useful for storing
global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are
directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
2018 Microchip Technology Inc. Data Sheet Complete DS40002071A-page 30
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