ATMEL AT91SAM9261 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• Incorporates the ARM926EJ-S™ ARM

– DSP Instruction Extensions – ARM Jazelle – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 210 MIPS at 190 MHz – Memory Management Unit – EmbeddedICE – Mid-level implementation Embedded Trace Macrocell

• Additional Embedded Memories

– 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed – 160 Kbytes of Internal SRAM, Single-cycle Access at Maximum Processor or Bus

Speed

• External Bus Interface (EBI)

– Supports SDRAM, Static Memory, NAND Flash and CompactFlash

• LCD Controller

– Supports Passive or Active Displays – Up to 16-bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 2048 x 2048

• USB

– USB 2.0 Full Speed (12 Mbits per second) Host Double Port

• Dual On-chip Transceivers

• Integrated FIFOs and Dedicated DMA Channels

– USB 2.0 Full Speed (12 Mbits per second) Device Port

• On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs

• Bus Matrix

– Handles Five Masters and Five Slaves – Boot Mode Select Option – Remap Command

• Fully Featured System Controller (SYSC) for Efficient System Management, including

– Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a

Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer – Three 32-bit PIO Controllers

• Reset Controller (RSTC)

– Based on Power-on Reset Cells, Reset Source Identification and Reset Output

Control

• Shutdown Controller (SHDWC)

– Programmable Shutdown Pin Control and Wake-up Circuitry

• Clock Generator (CKGR)

– 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a

Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and two PLLs

• Power Management Controller (PMC)

– Very Slow Clock Operating Mode, Software Programmable Power Optimization

Capabilities – Four Programmable External Clock Signals

Technology for Java® Acceleration

™

, Debug Communication Channel Support

Thumb® Processor

™

AT91 ARM Thumb-based Microcontrollers

AT91SAM9261

Preliminary

Summary

NOTE: This is a summary document.

The complete document is available on the Atmel website at www.atmel.com.

6062JS–ATARM–06-Feb-08

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected

• Debug Unit (DBGU)

– 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention

• Periodic Interval Timer (PIT)

– 20-bit Interval Timer plus 12-bit Interval Counter

• Watchdog Timer (WDT)

– Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock

• Real-Time Timer (RTT)

– 32-bit Free-running Backup Counter Running at Slow Clock

• Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC

– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

• Nineteen Peripheral DMA (PDC) Channels

• Multimedia Card Interface (MCI)

– SDCard and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant

• Three Synchronous Serial Controllers (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA – Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support

Infrared Modulation/Demodulation

• Two Master/Slave Serial Peripheral Interface (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

• One Three-channel 16-bit Timer/Counters (TC)

– Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

• Two-wire Interface (TWI)

– Master Mode Support, All Two-wire Atmel EEPROMs Supported

• IEEE

1149.1 JTAG Boundary Scan on All Digital Pins

• Required Power Supplies:

– 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 1.95V and 3.0V to 3.6V for VDDIOM (Memory I/Os)

• Available in a 217-ball LFBGA RoHS-compliant Package

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

1. Description

AT91SAM9261 Preliminary

The AT91SAM9261 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 210 MIPS at 190 MHz.

The AT91SAM9261 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The 160 Kbyte integrated SRAM can be configured as a frame buffer minimizing the impact for LCD refresh on the overall processor performance. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash.

The AT91SAM9261 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash ment Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency.

The AT91SAM9261 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints.

into external SDRAM. The software controlled Power Manage-

6062JS–ATARM–06-Feb-08

2. Block Diagram

Figure 2-1. AT91SAM9261 Block Diagram

JTAGSEL

TDI TDO TMS TCK

NTRST

RTCK

TST

FIQ

IRQ0-IRQ2

DRXD DTXD

PCK0-PCK3

PLLRCA PLLRCB

XIN

XOUT

XIN32

XOUT32

SHDN

WKUP

VDDBU GNDBU

VDDCORE

NRST

MCCK

MCCDA

MCDA0-MCDA3

RXD0 TXD0 SCK0

RTS0

CTS0

RXD1 TXD1 SCK1

RTS1

CTS1 RXD2

TXD2 SCK2

RTS2

CTS2

SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3

SPI0_MISO SPI0_MOSI

SPI0_SPCK

SPI1_NPCS10

SPI1_NPCS1

SPI1_NPCS12

SPI1_NPCS3

SPI1_MISO SPI1_MOSI

SPI1_SPCK

JTAG

Boundary Scan

System Controller

AIC

PIO

DBGU

PDC

PLLA

GPBREG

PIO

PMC

PIT

RTT

SHDWC

RSTC

PLLB

OSC

WDT

OSC

POR

PIOA PIOB PIOC

MCI

USART0

USART1

USART2

SPI0

SPI1

ICE

ITCM DTCM

PDC

Instruction Cache

16K bytes

TCM

Interface

Fast SRAM 160K bytes

Fast ROM 32K bytes

Peripheral

Bridge

Peripheral

DMA

Controller

APB

ARM926EJ-S Core

MMU

5-layer

Matrix

Data Cache

16K bytes

BIU

DMA FIFO

FIFO

DMA

FIFO

LUT

LCD Controller

PDC

Timer Counter

ETM

EBI

CompactFlash

NAND Flash

SDRAM

Controller

Static

Memory

Controller

USB Host

USB Device

SSC0

SSC1

SSC2

TC0

TC1

TC2

TWI

TSYNC TCLK

PIO

TPS0-TPS2 TPK0-TPK15

BMS D0-D15

A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A22/REG A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0

PIO

NCS5/CFCS1 CFCE1

CFCE2 NCS6/NANDOE NCS7/NANDWE D16-D31

HDMA HDPA

HDMB HDPB

DDM DDP

LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC

TF0 TK0 TD0 RD0 RK0 RF0

TF1 TK1 TD1 RD1 RK1 RF1

TF2 TK2

TD2 RD2 RK2 RF2

TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2

TWD TWCK

PIO

Transceiver

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

AT91SAM9261 Preliminary

3. Signal Description

Table 3-1. Signal Description by Peripheral

Signal Name Function Type Active Level Comments

Power

VDDIOM EBI I/O Lines Power Supply Power 1.65 V to 1.95V and 3.0V to 3.6V VDDIOP Peripherals I/O Lines Power Supply Power 2.7V to 3.6V VDDBU Backup I/O Lines Power Supply Power 1.08V to 1.32V VDDPLL PLL Power Supply Power 3.0V to 3.6V VDDOSC Oscillator Power Supply Power 3.0V to 3.6V VDDCORE Core Chip Power Supply Power 1.08V to 1.32V GND Ground Ground GNDPLL PLL Ground Ground GNDOSC Oscillator Ground Ground GNDBU Backup Ground Ground

Clocks, Oscillators and PLLs

XIN Main Oscillator Input Input XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output PLLRCA PLL Filter Input PLLRCB PLL Filter Input PCK0 - PCK3 Programmable Clock Output Output

Shutdown, Wakeup Logic

SHDN Shutdown Control Output Do not tie over VDDBU. WKUP Wake-Up Input Input Accepts between 0V and VDDBU.

ICE and JTAG

TCK Test Clock Input No pull-up resistor. RTCK Returned Test Clock Output No pull-up resistor. TDI Test Data In Input No pull-up resistor. TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor. NTRST Test Reset Signal Input Low Pull-up resistor.

JTAGSEL JTAG Selection Input

™

ETM

TSYNC Trace Synchronization Signal Output TCLK Trace Clock Output TPS0 - TPS2 Trace ARM Pipeline Status Output TPK0 - TPK15 Trace Packet Port Output

Pull-down resistor. Accepts between 0V and VDDBU.

6062JS–ATARM–06-Feb-08

Table 3-1. Signal Description by Peripheral (Continued)

Signal Name Function Type Active Level Comments

Reset/Test

NRST Microcontroller Reset I/O Low Pull-up resistor TST Test Mode Select Input Pull-down resistor. BMS Boot Mode Select Input

Debug Unit

DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

AIC

IRQ0 - IRQ2 External Interrupt Inputs Input FIQ Fast Interrupt Input Input

PIO

PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset PC0 - PC31 Parallel IO Controller C I/O Pulled-up input at reset

EBI

D0 - D31 Data Bus I/O Pulled-up input at reset A0 - A25 Address Bus Output 0 at reset NWAIT External Wait Signal Input Low

SMC

NCS0 - NCS7 Chip Select Lines Output Low NWR0 - NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0 - NBS3 Byte Mask Signal Output Low

CompactFlash Support

CFCE1 - CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output CFCS0 - CFCS1 CompactFlash Chip Select Lines Output Low

NAND Flash Support

NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDCS NAND Flash Chip Select Output Low

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

AT91SAM9261 Preliminary

Table 3-1. Signal Description by Peripheral (Continued)

Signal Name Function Type Active Level Comments

SDRAM Controller

SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA0 - BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output

Multimedia Card Interface

MCCK Multimedia Card Clock Output MCCDA Multimedia Card A Command I/O MCDA0 - MCDA3 Multimedia Card A Data I/O

USART

SCK0 - SCK2 Serial Clock I/O TXD0 - TXD2 Transmit Data Output RXD0 - RXD2 Receive Data Input RTS0 - RTS2 Request To Send Output CTS0 - CTS2 Clear To Send Input

Synchronous Serial Controller

TD0 - TD2 Transmit Data Output RD0 - RD2 Receive Data Input TK0 - TK2 Transmit Clock I/O RK0 - RK2 Receive Clock I/O TF0 - TF2 Transmit Frame Sync I/O RF0 - RF2 Receive Frame Sync I/O

Timer/Counter

TCLK0 - TCLK2 External Clock Input Input TIOA0 - TIOA2 I/O Line A I/O TIOB0 - TIOB2 I/O Line B I/O

SPI

SPI0_MISO SPI1_MISO

SPI0_MOSI SPI1_MOSI

SPI0_SPCK SPI1_SPCK

SPI0_NPCS0, SPI1_NPCS0

SPI0_NPCS1 SPI0_NPCS3

SPI1_NPCS1 SPI1_NPCS3

Master In Slave Out I/O

Master Out Slave In I/O

SPI Serial Clock I/O

SPI Peripheral Chip Select 0 I/O Low

SPI Peripheral Chip Select Output Low

6062JS–ATARM–06-Feb-08

Table 3-1. Signal Description by Peripheral (Continued)

Signal Name Function Type Active Level Comments

Two-Wire Interface

TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O

LCD Controller

LCDD0 - LCDD23 LCD Data Bus Output LCDVSYNC LCD Vertical Synchronization Output LCDHSYNC LCD Horizontal Synchronization Output LCDDOTCK LCD Dot Clock Output LCDDEN LCD Data Enable Output LCDCC LCD Contrast Control Output

USB Device Port

DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog

USB Host Port

HDMA USB Host Port A Data - Analog HDPA USB Host Port A Data + Analog HDMB USB Host Port B Data - Analog HDPB USB Host Port B Data + Analog

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

4. Package and Pinout

The AT91SAM9261 is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm, 0.8 mm ball pitch

4.1 217-ball LFBGA Package Outline

Figure 4-1 shows the orientation of the 217-ball LFBGA Package.

A detailed mechanical description is given in the section “AT91SAM9261 Mechanical Characteristics” of the product datasheet.

Figure 4-1. 217-ball LFBGA Package Outline (Top View)

AT91SAM9261 Preliminary

17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

Ball A1

ABCDEFGHJ K LMNPRTU

6062JS–ATARM–06-Feb-08

4.2 Pinout

Table 4-1. AT91SAM9261 Pinout for 217-ball LFBGA Package

(1)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 A19 D5 VDDCORE J14 VDDIOP P17 PA20 A2 A16/BA0 D6 A10 J15 PB9 R1 PC19 A3 A14 D7 A5 J16 PB6 R2 PC21 A4 A12 D8 A0/NBS0 J17 PB4 R3 GND A5 A9 D9 SHDN K1 D6 R4 PC27 A6 A6 D10 NC K2 D8 R5 PC29 A7 A3 D11 VDDIOP K3 D10 R6 PC4 A8 A2 D12 PB29 K4 D7 R7 PC8 A9 NC D13 PB28 K8 GND R8 PC12 A10 XOUT32 D14 PB23 K9 GND R9 PC14 A11 XIN32 D15 PB20 K10 GND R10 VDDPLL A12 DDP D16 PB17 K14 VDDCORE R11 PA0 A13 HDPB D17 TCK K15 PB3/BMS R12 PA7 A14 HDMB A15 PB27 A16 GND A17 PB24 B1 A20 E14 PB22 L3 D12 R17 PA18 B2 A18 E15 PB18 L4 VDDIOM T1 PC20 B3 A15 E16 PB15 L14 PA30 T2 PC23 B4 A13 E17 TDI L15 PA27 T3 PC26 B5 A11 F1 SDCKE L16 PA31 T4 PC2 B6 A7 F2 RAS L17 PB0 T5 VDDIOP B7 A4 F3 NWR3/NBS3/CFIOW M1 D13 T6 PC5 B8 A1/NBS2/NWR2 F4 NCS0 M2 D15 T7 PC9 B9 VDDBU F14 PB16 B10 JTAGSEL F15 NRST M4 VDDCORE T9 PC15 B11 WKUP F16 TDO M14 PA25 T10 VDDOSC B12 DDM F17 NTRST M15 PA26 T11 GNDOSC B13 PB31 B14 HDMA B15 PB26 B16 PB25 B17 PB19 G14 PB14 C1 A22 G15 PB12 N4 VDDIOM T17 PA14 C2 A21 G16 PB11 N14 PA22 U1 PC25 C3 VDDIOM G17 PB8 N15 PA21 U2 PC0 C4 A17/BA1 H1 D2 N16 PA23 U3 PC3 C5 VDDIOM H2 D3 N17 PA24 U4 GND C6 A8 H3 VDDIOM P1 PC16 U5 PC6 C7 GND C8 VDDIOM H8 GND P3 PC22 U7 GND C9 GNDBU H9 GND C10 TST H10 GND C11 GND H14 PB10 P6 PC1 U10 PLLRCA C12 HDPA H15 PB13 P7 PC7 U11 XIN C13 PB30 H16 PB7 P8 PC11 U12 XOUT C14 NC H17 PB5 P9 GNDPLL U13 PA2 C15 VDDIOP C16 PB21 C17 TMS J3 GND P12 VDDCORE U16 PA9 D1 NCS2 J4 CAS P13 PA15 U17 RTCK D2 NCS1/SDCS J8 GND P14 PA16 D3 GND J9 GND P15 VDDIOP D4 VDDIOM J10 GND P16 PA19

E1 NWR1/NBS1/CFIOR K16 PB1 R13 PA10 E2 NWR0/NWE/CFWE K17 PB2 R14 PA13 E3 NRD/CFOE L1 D9 R15 PA17 E4 SDA10 L2 D11 R16 GND

M3 PC18 T8 PC10

G1 D0 M16 PA28 T12 PA1 G2 D1 M17 PA29 T13 PA4 G3 SDWE N1 D14 T14 PA6 G4 NCS3/NANDCS N2 PC17 T15 PA8

N3 PC31 T16 PA11

H4 SDCK P2 PC30 U6 VDDIOP

P4 PC24 U8 PC13 P5 PC28 U9 PLLRCB

J1 D4 P10 PA3 U14 PA5 J2 D5 P11 VDDIOP U15 PA12

Note: 1. Shaded cells define the pins powered by VDDIOM.

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

5. Power Considerations

5.1 Power Supplies

The AT91SAM9261 has six types of power supply pins:

• VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal.

• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to

1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal.

• VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from

2.7V and 3.6V, 3.3V nominal.

• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal.

• VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal.

• VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal.

The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals.

AT91SAM9261 Preliminary

Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are GNDBU, GNDOSC and GNDPLL, respectively.

5.2 Power Consumption

The AT91SAM9261 consumes about 550 µA of static current on VDDCORE at 25°C. This static current rises at up to 5.5 mA if the temperature increases to 85°C.

On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C.

For dynamic power consumption, the AT91SAM9261 consumes a maximum of 50 mA on VDDCORE at maximum speed in typical conditions (1.2V, 25°C), processor running full-performance algorithm.

6. I/O Line Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.

6062JS–ATARM–06-Feb-08

The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 kΩ to VDDIOP, so that it can be left unconnected for normal operations.

6.2 Test Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.

6.3 Reset Pin

NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product.

The NRST pin integrates a permanent pull-up resistor of 100 kΩ minimum to VDDIOP.

The NRST signal is inserted in the Boundary Scan.

6.4 PIO Controller A, B and C Lines

All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up resistor of 100 kΩ. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers.

After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables.

6.5 Shutdown Logic Pins

The SHDN pin is an output only, driven by Shutdown Controller.

The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

7. Processor and Architecture

7.1 ARM926EJ-S Processor

• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set

• DSP Instruction Extensions

• 5-Stage Pipeline Architecture:

– Instruction Fetch (F) – Instruction – Execute (E) – Data Memory (M) – Register Write (W)

• 16 Kbyte Data Cache, 16 Kbyte Instruction Cache

– Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement

• Write Buffer

– Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain

• Standard ARM v4 and v5 Memory Management Unit (MMU)

– Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for

each quarter of the page

– 16 embedded domains

• Bus Interface Unit (BIU)

– Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete AHB

system flexibility

– Separate Address and Data Buses for both the 32-bit instruction interface and the

32-bit data interface

– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit

(Words)

Decode (D)

AT91SAM9261 Preliminary

6062JS–ATARM–06-Feb-08

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