• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP
Package and Double Port in 217-ball LFBGA Package
– Single or Dual On-chip Transceivers
– Integrated FIFOs and Dedicated DMA Channels
• Ethernet MAC 10/100 Base T
– Media Independent Interface or Reduced Media Independent Interface
– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
• Image Sensor Interface
– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
– 12-bit Data Interface for Support of High Sensibility Sensors
– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer
• Reset Controller (RSTC)
– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
Control
• Clock Generator (CKGR)
– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization
Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Three External Interrupt Sources and One Fast Interrupt Source, Spurious
Interrupt Protected
™
ARM® Thumb® Processor
®
Technology for Java® Acceleration
AT91 ARM
®
Thumb
Microcontrollers
AT91SAM9260
Summary
6221HS–ATARM–31-Jan-08
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• One 4-channel 10-bit Analog-to-Digital Converter
• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC)
– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
– High-current Drive I/O Lines, Up to 16 mA Each
• Peripheral DMA Controller Channels (PDC)
• One Two-slot MultiMedia Card Interface (MCI)
™
– SDCard/SDIO and MultiMediaCard
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
Compliant
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Signal Control on USART0
• Two 2-wire UARTs
• Two Master/Slave Serial Peripheral Interfaces (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– Synchronous Communications
• Two Three-channel 16-bit Timer/Counters (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2
• One Two-wire Interface (TWI)
– Master, Multi-master and Slave Mode Operation
– General Call Supported in Slave Mode
®
• IEEE
1149.1 JTAG Boundary Scan on All Digital Pins
• Required Power Supplies:
– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL
– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)
– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)
• Available in a 208-lead PQFP Green and a 217-ball LFBGA Green Package
2
AT91SAM9260
6221HS–ATARM–31-Jan-08
1.Description
The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM
and RAM memories and a wide range of peripherals.
The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer
Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface.
The AT91SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth
of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide
range of memory devices.
2.AT91SAM9260 Block Diagram
The block diagram shows all the features for the 217-LFBGA package. Some functions are not
accessible in the 208-pin PQFP package and the unavailable pins are highlighted in “Multiplex-
ing on PIO Controller A” on page 34, “Multiplexing on PIO Controller B” on page 35,
“Multiplexing on PIO Controller C” on page 36. The USB Host Port B is not available in the 208-
pin package. Table 2-1 on page 3 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.
AT91SAM9260
Table 2-1.Unavailable Signals in 208-lead PQFP Package
VDDIOMEBI I/O Lines Power SupplyPower1.65V to 1.95V or 3.0V to3.6V
VDDIOP0Peripherals I/O Lines Power SupplyPower 3.0V to 3.6V
VDDIOP1Peripherals I/O Lines Power SupplyPower 1.65V to 3.6V
VDDBUBackup I/O Lines Power SupplyPower1.65V to 1.95V
VDDANAAnalog Power SupplyPower3.0V to 3.6V
VDDPLLPLL Power SupplyPower1.65V to 1.95V
VDDCORECore Chip Power SupplyPower1.65V to 1.95V
GNDGroundGround
GNDPLLPLL and Oscillator GroundGround
GNDANAAnalog GroundGround
GNDBUBackup GroundGround
SCKxUSARTx Serial ClockI/O
TXDxUSARTx Transmit DataI/O
RXDxUSARTx Receive DataInput
RTSxUSARTx Request To SendOutput
CTSxUSARTx Clear To Send Input
DTR0USART0 Data Terminal ReadyOutput
DSR0USART0 Data Set ReadyInput
DCD0USART0 Data Carrier DetectInput
RI0USART0 Ring IndicatorInput
TCLKxTC Channel x External Clock InputInput
TIOAxTC Channel x I/O Line AI/O
TIOBxTC Channel x I/O Line BI/O
Serial Peripheral Interface - SPIx_
SPIx_MISOMaster In Slave OutI/O
SPIx_MOSIMaster Out Slave InI/O
SPIx_SPCKSPI Serial ClockI/O
SPIx_NPCS0SPI Peripheral Chip Select 0I/OLow
SPIx_NPCS1-SPIx_NPCS3SPI Peripheral Chip SelectOutputLow
Two-Wire Interface
TWDTwo-wire Serial Data I/O
TWCKTwo-wire Serial ClockI/O
USB Host Port
HDPAUSB Host Port A Data +Analog
HDMAUSB Host Port A Data -Analog
HDPBUSB Host Port B Data +Analog
HDMBUSB Host Port B Data +Analog
USB Device Port
DDMUSB Device Port Data -Analog
DDPUSB Device Port Data +Analog
Ethernet 10/100
ETXCKTransmit Clock or Reference ClockInputMII only, REFCK in RMII
ERXCKReceive ClockInputMII only
ETXENTransmit EnableOutput
ETX0-ETX3Transmit DataOutputETX0-ETX1 only in RMII
ETXERTransmit Coding ErrorOutputMII only
ERXDVReceive Data ValidInputRXDV in MII , CRSDV in RMII
ERX0-ERX3Receive DataInputERX0-ERX1 only in RMII
ERXERReceive ErrorInput
ECRSCarrier Sense and Data ValidInputMII only
ECOLCollision DetectInputMII only
EMDCManagement Data ClockOutput
EMDIOManagement Data Input/OutputI/O
EF100Force 100Mbit/sec.OutputHigh
The AT91SAM9260 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal.
• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and
1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is
selectable by software.
• VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from
3.0V and 3.6V, 3V or 3.3V nominal.
• VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage
ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.65V to 1.95V, 1.8V nominal.
• VDDPLL pin: Powers the Main Oscillator and PLL cells; voltage ranges from 1.65V and
1.95V, 1.8V nominal.
• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V,
3.3V nominal.
The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the
multiplexing tables. These supplies enable the user to power the device differently for interfacing
with memories and for interfacing with peripherals.
Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power
supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These
ground pins are respectively GNDBU, GNDPLL and GNDANA.
5.2Power Consumption
The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static
current rises up to 5 mA if the temperature increases to 85°C.
On VDDBU, the current does not exceed 10 µA in worst case conditions.
For dynamic power consumption, the AT91SAM9260 consumes a maximum of 100 mA on
VDDCORE at maximum conditions (1.8V, 25°C, processor running full-performance algorithm
out of high speed memories).
14
AT91SAM9260
6221HS–ATARM–31-Jan-08
5.3Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its
maximum speed either out of 1.8V or 3.3V external memories.
The target maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for
power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address
and data signals) do not exceed 50 MHz.
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either
1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to
the pins is 1.8V only. The user must program the EBI voltage range before getting the device out
of its Slow Clock Mode.
6.I/O Line Considerations
6.1JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.
AT91SAM9260
6.2Test Pin
6.3Reset Pins
TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied
to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it
can be left unconnected for normal operations.
The NTRST signal is described in Section 6.3.
All the JTAG signals are supplied with VDDIOP0.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
6221HS–ATARM–31-Jan-08
The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value
can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Characteristics” in the product datasheet.
The NRST signal is inserted in the Boundary Scan.
15
6.4PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor.
Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for
more information. Programming of this pull-up resistor is performed independently for each I/O
line through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
6.5I/O Line Drive Levels
The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently except PC4 to PC31 that are VDDIOM powered.
6.6Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
6.7Slow Clock Selection
The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the
on-chip RC oscillator.
Table 6-1 defines the states for OSCSEL signal.
Table 6-1.Slow Clock Selection
OSCSELSlow ClockStartup Time
0Internal RC240 µs
1External 32768 Hz1200 ms
The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The
32,768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to
Table 6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the
device.
7.Processor and Architecture
7.1ARM926EJ-S Processor
• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
• Two Instruction Sets
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
– Virtually-addressed 4-way Associative Cache
– Eight words per line
– Write-through and Write-back Operation
– Pseudo-random or Round-robin Replacement
• Write Buffer
– Main Write Buffer with 16-word Data Buffer and 4-address Buffer
– DCache Write-back Buffer with 8-word Entries and a Single Address Entry
– Software Control Drain
• Standard ARM v4 and v5 Memory Management Unit (MMU)
– Access Permission for Sections
– Access Permission for large pages and small pages can be specified separately for
each quarter of the page
– 16 embedded domains
• Bus Interface Unit (BIU)
– Arbitrates and Schedules AHB Requests
– Separate Masters for both instruction and data access providing complete Matrix
system flexibility
– Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
7.2Bus Matrix
6221HS–ATARM–31-Jan-08
• 6-layer Matrix, handling requests from 6 masters
• Programmable Arbitration strategy
– Fixed-priority Arbitration
– Round-Robin Arbitration, either with no default master, last accessed default master
or fixed default master
• Burst Management
– Breaking with Slot Cycle Limit Support
– Undefined Burst Length Support
• One Address Decoder provided per Master
– Three different slaves may be assigned to each decoded memory area: one for
internal boot, one for external boot, one after remap
• Boot Mode Select
– Non-volatile Boot Memory can be internal or external
– Selection is made by BMS pin sampled at reset
17
7.2.1Matrix Masters
7.2.2Matrix Slaves
• Remap Command
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
The Bus Matrix of the AT91SAM9260 manages six Masters, which means that each master can
perform an access concurrently with others, according the slave it accesses is available.
Each Master has its own decoder that can be defined specifically for each master. In order to
simplify the addressing, all the masters have the same decodings.
Table 7-1.List of Bus Matrix Masters
Master 0ARM926™ Instruction
Master 1ARM926 Data
Master 2PDC
Master 3USB Host DMA
Master 4ISI Controller
Master 5Ethernet MAC
Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.
Table 7-2.List of Bus Matrix Slaves
Slave 0Internal SRAM0 4 KBytes
Slave 1Internal SRAM1 4 KBytes
Slave 2
Slave 3External Bus Interface
Slave 4Internal Peripherals
7.2.3Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths
are forbidden or simply not wired, and shown “-” in the following table.
Table 7-3.AT91SAM9260 Masters to Slaves Access
0
1
Internal ROM
USB Host User Interface
Master0 & 12345
Slave
Internal SRAM
4 KBytes
Internal SRAM
4 KBytes
ARM926
Instruction &
Data
X XXXX
X XXXX
Peripheral
DMA
Controller
USB Host
Controller
ISI
Controller
Ethernet
MAC
18
AT91SAM9260
6221HS–ATARM–31-Jan-08
Table 7-3.AT91SAM9260 Masters to Slaves Access
AT91SAM9260
2
3External Bus InterfaceX XXXX
4Internal PeripheralsXXX--
Internal ROMXXX--
UHP User InterfaceX ----
7.3Peripheral DMA Controller
• Acting as one Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Twenty-two channels
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for Multimedia Card Interface
– One for Analog-to-Digital Converter
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
• Debug Unit
–Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
20
AT91SAM9260
6221HS–ATARM–31-Jan-08
8.Memories
Figure 8-1.AT91SAM9260 Memory Mapping
Address Memory Space
0x0000 0000
0x0FFF FFFF
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF
0x9000 0000
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
Internal Memories
EBI
Chip Select 0
EBI
Chip Select 1/
SDRAMC
EBI
Chip Select 2
EBI
Chip Select 3/
NANDFlash
EBI
Chip Select 4/
Compact Flash
Slot 0
EBI
Chip Select 5/
Compact Flash
Slot 1
EBI
Chip Select 6
EBI
Chip Select 7
Undefined
(Abort)
Internal Peripherals
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
1,518M Bytes
256M Bytes
0xF000 0000
0xFFFA 0000
0xFFFA 4000
0xFFFA 8000
0xFFFA C000
0xFFFB 0000
0xFFFB 4000
0xFFFB 8000
0xFFFB C000
0xFFFC 0000
0xFFFC 4000
0xFFFC 8000
0xFFFC C000
0xFFFD 0000
0xFFFD 4000
0xFFFD 8000
0xFFFD C000
0xFFFE 0000
0xFFFE 4000
0xFFFF C000
0xFFFF FFFF
0x0000 0000
0x10 0000
0x10 8000
0x20 0000
0x20 1000
0x30 0000
0x30 1000
0x50 0000
0x50 4000
0x0FFF FFFF
Internal Memory Mapping
Boot Memory (1)
ROM
Reserved
SRAM0
Reserved
SRAM1
Reserved
UHP
Reserved
Peripheral Mapping
Reserved
TCO, TC1, TC2
UDP
MCI
TWI
USART0
USART1
USART2
SSC
ISI
EMAC
SPI0
SPI1
USART3
USART4
USART5
TC3, TC4, TC5
ADC
Reserved
SYSC
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
32K Bytes
4K Bytes
4K Bytes
16K Bytes
AT91SAM9260
Notes :
(1) Can be ROM, EBI_NCS0 or SRAM
depending on BMS and REMAP
System Controller Mapping
0xFFFF C000
0xFFFF E800
0xFFFF EA00
0xFFFF EC00
0xFFFF EE00
0xFFFF EF10
0xFFFF F000
0xFFFF F200
0xFFFF F400
0xFFFF F600
0xFFFF F800
0xFFFF FA00
0xFFFF FC00
0xFFFF FD00
0xFFFF FD10
0xFFFF FD20
0xFFFF FD30
0xFFFF FD40
0xFFFF FD50
0xFFFF FD60
0xFFFF FFFF
Reserved
ECC512 Bytes
512 BytesSDRAMC
512 BytesSMC
MATRIX
CCFG
AIC
DBGU
PIOA
PIOB
PIOC
Reserved
PMC
RSTC
SHDWC
RTTC
PITC
WDTC
GPBR
Reserved
512 Bytes
512 Bytes
512 Bytes
512 Bytes
512 bytes
512 bytes
256 Bytes
16 Bytes
16 Bytes
16 Bytes
16 Bytes
16 Bytes
16 Bytes
6221HS–ATARM–31-Jan-08
21
A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the
Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to
7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level
of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals
and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
Each Master has its own bus and its own decoder, thus allowing a different memory mapping
per Master. However, in order to simplify the mappings, all the masters have a similar address
decoding.
Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are
assigned to the memory space decoded at address 0x0: one for internal boot, one for external
boot, one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 22 for details.
A complete memory map is presented in Figure 8-1 on page 21.
8.1Embedded Memories
• 32 KB ROM
– Single Cycle Access at full matrix speed
• Two 4 KB Fast SRAM
– Single Cycle Access at full matrix speed
8.1.1Boot Strategies
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status and the BMS state at reset.
Table 8-1.Internal Memory Mapping
Address
0x0000 0000ROMEBI_NCS0SRAM0 4K
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. Refer to the Bus Matrix Section for more
details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in
REMAP = 0REMAP = 1
BMS = 1BMS = 0
Figure 8-1 on page 21.
22
AT91SAM9260
6221HS–ATARM–31-Jan-08
The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin
at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved
for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.1.1BMS = 1, Boot on Embedded ROM
The system boots using the Boot Program.
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
– SPI DataFlash
– 8-bit and/or 16-bit NANDFlash
• SAM-BA
®
Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device Port
®
connected on NPCS0 and NPCS1 of the SPI0
AT91SAM9260
8.1.1.2BMS = 0, Boot on External Memory
• Boot on slow clock (On-chip RC or 32,768 Hz)
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
The customer-programmed software must perform a complete configuration.
To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take
the following steps:
1. Program the PMC (main oscillator enable or bypass mode).
2. Program and start the PLL.
3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them
to the new clock.
4. Switch the main clock to the new value.
8.2External Memories
The external memories are accessed through the External Bus Interface. Each Chip Select line
has a 256-Mbyte memory area assigned.
Refer to the memory map in Figure 8-1 on page 21.
8.2.1External Bus Interface
• Integrates three External Memory Controllers
– Static Memory Controller
– SDRAM Controller
6221HS–ATARM–31-Jan-08
23
– ECC Controller
• Additional logic for NANDFlash
• Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear)
• Up to 8 chip selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
– Static Memory Controller on NCS6-NCS7
8.2.2Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Compliant with LCD Module
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
8.2.3SDRAM Controller
• Supported devices
• Numerous configurations supported
• Programming facilities
• Energy-saving capabilities
24
AT91SAM9260
– Standard and Low-power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Datapath
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh, power down and deep power down modes supported
6221HS–ATARM–31-Jan-08
• Error detection
– Refresh Error Interrupt
• SDRAM Power-up Initialization by software
• CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
8.2.4Error Corrected Code Controller
• Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select
• Single bit error correction and 2-bit Random detection
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes
pages
AT91SAM9260
6221HS–ATARM–31-Jan-08
25
9.System Controller
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a
set of registers for the chip configuration. The chip configuration registers configure EBI chip
select assignment and voltage range for external memories
The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address
space, between addresses 0xFFFF E800 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space. All
the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes.
Figure 9-1 on page 27 shows the System Controller block diagram.
Figure 8-1 on page 21 shows the mapping of the User Interfaces of the System Controller
peripherals.
26
AT91SAM9260
6221HS–ATARM–31-Jan-08
9.1Block Diagram
Figure 9-1.AT91SAM9260 System Controller Block Diagram
AT91SAM9260
NRST
VDDBU
SHDN
WKUP
OSC_SEL
XIN32
XOUT32
XIN
XOUT
PLLRCA
periph_irq[2..24]
pit_irq
rtt_irq
wdt_irq
dbgu_irq
pmc_irq
rstc_irq
periph_nreset
dbgu_rxd
periph_nreset
proc_nreset
VDDCORE
POR
VDDBU
POR
backup_nreset
RC
OSC
SLOW
CLOCK
OSC
MAIN
OSC
PLLA
PLLB
irq0-irq2
fiq
MCK
MCK
debug
SLCK
debug
idle
SLCK
SLCK
SLCK
backup_nreset
rtt0_alarm
SLCK
int
por_ntrst
jtag_nreset
MAINCK
PLLACK
PLLBCK
System Controller
Advanced
Interrupt
Controller
Debug
Unit
Periodic
Interval
Timer
Watchdog
Timer
Reset
Controller
Real-time
Timer
Shutdown
Controller
Power
Management
Controller
wdt_fault
WDRPROC
VDDCORE Powered
int
dbgu_irq
dbgu_txd
pit_irq
wdt_irq
rstc_irq
periph_nreset
proc_nreset
backup_nreset
VDDBU Powered
rtt_irq
rtt_alarm
4 General-purpose
Backup Registers
periph_clk[2..27]
pck[0-1]
PCK
UDPCK
UHPCK
MCK
por_ntrst
nirq
nfiq
proc_nreset
PCK
debug
jtag_nreset
MCK
periph_nreset
UHPCK
periph_clk[20]
periph_nreset
periph_irq[20]
UDPCK
periph_clk[10]
periph_nreset
periph_irq[10]
ntrst
ARM926EJ-S
Boundary Scan
TAP Controller
Bus Matrix
USB Host
Por t
USB
Device
Por t
PA0-PA31
PB0-PB31
PC0-PC31
6221HS–ATARM–31-Jan-08
periph_nreset
periph_nreset
periph_clk[2..4]
dbgu_rxd
PIO
Controllers
pmc_irq
idle
periph_irq[2..4]
irq0-irq2
fiq
dbgu_txd
periph_clk[6..24]
periph_nreset
periph_irq[6..24]
in
out
enable
Embedded
Peripherals
27
9.2Reset Controller
• Based on two Power-on-reset cells
– One on VDDBU and one on VDDCORE
• Status of the last reset
– Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software
• Controls the internal resets and the NRST pin output
– Allows shaping a reset signal for the external devices
9.3Shutdown Controller
• Shutdown and Wake-up logic
– Software programmable assertion of the SHDN pin
– Deassertion Programmable on a WKUP pin level change or on alarm
9.4Clock Generator
• Embeds a Low-power 32,768 Hz Slow Clock Oscillator and a Low-power RC oscillator
selectable with OSCSEL signal
– Provides the permanent Slow Clock SLCK to the system
– PLLA outputs 80 to 240 MHz clock
– PLLB outputs 70 to 130 MHz clock
– Both integrate an input divider to increase output accuracy
– PLLB embeds its own filter
reset, user reset or watchdog reset
28
AT91SAM9260
6221HS–ATARM–31-Jan-08
Figure 9-2.Clock Generator Block Diagram
AT91SAM9260
9.5Power Management Controller
•Provides:
– the Processor Clock PCK
– the Master Clock MCK, in particular to the Matrix and the memory interfaces
– the USB Device Clock UDPCK
– independent peripheral clocks, typically at the frequency of MCK
– 2 programmable clock outputs: PCK0, PCK1
• Five flexible operating modes:
– Normal Mode, processor and peripherals running at a programmable frequency
– Idle Mode, processor stopped waiting for an interrupt
– Slow Clock Mode, processor and peripherals running at low frequency
– Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency,
processor stopped waiting for an interrupt
– Backup Mode, Main Power Supplies off, VDDBU powered by a battery
OSC_SEL
XIN32
XOUT32
XIN
XOUT
PLLRCA
Clock Generator
On Chip
RC OSC
Slow Clock
Oscillator
Main
Oscillator
PLL and
Divider A
PLL and
Divider B
ControlStatus
Power
Management
Controller
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
PLLB Clock
PLLBCK
6221HS–ATARM–31-Jan-08
29
Figure 9-3.AT91SAM9260 Power Management Controller Block Diagram
Processor
Clock
Controller
SLCK
MAINCK
PLLACK
PLLBCK
Master Clock Controller
Prescaler
/1,/2,/4,...,/64
Divider
/1,/2,/4
Programmable Clock Controller
Idle Mode
Peripherals
Clock Controller
ON/OFF
PCK
int
MCK
periph_clk[..]
9.6Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Windowed, prevents the processor being in a dead-lock on the watchdog access
9.8Real-time Timer
– Real-time Timer 32-bit free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable of generating a wake-up of the system through the
Shutdown Controller
SLCK
MAINCK
PLLACK
PLLBCK
PLLBCK
®
/Windows CE® compliant tick generator
Prescaler
/1,/2,/4,...,/64
USB Clock Controller
Divider
/1,/2,/4
ON/OFF
ON/OFF
pck[..]
UDPCK
UHPCK
9.9General-purpose Back-up Registers
• Four 32-bit backup general-purpose registers
9.10Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
30
AT91SAM9260
6221HS–ATARM–31-Jan-08
AT91SAM9260
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• Three External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
•Protect Mode
– Easy debugging by preventing automatic operations when protect models are
enabled
•Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.11Debug Unit
• Composed of two functions:
•Two-pin UART
• Debug Communication Channel Support
9.12Chip Identification
• Chip ID: 0x019803A2
• JTAG ID: 0x05B1303F
• ARM926 TAP ID: 0x0792603F
–Two-pin UART
– Debug Communication Channel (DCC) support
– Implemented features are 100% compatible with the standard Atmel
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
– Support for two PDC channels with connection to receiver and transmitter
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
®
USART
6221HS–ATARM–31-Jan-08
31
10. Peripherals
10.1User Interface
10.2Identifiers
The peripherals are mapped in the upper 256 Mbytes of the address space between the
addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of
address space. A complete memory map is presented in Figure 8-1 on page 21.
Table 10-1 defines the Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is
required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for
the control of the peripheral clock with the Power Management Controller.
Note:Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is auto-
matically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.
10.2.1Peripheral Interrupts and Clock Control
10.2.1.1System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.2.1.2External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to
IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these
peripheral IDs.
10.3Peripheral Signal Multiplexing on I/O Lines
The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of
the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. Table 10-2 on page 34, Table 10-3 on page 35 and Table 10-4 on page 36
define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The
two columns “Function” and “Comments” have been inserted in this table for the user’s own
comments; they may be used to track how pins are defined in an application.
Note that some peripheral functions which are output only might be duplicated within both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is
maintained in a static state as soon as the reset is released. As a result, the bit corresponding to
the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function
and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories,
in particular the address lines, which require the pin to be driven as soon as the reset is
released. Note that the pull-up resistor is also enabled in this case.
Note:1. Not available in the 208-lead PQFP package.
36
AT91SAM9260
6221HS–ATARM–31-Jan-08
10.4Embedded Peripherals
10.4.1Serial Peripheral Interface
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
AT91SAM9260
10.4.2Two-wire Interface
• Master, MultiMaster and Slave modes supported
• General Call supported in Slave mode
10.4.3USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
• RS485 with driver control signal
• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
• IrDA modulation and demodulation
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
– Parity generation and error detection
– Framing error detection, overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– By 8 or by-16 over-sampling receiver frequency
– Hardware handshaking RTS-CTS
– Optional modem signal management DTR-DSR-DCD-RI
– Receiver time-out and transmitter timeguard
– Optional Multi-drop Mode with address generation and detection
– NACK handling, error counter with repetition and iteration limit
6221HS–ATARM–31-Jan-08
37
– Communication at up to 115.2 Kbps
• Test Modes
– Remote Loopback, Local Loopback, Automatic Echo
The USART contains features allowing management of the Modem Signals DTR, DSR, DCD
and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0,
DSR0, DCD0 and RI0.
The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1
and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features.
Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect
and the status bits relating the status of the modem signals are never activated.
10.4.4Serial Synchronous Controller
• Provides serial synchronous communication links used in audio and telecom applications
(with CODECs in Master or Slave Modes, I
• Contains an independent receiver and transmitter and a common clock divider
• Offers a configurable frame sync and data length
• Receiver and transmitter can be programmed to start automatically or on detection of
different event on the frame sync signal
• Receiver and transmitter include a data signal, a clock signal and a frame synchronization
signal
2
S, TDM Buses, Magnetic Card Reader, etc.)
10.4.5Timer Counter
• Two blocks of three 16-bit Timer Counter channels
• Each channel can be individually programmed to perfom a wide range of functions including:
– Frequency Measurement
– Event Counting
– Interval Measurement
– Pulse Generation
–Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
• Each channel is user-configurable and contains:
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
• Each block contains two global registers that act on all three TC Channels
Note:TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See
Figure 8-1, “AT91SAM9260 Memory Mapping,” on page 21 for TC Block 0 and TC Block 1
base addresses.
10.4.6Multimedia Card Interface
• One double-channel MultiMedia Card Interface
• Compatibility with MultiMedia Card Specification Version 3.11
38
AT91SAM9260
6221HS–ATARM–31-Jan-08
10.4.7USB Host Port
AT91SAM9260
• Compatibility with SD Memory Card Specification Version 1.1
• Compatibility with SDIO Specification Version V1.0.
• Card clock rate up to Master Clock divided by 2
• Embedded power management to slow down clock rate when not used
• MCI has two slots, each supporting
– One slot for one MultiMediaCard bus (up to 30 cards) or
– One SD Memory Card
• Support for stream, block and multi-block data read and write
• Compliance with Open HCI Rev 1.0 Specification
• Compliance with USB V2.0 Full-speed and Low-speed Specification
• Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices
• Root hub integrated with two downstream USB ports in the 217-LFBGA package
• Two embedded USB transceivers
• Supports power management
• Operates as a master on the Matrix
10.4.8USB Device Port
• USB V2.0 full-speed compliant, 12 MBits per second
• Embedded USB V2.0 full-speed transceiver
• Embedded 2,432-byte dual-port RAM for endpoints
• Suspend/Resume logic
• Ping-pong mode (two memory banks) for isochronous and bulk endpoints
• Six general-purpose endpoints
• Embedded pad pull-up
10.4.9Ethernet 10/100 MAC
• Compatibility with IEEE Standard 802.3
• 10 and 100 MBits per second data throughput capability
• Full- and half-duplex operations
• MII or RMII interface to the physical layer
• Register Interface to address, data, status and control registers
• DMA Interface, operating as a master on the Memory Controller
• Interrupt generation to signal receive and transmit completion
• 28-byte transmit and 28-byte receive FIFOs
• Automatic pad and CRC generation on transmitted frames
• Address checking logic to recognize four 48-bit addresses
• Support promiscuous mode where all valid frames are copied to memory
– Endpoint 0 and 3: 64 bytes, no ping-pong mode
– Endpoint 1 and 2: 64 bytes, ping-pong mode
– Endpoint 4 and 5: 512 bytes, ping-pong mode
6221HS–ATARM–31-Jan-08
39
• Support physical layer management through MDIO interface
10.4.10Image Sensor Interface
• ITU-R BT. 601/656 8-bit mode external interface support
• Support for ITU-R BT.656-4 SAV and EAV synchronization
• Vertical and horizontal resolutions up to 2048 x 2048
• Preview Path up to 640*480
• Support for packed data formatting for YCbCr 4:2:2 formats