ATMEL AT91SAM7S256 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Incorporates the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
• Internal High-speed Flash
– 512 Kbytes (AT91SAM7S512) Organized in Two Contiguous Banks of 1024 Pages
of 256 Bytes (Dual Plane)
– 256 Kbytes (AT91SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)
– 128 Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)
– 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)
– 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)
– 16 Kbytes (AT91SAM7S161/16 Organized in 256 Pages of 64 Bytes (Single Plane)
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions
– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
Flash Security Bit
– Fast Flash Programming Interface for High Volume Production
• Internal High-speed SRAM, Single-cycle Access at Maximum Speed
– 64 Kbytes (AT91SAM7S512/256)
– 32 Kbytes (AT91SAM7S128)
– 16 Kbytes (AT91SAM7S64)
– 8 Kbytes (AT91SAM7S321/32)
– 4 Kbytes (AT91SAM7S161/16)
• Memory Controller (MC)
– Embedded Flash Controller, Abort Status and Misalignment Detection
• Reset Controller (RSTC)
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
• Clock Generator (CKGR)
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
• Power Management Controller (PMC)
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to
500 Hz) and Idle Mode
– Three Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two (AT91SAM7S512/256/128/64/321/161) or One (AT91SAM7S32/16) External
Interrupt Source(s) and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel interrupt,
Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Programmable Counter plus 12-bit Interval Counter
• Windowed Watchdog (WDT)
– 12-bit key-protected Programmable Counter
– Provides Reset or Interrupt Signals to the System
™
In-circuit Emulation, Debug Communication Channel Support
®
ARM® Thumb® Processor
AT91 ARM
Thumb-based
Microcontrollers
AT91SAM7S512
AT91SAM7S256
AT91SAM7S128
AT91SAM7S64
AT91SAM7S321
AT91SAM7S32
AT91SAM7S161
AT91SAM7S16
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6175GS–ATARM–24-Dec-08
– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode
• Real-time Timer (RTT)
– 32-bit Free-running Counter with Alarm
– Runs Off the Internal RC Oscillator
• One Parallel Input/Output Controller (PIOA)
– Thirty-two (AT91SAM7S512/256/128/64/321/161) or twenty-one (AT91SAM7S32/16) Programmable I/O Lines Multiplexed
with up to Two Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up resistor and Synchronous Output
• Eleven (AT91SAM7S512/256/128/64/321/161) or Nine (AT91SAM7S32/16) Peripheral DMA Controller (PDC) Channels
• One USB 2.0 Full Speed (12 Mbits per Second) Device Port (Except for the AT91SAM7S32/16).
– On-chip Transceiver, 328-byte Configurable Integrated FIFOs
• One Synchronous Serial Controller (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• Two (AT91SAM7S512/256/128/64/321/161) or One (AT91SAM7S32/16) Universal Synchronous/Asynchronous Receiver
Transmitters (USART)
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
– Full Modem Line Support on USART1 (AT91SAM7S512/256/128/64/321/161)
®
Infrared Modulation/Demodulation
• One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Input and Two Multi-purpose I/O Pins per Channel (AT91SAM7S512/256/128/64/321/161)
– One External Clock Input and Two Multi-purpose I/O Pins for the first Two Channels Only (AT91SAM7S32/16)
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• One Two-wire Interface (TWI)
– Master Mode Support Only, All Two-wire Atmel EEPROMs and I2C Compatible Devices Supported
(AT91SAM7S512/256/128/64/321/32)
– Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs and I
(AT91SAM7S161/16)
2
C Compatible Devices Supported
• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os
• SAM-BA
• IEEE
™
Boot Assistant
– Default Boot program
– Interface with SAM-BA Graphic User Interface
®
1149.1 JTAG Boundary Scan on All Digital Pins
• 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each (AT91SAM7S161/16 I/Os Not 5V-tolerant)
• Power Supplies
– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components
– 3.3V or 1.8V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply
– 1.8V VDDCORE Core Power Supply with Brown-out Detector
• Fully Static Operation: Up to 55 MHz at 1.65V and 85⋅ C Worst Case Conditions
• Available in 64-lead LQFP Green or 64-pad QFN Green Package (AT91SAM7S512/256/128/64/321/161) and 48-lead LQFP Green
or 48-pad QFN Green Package (AT91SAM7S32/16)
2
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
1. Description
AT91SAM7S Series Summary
Atmel’s AT91SAM7S is a series of low pincount Flash microcontrollers based on the 32-bit ARM
RISC processor. It features a high-speed Flash and an SRAM, a large set of peripherals, including a USB 2.0 device (except for the AT91SAM7S32 and AT91SAM7S16), and a complete set
of system functions minimizing the number of external components. The device is an ideal
migration path for 8-bit microcontroller users looking for additional performance and extended
memory.
The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via
a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.
The AT91SAM7S Series system controller includes a reset controller capable of managing the
power-on sequence of the microcontroller and the complete system. Correct device operation
can be monitored by a built-in brownout detector and a watchdog running off an integrated RC
oscillator.
The AT91SAM7S Series are general-purpose microcontrollers. Their integrated USB Device
port makes them ideal devices for peripheral applications requiring connectivity to a PC or cellular phone. Their aggressive price point and high level of integration pushes their scope of use far
into the cost-sensitive, high-volume consumer market.
1.1 Configuration Summary of the AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321, AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16
The AT91SAM7S512, AT91SAM7S256, AT91SAM7S128, AT91SAM7S64, AT91SAM7S321,
AT91SAM7S32, AT91SAM7S161 and AT91SAM7S16 differ in memory size, peripheral set and
package. Table 1-1 summarizes the configuration of the six devices.
Except for the AT91SAM7S32/16, all other AT91SAM7S devices are package and pinout
compatible.
Table 1-1. Configuration Summary
USB
Flash
Device Flash TWI
AT91SAM7S512 512 Kbytes Master dual plane 64 Kbytes 1 2
AT91SAM7S256 256 Kbytes Master single plane 64 Kbytes 1 2
AT91SAM7S128 128 Kbytes Master single plane 32 Kbytes 1 2
AT91SAM7S64 64 Kbytes Master single plane 16 Kbytes 1 2
AT91SAM7S321 32 Kbytes Master single plane 8 Kbytes 1 2
AT91SAM7S32 32 Kbytes Master single plane 8 Kbytes
AT91SAM7S161 16 Kbytes
AT91SAM7S16 16 Kbytes
Master/
Slave
Master/
Slave
Organization SRAM
single plane 4 Kbytes 1 2
single plane 4 Kbytes
Device
Port USART
not
present
not
present
Notes: 1. Fractional Baud Rate.
2. Full modem line support on USART1.
3. Only two TC channels are accessible through the PIO.
11 9 3
11 9 3
External
Interrupt
Source
(1) (2)
2113 Yes32
(1) (2)
2113 Yes32
(1) (2)
2113 Yes32
(2)
2113 Yes32
(2)
2113 Yes32
(2)
2113 No32LQFP
PDC
Channels
TC
Channels
(3)
(3)
I/O 5V
Tol erant
Ye s 2 1
No 21
I/O
Lines Package
LQFP/
QFN 64
LQFP/
QFN 64
LQFP/
QFN 64
LQFP/
QFN 64
LQFP/
QFN 64
LQFP/
QFN 48
LQFP/
QFN 48
6175GS–ATARM–24-Dec-08
3
TDI
TDO
TMS
TCK
NRST
FIQ
IRQ0-IRQ1
PCK0-PCK2
PMC
Peripheral Bridge
Peripheral Data
Controller
AIC
PLL
RCOSC
SRAM
64/32/16/8/4 Kbytes
ARM7TDMI
Processor
ICE
JTAG
SCAN
JTAGSEL
PIOA
USART0
SSC
Timer Counter
RXD0
TXD0
SCK0
RTS0
CTS0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
Flash
512/256/
128/64/32/16 Kbytes
Reset
Controller
DRXD
DTXD
TF
TK
TD
RD
RK
RF
TCLK0
TCLK1
TCLK2
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
Memory Controller
Abort
Status
Address
Decoder
Misalignment
Detection
PIO
PIO
APB
POR
Embedded
Flash
Controller
AD0
AD1
AD2
AD3
ADTRG
PLLRC
11 Channels
PDC
PDC
USART1
RXD1
TXD1
SCK1
RTS1
CTS1
DCD1
DSR1
DTR1
RI1
PDC
PDC
PDC
PDC
SPI
PDC
ADC
ADVREF
PDC
PDC
TC0
TC1
TC2
TWD
TWCK
TWI
OSC
XIN
XOUT
VDDIN
PWMC
PWM0
PWM1
PWM2
PWM3
1.8 V
Voltage
Regulator
USB Device
FIFO
DDM
DDP
Transceiver
GND
VDDOUT
BOD
VDDCORE
VDDCORE
AD4
AD5
AD6
AD7
VDDFLASH
Fast Flash
Programming
Interface
ERASE
PIO
PGMD0-PGMD15
PGMNCMD
PGMEN0-PGMEN2
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
VDDIO
TST
DBGU
PDC
PDC
PIO
PIT
WDT
RTT
System Controller
VDDCORE
SAM-BA
ROM
2. Block Diagram
Figure 2-1. AT91SAM7S512/256/128/64/321/161 Block Diagram
4
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
ROM
TDI
TDO
TMS
TCK
NRST
FIQ
IRQ0
PCK0-PCK2
JTAGSEL
RXD0
TXD0
SCK0
RTS0
CTS0
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
DRXD
DTXD
TF
TK
TD
RD
RK
RF
TCLK0
TIOA0
TIOB0
TIOA1
TIOB1
AD0
AD1
AD2
AD3
ADTRG
PLLRC
9 Channels
ADVREF
TWD
TWCK
XIN
XOUT
VDDIN
PWM0
PWM1
PWM2
PWM3
GND
VDDOUT
VDDCORE
VDDCORE
AD4
AD5
AD6
AD7
VDDFLASH
ERASE
PGMD0-PGMD7
PGMNCMD
PGMEN0-PGMEN2
PGMRDY
PGMNVALID
PGMNOE
PGMCK
PGMM0-PGMM3
VDDIO
TST
VDDCORE
SRAM
8/4 Kbytes
ARM7TDMI
Processor
Flash
32/16 Kbytes
APB
SAM-BA
PMC
Peripheral Bridge
Peripheral DMA
Controller
AIC
PLL
RCOSC
ICE
JTAG
SCAN
PIOA
USART0
SSC
Timer Counter
Reset
Controller
Memory Controller
Abort
Status
Address
Decoder
Misalignment
Detection
PIO
PIO
POR
Embedded
Flash
Controller
PDC
PDC
PDC
PDC
SPI
PDC
ADC
PDC
PDC
TC0
TC1
TC2
TWI
OSC
PWMC
1.8 V
Voltage
Regulator
BOD
Fast Flash
Programming
Interface
PIO
DBGU
PDC
PDC
PIO
PIT
WDT
RTT
System Controller
Figure 2-2. AT91SAM7S32/16 Block Diagram
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
5
3. Signal Description
Table 3-1. Signal Description List
Active
Signal Name Function Type
Power
VDDIN
VDDOUT Voltage Regulator Output Power 1.85V nominal
VDDFLASH Flash Power Supply Power 3.0V to 3.6V
VDDIO I/O Lines Power Supply Power 3.0V to 3.6V or 1.65V to 1.95V
VDDCORE Core Power Supply Power 1.65V to 1.95V
VDDPLL PLL Power 1.65V to 1.95V
GND Ground Ground
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
PLLRC PLL Filter Input
PCK0 - PCK2 Programmable Clock Output Output
TCK Test Clock Input No pull-up resistor
TDI Test Data In Input No pull-up resistor
TDO Test Data Out Output
TMS Test Mode Select Input No pull-up resistor
JTAGSEL JTAG Selection Input Pull-down resistor
ERASE
NRST Microcontroller Reset I/O Low Open-drain with pull-Up resistor
TST Test Mode Select Input High Pull-down resistor
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
IRQ0 - IRQ1 External Interrupt Inputs Input IRQ1 not present on AT91SAM7S32/16
FIQ Fast Interrupt Input Input
PA0 - PA31 Parallel IO Controller A I/O
Voltage and ADC Regulator Power Supply
Input
Clocks, Oscillators and PLLs
ICE and JTAG
Flash Memory
Flash and NVM Configuration Bits Erase
Command
Reset/Test
Debug Unit
Power 3.0 to 3.6V
Input High Pull-down resistor
AIC
PIO
Level Comments
(1)
(1)
(1)
Pulled-up input at reset
PA0 - PA20 only on AT91SAM7S32/16
6
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
AT91SAM7S Series Summary
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
USB Device Port
DDM USB Device Port Data - Analog not present on AT91SAM7S32/16
DDP USB Device Port Data + Analog not present on AT91SAM7S32/16
USART
SCK0 - SCK1 Serial Clock I/O SCK1 not present on AT91SAM7S32/16
TXD0 - TXD1 Transmit Data I/O TXD1 not present on AT91SAM7S32/16
RXD0 - RXD1 Receive Data Input RXD1 not present on AT91SAM7S32/16
RTS0 - RTS1 Request To Send Output RTS1 not present on AT91SAM7S32/16
CTS0 - CTS1 Clear To Send Input CTS1 not present on AT91SAM7S32/16
DCD1 Data Carrier Detect Input not present on AT91SAM7S32/16
DTR1 Data Terminal Ready Output not present on AT91SAM7S32/16
DSR1 Data Set Ready Input not present on AT91SAM7S32/16
RI1 Ring Indicator Input not present on AT91SAM7S32/16
Synchronous Serial Controller
TD Transmit Data Output
RD Receive Data Input
TK Transmit Clock I/O
RK Receive Clock I/O
TF Transmit Frame Sync I/O
RF Receive Frame Sync I/O
Timer/Counter
TCLK0 - TCLK2 External Clock Inputs Input
TIOA0 - TIOA2 I/O Line A I/O TIOA2 not present on AT91SAM7S32/16
TIOB0 - TIOB2 I/O Line B I/O TIOB2 not present on AT91SAM7S32/16
PWM Controller
PWM0 - PWM3 PWM Channels Output
SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
NPCS0 SPI Peripheral Chip Select 0 I/O Low
NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low
Level Comments
TCLK1 and TCLK2 not present on
AT91SAM7S32/16
6175GS–ATARM–24-Dec-08
7
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
Two-Wire Interface
TWD Two-wire Serial Data I/O
TWCK Two-wire Serial Clock I/O
Analog-to-Digital Converter
AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset
AD4-AD7 Analog Inputs Analog Analog Inputs
ADTRG ADC Trigger Input
ADVREF ADC Reference Analog
Fast Flash Programming Interface
PGMEN0-PGMEN2 Programming Enabling Input
PGMM0-PGMM3 Programming Mode Input
PGMD0-PGMD15 Programming Data I/O
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Programming Read Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
Level Comments
PGMD0-PGMD7 only on
AT91SAM7S32/16
Note: 1. Refer to Section 6. “I/O Lines Considerations” on page 14.
8
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
AT91SAM7S Series Summary
116
17
32
3348
49
64
3348
161
49
64
32
17
4. Package and Pinout
The AT91SAM7S512/256/128/64/321 are available in a 64-lead LQFP or 64-pad QFN package.
The AT91SAM7S161 is available in a 64-Lead LQFP package.
The AT91SAM7S32/16 are available in a 48-lead LQFP or 48-pad QFN package.
4.1 64-lead LQFP and 64-pad QFN Package Outlines
Figure 4-1 and Figure 4-2 show the orientation of the 64-lead LQFP and the 64-pad QFN pack-
age. A detailed mechanical description is given in the section Mechanical Characteristics of the
full datasheet.
Figure 4-1. 64-lead LQFP Package (Top View)
Figure 4-2. 64-pad QFN Package (Top View)
6175GS–ATARM–24-Dec-08
9
4.2 64-lead LQFP and 64-pad QFN Pinout
Table 4-1. AT91SAM7S512/256/128/64/321/161 Pinout
1 ADVREF 17 GND 33 TDI 49 TDO
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS
4 AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK
6 AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE
8 VDDOUT 24 VDDCORE 40 TST 56 DDM
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9 27 PA12/PGMD0 43 PA3 59 VDDFLASH
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT
14 PA22/PGMD10 30 PA9/PGMM1 46 GND 62 XIN/PGMCK
15 PA23/PGMD11 31 PA8/PGMM0 47 PA1/PGMEN1 63 PLLRC
16 PA20/PGMD8/AD3 32 PA7/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
Note: 1. The bottom pad of the QFN package must be connected to ground.
(1)
10
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
AT91SAM7S Series Summary
112
13
24
2536
37
48
2536
121
37
48
24
13
4.3 48-lead LQFP and 48-pad QFN Package Outlines
Figure 4-3 and Figure 4-4 show the orientation of the 48-lead LQFP and the 48-pad QFN pack-
age. A detailed mechanical description is given in the section Mechanical Characteristics of the
full datasheet.
Figure 4-3. 48-lead LQFP Package (Top View)
Figure 4-4. 48-pad QFN Package (Top View)
4.4 48-lead LQFP and 48-pad QFN Pinout
Table 4-2. AT91SAM7S32/16 Pinout
1 ADVREF 13 VDDIO 25 TDI 37 TDO
2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL
3 AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS
4 AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK
5 AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE
6 AD7 18 VDDCORE 30 TST 42 ERASE
7 VDDIN 19 PA12/PGMD0 31 PA3 43 VDDFLASH
8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 GND
9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT
10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/PGMCK
11 PA19/PGMD7/AD2 23 PA8/PGMM0 35 PA1/PGMEN1 47 PLLRC
12 PA20/AD3 24 PA7/PGMNVALID 36 PA0/PGMEN0 48 VDDPLL
Note: 1. The bottom pad of the QFN package must be connected to ground.
6175GS–ATARM–24-Dec-08
(1)
11
5. Power Considerations
5.1 Power Supplies
The AT91SAM7S Series has six types of power supply pins and integrates a voltage regulator,
allowing the device to be supplied with only one voltage. The six power supply pin types are:
• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,
3.3V nominal.
• VDDOUT pin. It is the output of the 1.8V voltage regulator.
• VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is
supported. Ranges from 3.0V to 3.6V, 3.3V nominal or from 1.65V to 1.95V, 1.8V nominal.
Note that supplying less than 3.0V to VDDIO prevents any use of the USB transceivers.
• VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate
correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.
• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,
1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE
is required for the device, including its embedded Flash, to operate correctly.
During startup, core supply voltage (VDDCORE) slope must be superior or equal to 6V/ms.
• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the
VDDOUT pin.
No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.
In order to decrease current consumption, if the voltage regulator and the ADC are not used,
VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case VDDOUT
should be left unconnected.
5.2 Power Consumption
The AT91SAM7S Series has a static current of less than 60 µA on VDDCORE at 25°C, including
the RC oscillator, the voltage regulator and the power-on reset. When the brown-out detector is
activated, 20 µA static current is added.
The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running
out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not
exceed 10 mA.
5.3 Voltage Regulator
The AT91SAM7S Series embeds a voltage regulator that is managed by the System Controller.
In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100
mA of output current.
The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA
static current and draws 1 mA of output current.
Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or
1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as
possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT
and GND.
12
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
Power Source
ranges
from 4.5V (USB)
to 18V
3.3V
VDDIN
Voltage
Regulator
VDDOUT
VDDIO
DC/DC Converter
VDDCORE
VDDFLASH
VDDPLL
and reduce source voltage drop. The input decoupling capacitor should be placed close to the
chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
5.4 Typical Powering Schematics
The AT91SAM7S Series supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows
the power schematics to be used for USB bus-powered systems.
Figure 5-1. 3.3V System Single Power Supply Schematic
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
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6. I/O Lines Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS,
TDI and TCK do not integrate a pull-up resistor.
TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The
JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be
left unconnected for normal operations.
6.2 Test Pin
The TST pin is used for manufacturing test, fast programming mode or SAM-BA Boot Recovery
of the AT91SAM7S Series when asserted high. The TST pin integrates a permanent pull-down
resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.
To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high
and PA2 tied to low.
To enter SAM-BA Boot Recovery, the TST pin and the PA0, PA1 and PA2 pins should be tied
high fo at least 10 seconds.
Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.
6.3 Reset Pin
The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset
controller and can be driven low to provide a reset signal to the external components or asserted
low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,
and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset
all the components of the system.
The NRST pin integrates a permanent pull-up resistor to VDDIO.
6.4 ERASE Pin
The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a
permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor-
mal operations.
6.5 PIO Controller A Lines
• All the I/O lines PA0 to PA31on AT91SAM7S512/256/128/64/321 (PA0 to PA20 on
AT91SAM7S32) are 5V-tolerant and all integrate a programmable pull-up resistor.
• All the I/O lines PA0 to PA31 on AT91SAM7S161 (PA0 to PA20 on AT91SAM7S16) are not
5V-tolerant and all integrate a programmable pull-up resistor.
Programming of this pull-up resistor is performed independently for each I/O line through the
PIO controllers.
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5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be
driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while
the programmable pull-up resistor is enabled will create a current path through the pull-up resis-
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
tor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines
default to input with the pull-up resistor enabled at reset.
6.6 I/O Line Drive Levels
The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to
16 mA permanently.
The remaining I/O lines can draw only 8 mA.
However, the total current drawn by all the I/O lines cannot exceed 150 mA (100 mA for
AT91SAM7S32/16).
AT91SAM7S Series Summary
6175GS–ATARM–24-Dec-08
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