ATMEL AT91M40800 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Incorporates the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
• 8K Bytes On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
• Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Databus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripheral Can Be Deactivated Individually
• Fully Static Operation:
– 0 Hz to 40 MHz Internal Frequency Range at 3.0V, 85°C
• 1.8V to 3.6V Operating Range
• -40°C to +85° C Temperature Range
• Available in a 100-lead LQFP Package (Green)
™
®
ARM® Thumb® Processor Core
AT91 ARM
Thumb
Microcontrollers
AT91M40800
Summary
1. Description
The AT91M40800 microcontroller is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance 32-bit RISC architecture with a high-density 16-bit instruction set
and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time
control applications.
The AT91M40800 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An
eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data
Controller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with on-chip high-speed memory and a wide
range of peripheral functions on a monolithic chip, the AT91M40800 is a powerful
microcontroller that offers a flexible, cost-effective solution to many compute-intensive
embedded control applications.
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
1348FS–ATARM–13-Apr-06
2. Pin Configuration
Figure 2-1. AT91M40800 Pinout (Top View)
P16
P15/RXD0
P21/TXD1/NTRI
P18
P20/SCK1
P19
P17
P14/TXD0
P13/SCK0
P12/FIQ
GND
P10/IRQ1
P11/IRQ2
VDD
VDD
P9/IRQ0
P8/TIOB2
P7/TIOA2
P6/TCLK2
P4/TIOA1
P5/TIOB1
P3/TCLK1
GND
GND
P2/TIOB0
P22/RXD1
NWR1/NUB
GND
NRST
NWDOVF
VDD
MCKI
P23
P24/BMS
P25/MCKO
GND
GND
TMS
TDI
TDO
TCK
NRD/NOE
NWR0/NWE
VDD
VDD
NWAIT
NCS0
NCS1
P26/NCS2
P27/NCS3
7551747372717069686766656463626160595857565554
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
100-lead TQFP
53
52
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P1/TIOA0
P0/TCLK0
D15
D14
D13
D12
VDD
D11
D10
D9
D8
D7
D6
D5
GND
D4
D3
D2
D1
D0
P31/A23/CS4
P30/A22/CS5
VDD
VDD
P29/A21/CS6
2
3
4
5
6
7
8
9
1
A5A6A7
A2A2
A3
A4
GND
A1
101112131415116171819202122
A9
VDD
A8
A10
A11
A12
A13
A14
GND
GND
A15
A16
A17
23
A18
24
A19
25
A0/NLB
P28/A20/CS7
2
AT91M40800
1348FS–ATARM–13-Apr-06
3. Pin Description
Table 3-1. AT91M40800 Pin Description
Module Name Function Type
A0 - A23 Address Bus Output – All valid after reset
D0 - D15 Data Bus I/O –
NCS0 - NCS3 Chip Select Output Low
CS4 - CS7 Chip Select Output High A23 - A20 after reset
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write option
EBI
NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select Output Low Used in Byte Select option
NLB Lower Byte Select Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input – Sampled during reset
AT91M40800
Active
Level Comments
AIC
TC
USART
PIO P0 - P31 Parallel IO line I/O –
WD NWDOVF Watchdog Overflow Output Low Open-drain
Clock
Reset
ICE
Power
FIQ Fast Interrupt Request Input – PIO-controlled after reset
IRQ0 - IRQ2 External Interrupt Request Input – PIO-controlled after reset
TCLK0 - TCLK2 Timer External Clock Input – PIO-controlled after reset
TIOA0 - TIOA2 Multipurpose Timer I/O pin A I/O – PIO-controlled after reset
TIOB0 - TIOB2 Multipurpose Timer I/O pin B I/O – PIO-controlled after reset
SCK0 - SCK1 External Serial Clock I/O – PIO-controlled after reset
TXD0 - TXD1 Transmit Data Output Output – PIO-controlled after reset
RXD0 - RXD1 Receive Data Input Input – PIO-controlled after reset
MCKI Master Clock Input Input – Schmidt trigger
MCKO Master Clock Output Output –
NRST Hardware Reset Input Input Low Schmidt trigger
NTRI Tri-state Mode Select Input Low Sampled during reset
TMS Test Mode Select Input – Schmidt trigger, internal pull-up
TDI Test Data Input Input – Schmidt trigger, internal pull-up
TDO Test Data Output Output –
TCK Test Clock Input – Schmidt trigger, internal pull-up
VDD Power Power –
GND Ground Ground –
1348FS–ATARM–13-Apr-06
3
4. Block Diagram
Figure 4-1. AT91M40800
MCKI
P25/MCKO
P12/FIQ
P9/IRQ0
P10/IRQ1
P11/IRQ2
P13/SCK0
P14/TXD0
P15/RXD0
P20/SCK1
P21/TXD1/NTRI
P22/RXD1
P16
P17
P18
P19
P23
P24/BMS
TMS
TDO
TDI
TCK
Embedded
ICE
Reset
ARM7TDMI Core
ASB
Clock
AIC: Advanced
Interrupt Controller
P
I
O
USART0
USART1
PS: Power Saving
8K-byte RAM
ASB
Controller
2 PDC
Channels
2 PDC
Channels
Chip ID
PIO: Parallel I/O Controller
AMBA Bridge
APB
EBI: External Bus Interface
EBI User
Interface
TC: Timer
Counter
TC0
TC1
TC2
WD: Watchdog
Timer
P
I
O
NRST
D0-D15
A1-A19
A0/NLB
NRD/NOE
NWR0/NWE
NWR1/NUB
NWAIT
NCS0
NCS1
P26/NCS2
P27/NCS3
P28/A20/CS7
P29/A21/CS6
P30/A22/CS5
P31/A23/CS4
P0/TCLK0
P3/TCLK1
P6/TCLK2
P1/TIOA0
P2/TIOB0
P4/TIOA1
P5/TIOB1
P7/TIOA2
P8/TIOB2
NWDOVF
4
AT91M40800
1348FS–ATARM–13-Apr-06
5. Architectural Overview
The AT91M40800 microcontroller integrates an ARM7TDMI with Embedded ICE interface,
memories and peripherals. The architecture consists of two main buses, the Advanced System
Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and
controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the onchip 32-bit memories, the External Bus Interface (EBI) and the AMBA
Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for
low power consumption.
The AT91M40800 microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low cost and easy-to-use debug solution for target debugging.
5.1 Memories
The AT91M40800 microcontroller embeds up to 8K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible.
The AT91M40800 microcontroller features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit
devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the
early read protocol, enabling faster memory accesses than standard memory interfaces.
AT91M40800
™
Bridge. The AMBA
5.2 Peripherals
The AT91M40800 microcontrollers integrate several peripherals, which are classified as system
or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can
be programmed with a minimum number of instructions. The peripheral register set is composed
of control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and
on- and off-chip memories address space without processor intervention. Most importantly, the
PDC removes the processor interrupt handling overhead, making it possible to transfer up to
64K contiguous bytes without reprogramming the start address, thus increasing the performance of the microcontroller, and reducing the power consumption.
5.2.1 System Peripherals
The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or
16-bit databus and is programmed through the APB. Each chip select line has its own programming register.
The Power-saving (PS) module implements the Idle mode (ARM7TDMI core clock stopped until
the next interrupt) and enables the user to adapt the power consumption of the microcontroller to
application requirements (independent peripheral clock control).
The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal
peripherals and the four external interrupt lines (including the FIQ), to provide an interrupt and/or
fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the
Auto-vectoring feature, reduces the interrupt latency time.
1348FS–ATARM–13-Apr-06
The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to
select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controller can be programmed to detect an interrupt on a signal change
from each line.
5
The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in
a deadlock.
The Special Function (SF) module integrates the Chip ID, the Reset Status and the Protect
registers.
5.2.2 User Peripherals
Two USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data
bits. Each USART also features a Timeout and a Time Guard register, facilitating the use of the
two dedicated Peripheral Data Controller (PDC) channels.
The 3-channel, 16-bit Timer Counter (TC) is highly-programmable and supports capture or
waveform modes. Each TC channel can be programmed to measure or generate different kinds
of waves, and can detect and control two input/output signals. The TC has also three external
clock signals.
6. Associated Documentation
The AT91M40800 is part of the AT91x40 Series microcontrollers, a member of the Atmel AT91 16/32-bit microcontroller
family which is based on the ARM7TDMI processor core. Table 6-1 contains details of associated documentation for further
reference.
Table 6-1. Associated Documentation
Product Information Document Title
Internal architecture of processor
AT91M40800
ARM/Thumb instruction sets
Embedded in-circuit-emulator
External memory interface mapping
Peripheral operations
Peripheral user interfaces
DC characteristics
Power consumption
Thermal and reliability considerations
AC characteristics
Product overview
Ordering information
Packaging information
Soldering profile
ARM7TDMI (Thumb) Datasheet
AT91x40 Series Datasheet
AT91M40800 Electrical Characteristics
AT91M40800 Summary Datasheet (this document)
6
AT91M40800
1348FS–ATARM–13-Apr-06
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