Atmel AT90USB82, AT90USB162 Datasheet

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 125 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz

• Non-volatile Program and Data Memories

– 8K / 16K Bytes of In-System Self-Programmable Flash

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• USB boot-loader programmed by default in the factory

• In-System Programming by on-chip Boot Program hardware-activated after reset

• True Read-While-Write Operation

– 512 Bytes EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM – Programming Lock for Software Security

• USB 2.0 Full-speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification REV 2.0 – 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s – Fully independant 176 bytes USB DPRAM for endpoint memory allocation – Endpoint 0 for Control Transfers: from 8 up to 64-bytes – 4 Programmable Endpoints:

• IN or Out Directions

• Bulk, Interrupt and IsochronousTransfers

• Programmable maximum packet size from 8 to 64 bytes

• Programmable single or double buffer

– Suspend/Resume Interrupts – Microcontroller reset on USB Bus Reset without detach – USB Bus Disconnection on Microcontroller Request – USB pad multiplexed with PS/2 peripheral for single cable capability

• Peripheral Features

– PS/2 compliant pad – One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit

PWM channels)

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode

(three 8-bit PWM channels) – USART with SPI master only mode and hardware flow control (RTS/CTS) – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• On Chip Debug Interface (debugWIRE)

• Special Microcontroller Features

– Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources

8-Bit Microcontroller

8-bit Microcontroller with 8/16K Bytes of ISP Flash and USB Controller

AT90USB82 AT90USB162

7707F–AVR–11/10

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 22 Programable I/O Lines – QFN32 (5x5mm) / TQFP32 packages

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range

AT90USB82/162

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1. Pin Configurations

UVCC

QFN32

(PCINT11) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5) PD4

(TXD1 / INT3) PD3

(XCK / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

282726 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D- / SDATA

D+ / SCK

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / INT6) PD6

(CTS

/ HWB / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVC C

UVCC

TQFP32

(PCINT11) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5) PD4

(TXD1 / INT3) PD3

(XCK / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

282726 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D- / SDATA

D+ / SCK

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / INT6) PD6

(CTS

/ HWB / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVCC

Figure 1-1. Pinout AT90USB82/162

AT90USB82/162

Note: The large center pad underneath the QFN packages is made of metal and must be connected to

GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

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2. Overview

PROGRAM COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

INTERRUPT

UNIT

EEPROM

USART1

STATUS

ALU

PORTC DRIVERS

PORTD DRIVERS

PORTB DRIVERS

PC7 - PC0 PD7 - PD0

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PB7 - PB0

D+/SCK D-/SDATA

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB

PS/2

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

ON-CHIP DEBUG

Debug-Wire

PROGRAMMING

LOGIC

DATA DIR.

REG. PORTD

DATA REGISTER

PORTD

POR - BOD

RESET

PLL

SPI

ON-CHIP

3.3V

REGULATOR

UVcc

UCap

1uF

The AT90USB82/162 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90USB82/162 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting

AT90USB82/162

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AT90USB82/162

architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90USB82/162 provides the following features: 8K / 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 22 general purpose I/O lines, 32 general purpose working registers, two flexible Timer/Counters with compare modes and PWM, one USART, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, debugWIRE interface, also used for accessing the On-chip Debug system and programming and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, the main Oscillator continues to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB82/162 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90USB82/162 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the AT90USB82/162 as listed on

page 74.

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2.2.4 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of various special features of the AT90USB82/162 as listed on

page 76.

2.2.5 Port D (PD7..PD0)

Port D serves as analog inputs to the analog comparator.

Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (concerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.2.6 D-/SDATA

USB Full Speed Negative Data Upstream Port / Data port for PS/2

2.2.7 D+/SCK

USB Full Speed Positive Data Upstream Port / Clock port for PS/2

2.2.8 UGND

2.2.9 UVCC

2.2.10 UCAP

2.2.11 RESET/PC1/dW

2.2.12 XTAL1

2.2.13 XTAL2/PC0

USB Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Section 9.. Shorter pulses are not guaranteed to generate a reset. This pin alternatively serves as debugWire channel or as generic I/O. The configuration depends on the fuses RSTDISBL and DWEN.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.

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3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

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4. AVR CPU Core

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

AT90USB82/162

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AT90USB82/162

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90USB82/162 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. See the “Instruction Set” section for a detailed description.

4.4 Status Register

7707F–AVR–11/10

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 76543210

ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

AT90USB82/162

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

7707F–AVR–11/10

4.6 Stack Pointer

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 1514131211109 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

11111111

4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

, directly generated from the selected clock source for the

CPU

AT90USB82/162

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AT90USB82/162

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 4-5. Single Cycle ALU Operation

4.8 Reset and Interrupt Handling

7707F–AVR–11/10

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 243 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 63. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 63 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 243.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

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Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

AT90USB82/162

A return from an interrupt handling routine takes three clock cycles. During these three clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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5. AVR AT90USB82/162 Memories

This section describes the different memories in the AT90USB82/162. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB82/162 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

5.1 In-System Reprogrammable Flash Program Memory

The AT90USB82/162 contains 8K / 16K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The AT90USB82/162 Program Counter (PC) is 16 bits wide, thus addressing the 8K / 16K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Memory Programming” on page 243. “Memory

Programming” on page 243 contains a detailed description on Flash data serial downloading

using the SPI pins or the debugWIRE interface.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description and ELPM - Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

AT90USB82/162

7707F–AVR–11/10

Figure 5-1. Program Memory Map

0x00000

0x1FFF (8KBytes)

0x3FFF (16KBytes)

Program Memory

Application Flash Section

Boot Flash Section

AT90USB82/162

5.2 SRAM Data Memory

Figure 5-2 shows how the AT90USB82/162 SRAM Memory is organized.

The AT90USB82/162 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $0FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 768 Data Memory locations address the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory, and the 512 locations of internal data SRAM.The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Postincrement. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

7707F–AVR–11/10

The 32 general purpose working registers, 64 I/O registers, and the 512 bytes of internal data

32 R

egister

I/O

egister

nterna

SRA

(

512

x 8)

$0000 - $001

$0020 - $005

$0060 - $00

ata

emory

160

Ext I/O

Reg.

$0100

clk

Data

Address

Address valid

T1 T2 T3

Compute Address

Read

Write

CPU

Memory Access Instruction

Next Instruction

SRAM in the AT90USB82/162 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 11.

Figure 5-2. Data Memory Map

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 5-3. On-chip Data SRAM Access Cycles

cycles as described in Figure 5-3.

CPU

5.3 EEPROM Data Memory

The AT90USB82/162 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

AT90USB82/162

7707F–AVR–11/10

For a detailed description of SPI, debugWIRE and Parallel data downloading to the EEPROM, see page 257, page 241, and page 246 respectively.

5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 5-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 23. for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 The EEPROM Address Register – EEARH and EEARL

Bit 1514131211 10 9 8

– – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 2 10

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

XXXXX X XX

AT90USB82/162

• Bits 15..12 – Res: Reserved Bits

These bits are reserved bits in the AT90USB82/162 and will always read as zero.

• Bits 11..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

512. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.3 The EEPROM Data Register – EEDR

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

7707F–AVR–11/10

5.3.4 The EEPROM Control Register – EECR

Bit 765432 10

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the AT90USB82/162 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 5-1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 5-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

Time Operation

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

AT90USB82/162

7707F–AVR–11/10

AT90USB82/162

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Memory Pro-

gramming” on page 243 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 5-2 lists the typical programming time for EEPROM access from the CPU.

Table 5-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also

26,368 3.3 ms

7707F–AVR–11/10

assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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Note: 1. See “About Code Examples” on page 7.

AT90USB82/162

7707F–AVR–11/10

AT90USB82/162

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

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Note: 1. See “About Code Examples” on page 7.

5.3.5 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V

7707F–AVR–11/10

the EEPROM data can be corrupted because the supply voltage is

CC,

reset Protection circuit can

5.4 I/O Memory

be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

The I/O space definition of the AT90USB82/162 is shown in “Register Summary” on page 288.

All AT90USB82/162 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90USB82/162 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1 General Purpose I/O Registers

The AT90USB82/162 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2 General Purpose I/O Register 2 – GPIOR2

Bit 76543210

MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

5.4.3 General Purpose I/O Register 1 – GPIOR1

Bit 76543210

MSB LSB GPIOR1

Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W

Initial Value00000000

5.4.4 General Purpose I/O Register 0 – GPIOR0

Bit 76543210

MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

AT90USB82/162

7707F–AVR–11/10

6. System Clock and Clock Options

General I/O

Modules

CPU Core RAM

clk

I/O

AVR Clock

Control Unit

clk

CPU

Flash and EEPROM

clk

FLASH

Source clock

Watchdog TimerReset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Crystal

Oscillator

External Clock

System Clock

Prescaler

Clock

Switch

Watchdog

Oscillator

USB

clk

USB (48MHz)

PLL Clock

Prescaler

clk

Pllin (8MHz)

USB PLL

clk

XTAL (2-16 MHz)

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 41. The clock systems are detailed below.

Figure 6-1. Clock Distribution

AT90USB82/162

6.1.1 CPU Clock – clk

6.1.2 I/O Clock – clk

6.1.3 Flash Clock – clk

7707F–AVR–11/10

CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

6.1.4 USB Clock – clk

USB

CPU Clock

External Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

3ms

resume

Resume from Host

watchdog wake-up from power-down

6.2 Clock Switch

6.2.1 Exemple of use

USB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48MHz. The PLL always multiply its input frequency by 6. Thus the PLL clock register should be programmed by software to generate a 8MHz clock on the PLL input.

In the AT90USB82/162 product, the Clock Multiplexer and the System Clock Prescaler can be modified by software.

The modification can occur when the device enters in USB Suspend mode. It then switches from External Clock to Calibrated RC Oscillator in order to reduce consumption. In such a configuration, the External Clock is disabled.

The firmware can use the watchdog timer to be woken-up from power-down in order to check if there is an event on the application.

If an event occurs on the application or if the USB controller signals a non-idle state on the USB line (Resume for example), the firmware switches the Clock Multiplexer from the Calibrated RC Oscillator to the External Clock.

Figure 6-2. Example of clock switching with wake-up from USB Host

AT90USB82/162

7707F–AVR–11/10

Figure 6-3. Example of clock switching with wake-up from Device

USB

CPU Clock

External Oscillator

RC oscillator

Ext RC Ext

non-Idle Idle

(Suspend)

non-Idle

3ms

upstream-resume

Upstream Resume from device

watchdog wake-up from power-down

6.2.2 Clock switch Algorythm

6.2.2.1 Swith from external clock to RC clock

if (Usb_suspend_detected()) // if (UDINT.SUSPI == 1)

{

Usb_ack_suspend(); // UDINT.SUSPI = 0;

Usb_freeze_clock(); // USBCON.FRZCLK = 1;

Disable_pll(); // PLLCSR.PLLE = 0;

Enable_RC_clock(); // CLKSEL0.RCE = 1;

while (!RC_clock_ready()); // while (CLKSTA.RCON != 1);

Select_RC_clock(); // CLKSEL0.CLKS = 0;

Disable_external_clock(); // CLKSEL0.EXTE = 0;

}

AT90USB82/162

6.2.2.2 Switch from RC clock to external clock

if (Usb_wake_up_detected()) // if (UDINT.WAKEUPI == 1)

{

Usb_ack_wake_up(); // UDINT.WAKEUPI = 0;

Enable_external_clock(); // CLKSEL0.EXTE = 1;

while (!External_clock_ready()); // while (CLKSTA.EXTON != 1);

Select_external_clock(); // CLKSEL0.CLKS = 1;

Enable_pll(); // PLLCSR.PLLE = 1;

Disable_RC_clock(); // CLKSEL0.RCE = 0;

while (!Pll_ready()); // while (PLLCSR.PLOCK != 1);

Usb_unfreeze_clock(); // USBCON.FRZCLK = 0;

}

6.2.3 Clock Selection Register 0 – CLKSEL0

Bit 7 6543210

Read/Write R/W R/W R/W R/W R/W R/W R R/W

Initial Value 0 0 0 0 See Bit Description

7707F–AVR–11/10

RCSUT1 RCSUT0 EXSUT1 EXSUT0 RCE EXTE - CLKS CLKSEL0

• Bit 7-6 – RCSUT[1:0]: SUT for RC oscillator

These 2 bits are the SUT value for the RC Oscillator. If the RC oscillator is selected by fuse bits, the SUT fuse are copied into these bits. A firmware change will not have any effect because this additionnal start-up time is only used after a reset and not after a clock switch.

• Bit 5-4 – EXSUT[1:0]: SUT for External Oscillator / Low Power Oscillator

These 2 bits are the SUT value for the External Oscillator / Low Power Oscillator. If the External oscillator / Low Power Oscillator is selected by fuse bits, the SUT fuse are copyed into these bits. The firmware can modify these bits by writing a new value. This value will be used at the next start of the External Oscillator / Low Power Oscillator.

• Bit 3 – RCE: Enable RC Oscillator

The RCE bit must be written to logic one to enable the RC Oscillator. The RCE bit must be written to logic zero to disable the RC Oscillator.

• Bit 2 – EXTE: Enable External Oscillator / Low Power Oscillator

The OSCE bit must be written to logic one to enable External Oscillator / Low Power Oscillator. The OSCE bit must be written to logic zero to disable the External Oscillator / Low Power Oscillator.

• Bit 0 – CLKS: Clock Selector

The CLKS bit must be written to logic one to select the External Oscillator / Low Power Oscillator as CPU clock. The CLKS bit must be written to logic zero to select the RC Oscillator as CPU clock. After a reset, the CLKS bit is set by hardware if the External Oscillator / Low Power Oscillator is selected by the fuse bits configuration. The firmware has to check if the clock is correctly started before selected it.

6.2.4 Clock Selection Register 1 – CLKSEL1

Bit 7 6543210

RCCKSEL3RCCKS

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

• Bit 7-4 – RCCKSEL[3:0]: CKSEL for RC oscillator

Clock configuration for the RC Oscillator. After a reset, this part of the register is loaded with the 0010b value that corresponds to the RC oscillator. Modifying this value by firmware before switching to RC oscillator is prohibited because the RC clock will not start.

• Bit 3-0 – EXCKSEL[3:0]: CKSEL for External oscillator / Low Power Oscillator

Clock configuration for the External Oscillator / Low Power Oscillator. After a reset, if the External oscillator / Low Power Oscillator is selected by fuse bits, this part of the register is loaded with the fuse configuration. Firmware can modify it to change the start-up time after the clock switch.

EL2

RCCLK SEL1

RCCLK SEL0

EXCKSEL3EXCKSEL2EXCLKS

EL1

EXCLKS EL0

CLKSEL1

AT90USB82/162

7707F–AVR–11/10

6.2.5 Clock Status Register – CLKSTA

Bit 7 6543210

- - - - - - RCON EXTON CLKSTA

Read/Write R R R R R R R R

Initial Value 0 0 0 0 See Bit Description

• Bit 7-2 - Reserved bits

These bits are reserved and will always read as zero.

• Bit 1 – RCON: RC Oscillator On

This bit is set by hardware to one if the RC Oscillator is running. This bit is set by hardware to zero if the RC Oscillator is stoped.

• Bit 0 – EXTON: External Oscillator / Low Power Oscillator On

This bit is set by hardware to one if the External Oscillator / Low Power Oscillator is running. This bit is set by hardware to zero if the External Oscillator / Low Power Oscillator is stoped.

6.3 Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

AT90USB82/162

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

Low Power Crystal Oscillator 1111 - 1000

Reserved 0111 - 0110

Reserved 0101 - 0100

Reserved 0011

Calibrated Internal RC Oscillator 0010

External Clock 0000

Reserved 0001

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

6.3.1 Default Clock Source

The device is shipped with low power crystal oscillator and with the fuse CKDIV8 programmed. The startup time is set to maximum and time-out period enabled. (CKSEL = "1110", SUT = "01", CKDIV8 = "0").

6.3.2 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.

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to start oscillating and a minimum number of oscillating

7707F–AVR–11/10

To ensure sufficient V

, the device issues an internal reset with a time-out delay (t

TOUT

) after the device reset is released by all other reset sources. “On-chip Debug System” on page 45 describes the start conditions for the internal reset. The delay (t

) is timed from the Watchdog

TOUT

Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage

dependent as shown in “AT90USB82/162 Typical Characteristics – Preliminary Data” on page

268.

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512

65 ms 69 ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.

6.4 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-4. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

AT90USB82/162

7707F–AVR–11/10

+ 277 hidden pages

Atmel AT90USB82, AT90USB162 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

2. Overview

2.1 Block Diagram

2.2 Pin Descriptions

3. About Code Examples

4. AVR CPU Core

4.1 Introduction

4.2 Architectural Overview

4.3 ALU – Arithmetic Logic Unit

4.4 Status Register

4.5 General Purpose Register File

4.6 Stack Pointer

4.7 Instruction Execution Timing

4.8 Reset and Interrupt Handling

5. AVR AT90USB82/162 Memories

5.1 In-System Reprogrammable Flash Program Memory

5.2 SRAM Data Memory

5.3 EEPROM Data Memory

5.4 I/O Memory

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

6.2 Clock Switch

6.3 Clock Sources

6.4 Low Power Crystal Oscillator