– 135 Powe rful Instructions – Most Single Clock Cy cle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 32/64/128K Bytes of In-System Self-Programmable Flash
• Endurance: 100,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• USB Bootloader programmed by default in the Factory
• In-System Programming by On-chip Boot Program hardware activated after
reset
• True Read-While-Write Operation
• All supplied parts are preprogramed with a default USB bootloader
– 2.5K/4K/8K (32K/64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
• JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• USB 2.0 Full-speed/Low-speed Device and On-The-Go Module
– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s
• USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion
– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or
Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request
for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
®
8-Bit Microcontroller
8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channels, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power -on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby
Note:The large center pad underneath the MLF packages is made of metal and internally connected to
GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.
The ATmega32U6/AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
4
7593IS–AVR–02/09
ATmega32U6/AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing
PROGRAM
COUNTER
ST ACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORT A
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORT A
DATA REGISTER
PORTD
INTERRUPT
UNIT
EEPROM
SPIUSART1
ST ATUS
REGISTER
Z
Y
X
ALU
POR TB DRIVERS
POR TE DRIVERS
POR TA DRIVERS
POR TF DRIVERS
POR TD DRIVERS
POR TC DRIVERS
PB7 - PB0PE7 - PE0
PA7 - P A0PF7 - PF0
RESET
VCC
AGND
GND
AREF
XT AL1
XT AL2
CONTROL
LINES
+
-
ANALOG
COMP ARATOR
PC7 - PC0
INTERNAL
OSCILLA TOR
WATCHDOG
TIMER
8-BIT DA TA BUS
AVCC
USB
TIMING AND
CONTROL
OSCILLA TOR
CALIB. OSC
DATA DIR.
REG. PORT C
DATA REGISTER
PORT C
ON-CHIP DEBUG
JTAG TAP
PROGRAMMING
LOGIC
BOUNDARY-
SCAN
DATA DIR.
REG. PORT F
DATA REGISTER
PORT F
ADC
POR - BOD
RESET
PD7 - PD0
TWO-WIRE SERIAL
INTERFACE
PLL
the system designer to optimize power consumption versus processing speed.
2.1Block Diagram
Figure 2-1.Block Diagram
ATmega32U6/AT90USB64/128
7593IS–AVR–02/09
5
ATmega32U6/AT90USB64/128
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega32U6/AT90USB64/128 provides the following features: 32 /64/128K bytes of InSystem Programmable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM,
2.5K/4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers,
Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one
USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the
On-chip Debug system and programming and six software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counte rs , SPI po rt , an d inte rr upt system to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega32U6/AT90USB64/128 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega32U6/AT90USB64/128 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits.
6
7593IS–AVR–02/09
2.2Pin Descriptions
2.2.1VCC
Digital supply voltage.
2.2.2GND
Ground.
2.2.3AVCC
Analog supply voltage.
2.2.4Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 79.
ATmega32U6/AT90USB64/128
2.2.5Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 80.
2.2.6Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega32U6/AT90USB64/128 as
listed on page 83.
2.2.7Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
7593IS–AVR–02/09
Port D also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 84.
7
ATmega32U6/AT90USB64/128
2.2.8Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 87.
2.2.9Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.2.10D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected t o the USB Dconnector pin with a serial 22 Ohms resistor.
2.2.11D+
2.2.12UGND
2.2.13UVCC
2.2.14UCAP
2.2.15VBUS
2.2.16
2.2.17XTAL1
RESET
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.
USB Pads Ground.
USB Pads Internal Regulator Input supply voltage.
USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).
USB VBUS monitor and OTG negociations.
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page
58. Shorter pulses are not guaranteed to gener ate a reset.
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
8
7593IS–AVR–02/09
2.2.18XTAL2
Output from the inverting Oscillator amplifier.
2.2.19AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V
through a low-pass filter.
2.2.20AREF
This is the analog reference pin for the A/D Converter.
CC
3.About Code Examples
This documentation contains simple code examples t hat brief ly show h ow to us e various parts of
the device. Be aware that not all C compiler vendors include bit def initions in the header files
and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
ATmega32U6/AT90USB64/128
, even if the ADC is not used. If the ADC is used, it should be connected to V
Note:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will o perate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instruction s
work with registers 0x00 to 0x1F on ly.
4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The
ATmega32U6/AT90USB64/128 is a complex microcontroller with more peripheral units than can be supported within the 64
location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
--ICF1-OCF1COCF1BOCF1ATOV1
-----OCF0BOCF0ATOV0
7593IS–AVR–02/09
13
ATmega32U6/AT90USB64/128
5.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kB ranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
PC ←(EIND:Z)
PC ←(EIND:Z)
← PC + k + 1None1/2
None2
None4
14
7593IS–AVR–02/09
ATmega32U6/AT90USB64/128
MnemonicsOperandsDescriptionOperationFlags#Clocks
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
SBIP,bSet Bit in I/O RegisterI/O(P,b) ← 1None2
CBIP,bClear Bit in I/O RegisterI/O(P,b) ← 0None2
LSLRdLogical Shift LeftRd(n+1) ← Rd(n), Rd(0) ← 0Z,C,N,V1
LSRRdLogical Shift RightRd(n) ← Rd(n+1), Rd(7) ← 0Z,C,N,V1
ROLRdRotate Left Through CarryRd(0)←C,Rd(n+1)← Rd(n),C← Rd(7)Z,C,N,V1
RORRdRotate Right Through CarryRd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)Z,C,N,V1
ASRRdArithmetic Shift RightRd(n) ← Rd(n+1), n=0..6Z,C,N,V1
BSTRr, bBit Store from Register to TT ← Rr(b)T1
BLDRd, bBit load from T to RegisterRd(b) ← TNone1
SECSet CarryC ← 1C1
CLCClear CarryC ← 0 C1
SENSet Negative FlagN ← 1N1
CLNClear Negative FlagN ← 0 N1
SEZSet Zero FlagZ ← 1Z1
CLZClear Zero FlagZ ← 0 Z1
SEIGlobal Interrupt EnableI ← 1I1
CLIGlobal Interrupt DisableI ← 0 I1
SESSet Signed Test FlagS ← 1S1
CLSClear Signed Test FlagS ← 0 S1
SEVSet Twos Complement Overflow.V ← 1V1
CLVClear Twos Complement OverflowV ← 0 V1
SETSet T in SREGT ← 1T1
CLTClear T in SREGT ← 0 T1
SEHSet Half Carry Flag in SREGH ← 1H1
CLHClear Half Carry Flag in SREGH ← 0 H1
MOVRd, RrMove Between RegistersRd ← RrNone1
MOVWRd, RrCopy Register Word
LDIRd, KLoad ImmediateRd ← KNone1
LDRd, XLoad IndirectRd ← (X)None2
LDRd, X+Load Indirect and Post-Inc.Rd ← (X), X ← X + 1None2
LDRd, - XLoad Indirect and Pre-Dec.X ← X - 1, Rd ← (X)None2
LDRd, YLoad IndirectRd ← (Y)None2
LDRd, Y+Load Indirect and Post-Inc.Rd ← (Y), Y ← Y + 1None2
LDRd, - YLoad Indirect and Pre-Dec.Y ← Y - 1, Rd ← (Y)None2
LDDRd,Y+qLoad Indirect with DisplacementRd ← (Y + q)None2
LDRd, ZLoad Indirect Rd ← (Z)None2
LDRd, Z+Load Indirect and Post-Inc.Rd ← (Z), Z ← Z+1None2
LDRd, -ZLoad Indirect and Pre-Dec.Z ← Z - 1, Rd ← (Z)None2
LDDRd, Z+qLoad Indirect with DisplacementRd ← (Z + q)None2
LDSRd, kLoad Direct from SRAMRd ← (k)None2
STX, RrStore Indirect(X) ← RrNone2
STX+, RrStore Indirect and Post-Inc.(X) ← Rr, X ← X + 1None2
ST- X, RrStore Indirect and Pre-Dec.X ← X - 1, (X) ← RrNone2
STY, RrStore Indirect(Y) ← RrNone2
STY+, RrStore Indirect and Post-Inc.(Y) ← Rr, Y ← Y + 1None2
ST- Y, RrStore Indirect and Pre-Dec.Y ← Y - 1, (Y) ← RrNone2
STDY+q,RrStore Indirect with Displacement(Y + q) ← RrNone2
STZ, RrStore Indirect(Z) ← RrNone2
STZ+, RrStore Indirect and Post-Inc.(Z) ← Rr, Z ← Z + 1None2
ST-Z, RrStore Indirect and Pre-Dec.Z ← Z - 1, (Z) ← RrNone2
STDZ+q,RrStore Indirect with Displacement(Z + q) ← RrNone2
STSk, RrStore Direct to SRAM(k) ← RrNone2
LPMLoad Program MemoryR0 ← (Z)None3
LPMRd, ZLoad Program MemoryRd ← (Z)None3
LPMRd, Z+Load Program Memory and Post-IncRd ← (Z), Z ← Z+1None3
ELPMExtended Load Program MemoryR0 ← (RAMPZ:Z)None3
ELPMRd, ZExtended Load Program MemoryRd ← (Z)None3
ELPMRd, Z+Extended Load Program MemoryRd ← (RAMPZ:Z), RAMPZ:Z ←RAMPZ:Z+1None3
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
Rd+1:Rd ← Rr+1:Rr
None1
7593IS–AVR–02/09
15
ATmega32U6/AT90USB64/128
MnemonicsOperandsDescriptionOperationFlags#Clocks
SPMStore Program Memory(Z) ← R1:R0None-
INRd, PIn PortRd ← PNone1
OUTP, RrOut PortP ← RrNon e1
PUSHRrPush Register on StackSTACK ← RrNone2
POPRdPop Register from StackRd ← STACKNone2
NOPNo OperationNone1
SLEEPSleep(see spec ific descr. for Sleep function)None1
WDRWatchdog Reset(see specific descr. for WDR/timer)None1
BREAKBreakFor On-chip Debug OnlyNoneN/A
MCU CONTROL INSTRUCTIONS
16
7593IS–AVR–02/09
6.Ordering Information
Table 6-1.Possible Order Entries
USB
Ordering Code
interface
Speed
(MHz)
ATmega32U6/AT90USB64/128
Power Supply
(V)PackageOperation RangeProduct Marking
AT90USB1287-16AUOTG8-162.7 - 5.5MD
AT90USB1287-16MU
AT
90USB1286-16MU
AT90USB647-16AUOTG8-162.7 - 5.5MD
AT90USB647-16MU
AT
90USB646-16MU
OTG8-162.7 - 5.5PS
Device
only
OTG8-162.7 - 5.5PS
Device
only
8-162.7 - 5.5PS
8-162.7 - 5.5PS
Industrial (-40° to +85°C)
Green
Industrial (-40° to +85°C)
Green
Industrial (-40° to +85°C)
Green
Industrial (-40° to +85°C)
Green
Industrial (-40° to +85°C)
Green
Industrial (-40° to +85°C)
Green
90USB1287-16AU
90USB1287-16MU
90USB1286-16MU
90USB647-16AU
90USB647-16MU
90USB646-16MU
MD64 - Lead, 14x14 mm Body Size, 1.0mm Body Thickness
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
PS64 - Lead, 9x9 mm Body Size, 0.50mm Pitch
Quad Flat No Lead Package (QFN)
7593IS–AVR–02/09
17
ATmega32U6/AT90USB64/128
6.1TQFP64
18
7593IS–AVR–02/09
ATmega32U6/AT90USB64/128
7593IS–AVR–02/09
19
ATmega32U6/AT90USB64/128
6.2QFN64
20
7593IS–AVR–02/09
ATmega32U6/AT90USB64/128
7593IS–AVR–02/09
21
ATmega32U6/AT90USB64/128
7.Errata
8.AT90USB1287/6 Errata.
8.1AT90USB1287/6 Errata History
Silicon
Release
First ReleaseDate Code up to 0648
Second Release
Third Release
90USB1286-16MU90USB1287-16AU90USB1287-16MU
Date Code from 0709 to 0801
except lots 0801 7H5103*
Lots 0801 7H5103* and
Date Code from 0814
Note ‘*’ means a blank or any alphanumeric string
8.2AT90USB1287/6 First Release
• Incorrect CPU behavior for VBUSTI and IDTI inter rupts rout ines
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• USB signal rate
• VBUS residual level
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
Date Code up to 0714
and lots 0735 6H2726*
from Date Code 0722 to 0806
except lots 0735 6H2726*
Date Code from 0814
Date Code up to 0701
Date Code from 0714 to 0810
except lots 0748 7H5103*
Lots 0748 7H5103* and
Date Code from 0814
22
9. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
8. USB Eye Diagram violation in low-speed mode
The low to high transition of D- violates t he USB eye di agram specificati on when tr ansmitting
with low-speed signaling.
Problem fix/workaround
None.
7. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state f ollowing the per turbation does
7593IS–AVR–02/09
ATmega32U6/AT90USB64/128
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power consumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
6. VBUS Session valid threshold voltage
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
5. UBS signal rate
The average USB signal rate may sometime be measured out of the USB specificatio ns
(12MHz ±30kHz) with short frames. When measured on a long period, the average signal
rate value complies with the specifications. This bit rate deviation does not generates communication or functional errors.
Problem fix/workaround
None.
4. VBUS residual level
In USB device and host mode, once a 5V level has been detected to the VBUS pad, a residual level (about 3V) can be measured on the VBUS pin.
Problem fix/workaround
None.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mod e, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
7593IS–AVR–02/09
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
23
ATmega32U6/AT90USB64/128
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
24
7593IS–AVR–02/09
8.3AT90USB1287/6 Second Release
• Incorrect CPU behavior for VBUSTI and IDTI inter rupts rout ines
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• VBUS Session valid threshold voltage
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
7. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
6. USB Eye Diagram violation in low-speed mode
ATmega32U6/AT90USB64/128
The low to high transition of D- violates t he USB eye di agram specificati on when tr ansmitting
with low-speed signaling.
Problem fix/workaround
None.
5. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state f ollowing the per turbation does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power consumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
4. VBUS Session valid threshold voltage
The VSession valid threshold voltage is internally connected to VBus_Valid (4.4V approx.).
That causes the device to attach to the bus only when Vbus is greater than VBusValid
instead of V_Session Valid. Thus if VBUS is lower than 4.4V, the device is detached.
Problem fix/workaround
According to the USB power drop budget, this may require connecting the device toa root
hub or a self-powered hub.
7593IS–AVR–02/09
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
25
ATmega32U6/AT90USB64/128
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mod e, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep again it may wake up multiple times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
26
7593IS–AVR–02/09
8.4AT90USB1287/6 Third Release
• Incorrect CPU behavior for VBUSTI and IDTI inter rupts rout ines
• Transient perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
5. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
4. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state f ollowing the per turbation does
not set the SUSPI bit. The internal USB e ngine remains in suspend mode but the USB differential receiver is still enabled and generates a typical 300µA extra-power consumption.
Detection of the suspend state after the transient perturbation should be performed by software (instead of reading the SUSPI bit).
ATmega32U6/AT90USB64/128
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega3 2U6/AT90USB64/128 TW I first, before the others
nodes of the TWI network.
2. High current consumption in sleep mode
If a pending interrupt cannot wake the part up from the selected mod e, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from sleep mode should be
disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep mode and wakes-up from an asynchronous timer interrupt and
then goes back into sleep mode, it may wake up multiple times.
7593IS–AVR–02/09
Problem Fix/workaround
27
ATmega32U6/AT90USB64/128
A software workaround is to wait beforeperforming the slee p instruction: until
TCNT2>OCR2+1.
9.AT90USB647/6 Errata.
• Incorrect interrupt routine exection for VBUSTI, IDTI interrupts flags
• USB Eye Diagram violation in low-speed mode
• Transient perturbation in USB suspend mode generates over consumption
• Spike on TWI pins when TWI is enabled
• High current consumption in sleep mode
• Async timer interrupt wake up from sleep generate multiple interrupts
6. Incorrect CPU behavior for VBUSTI and IDTI interrupts routines
The CPU core may incorrectly execute the interrupt vector related to the VBUSTI and IDTI
interrupt flags.
Problem fix/workaround
Do not enable these interrupts, firmware must process these USB events by polling VBUSTI
and IDTI flags.
5. USB Eye Diagram violation in low-speed mode
The low to high transition of D- violates t he USB eye di agram specificati on when tr ansmitting
with low-speed signaling.
Problem fix/workaround
None.
4. Transient perturbation in USB suspend mode generates overconsumption
In device mode and when the USB is suspended, transient perturbation received on the
USB lines generates a wake up state. However the idle state f ollowing the per turbation does
not set the SUSPI bit anymore. The internal USB engine remains in suspend mode but the
USB differential receiver is still enabled and generates a typical 300µA extra-power consumption. Detection of the suspend state after the transient perturbation should be
performed by software (instead of reading the SUSPI bit).
Problem fix/workaround
USB waiver allows bus powered devices to consume up to 2.5mA in suspend state.
3. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
2. High current consumption in sleep mode
28
7593IS–AVR–02/09
If a pending interrupt cannot wake the part up from the selected mod e, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI
instruction.
Problem Fix/workaround
Before entering sleep, interrupts not used to wake up the part from the sleep mode should
be disabled.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep mode again it may wake up several times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
10. ATmega32U6 Errata.
• Spike on TWI pins when TWI is enabled
• Async timer interrupt wake up from sleep generate multiple interrupts
ATmega32U6/AT90USB64/128
2. Spike on TWI pins when TWI is enabled
100 ns negative spike occurs on SDA and SCL pins when TWI is enabled.
Problem Fix/workaround
No known workaround, enable ATmega32U6/AT90USB64/128 TWI first versus the others
nodes of the TWI network.
1. Asynchronous timer interrupt wake up from sleep generates multiple interrupts
If the CPU core is in sleep and wakes-up from an asynchronous timer interrupt and then go
back in sleep mode again it may wake up several times.
Problem Fix/workaround
A software workaround is to wait with performing the sleep instruction until
TCNT2>OCR2+1.
7593IS–AVR–02/09
29
ATmega32U6/AT90USB64/128
11. Datasheet Revision History for ATmega32U6/AT90USB64/128
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
11.1Changes from 7593A to 7593B
1. Changed default configuration for fuse byte s and security byte.
2. Suppression of timer 4,5 registers which does not exist.
3. Updated typical application schematics in USB section
11.2Changes from 7593B to 7593C
1. Update to package drawings, MQFP64 and TQFP64.
11.3Changes from 7593C to 7593D
1. For further product compatibility, changed USB PLL possible prescaler configurations.
Only 8MHz and 16MHz crystal frequencies allows USB operation (See Table 6-11 on
page 49).
11.4Changes from 7593D to 7593E
1. Updated PLL Prescaler table: configuration words are different between AT90USB64x
and AT90USB128x to enable the PLL with a 16 MHz source.
2. Cleaned up some bits from USB registers, and updat ed information about OTG timers ,
remote wake-up, reset and connection timings.
3. Updated clock distribution tree diagram (USB prescaler source and configuration
register).
4. Cleaned up register summary.
5. Suppressed PCINT23:8 that do not exist from External Interrupts.
6. Updated Electrical Characteristics.
7. Added Typical Characteristics.
8. Update Errata section.
11.5Changes from 7593E to 7593F
1. Removed ’Preliminary’ from document status.
2. Clarification in Stand by mode regarding USB.
11.6Changes from 7593F to 7593G
1. Updated Errata section.
11.7Changes from 7593G to 7593H
1. Added Signature information for 64K devices.
2. Fixed figure for typical bus powered application
3. Added min/max values for BOD levels
4. Added ATmega32U6 product
5. Update Errata section
6. Modified descriptions for HWUPE and WAKEUPE interrupts enable (these interrupts
should be enabled only to wake up the CPU core from power down mode).
30
7593IS–AVR–02/09
7. Added description to access unique serial number located in Signature Row see
“Reading the Signature Row from Software” on page 360.
11.8Changes from 7593H to 7593I
1. Updated Table 8-2 in “Brown-out Detection” on page 60. Unused BOD levels removed.
ATmega32U6/AT90USB64/128
7593IS–AVR–02/09
31
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