ATMEL AT90USB647 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 135 Powe rful Instructions – Most Single Clock Cy cle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 32/64/128K Bytes of In-System Self-Programmable Flash

• Endurance: 100,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• USB Bootloader programmed by default in the Factory

• In-System Programming by On-chip Boot Program hardware activated after
reset

• True Read-While-Write Operation

• All supplied parts are preprogramed with a default USB bootloader

– 1K/2K/4K (32K/64K/128K Flash version) Bytes EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 2.5K/4K/8K (32K/64K/128K Flash version) Bytes Internal SRAM
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• USB 2.0 Full-speed/Low-speed Device and On-The-Go Module

– Complies fully with:
– Universal Serial Bus Specification REV 2.0
– On-The-Go Supplement to the USB 2.0 Specification Rev 1.0
– Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s

• USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers : up to 64-bytes
– 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers
– Configurable Endpoints size up to 256 bytes in double bank mode
– Fully independant 832 bytes USB DPRAM for endpoint memory allocation
– Suspend/Resume Interrupts
– Power-on Reset and USB Bus Reset
– 48 MHz PLL for Full-speed Bus Operation
– USB Bus Disconnection on Microcontroller Request

• USB OTG Reduced Host :

– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

for OTG dual-role devices
– Provide Status and control signals for software implementation of HNP and SRP
– Provides programmable times required for HNP and SRP

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode

®

8-Bit Microcontroller

8-bit
Microcontroller
with
64/128K Bytes
of ISP Flash
and USB
Controller

ATmega32U6*
AT90USB646
AT90USB647
AT90USB1286
AT90USB1287

*Preliminary
Summary

7593IS–AVR–02/09

ATmega32U6/AT90USB64/128

– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channels, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power -on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Pac kages

– 48 Programmable I/O Lines
– 64-lead TQFP and 64-lead QFN

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range
– 16 MHz at 4.5V - Industrial range

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7593IS–AVR–02/09

1. Pin Configurations

ATmega32U6

AT90USB90128/64

TQFP64

(INT.7/AIN.1/UVcon) PE7

UVcc

D-

D+
UGnd
UCap

VBus

(IUID) PE3

(SS/PCINT0) PB0

(INT.6/AIN.0) PE6

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

(PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4
(PCINT5/OC.1A) PB5
(PCINT6/OC.1B) PB6

(PCINT7/OC.0A/OC.1C) PB7

(INT4/TOSC1) PE4

(INT.5/TOSC2) PE5

RESET

VCC

GND

XTAL2

XTAL1

(OC0B/SCL/INT0) PD0

(OC2B/SDA/INT1) PD1

(RXD1/INT2) PD2

(TXD1/INT3) PD3

(ICP1) PD4

(XCK1) PD5

PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PE2 (ALE/HWB)
PC7 (A15/IC.3/CLKO)
PC6 (A14/OC.3A)
PC5 (A13/OC.3B)
PC4 (A12/OC.3C)
PC3 (A11/T.3)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PE1 (RD)
PE0 (WR)

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

(T1) PD6

(T0) PD7

INDEX CORNER

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Figure 1-1. Pinout ATmega32U6/AT90USB64/128-TQFP

ATmega32U6/AT90USB64/128

7593IS–AVR–02/09

3

ATmega32U6/AT90USB64/128

Figure 1-2. Pinout ATmega32U6/AT90USB64/128-QFN

2

3

1

4
5
6
7
8

9
10
11
12
13
14

16 33

15

47

46

48

45
44
43
42
41
40
39
38
37
36
35
34

17

182019

21222324252627

29

28

32

31

30

525150

49

6463625361

60

59

58

57

56

55

54

ATmega32U6

AT90USB128/64

(64-lead QFN top view)

INDEX CORNER

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

(INT.7/AIN.1/UVcon) PE7

UVcc

D-

D+

UGnd

UCap

VBus

(IUID) PE3

(SS/PCINT0) PB0

(INT.6/AIN.0) PE6

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

(PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4

(PCINT5/OC.1A) PB5

(PCINT6/OC.1B) PB6

(INT4/TOSC1) PE4

(INT.5/TOSC2) PE5

VCC

GND

XTAL2

XTAL1

(OC0B/SCL/INT0) PD0

(OC2B/SDA/INT1) PD1

(RXD1/INT2) PD2

(TXD1/INT3) PD3

(ICP1) PD4

(XCK1) PD5

(T1) PD6

(T0) PD7

RESET

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE2 (ALE/HWB)

PC7 (A15/IC.3/CLKO)

PC6 (A14/OC.3A)

PC5 (A13/OC.3B)

PC4 (A12/OC.3C)

PC3 (A11/T.3)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PE1 (RD)

PE0 (WR)

1.1 Disclaimer

2. Overview

Note: The large center pad underneath the MLF packages is made of metal and internally connected to

GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center
pad is left unconnected, the package might loosen from the board.

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es
will be available after the device is characterized.

The ATmega32U6/AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

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7593IS–AVR–02/09

ATmega32U6/AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing

PROGRAM
COUNTER

ST ACK

POINTER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

GENERAL
PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTB

DATA DIR.

REG. PORTE

DATA DIR.

REG. PORT A

DATA DIR.

REG. PORTD

DATA REGISTER

PORTB

DATA REGISTER

PORTE

DATA REGISTER

PORT A

DATA REGISTER

PORTD

INTERRUPT

UNIT

EEPROM

SPIUSART1

ST ATUS

REGISTER

Z

Y

X

ALU

POR TB DRIVERS

POR TE DRIVERS

POR TA DRIVERS

POR TF DRIVERS

POR TD DRIVERS

POR TC DRIVERS

PB7 - PB0PE7 - PE0

PA7 - P A0PF7 - PF0

RESET

VCC

AGND

GND

AREF

XT AL1

XT AL2

CONTROL

LINES

+

-

ANALOG

COMP ARATOR

PC7 - PC0

INTERNAL

OSCILLA TOR

WATCHDOG

TIMER

8-BIT DA TA BUS

AVCC

USB

TIMING AND

CONTROL

OSCILLA TOR

CALIB. OSC

DATA DIR.

REG. PORT C

DATA REGISTER

PORT C

ON-CHIP DEBUG

JTAG TAP

PROGRAMMING

LOGIC

BOUNDARY-

SCAN

DATA DIR.

REG. PORT F

DATA REGISTER

PORT F

ADC

POR - BOD

RESET

PD7 - PD0

TWO-WIRE SERIAL

INTERFACE

PLL

the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

ATmega32U6/AT90USB64/128

7593IS–AVR–02/09

5

ATmega32U6/AT90USB64/128

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega32U6/AT90USB64/128 provides the following features: 32 /64/128K bytes of In­System Programmable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM,

2.5K/4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers,
Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one
USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differen­tial input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the
On-chip Debug system and programming and six software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counte rs , SPI po rt , an d inte rr upt sys­tem to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power­save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On­chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega32U6/AT90USB64/128 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.

The ATmega32U6/AT90USB64/128 AVR is supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators, in­circuit emulators, and evaluation kits.

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7593IS–AVR–02/09

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 AVCC

Analog supply voltage.

2.2.4 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port A also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 79.

ATmega32U6/AT90USB64/128

2.2.5 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the

ATmega32U6/AT90USB64/128 as listed on page 80.

2.2.6 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port C also serves the functions of special features of the ATmega32U6/AT90USB64/128 as
listed on page 83.

2.2.7 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

7593IS–AVR–02/09

Port D also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 84.

7

ATmega32U6/AT90USB64/128

2.2.8 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active,
even if the clock is not running.

Port E also serves the functions of various special features of the
ATmega32U6/AT90USB64/128 as listed on page 87.

2.2.9 Port F (PF7..PF0)

Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit) . The Por t F outpu t buffers ha ve sym­metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a res et cond ition beco mes a ctive, ev en if th e clock is not ru nning. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.2.10 D-

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected t o the USB D­connector pin with a serial 22 Ohms resistor.

2.2.11 D+

2.2.12 UGND

2.2.13 UVCC

2.2.14 UCAP

2.2.15 VBUS

2.2.16

2.2.17 XTAL1

RESET

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.

USB Pads Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capac­itor (1µF).

USB VBUS monitor and OTG negociations.

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

58. Shorter pulses are not guaranteed to gener ate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

8

7593IS–AVR–02/09

2.2.18 XTAL2

Output from the inverting Oscillator amplifier.

2.2.19 AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con­nected to V
through a low-pass filter.

2.2.20 AREF

This is the analog reference pin for the A/D Converter.

CC

3. About Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of
the device. Be aware that not all C compiler vendors include bit def initions in the header files
and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume n­tation for more details.

These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

ATmega32U6/AT90USB64/128

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

7593IS–AVR–02/09

9

ATmega32U6/AT90USB64/128

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - - ­(0xFE) Reserved - - - - - - - ­(0xFD) Reserved - - - - - - - ­(0xFC) Reserved - - - - - - - ­(0xFB) Reserved
(0xFA) Reserved
(0xF9) OTGTCON PAGE VALUE
(0xF8) UPINT PINT7:0
(0xF7) UPBCHX - - - - - PBYCT10:8
(0xF6) UPBCLX PBYCT7:0
(0xF5) UPERRX - COUNTER1:0 CRC16 TIMEOUT PID DATAPID DATATGL
(0xF4) UEINT EPINT6:0
(0xF3) UEBCHX - - - - -BYCT10:8
(0xF2) UEBCLX BYCT7:0
(0xF1) UEDATX DAT7:0
(0xF0) UEIENX FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE
(0xEF) UESTA1X
(0xEE) UESTA0X CFGOK OVERFI UNDERFI
(0xED) UECFG1X EPSIZE2:0 EPBK1:0 ALLOC
(0xEC) UECFG0X EPTYPE1:0 - - EPDIR
(0xEB) UECONX STALLRQ STALLRQC RSTDT EPEN
(0xEA) UERST EPRST6:0
(0xE9) UENUM EPNUM2:0
(0xE8) UEINTX FIFOCON NAKINI RWAL NAKOUTI RXSTPI RXOUTI STALLEDI TXINI
(0xE7) Reserved - - - ­(0xE6) UDMFN FNCERR
(0xE5) UDFNUMH FNUM10:8
(0xE4) UDFNUML FNUM7:0
(0xE3) UDADDR ADDEN UADD6:0
(0xE2) UDIEN UPRSME EORSME WAKEUPE EORSTE SOFE SUSPE
(0xE1) UDINT UPRSMI EORSMI WAKEUPI EORSTI SOFI SUSPI
(0xE0) UDCON LSM RMWKUP DETACH
(0xDF) OTGINT STOI HNPERRI ROLEEXI BCERRI VBERRI SRPI
(0xDE) OTGIEN STOE HNPERRE ROLEEXE BCERRE VBERRE SRPE
(0xDD) OTGCON HNPREQ SRPREQ SRPSEL VBUSHWC VBUSREQ VBUSRQC
(0xDC) Reserved
(0xDB) Reserved
(0xDA) USBINT IDTI VBUSTI
(0xD9) USBSTA SPEED ID VBUS
(0xD8) USBCON USBE HOST FRZCLK OTGPADE IDTE VBUSTE
(0xD7) UHWCON UIMOD UIDE UVCONE UVREGE
(0xD6) Reserved
(0xD5) Reserved
(0xD4) Reserved
(0xD3) Reserved
(0xD2) Reserved - - - - - - - ­(0xD1) Reserved
(0xD0) Reserved
(0xCF) Reserved
(0xCE) UDR1 USART1 I/O Data Register
(0xCD) UBRR1H
(0xCC) UBRR1L USART1 Baud Rate Register Low Byte
(0xCB) Reserved
(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1
(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81
(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 PE1 U2X1 MPCM1
(0xC7) Reserved
(0xC6) Reserved
(0xC5) Reserved - - - - - - - ­(0xC4) Reserved
(0xC3) Reserved - - - - - - - ­(0xC2) Reserved
(0xC1) Reserved
(0xC0) Reserved - - - - - - - ­(0xBF) Reserved

- - - - - - - -

- - - - - - - -

- - - - - CTRLDIR CURRBK1:0

- DTSEQ1:0 NBUSYBK1:0

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - USART1 Baud Rate Register High Byte

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

- - - - - - - -

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