ATMEL AT90USB162 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High Perf ormance, Low Power AVR

• Advanced RISC Architecture

– 125 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Ope ration – Up to 16 MIPS Throughput at 16 MHz

• Non-volatile Program and Data Memories

– 8K / 16K Bytes of In-System Self-Programmable Flash

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• USB boot-loader programmed by default in the factory

• In-System Programming by on-chip Boot Pr ogram hardware-activated after reset

• True Read-While-Write Operation

– 512 Bytes EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 512 Bytes Internal SRAM – Programming Lock for Software Security

• USB 2.0 Ful l-speed Device Module with Interrupt on Transfer Completion

– Complies fully with Universal Serial Bus Specification REV 2.0 – 48 MHz PLL for Full-speed Bus Operation : data transfer rates at 12 Mbit/s – Fully independant 176 bytes USB DPRAM for endpoint memory allocation – Endpoint 0 for Control Transfers: from 8 up to 64-bytes – 4 Programmable Endpoints:

• IN or Out Directions

• Bulk, Interrupt and IsochronousTransfers

• Programmable maximum packet size from 8 to 64 bytes

• Programmable single or double buffer

– Suspend/Resume Interrupts – Microcontroller reset on USB Bus Reset without detach – USB Bus Disconnection on Microcontroller Request – USB pad multiplexed with PS/2 peripheral for single cable capability

• Peripheral Features

– PS/2 compliant pad – One 8-bit Timer/Counters with Separate Prescaler and Compare Mode (two 8-bit

PWM channels)

– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Mode

(three 8-bit PWM channels) – USART with SPI master only mode and hardware flow control (RTS/CTS) – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• On Chip Debug Interface (debugWIRE)

• Special Microcontroller Features

– Power-On Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources

8-Bit Microcontroller

8-bit Microcontroller with 8/16K Bytes of ISP Flash and USB Controller

AT90USB82 AT90USB162

7707DS–AVR–07/08

– Five Sleep Modes: Idle, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 22 Programable I/O Lines – QFN32 (5x5mm) / TQFP32 packages

• Operating Voltages

– 2.7 - 5.5V

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range

AT90USB82/162

7707DS–AVR–07/08

1. Pin Configurations

UVCC

QFN32

(PCINT11) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5) PD4

(TXD1 / INT3) PD3

(XCK / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

2827 26 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D- / SDATA

D+ / SCK

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / INT6) PD6

(CTS / HWB / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVCC

UVCC

VQFP32

(PCINT11) PC2

(OC.0B / INT0) PD0

VCC

XTAL1

(INT5) PD4

(TXD1 / INT3) PD3

(XCK / PCINT12) PD5

PB3 (PDO / MISO / PCINT3)

GND

(PC0) XTAL2

UGND

PB4 (T1 / PCINT4)

2827 26 1 2 3 4 5

6 7

24 23 22 21 20 19 18

1211109131415

(AIN0 / INT1) PD1

PB6 (PCINT6)

D- / SDATA

D+ / SCK

2529303132

PB7 (PCINT7 / OC.0A / OC.1C)

PB5 (PCINT5)

PC7 (INT4 / ICP1 / CLKO)

PC6 (OC.1A / PCINT8)

Reset

(PC1 / dW)

PC5 ( PCINT9/ OC.1B)

PC4 (PCINT10)

UCAP

(RXD1 / AIN1 / INT2) PD2

(RTS / INT6) PD6

(CTS / HWB / T0 / INT7) PD7

(SS

/ PCINT0) PB0

(SCLK / PCINT1) PB1

(PDI / MOSI / PCINT2) PB2

AVCC

Figure 1-1. Pinout AT90USB82/162

AT90USB82/162

1.1 Disclaimer

Note: The large center pad underneath the QFN packages is made of metal and must be connected to

GND. It should be sold ered or g lued to the boar d to ens ure good mech anica l st abili ty. If the c enter pad is left unconnected, the package might loosen from the board.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

7707DS–AVR–07/08

2. Overview

PROGRAM COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

SRAM

GENERAL PURPOSE

REGISTERS

INSTRUCTION

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

INTERRUPT

UNIT

EEPROM

USART1

STATUS

ALU

PORTC DRIVERS

PORTD DRIVERS

PORTB DRIVERS

PC7 - PC0 PD7 - PD0

RESET

VCC

GND

XTAL1

XTAL2

CONTROL

LINES

ANALOG

COMPARATOR

PB7 - PB0

D+/SCK D-/SDATA

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB

PS/2

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

ON-CHIP DEBUG

Debug-Wire

PROGRAMMING

LOGIC

DATA DIR.

REG. PORTD

DATA REGISTER

PORTD

POR - BOD

RESET

PLL

SPI

ON-CHIP

3.3V

REGULATOR

UVcc

UCap

1uF

The AT90USB82/162 is a low-power CMOS 8- bit micr ocon troller bas ed on th e AVR en hanced RISC ar chite cture. By executing powerful instructions in a single clock cycl e, the AT90USB82/162 ac hieves throughputs app roaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core com bin es a rich instruction set with 32 general pur pos e worki ng regi ste rs . A ll the 32 registers are direc tly c onn ec ted to the Ari thme t ic Lo gi c Un it ( A LU), al lo wing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting

AT90USB82/162

7707DS–AVR–07/08

AT90USB82/162

architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90USB82/162 pro vides the followi ng featu res: 8K / 16 K byte s of In-Sy stem Pr ogram mable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 22 general purpose I/O lines , 32 gene ral purp ose work ing reg isters , two flex ible Time r/Coun ters with compare modes and PWM, one USART, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, debugW IRE interface, als o used for access ing the On-chip Deb ug system and programming and five software selectable power saving modes. Th e Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-do wn mode sav es the registe r content s but freezes the Oscil lator, disa bling all other chip functions until the next interrupt or Hardware Reset. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined wit h low power co ns ump tio n. In E xte nde d Sta ndb y mo de, the main Oscillator continues to run.

The device is manufac ture d using Atmel’s high-density nonv ol atil e me mory tec hno log y. Th e onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventi onal nonvola tile memory progr ammer, or by an on-chi p Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, prov iding true Read-Whi le-Write operation. By combining an 8-bit RISC CP U with In-System Self-Programm able Flash on a monolithi c chip, the Atmel AT90US B82/ 162 i s a powerful mic rocon troller tha t pr ovides a hi ghly flexi ble a nd c ost effective solution to many embedded control applications.

The AT90USB82/162 AVR is supported with a full suite of program and system develop ment tools including: C co mpile rs, m acro as sembl ers, pr ogram deb ugg er/simu lator s, in-c ircuit e mulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port B (PB7..PB0)

Port B is an 8-bi t b i- dire ctional I/O port with in terna l pul l- up res ist ors (se le cte d f or ea ch bi t). T h e Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated whe n a rese t condition bec omes activ e, even if the clock is not running.

Port B also ser ves th e f unctions of variou s spec ial featu res of the A T90USB 82/16 2 as listed o n

page 74.

7707DS–AVR–07/08

2.2.4 Port C (PC7..PC0)

Port C is an 8-bit bi- dire ct ion al I/O po rt with in ter na l p ull- up r esi sto rs ( s ele ct ed fo r eac h b it). T h e Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pi ns are tri-stated when a res et condition bec omes active, even if the clock is not running.

Port C also serves the function s of various spe cial features of the AT 90USB82 /162 as liste d on

page 76.

2.2.5 Port D (PD7..PD0)

Port D serves as analog inputs to the analog comparator. Port D also serves as an 8-bit bi-directional I/O port, if the analog comparator is not used (con-

cerns PD2/PD1 pins). Port pins can provide internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pi ns are tri-stated when a res et condition bec omes active, even if the clock is not running.

2.2.6 D-/SDATA

USB Full Speed Negative Data Upstream Port / Data port for PS/2

2.2.7 D+/SCK

USB Full Speed Positive Data Upstream Port / Clock port for PS/2

2.2.8 UGND

2.2.9 UVCC

2.2.10 UCAP

2.2.11 RESET/PC1/dW

2.2.12 XTAL1

2.2.13 XTAL2/PC0

USB Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not runni ng. The minim um pulse l ength is given in Section 9.. Shorter pulses are not guaranteed to generate a reset. This pin alternatively serves as debugWire channel or as generic I/O. The configuration depends on the fuses RSTDISBL and DWEN.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier if enabled by Fuse. Also serves as a generic I/O.

AT90USB82/162

7707DS–AVR–07/08

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