Apple iPhone X Schematics

8

7

6 5 4 3

1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA

PCB 820-00863-09 X891 Intel Edition TOP MLB

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C

B

A

8

TOP SIDE ASSEMBLY

3

APPLE

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR

062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.

DESIGNER

KEN KIPLINGER

DATE

03/31/17

SCALE

1:1

TITLE

PCBF, X891

TOP MLB

DRAWING NUMBER

820-00863-09

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

124567

A

8

7

6 5 4 3

1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA

PCB 820-00869-06 X893 Intel Edition TOP MLB

2 1

D

C

B

A

R5807

C5807

FL5806

C5806

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*

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QUADP_K

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C600_K

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PP7630_W

PP7631_W

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PP7624_W

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PP1643_K

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C5029

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L1010_K

L1001_K

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C602_K

R7600_W

R614_K

*

MHBPA_K

C416_K

*

C605_K

XCVR0_K

L1012_K

C614_K

C610_K

L1027_K

C604_K

R1000_K

L1009_K

L1006_K

C430_K

L1003_K
L1013_K

C7603_W

XW600_K

*

*

L1007_K

C7600_W

C616_K

*

L1011_K

C7601_W

C645_K

L1005_K

C432_K

C907_K

C615_K

R603_KR606_KC620_KC649_K

R1605_K

C7606_W

*

R1606_K

C7604_W

*

C905_K

R1611_K

C7609_W

R1612_K

*

L7600_W

*

C411_K

*

C607_K

*

C619_K

XW503_K

R1602_K

*

J_SIM_K

C511_K

C517_K

R1603_K

*

C7611_W

C906_KC900_K

R5001

C5016

C5015

C5018

C518_K

C516_K

C5019

**

C508_K

C523_KC509_K

XW500_K

C522_K

BBPMU_K

C503_K

*

C439_KC419_K

R205_K

C410_K

C438_K

R1601_K

C435_K

C424_K

R1600_K

*

C7602_W

*

C7608_W

C7607_W

*

C7612_WC720_K

XW3043

DSM_K

LBPA_K

EPROM_K

R0630

R203_K

R501_K

C200_K

R209_K

R204_K

R207_K

C510_K

C505_K

C404_K

C413_K

C415_K

C437_K

C428_K

C403_K

R206_K

C409_K

C301_K

C431_K

C422_K

C4927

C408_K

*

C507_K

C4905

ET_K

C722_K

C721_K

XW701_K

R1200_K

C1200_KR1202_K

C1202_K

C635_KR609_K

C638_K

C627_K

FL600_K

*

C513_K

C4928

R1201_KC1201_K

C637_K

C1204_KC1203_K

C628_K

R610_K

C632_K

C512_K

C4914

C421_K

C4904

C4932

C4903

*

C4931

*

C723_K

L1016_K

*

C903_K

L800_K

*

*

*

*

*

C626_K

R600_K

*

C809_K

C804_K

C519_K

C4926

C625_K

SWTX1_K

C904_K

C813_K

R800_K

*

C631_K

C630_K

C810_K

C806_K

C812_K

L803_K

*

C803_K

*

*

*

*

C1001_K

C520_K

*

*

C506_K

*

C504_KC521_K

*

*

R607_K

C622_K

C805_K

C807_K

C811_K

C4925

C4909

*

C4907

*

L1021_K

C621_K

*

L503_K

XW504_K

C500_K

XW501_K

L500_K

*

C514_K

*

C515_K

L501_K

C502_K

XW502_K

C4934

C4929

C4922

U4900

C4930

L4900

*

FD0401

FD0410

*

C623_K

*

*

C624_K

L1023_K

C629_K

R616_K

XCVR1_K

* *

L1000_K

TDDPA_K

GSMPA_K

*

L1024_K

*

L1017_K

C634_K

C636_K

R801_K

C801_K

C815_K

*

*

XW800_K

C808_K

R615_K

C5945_K

C633_K

*

C642_K

C650_K

DZ1609_K

*

C644_K

*

C643_K

DZ1606_K

*

*

*

C800_K

L1015_K

L1018_KL1019_K

L1020_KL1025_KL1026_K

FD0402

FD0411

TP0720

TP0721

PP1602_K

PP1601_K

*

JUAT1_K

FD0406

FD0415

L1700_K

L1701_KC1305_KC1304_KL1300_K

*

C1306_K

C1302_K

*

C1303_K

C1406_K

C7515_S

C7533_S

C7532_S

C7531_S

C7530_S

L7500_S

C7504_S

MC_K

FD0405

FD0414

C7709_W

R7700_W

C7701_W

*

FL5809

C5809

FL5810

C5810

FL5802

C5802

FL5895

C5895

C5804

FL5804

C5803

FL5803

C5891

C5896

C5894

C5893

C5847

FL5847

C5892

C5840

C5841

C1707_K

GPOLAT_K

C1101_K

*

R1406_K

R1405_K

C1402_K

C1405_K

*

GPOUAT_K

C1407_K
R1500_K

*

FL1400_K

Q7502_S

*

Q7501_S

C7526_S

C7506_S

C7511_S

*

C7520_S

C7517_S

C7503_S

*

*

*

NFC_S

C5000

C3451

C3452

C3453

*

*

C3403

C3402

*

C5530

R3460

R302_K

C303_K

TCXO_K

*

W5BPF_W

*

R7711_W

*

C1601_K

C5860

R5801

C5890

FL5890

FL5896

FL5894

FL5893

*

FL5891

FL5840

FD0404

FL5841

FD0412

*

C7712_W

R7701_W

C7703_W

L1100_K

C1103_K

*

C1706_K

C1705_K

C1703_K

L1703_K

*

C1704_K

FL1102_K

*

C1114_K

L1702_K

C1711_K

C1710_K

C1708_K

C1115_K

*

C1116_K

*

C1102_K

R1102_K

R1101_K

LBLN_K

*

*

C1700_K

R1700_K

C1701_K

C7507_S

C7518_S

C7516_S

R7508_S

C7512_S

C7514_S

C7510_S

T7500_S

L7501_S

C7505_S

C7513_S

R7502_S

C5001

C3455

C3456

C3454

*

*

R7702_W

C7708_W

*

*

C7705_W

L7704_W

*

W25DI_W

W2BPF_W

*

L7700_WL7701_W

W2XSW_W

R7703_W

*

C7716_W

*

J5800

*

JLAT1_K

*

SB0400

FD0403

FD0413

PP7508_S

PP7510_S

PP7505_S

PP7504_S

PP7503_S

PP7509_S

PP1613_K

TP0730

TP0731

TP0522

TP0515

TP0768

PP7507_S

PP7506_S

TP0766

TP0760

TP0762

TP0758

TP0771

TP0772

TP0767

D

C

B

A

8

TOP SIDE ASSEMBLY

3

APPLE

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR
062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.

DESIGNER

TIM REID

DATE

04/06/17

SCALE

1:1

TITLE

PCBF, X893

MLB BOT

DRAWING NUMBER

820-00869-06

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE
THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

124567

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6 5 4 3

X891/X893 MLB Top: EVT

LAST_MODIFICATION=Mon Apr 3 13:03:06 2017

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2017-04-0500084097609 ENGINEERING RELEASED

D

1
2
3
4
5
6
7
8
9
10
11
12

1
2
4
5
6
10
11
12
13
14
15
16

TABLE OF CONTENTS
SYSTEM:BOM Tables
SYSTEM: Mechanical Components
SYSTEM: Testpoints (Top)
BOOTSTRAPPING
SOC: JTAG,USB,XTAL
SOC: PCIE
SOC: MIPI & ISP
SOC: LPDP
SOC: Serial
SOC: GPIO & UART
SOC: AOP

test_mlb

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

10/13/2016

10/13/2016
10/13/2016
10/17/2016
10/17/2016
10/13/2016
10/13/2016
10/17/2016
10/13/2016
10/17/2016

46
47
48
49
50
51

61
62
63
64
65
80

I/O: Accessory Buck
I/O: USB PD
I/O: Hydra
I/O: B2B Dock
I/O: Interposer (Bottom)
RADIOS

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

D

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

10/17/2016
10/13/2016
10/13/2016
10/13/2016
10/13/2016
06/04/2015

C

13
14
15
16
17
18
19
20
21
22
23
24
25
26

17
18
19
26
27
28
29
30
31
32
33
34
35
36

SOC: Power (1/3)
SOC: Power (2/3)
SOC: Power (3/3)
NAND
SYSTEM POWER: PMU Bucks (1/4)
SYSTEM POWER: PMU Bucks (2/4)
SYSTEM POWER: PMU LDOs (3/4)
SYSTEM POWER: PMU (4/4)
SYSTEM POWER: Boost
SYSTEM POWER: B2B Battery
SYSTEM POWER: Charger
SYSTEM POWER: Iktara
SYSTEM POWER: B2B Cyclone + Button
SENSORS

test_mlb
test_mlb
test_mlb
test_mlb

10/17/2016
10/17/2016
10/17/2016

10/13/2016
test_mlb 10/13/2016
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

test_mlb
test_mlb

10/13/2016

10/13/2016

11/01/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

C

B

27
28
29
30
31
32

34
35
36
37
38
39
40

37
38
39
40
41
42
4333
44
45
46
47 test_mlb
48

CAMERA: PMU (1/2)
CAMERA: PMU (2/2)
CAMERA: B2B Wide (WY)
CAMERA: B2B Tele (MT)
CAMERA: Strobe Drivers
CAMERA: B2B FCAM
CAMERA: B2B Strobe + Hold Button
PEARL: Power
PEARL: B2B Romeo + Juliet
PEARL: B2B Rosaline + Misc
AUDIO: CODEC (1/2)
AUDIO: CODEC (2/2)

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

test_mlb

49 AUDIO: Speaker Amp Bottom
50

AUDIO: Speaker Amp Top

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

B

10/13/2016

10/13/2016

10/13/2016

10/13/2016

08/25/2015

08/25/2015

A

41
42
43
44
45

51
56
57
58
59

ARC: Driver
CG: Power Supplies - Touch & Display
CG: B2B Display
CG: B2B Orb & Touch
I/O: Overvoltage Cut-Off Circuit

BOM:639-04583 (Ultimate)
BOM:639-03409 (Extreme)
MCO:056-04077

1 SCH051-02221 SCH,MLB_TOP,X891 COMMON

820-00863 1 PCB,MLB_TOP,X891

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NO

BOM OPTIONCRITICAL

COMMONNOPCB

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

test_mlb
test_mlb
test_mlb

sync

10/13/2016

10/13/2016

10/13/2016

08/25/2015

01/10/2017

TABLE OF CONTENTS

DRAWING TITLE

SCH,MLB,TOP,X891

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

1 OF 80

SHEET

1 OF 51

A

SIZEDRAWING NUMBER

D

8

3

124567

678

3 245

1

D

EEEE Codes

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

825-7691

825-7691

EEEE FOR (MLB_TOP,639-04583,ULTIMATE)

1

EEEE FOR (MLB_TOP,639-03409,EXTREME)

1

EEEE_J2WJ

EEEE_HP26

NO

NO

SOC

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

339S00358 CRITICAL1 COMMON

339S00359 DDR-H,3G, B0

SKYE+3GB, B0, M, DEV

PART NUMBER

339S00358

339S00358

339S00358

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

U1000

U1000339S00361 DDR-S-18,3G, B0

U1000

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TABLE_ALT_ITEM

DDR-S-20,3G, B0U1000339S00360

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

ULTIMATE

EXTREME

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

Global Ferrites

TABLE_ALT_HEAD

PART NUMBER

155S0610

BOM_TABLE_ALTS

BOM_TABLE_ALTS

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

ALL155S00194

ALL155S0610155S00200

FERR BD, 150OHM, TDK

TABLE_ALT_ITEM

FERR BD, 150OHM, TY

CRITICAL PART# COMMENT

155S0610

FERR BD, 150OHM, 01005

Global R/C Alternates

TABLE_ALT_HEAD

PART NUMBER

118S0717

138S0652 ALL138S0648

132S0436 ALL132S0400

138S00049

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL118S0764

ALL138S0706138S0739

ALL138S0831

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RES, 3.92K, 0.1%, 0201

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,CER,X5R,0.22UF,20%,6.3V,20%

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

118S0717

138S0652

138S0706

132S0400

138S0831

RES, 3.92K, 0.1%, 0201

CAP,X5R,4.7UF,6.3V,0.65MM,0402

CAP,CER,X5R,0.22UF,20%,6.3V,20%

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

Soft-Term Cap Sub BOMs

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SUBBOM,MLB,TOP,CAP,TYPICAL,X891

1685-00155

SUBBOM_CAP CRITICAL COMMON

Agnes Input

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

Agnes Output

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

138S00159

138S0831 TYPICAL_CAPCRITICAL

9

9

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914

C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914

Sensors

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

138S00159 SOFT_CAPCRITICALC3602,C3622

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

2

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

BOM OPTIONCRITICAL

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC2970,C2971,C2980,C29814138S00159

TYPICAL_CAPCRITICALC2970,C2971,C2980,C2981138S0831 4

BOM OPTIONCRITICAL

SOFT_CAPCRITICAL

BOM OPTIONCRITICAL

TYPICAL_CAPCRITICALC3602,C36222138S0831

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

D

C

B

A

NAND

Ultimate

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

HYNIX, 3DV3, ULTIMATE U2600

PART NUMBER

335S00284 335S00287

335S00287335S00288 U2600

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

U2600BOM_TABLE_ALTS

U2600335S00285 335S00287

U2600335S00286 335S00287

TOSHIBA, 1Z, ULTIMATE

TOSHIBA, BICS3, ULTIMATE

SANDISK, BICS3, ULTIMATE

SAMSUNG, 3DV4, ULTIMATE

CRITICAL ULTIMATE1335S00287

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

Extreme

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1335S00240 EXTREMECRITICALHYNIX, 3DV3, EXTREME U2600

TABLE_ALT_HEAD

PART NUMBER

335S00228 335S00240

335S00247 335S00240

335S00276 335S00240

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

U2600

U2600

U2600

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TOSHIBA, BICS3, EXTREME

TABLE_ALT_ITEM

SANDISK, BICS3, EXTREME

TABLE_ALT_ITEM

SAMSUNG, 3DV4, EXTREME

Global Capacitors

TABLE_ALT_HEAD

PART NUMBER

BOM_TABLE_ALTS

138S00150 138S00149 ALL

138S00151

PART NUMBER

138S00143 ALL138S00144

138S00163

138S00144

PART NUMBER

138S00139138S00138 ALL

138S00164 ALL138S00139

PART NUMBER

138S00145 138S00146 ALL

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

PART NUMBER

138S00140

138S00142

138S00166

138S00141

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL138S00148 138S00149

ALL138S00149

ALL

ALL138S00146138S00165

ALL138S00141

ALL

ALL138S00141

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, Kyocera

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, SEMCO

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, TY

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402,16uF@1V, Kyocera

TABLE_ALT_ITEM

0402,16uF@1V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0201,3uF@1V, Kyocera

TABLE_ALT_ITEM

0201,3uF@1V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402,5.1uF@3V, Kyocera

TABLE_ALT_ITEM

0402,5.1uF@3V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0201,1.1uF@3V, Kyocera

TABLE_ALT_ITEM

0201,1.1uF@3V, SEMCO

TABLE_ALT_ITEM

0201,1.1uF@3V, Taiyo

CRITICAL PART# COMMENT

138S00149

CRITICAL PART# COMMENT

138S00144

CRITICAL PART# COMMENT

138S00139

CRITICAL PART# COMMENT

138S00146

CRITICAL PART# COMMENT

138S00141

RCAM B2Bs

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

Global Inductors

TABLE_ALT_HEAD

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

152S00710 152S00617

152S00712 ALL

152S00713 ALL

152S00714 ALL

152S00720

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

152S00649 152S00650

PART NUMBER

152S00620

152S00621

152S00622

152S00626

152S00631

152S00623152S00715

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL

ALL152S00716

ALL152S00717

ALL152S00632152S00718

ALL152S00640

ALL152S00641152S00721

ALL

ALL152S00651152S00653

L3340,L3341

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608

IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012

IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012

IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012

IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012

IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012

IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016

IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012

IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012

IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016

IND,1.2UH,3A,2016,0.65Z

IND,0.47UH,6.6A,3225,0.8Z

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

152S00617

152S00620

152S00621

152S00622

152S00626

152S00631

152S00632

152S00640

152S00641

152S00623

152S00651

152S00650

IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608

IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012

IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012

IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012

IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012

IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012

IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016

IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012

IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012

IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016

IND,1.2UH, 3A, 2016, 0.65Z

IND,0.47UH,6.6A,3225,0.8Z

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

138S0831 TYPICAL_CAPCRITICALC3909,C3925,C4025

Strobe B2B

Audio

Pearl B2B

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

3 SOFT_CAPCRITICALC3909,C3925,C4025138S00159

3

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

1138S00159

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

1138S0831

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

2138S00159

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

2138S0831

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

1138S0831

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC4303

TABLE_5_ITEM

C

TYPICAL_CAPCRITICALC4303

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC4809,C4805

TABLE_5_ITEM

TYPICAL_CAPCRITICALC4809,C4805

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC46131138S00159

TABLE_5_ITEM

TYPICAL_CAPCRITICALC4613

Acorn

TABLE_5_HEAD

0402-3T,10.5uF@1V

0402,16uF@1V

0201,3uF@1V

0402,5.1uF@3V

0201,1.1uF@3V

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEADTABLE_ALT_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

XTAL Alternate

TABLE_ALT_HEAD

PART NUMBER

197S0612 197S0446

BOM_TABLE_ALTS

Y1000

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

XTAL, 24M, 1612

CRITICAL PART# COMMENT

TABLE_ALT_ITEM

197S0446

XTAL, 24M, 1612

Multi-Vendor Criticals

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEMTABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

CRITICAL PART# COMMENT

377S0106

197S0446

155S0576

155S00168

138S0979

138S0692

138S0683

138S0652

138S00070

138S00014

132S0664

132S0663

132S0534

132S0436

132S0396

132S0316

132S0304

132S0296

132S0318

SUPPR,TRANS,VARISTOR,12V,33PF,01005

XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612

FERR BD,10 OHM,50%,750MA,0.07 DCR,01005

FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605

CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM

CAP,CER,X5R,1UF,20%,6.3V,0201

CAP,CER,X5R,1UF,10%,25V,0402

CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402

CAP,X5R,4.7UF,20%,25V,0402

CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM

CAP,CER,0.047UF,10%,25V,X5R,0201

CAP,CER,X5R,1UF,10%,25V,0402

CAP,CER,X5R,0.1UF,10%,25V,0201

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,1000PF,10%,10V,01005 CAP,CER,C0G,220PF,5%,10V,01005

CAP,CER,X5R,0.1UF,20%,6.3V,01005

CAP,CER,X5R,0.22UF,20%,6.3V,0201

CAP,CER,X5R,1000PF,10%,6.3V,01005

CAP,CER,X5R,820PF,10%,10V,01005

TABLE_CRITICAL_HEAD

CRITICAL PART# COMMENT

TABLE_CRITICAL_ITEM

132S0288

TABLE_CRITICAL_ITEM

132S0275

TABLE_CRITICAL_ITEM

132S0249

TABLE_CRITICAL_ITEM

132S0245

TABLE_CRITICAL_ITEM

132S00093

TABLE_CRITICAL_ITEM

132S00025

TABLE_CRITICAL_ITEM

132S00008

TABLE_CRITICAL_ITEM

131S0883

TABLE_CRITICAL_ITEM

131S0804

TABLE_CRITICAL_ITEM

131S0307

TABLE_CRITICAL_ITEM

131S0225

TABLE_CRITICAL_ITEM

131S0223

TABLE_CRITICAL_ITEM

131S0220

131S0216

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

CAP,CER,X5R,0.1UF,10%,16V,0201

CAP,CER,X5R,470PF,10%,10V,01005

CAP,CER,X7R,220PF,10%,10V,01005

CAP,CER,X5R,0.01UF,10%,6.3V,01005

CAP,X5R,0.022UF,20%,6.3V,01005

CAP,CER,X5R,0.047UF,20%,6.3V,01005

CAP,CER,0.1UF,10%,50V,X7R,0402

CAP,CER,NP0/C0G,220PF,2%,50V,0201

CAP,CER,27PF,5%,C0G,25V,0201

CAP,CER,NP0/C0G,100PF,5%,16V,01005

CAP,CER,NP0/C0G,15PF,5%,16V,01005

CAP,CER,NP0/C0G,27PF,5%,16V,01005

CAP,CER,NP0/C0G,12PF,5%,16V,01005

CAP,CER,NP0/C0G,47PF,5%,16V,01005

131S00053

TABLE_CRITICAL_ITEM

118S00068

TABLE_CRITICAL_ITEM

117S0055

TABLE_CRITICAL_ITEM

107S0257

TABLE_CRITICAL_ITEM

RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201

RES,MF,1/20W,2M OHM,5,0201,SMD

THERMISTOR,NTC,10K OHM,1%,B=3435,01005

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

CODEC

Ansel

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,10UF,10V,0402,MURATA

2138S00160

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

2138S0979

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,10UF,10V,0402,MURATA

2138S00160

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

2138S0979

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1138S00160

CAP,SOFT-TERM,10UF,10V,0402,MURATA

1138S0979 CRITICAL

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

PART NUMBER

685-00155685-00156

BOM_TABLE_ALTS

SYNC_MASTER=test_mlb

PAGE TITLE

SUBBOM_CAP

C4811,C4808 SOFT_CAPCRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SUBBOM,MLB,TOP,CAP,SOFT,X891

SYSTEM:BOM Tables

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC5641,C5653

TYPICAL_CAPCRITICALC5641,C5653

BOM OPTIONCRITICAL

TYPICAL_CAPCRITICALC4811,C4808

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC3710

TYPICAL_CAPC3710

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

051-02221

9.0.0

evt-1
2 OF 80
2 OF 51

SYNC_DATE=10/13/2016

SIZE

D

B

A

8

67

35 4

2

1

678

3 245

1

FIDUCIALS

FD0401

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

D

CL0400

2.10R1.60-NSP

1

FD0402

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0403

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0404

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0420

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0405

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

D

C

CRITICAL

SB0400

STDOFF-2.9OD1.4ID-0.77H-SM

1

CL0401

2.10R1.60-NSP

1

FD0410

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0411

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0412

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

C

B

CRITICAL

SB0402

STDOFF-MLB-TUBE

1

CL0402

2.10R1.60-NSP

1

B

CRITICAL

1

SH0401

SM

SHLD-EMI-HARD-X891

A

CRITICAL

SB0401

STDOFF-2.9OD1.4ID-0.77H-SM

1

CRITICAL

1

SH0400

SM

SHIELD-EMI-TOP-X891

CL0403

2.10R1.60-NSP

1

PAGE TITLE

SYSTEM: Mechanical Components

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

4 OF 80

SHEET

3 OF 51

A

SIZE

D

8

67

35 4

2

1

678

3 245

1

D

C

PP_ROMEO_DENSE_ANODE

34 35

PP_ROMEO_CATHODE

34 35

POWER

TP0540

P2MM-NSM

SM

1

TP0543

P2MM-NSM

1

PP

SM

PP

ROOM=TEST

ROOM=TEST

Test Points

20

XW0510

SHORT-10L-0.05MM-SM

XW0511

SHORT-10L-0.05MM-SM

17 13

PP_GPU

20 6

11 5

32 8

11

11 6

20 6

Probe Points

SOC Debug

PP0500

P2MM-NSM

AP_TO_PMU_TEST_CLKOUT

IN

BOARD_ID0

IN

AP_TO_FCAM_SHUTDOWN_L

IN

8

AP_DEBUG3

IN

DFU_STATUS

IN

PMU_TO_AP_PRE_UVLO_L

IN

AP_TO_PMU_SOCHOT_L

IN

SOC CPU/GPU

21

21

PP_GPU_LVCC

PP_CPU_PCORE_LVCCPP_CPU_PCORE

SM

1

PP

ROOM=TEST

PP0501

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0502

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0503

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0504

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0505

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0506

P2MM-NSM

SM

1

PP

ROOM=TEST

50

50 17 13

26 12

26 12

26 12

26 12

26 12

49 25 12

26 12

48 23

Sensors

SPI_AOP_TO_IMU_SCLK

IN

SPI_AOP_TO_IMU_MOSI

IN

SPI_IMU_TO_AOP_MISO

IN

ACCEL_GYRO_TO_AOP_DATARDY

IN

ACCEL_GYRO_TO_AOP_INT

IN

COMPASS_TO_AOP_INT

IN

PHOSPHORUS_TO_AOP_INT

IN

Hydra VBUS

HYDRA_TO_TIGRIS_VBUS1_VALID_L

IN

PP0540

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0541

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0542

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0544

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0545

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0546

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0547

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0550

P2MM-NSM

SM

1

PP

ROOM=TEST

41 37

41 37

47 10

47 10

50 49 41 25 12

50 49 41 25 12

PDM_CODEC_TO_ARC_CLK

IN

PDM_CODEC_TO_ARC_DATA

IN

AP_BI_CCG2_SWDIO

IN

AP_TO_CCG2_SWCLK

IN

SOC I2C1_AOP

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

IN

PP0582

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0583

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0586

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0587

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0590

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0591

P2MM-NSM

SM

1

PP

ROOM=TEST

D

C

B

20 13

20 13

13

15

15

AP_CPU_PCORE_SENSE

IN

AP_VDD_GPU_SENSE

IN

TP_SOC_SENSE

IN

TP_VSS_CPU_SENSE

IN

TP_VSS_SENSE

IN

PMU

PP0512

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0513

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0514

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0515

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0516

P2MM-NSM

SM

1

PP

ROOM=TEST

16 12

50 16 12

16 10 5

16

16

NAND CCG2

PP0560

P2MM-NSM

SWD_AP_BI_NAND_SWDIO

IN

SWD_AOP_TO_MANY_SWCLK

IN

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

IN

NAND_ANI1_VREF

IN

NAND_ANI0_VREF

IN

SM

1

PP

ROOM=TEST

PP0561

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0562

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0563

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0564

P2MM-NSM

SM

1

PP

ROOM=TEST

47 10

CCG2_TO_SMC_INT_L

IN

PP0592

P2MM-NSM

SM

1

PP

ROOM=TEST

B

14 12

20 10

48 20 6

16 7

16 7

AOP_TO_DDR_SLEEP1_READY

IN

SPMI_PMU_BI_PMGR_SDATA

IN

PMU_TO_AP_HYDRA_ACTIVE_READY

IN

PCIE Refclk

90_PCIE_AP_TO_NAND_REFCLK_P

IN

90_PCIE_AP_TO_NAND_REFCLK_N

IN

PP0520

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0521

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0522

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0530

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0531

P2MM-NSM

SM

1

PP

ROOM=TEST

34 28

34 20 8

Rigel

CAMPMU_TO_RIGEL_ENABLE

IN

RIGEL_TO_ISP_INT

IN

PP0570

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0571

P2MM-NSM

SM

1

PP

ROOM=TEST

A

8

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SYSTEM: Testpoints (Top)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

5 OF 80

SHEET

4 OF 51

1

SIZE

D

678

3 245

1

D

11

11

BOARD_REV3

OUT

BOARD_REV2

OUT

R0623

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0622

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

NOSTUFF

BOOTSTRAPPING:BOARD REV

BOARD ID
BOOT CONFIG

PP1V8_IO

43 35 34 32

30 29 28 27 17 16 14 10 8 7 6

D

C

11

11

11

BOARD_REV1

OUT

BOARD_REV0

OUT

BOARD_ID4

OUT

CKPLUS_WAIVE=SINGLE_NODENET

R0621

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0620

1.00K

1/32W
01005

ROOM=SOC

No connect

21

5%
MF

C

SELECTED -->

B

50 10

11

11

11 4

BOARD_ID3

OUT

CKPLUS_WAIVE=SINGLE_NODENET

PP1V8_IO

OUT

PP1V8_IO

OUT

BOARD_ID0

OUT

On mlb_bot

MAKE_BASE=TRUE

No connect

SELECTED -->

D221 Baseband Selected on RF Board

B

A

16 10 4

16 10

16 10

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

OUT

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

No connect

R0601

4.7K

1/32W
01005

ROOM=SOC

21

1%
MF

R0600

4.7K

1/32W
01005

ROOM=SOC

21

1%
MF

NOSTUFF

SELECTED -->

SYNC_MASTER=test_mlb

PAGE TITLE

BOOTSTRAPPING

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

6 OF 80

SHEET

5 OF 51

SYNC_DATE=10/13/2016

SIZE

D

A

8

67

35 4

2

1

SOC - USB, JTAG, XTAL

678

3 245

1

VDD11_XTAL:1.06-1.17V @ 2mA MAX

VDD18_USB: 1.62V - 1.98V @ 20mA MAX

D

PP1V8_XTAL

1

C1090

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

FL1092

240-OHM-25%-0.20A-0.9DCR

21

1

C1092

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1095

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

01005

ROOM=SOC

PP1V8_IO

1

C1093

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

3.14-3.46V @ 12mA MAX

PP3V3_USB

19

43 35 34 32

30 29 28 27 17 16 14 10 8 7 5

D

USB Reference

AP_USB_REXT

6

1

R1000

200

1%
1/32W
MF
01005

2

ROOM=SOC

C

NC
NC

BA4
AY4

AT7

VDD12_UH1_HSIC0

UH1_HSIC0_DATA
UH1_HSIC0_STB

AP14

VDD18_USB

OMIT_TABLE

U1000

TMIT78B0-C4

WLCSP

SYM 1 OF 16

ROOM=SOC

CRITICAL

AU28

VDD18_XTAL

AN14

VDD33_USB

ANALOGMUX_OUT

AN15

VDD_FIXED_USB

AT27

(Analog)

0.765V - 0.84V @ 5mA MAX

PP0V8_SOC_FIXED_S1

AP_TO_PMU_AMUX_OUT

OUT

17 14 13 9 8 7

C

20

B

20

PMU_TO_SYSTEM_COLD_RESET_L

IN

MAKE_BASE=TRUE

R1020

10K

1/32W
01005

21

5%
MF

MAKE_BASE=TRUE

48

48

48 20 4

20 4

16

16

GND

SWD_DOCK_BI_AP_SWDIO

BI

SWD_DOCK_TO_AP_SWCLK

IN

PMU_TO_SYSTEM_COLD_RESET_R_L
PMU_TO_AP_HYDRA_ACTIVE_READY

IN

AP_TO_PMU_TEST_CLKOUT

OUT

AP_TO_NAND_RESET_L

OUT

OUT

AP_TO_NAND_FW_STRAP
GND
GND

NC
NC
NC

AT8

AV6

AT9
AT12
AT10
AT13

AU7

AT34

AV5

V2

AF34

AG38

W5
W4

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*
CFSB

CFSB_AON
TST_CLKOUT
SSD_RESET*

SSD_BFH

HOLD_RESET
TESTMODE

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

CPU_TRIGGER0
CPU_TRIGGER1

GPU_TRIGGER0
GPU_TRIGGER1

SOCHOT1

DROOP

WDOG

XI0

XO0

AY6
BA6

AV7

AW6

AU8

AT22
AW21

AD2
AD3

A30
B31

AW5
BA28

BA27

NC

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

AP_USB_REXT

PMU_TO_AP_THROTTLE_PCORE_L
PMU_TO_AP_THROTTLE_ECORE_L

PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_THROTTLE_GPU1_L

AP_TO_PMU_SOCHOT_L
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_WDOG_RESET

IN

6

IN
IN

IN
IN

OUT

IN

OUT

XTAL_AP_24M_IN

XTAL_AP_24M_OUT

48

BI

48

BI

23

20

20

20

20

20

20 4

20 11 4

NOSTUFF

1

R1010

511K

1%
1/32W
MF
01005

2

ROOM=SOC

R1011

1.00K

5%

1/32W

MF

01005

ROOM=SOC

24.000MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C1010

12PF

5%
16V

2

CERM
01005

ROOM=SOC

ROOM=SOC

Y1000

1.60X1.20MM-SM

31

42

1

C1011

12PF

5%
16V

2

CERM
01005

ROOM=SOC

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: JTAG,USB,XTAL

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

10 OF 80

SHEET

6 OF 51

1

SIZE

D

SOC - PCIE INTERFACES

678

3 245

1

D

C

PCIe BB CLKREQ PU on BB domain

PCIe Clock Request Pull-Ups

29 28 27 17 16 14 10 8 7 6 5

PCIE_NAND_BI_AP_CLKREQ_L

16 7

PCIE_WLAN_BI_AP_CLKREQ_L

50 7

43 35 34 32 30

PP1V8_IO

R1100

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1130

PCIe Reset Pull-Downs

PCIE_AP_TO_WLAN_RESET_L

50 7

PCIE_AP_TO_BB_RESET_L

50 7

PCIE_AP_TO_NAND_RESET_L

16 7

R1101

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1121

100K

1/32W
01005

ROOM=SOC

100K

1/32W
01005

ROOM=SOC

5%
MF

5%
MF

(Analog)

R1198

19 14 13 9

1

2

1

2

R1131

ROOM=SOC

100K

5%

1/32W

MF

01005

1

2

PP1V2_SOC

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX

1

C1198

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AM31

AP26

AN26

VDD12_PCIE_REFBUF

VDD12_PCIE_REFBUF

AM29

VDD18_PCIE

VDD18_PCIE

AN30

VDD_FIXED_PCIE_ANA

ROOM=SOC

U1000

AP27

AP31

AP29

VDD_FIXED_PCIE_ANA

VDD_FIXED_PCIE_ANA

AM27

VDD_FIXED_PCIE_REFBUF

VDD_FIXED_PCIE_REFBUF

1

C1199

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

PP0V8_SOC_FIXED_PCIE_REFBUF

1

C1194

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

R1194

0.00

1/32W
01005

ROOM=SOC

21

0%
MF

VDD_FIXED_PCIE_REFBUF:0.765V - 0.84V @ 9mA MAX

VDD_FIXED_PCIE_ANA:0.765V - 0.84V @ 131mA MAX

1

C1193

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1192

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=SOC

1.62V - 1.98V @ 81mA MAX

PP1V8_IOPP1V2_SOC_PCIE_REFBUF

(Analog)

PP0V8_SOC_FIXED_S1

1

C1191

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

43 35 34 32 30

17 14 13 9 8 6

29 28 27 17 16 14 10 8 7 6 5

TMIT78B0-C4

WLCSP

D

C

B

16

IN

16

IN

16

OUT

16

PCIE LINK 0

OUT

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

0.22UF

0.22UF

0.22UF

0.22UF

2 1

6.3V

01005

ROOM=SOC

2 1

6.3V 20%

01005

ROOM=SOC

2 1

6.3V 20%

01005

ROOM=SOC

2 1

6.3V

01005

ROOM=SOC

20%
X5R

C1101

X5R

C1102

X5R

C1103

20%
X5R

C1100

GND_VOID

GND_VOID

GND_VOID

GND_VOID

16 7

16 4

16 4

16 7

PCIE_NAND_BI_AP_CLKREQ_L

BI

90_PCIE_AP_TO_NAND_REFCLK_P

OUT

90_PCIE_AP_TO_NAND_REFCLK_N

OUT

90_PCIE_NAND_TO_AP_RXD_C_P
90_PCIE_NAND_TO_AP_RXD_C_N

90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_AP_TO_NAND_TXD_C_N

PCIE_AP_TO_NAND_RESET_L

OUT

NC
NC

NC

AL38

AW27

AV27

AV29

AW29

AY30
BA30

AJ37

AL37

AW26

AY26

PCIE_CLKREQ0*
PCIE_REF_CLK0_P

PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

PCIE_TX0_P
PCIE_TX0_N

PCIE_PERST0*

PCIE_CLKREQ1*
PCIE_REF_CLK1_P

PCIE_REF_CLK1_N

SYM 2 OF 16

LINK0

LINK3

PCIE_CLKREQ3*

PCIE_REF_CLK3_P
PCIE_REF_CLK3_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_TX3_P

PCIE_TX3_N

PCIE_PERST3*

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

AJ36
AY24

BA24

BA36
AY36

AV35
AW35

AH36

AK37
AV25

AW25

PCIE_WLAN_BI_AP_CLKREQ_L

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N

BI

OUT
OUT

90_PCIE_WLAN_TO_AP_RXD_C_P
90_PCIE_WLAN_TO_AP_RXD_C_N

90_PCIE_AP_TO_WLAN_TXD_C_P
90_PCIE_AP_TO_WLAN_TXD_C_N

PCIE_AP_TO_WLAN_RESET_L

PCIE_BB_BI_AP_CLKREQ_L

OUT

BI

50

50

50

50 7

C1130

GND_VOID

20%

X5R-CERM

C1131

GND_VOID

20%

X5R-CERM

C1132

GND_VOID

20%

X5R-CERM

C1133

50 7

GND_VOID

X5R-CERM

21

6.3V
01005

ROOM=SOC

21

6.3V
01005

ROOM=SOC

21

6.3V
01005

ROOM=SOC

21

6.3V20%
01005

ROOM=SOC

0.1UF

0.1UF

0.1UF

0.1UF

1

C1124

4.7PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=SOC

1

C1125

4.7PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=SOC

90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_WLAN_TO_AP_RXD_N

90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

IN
IN

OUT
OUT

OUT
OUT

50

50

50

50

50

50

B

A

NC
NC

NC
NC

NC

AV31

AW31

AY32
BA32

AK38

AU30
AT30

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N

LINK1 LINK2

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_PERST2*

PCIE_REXT

BA34
AY34

AV33
AW33

AJ38

AU32

90_PCIE_BB_TO_AP_RXD_C_P
90_PCIE_BB_TO_AP_RXD_C_N

90_PCIE_AP_TO_BB_TXD_C_P
90_PCIE_AP_TO_BB_TXD_C_N

PCIE_AP_TO_BB_RESET_L

AP_PCIE_RCAL

1

R1150

200

1%
1/32W
MF
01005

2

ROOM=SOC

OUT

0.1UF

6.3V

ROOM=SOC

6.3V

ROOM=SOC

6.3V

ROOM=SOC

6.3V

ROOM=SOC

21

01005

21

01005

21

01005

21

01005

0.1UF

0.1UF

0.1UF

PAGE TITLE

90_PCIE_BB_TO_AP_RXD_P
90_PCIE_BB_TO_AP_RXD_N

90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_TXD_N

OUT
OUT

50

IN

50

IN

PCIE LINK 2 PCIE LINK 3

50

50

SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb

A

C1120

GND_VOID

20%

X5R-CERM

C1121

GND_VOID

20%

X5R-CERM

C1122

GND_VOID

20%

X5R-CERM

C1123

50 7

GND_VOID

20%

X5R-CERM

SOC: PCIE

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

11 OF 80

SHEET

7 OF 51

8

67

35 4

2

1

678

3 245

1

D

SOC - MIPI & ISP INTERFACES

MIPI Lane & Polarity Swapping

17 14 13 9 7 6

(Analog)

0.765V - 0.84V @ 40mA MAX

PP0V8_SOC_FIXED_S1

20%

6.3V

1

2

C1290

0.1UF 2.2UF

X5R-CERM

01005

ROOM=SOC

C1291

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=SOC

ISP I2C0

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

1.62V - 1.98V @ 10mA MAX

PP1V8_IO

43 35 34 32

1

2

G14

G12

F13

F11

VDD18_MIPI

1

C1295

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1296

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

30 29 28 27 17 16 14 10 8 7 6 5

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

29 8

I2C0_ISP_SCL

29 8

I2C0_ISP_SDA

ISP I2C1

PP1V8_IO

1

R1201

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1211

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1202

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1212

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

D

C

35

35

35

35

35

35

32

32

32

32

FCAM MIPI Juliet MIPI

32

32

43

43

43

43

43

43

43

43

90_MIPI_JULIET_TO_AP_DATA0_P

BI

90_MIPI_JULIET_TO_AP_DATA0_N

BI

90_MIPI_JULIET_TO_AP_DATA1_P

IN

90_MIPI_JULIET_TO_AP_DATA1_N

IN

90_MIPI_JULIET_TO_AP_CLK_N

IN

90_MIPI_JULIET_TO_AP_CLK_P

IN

90_MIPI_FCAM_TO_AP_DATA0_N

BI

90_MIPI_FCAM_TO_AP_DATA0_P

BI

90_MIPI_FCAM_TO_AP_DATA1_N

IN

90_MIPI_FCAM_TO_AP_DATA1_P

IN

90_MIPI_FCAM_TO_AP_CLK_P

IN

90_MIPI_FCAM_TO_AP_CLK_N

IN

90_MIPI_AP_TO_DISPLAY_DATA0_P

BI

90_MIPI_AP_TO_DISPLAY_DATA0_N

BI

90_MIPI_AP_TO_DISPLAY_DATA1_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA1_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_P

OUT

Display MIPI

43

43

90_MIPI_AP_TO_DISPLAY_CLK_N

OUT

90_MIPI_AP_TO_DISPLAY_CLK_P

OUT

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

90_MIPI_JULIET_TO_AP_DATA0_P
90_MIPI_JULIET_TO_AP_DATA0_N

90_MIPI_JULIET_TO_AP_DATA1_P
90_MIPI_JULIET_TO_AP_DATA1_N

90_MIPI_JULIET_TO_AP_CLK_N
90_MIPI_JULIET_TO_AP_CLK_P

MIPI0C_REXT

8

MIPI1C_REXT

8

90_MIPI_FCAM_TO_AP_DATA0_N
90_MIPI_FCAM_TO_AP_DATA0_P

90_MIPI_FCAM_TO_AP_DATA1_N
90_MIPI_FCAM_TO_AP_DATA1_P

90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_FCAM_TO_AP_CLK_N

90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_DATA1_N

90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA3_N

90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA2_P

90_MIPI_AP_TO_DISPLAY_CLK_N
90_MIPI_AP_TO_DISPLAY_CLK_P

B12
A12

B14
A14

A13
B13

D12
D13

B17
A17

B15

A15

A16
B16

A10

B10

B9

A9

A7

B7

A6
B6

A8
B8

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0C_REXT
MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

MIPID_DPDATA0
MIPID_DNDATA0

MIPID_DPDATA1
MIPID_DNDATA1

MIPID_DPDATA2
MIPID_DNDATA2

MIPID_DPDATA3
MIPID_DNDATA3

MIPID_DPCLK
MIPID_DNCLK

VDD_FIXED_MIPI

U1000

TMIT78B0-C4

WLCSP

SYM 3 OF 16

ROOM=SOC

ISP_I2C0_SCL

ISP_I2C0_SDA

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

SENSOR_INT

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST

SENSOR0_ISTRB
SENSOR1_ISTRB

W35
V38

W36
Y36

Y34
Y38

AA37
AB38

AB36

U38
R38
R37

V34
U35
AB34
AC37
AA35

V36
U36

NC

NC

I2C0_ISP_SCL
I2C0_ISP_SDA

I2C1_ISP_SCL
I2C1_ISP_SDA

I2C2_ISP_SCL
I2C2_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

RIGEL_TO_ISP_INT

OUT

BI

OUT

BI

OUT

BI

OUT

BI

IN

AP_TO_WIDE_CLK_R
AP_TO_TELE_CLK_R

AP_TO_FCAM_JULIET_RIGEL_CLK_R

AP_TO_JULIET_SHUTDOWN_L

AP_TO_TELE_SHUTDOWN_L
AP_TO_WIDE_SHUTDOWN_L

OUT
OUT
OUT

AP_TO_FCAM_SHUTDOWN_L

OUT

AP_DEBUG3

OUT

35

30

29

4

30 8

I2C1_ISP_SCL

30 8

I2C1_ISP_SDA

29 8

29 8

29 28 27 17 16 14 10 8 7 6 5

30 8

30 8

32 8

32 8

35 34 31 28 8

35 34 31 28 8

43 35 34 32 30

ISP I2C2

PP1V8_IO

32 8

I2C2_ISP_SCL

32 8

I2C2_ISP_SDA

1

R1221

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1222

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

C

R1240

33.2

34 20 4

1/32W
01005

ROOM=SOC

21

1%
MF

R1241

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

R1242

33.2

1/32W
01005

32 4

ROOM=SOC

21

1%
MF

AP_TO_FCAM_JULIET_CLK

AP_TO_WIDE_CLK

AP_TO_TELE_CLK

OUT

OUT

OUT

29

29 28 27 17 16 14 10 8 7 6 5

30

35 32

43 35 34 32 30

35 34 31 28 8

35 34 31 28 8

ISP I2C3

PP1V8_IO

I2C3_ISP_SCL
I2C3_ISP_SDA

1

R1231

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1232

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

R1243

33.2

1%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_RIGEL_CLK

OUT

34

B

50 28 21 20 12

43

AP_TO_MANY_BSYNC

OUT

DISPLAY_TO_AP_ALIVE

IN

MIPID_REXT

8

NC

NC
NC

NC

AA3

AB4

AB6

D11

AA4
AA5

Y4

DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1

DISP_TOUCH_EB

MIPID_REXT

DISP_I2C_SCL
DISP_I2C_SDA

DISP_POL

SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN

U37
T37

NC

ISP_TO_DISPLAY_FLASH_INT

OUT

43

B

A

MIPI Reference

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1252

200

1%

1/32W

MF

01005

ROOM=SOC

R1250

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1251

8

MIPI0C_REXT
MIPI1C_REXT

MIPID_REXT

1

8

8

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SOC: MIPI & ISP

DRAWING NUMBER

2

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

12 OF 80

SHEET

8 OF 51

1

SIZE

D

SOC - LPDP

19 14 13 7

678

VDD12_PLL_LPDP 1.14V - 1.26V @ 10mA MAX
VDD12_LPDP 1.14V - 1.26V @ 72mA MAX

PP1V2_SOC

3 245

(Analog)
VDD_FIXED_PLL_LPDP 0.765V - 0.84V @ 3mA MAX
VDD_FIXED_LPDP_TX 0.765V - 0.84V @ 16mA MAX
VDD_FIXED_LPDP_RX 0.765V - 0.84V @ 30mA MAX

PP0V8_SOC_FIXED_S1

1

17 14 13 9 8 7 6

D

1

C1390

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1391

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1392

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1393

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SOC

1

C1394

15PF2.2UF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

M9

VDD12_LPDP_TX

F16

F17

F15

VDD12_LPDP_RX

R9

T9

VDD12_PLL_LPDP

P9

VDD_FIXED_LPDP_TX

VDD_FIXED_PLL_LPDP

G18

G16

VDD_FIXED_LPDP_RX

1

C1395

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1396

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

D

C

29

29

29

29

29

29

30

30

30

30

90_LPDP_WIDE_TO_AP_D0_P

IN

90_LPDP_WIDE_TO_AP_D0_N

IN

90_LPDP_WIDE_TO_AP_D1_P

IN

90_LPDP_WIDE_TO_AP_D1_N

IN

90_LPDP_WIDE_TO_AP_D2_P

IN

90_LPDP_WIDE_TO_AP_D2_N

IN

90_LPDP_TELE_TO_AP_D0_P

IN

90_LPDP_TELE_TO_AP_D0_N

IN

90_LPDP_TELE_TO_AP_D1_P

IN

90_LPDP_TELE_TO_AP_D1_N

IN

A26
B26

A25
B25

A24
B24

A21
B21

A20
B20

LPDPRX_RX_D0_P
LPDPRX_RX_D0_N

LPDPRX_RX_D1_P
LPDPRX_RX_D1_N

LPDPRX_RX_D2_P
LPDPRX_RX_D2_N

LPDPRX_RX_D3_P
LPDPRX_RX_D3_N

LPDPRX_RX_D4_P
LPDPRX_RX_D4_N

U1000

TMIT78B0-C4

WLCSP

SYM 4 OF 16

LPDP_TX0P
LPDP_TX0N

LPDP_TX1P
LPDP_TX1N

LPDP_TX2P
LPDP_TX2N

LPDP_TX3P
LPDP_TX3N

M3
M4

L4
L5

K3
K4

J4
J5

NC
NC

NC
NC

NC
NC

NC
NC

C

B

17 14 13 9 8 7 6

30

IN

30

IN

29

BI

30

BI

MAKE_BASE=TRUE

PP0V8_SOC_FIXED_S1

300

1%

1/32W

MF

1

2

R1300

01005-1

ROOM=SOC

90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D2_N

LPDP_WIDE_BI_AP_AUX

LPDP_TELE_BI_AP_AUX

GND
GND

AP_LPDPRX_RCAL_NEG

NC
NC

NC
NC

A19
B19

D21
D20
D19
D17
D16
D15

A22
B22

B23

A23

LPDPRX_RX_D5_P
LPDPRX_RX_D5_N

LPDPRX_AUX_D0_P
LPDPRX_AUX_D1_P
LPDPRX_AUX_D2_P
LPDPRX_AUX_D3_P
LPDPRX_AUX_D4_P
LPDPRX_AUX_D5_P

LPDPRX_BYP_CLK_P
LPDPRX_BYP_CLK_N

LPDPRX_RCAL_P

LPDPRX_RCAL_N

LPDP_AUX_P
LPDP_AUX_N

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

EDP_HPD

DP_WAKEUP

G4
G5

H3
H6

Y6
Y2

NC
NC

NC
NC

NC
NC

B

A

C1301

100PF

5%

16V

NP0-C0G

01005

ROOM=SOC

1

D18

NC

2

LPDPRX_EXT_C

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SOC: LPDP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

13 OF 80

SHEET

9 OF 51

8

67

35 4

2

1

SOC - SERIAL INTERFACES

678

3 245

1

AP I2C0

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

R1400

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1401

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

D

C

B

R1460

38

I2S_AP_TO_CODEC_MCLK1

OUT

33.2

1%

1/32W

MF

01005

ROOM=SOC

R1464

50

I2S_AP_TO_SPKRAMP_TOP_MCLK

OUT

33.2

1%

1/32W

MF

01005

ROOM=SOC

R1465

16 5

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1461

50

SPI_AP_TO_RACER_SCLK

OUT

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1462

38

SPI_AP_TO_CODEC_SCLK

OUT

SPI: Route as Daisy-Chain. No T's Allowed

Place series terminations close to SoC Pins

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

21

21

21

21

38

38

38

38

47 4

47 4

38

50

50

50

50

16 5 4

16 5

50 5

50

50

50

38

38

38

I2S_AP_TO_CODEC_MCLK1_R
I2S_AP_TO_CODEC_ASP3_BCLK

OUT

I2S_AP_TO_CODEC_ASP3_LRCLK

OUT

I2S_CODEC_ASP3_TO_AP_DIN

IN

I2S_AP_TO_CODEC_ASP3_DOUT

OUT

I2S_AP_TO_SPKRAMP_TOP_MCLK_R

AP_BI_CCG2_SWDIO

BI

AP_TO_CCG2_SWCLK

OUT

CODEC_TO_AP_INT_L CCG2_TO_SMC_INT_L

IN

I2S_BB_TO_AP_BCLK

OUT

I2S_BB_TO_AP_LRCLK

OUT

I2S_BB_TO_AP_DIN

IN

I2S_AP_TO_BB_DOUT

OUT

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

IN

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R
BOARD_ID3

IN

SPI_RACER_TO_AP_MISO

IN

SPI_AP_TO_RACER_MOSI

OUT

SPI_AP_TO_RACER_SCLK_R
SPI_AP_TO_RACER_CS_L

OUT

SPI_CODEC_TO_AP_MISO

IN

SPI_AP_TO_CODEC_MOSI

OUT

SPI_AP_TO_CODEC_SCLK_R
SPI_AP_TO_CODEC_CS_L

OUT

NC
NC
NC
NC
NC

NC

NC

NC
NC
NC
NC

AV23

AW23

AT24
AT25
AT26

AH34
AG36
AG35
AH38
AG37

AT35

AT36

AR36

AR34

AR35

AG4
AG5

AH2
AH6
AH4

AV22

BA21

BA22

AU22

AU23

AY22

AW22

AT23

AE4
AE2
AD5
AE6

AE38

AE35

AF38

AE37

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

U1000

TMIT78B0-C4

WLCSP

SYM 6 OF 16

ROOM=SOC

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C3_SCL

I2C3_SDA

SMC_I2CM0_SCL

SMC_I2CM0_SDA

SMC_I2CM1_SCL

SMC_I2CM1_SDA

SMC_UART0_RXD

SMC_UART0_TXD

SEP_SPI0_SCLK
SEP_SPI0_MISO
SEP_SPI0_MOSI

SEP_I2C_SCL

SEP_I2C_SDA

SPMI_SCLK

SPMI_SDATA

DWI_CLK

DWI_DO

CLK24M_OUT

NAND_SYS_CLK

AG3
AG2

AD38
AD36

A34
B34

AC36
AC38

AY16
AW16

AT20
AU20

AW19
AW15

AL6

NC

AM5

NC

AM4

AL2

CKPLUS_WAIVE=I2C_PULLUP

AM3

CKPLUS_WAIVE=I2C_PULLUP

AV21
AW20

AE36

NC

AF36

NC

AV19

BA20

IKTARA_TO_SMC_INT

PMU_TO_SEP_DOUBLE_CLICK_DET

SPMI_PMGR_TO_PMU_SCLK_R SPMI_PMGR_TO_PMU_SCLK

SPMI_PMU_BI_PMGR_SDATA

AP_TO_RACER_REF_CLK_R

AP_TO_NAND_SYS_CLK_R

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C1_SMC_SCL
I2C1_SMC_SDA

I2C4_AP_SCL
I2C4_AP_SDA

49 46 20 10

49 46 20 10

I2C0_AP_SCL
I2C0_AP_SDA

D

AP I2C1

PP1V8_IO

R1410

2.2K

5%

1/32W

MF

01005

ROOM=SOC

AP I2C2

PP1V8_IO

R1420

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

R1411

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1421

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

IN

IN
IN

50

29 28 27 17 16 14 10 8 7 6 5

49 46 20 10

49 46 20 10

49 33 10

49 33 10

49 33 10

50 10

50 10

50 42 10

50 42 10

50 47 23 22 21 10

50 47 23 22 21 10

48 10

48 10

47 4

49 33 10

I2C1_AP_SCL
I2C1_AP_SDA

29 28 27 17 16 14 10 8 7 6 5

I2C2_AP_SCL

50 10

I2C2_AP_SDA

50 10

43 35 34 32 30

43 35 34 32 30

AP I2C3

PP1V8_IO

R1430

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1431

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

C

10

10

29 28 27 17 16 14 10 8 7 6 5

20

IN

50 42 10

50 42 10

I2C3_AP_SCL
I2C3_AP_SDA

43 35 34 32 30

SMC I2C

48 47 46 38 22 20 17 14 12 10

R1482

0.00

BI

20 4

1/32W
01005

21

0%
MF

ROOM=SOC

OUT

20

50 47 23 22 21 10

50 47 23 22 21 10

I2C0_SMC_SCL
I2C0_SMC_SDA

48 47 46 38 22 20 17 14 12 10

R1481

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_RACER_REF_CLK

OUT

50

I2C1_SMC_SCL

48 10

I2C1_SMC_SDA

48 10

R1480

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_NAND_SYS_CLK

OUT

16

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_S2

50 49

PP1V8_S2

50 49

AP I2C4

PP1V8_IO

R1440

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1450

4.7K

5%

1/32W

MF

01005

ROOM=SOC

R1470

4.7K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

1

2

R1441

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1451

4.7K

5%

1/32W

MF

01005

ROOM=SOC

R1471

4.7K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

B

1

2

A

335S00234

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

WLCSP U1490

1 CRITICAL COMMON

TABLE_ALT_HEAD

PART NUMBER

335S00234

BOM_TABLE_ALTS

U1490 U1490335S00233

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

1

C1490

0.47UF

20%

6.3V

2

X5R
01005

ROOM=SOC

SCL

VCC

U1490

WLCSP

OMIT_TABLE

VSS

ROOM=SOC

CRITICAL

B2 A1

SDA

I2C4_AP_SCL

10

I2C4_AP_SDA

10

A2B1

I2C4_AP_SDA
I2C4_AP_SCL

10

10

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Serial

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

14 OF 80

SHEET

10 OF 51

8

67

35 4

2

.

1

678

3 245

1

D

C

43

28

50

50

50

50

28

50

50

50

50

50

5 4

50

20

50

50

50 48 20

20

50

50

D

SOC - GPIO INTERFACES

U1000

TMIT78B0-C4

WLCSP

SYM 5 OF 16

ROOM=SOC

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD

UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD

UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD

UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD

UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD

UART4_TXD

UART6_RXD

UART6_TXD

UART7_RXD

UART7_TXD

D28
C30
A28

AF3
AF2

P34
L36
P36
M37

B28
B29
C28
B30

D30
B32
C32
D31

K36
M35
N36
N35

AF5
AF4

R5
P2

NC
NC

PMU_TO_AP_PRE_UVLO_L

IN

JULIET_PMU_TO_RIGEL_STROBE_R

WLAN_TO_AP_TIME_SYNC

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

UART_GNSS_TO_AP_CTS_L
UART_AP_TO_GNSS_RTS_L

UART_GNSS_TO_AP_RXD
UART_AP_TO_GNSS_TXD

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L

UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

20 6 4

50

48

48

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

48

48

NC

NC

NC

NC

NC

NC

NC
NC

NC

AL4

T35
R36
P38
R35
N37

L37
K38
K34

L35
D33
C34
D32
D29

B33

A32

P6

P4
R4
R3
R2

T5

T4

T3

T2
U6
U4
U2

V5

V4

V3

AJ3
AJ4
AJ5

AJ6
AK3
AK4
AK5

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37

AP_TO_DISPLAY_RESET_L

OUT

AP_TO_CAMPMU_RESET_L

OUT

AP_TO_NFC_DEV_WAKE

OUT

AP_TO_BB_COREDUMP

OUT

AP_TO_BB_RESET_L

OUT

AP_TO_BB_IPC_GPIO1

OUT

CAMPMU_TO_AP_IRQ_L

IN

AP_TO_GNSS_WAKE

OUT

AP_TO_BT_WAKE

OUT

AP_TO_SPKRAMP_TOP_RESET_L

OUT

AP_TO_NFC_FW_DWLD_REQ

OUT

AP_TO_RACER_RESET_L

OUT

BOARD_ID0

IN

SPKRAMP_TOP_TO_AP_INT_L

IN

PMU_TO_AP_BUTTON_VOL_UP_L

IN

AP_TO_BBPMU_RADIO_ON_L

OUT

AP_TO_WLAN_DEVICE_WAKE

OUT

5

4

5

5

5

5

5

5

PP1V8_IO

IN

PMU_HYDRA_TO_AP_FORCE_DFU

IN

DFU_STATUS

OUT

PP1V8_IO

IN

BOARD_ID4

IN

AP_TO_PMU_AMUX_SYNC

IN

AP_TO_BB_TIME_MARK

OUT

BB_TO_AP_RESET_DETECT_L

IN

BOARD_REV3

IN

BOARD_REV2

IN

BOARD_REV1

IN

BOARD_REV0

IN

NOSTUFF

R1500

200K

1%

1/32W

MF

01005

ROOM=SOC

21

JULIET_PMU_TO_RIGEL_STROBE

OUT

35 34

C

B

20

20

PMU_TO_AP_BUTTON_POWER_KEY_L

IN

PMU_TO_AP_BUTTON_VOL_DOWN_L

IN

AB2
AC4

B

REQUEST_DFU1
REQUEST_DFU2

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SOC: GPIO & UART

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

15 OF 80

SHEET

11 OF 51

1

SIZE

D

SOC - AOP

678

3 245

1

1.8V @ 15mA MAX

D

C

AOP I2C Pull-Ups

1

R1620

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1621

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

50 49 41 38

50 49 41 38

1

R1622

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

IN

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

PP1V8_S2

1

R1623

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

I2C1_AOP_SCL
I2C1_AOP_SDA
I2C0_AOP_SCL
I2C0_AOP_SDA

26 4

50 49

50 49 41 25 12 4

50 49 41 25 12 4

36 12

36 12

SPI_AOP_TO_IMU_SCLK

OUT

48 47 46 38 22 20 17 14 12 10

PP1V8_S2

50 49

1

C1690

4UF

20%

6.3V

2

CER-X5R
0201

1

C1691

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOCROOM=SOC

D

AP19

AP17

AP15

AP13

VDDIO18_AOP

VDDIO18_AOP

VDDIO18_AOP

VDDIO18_AOP

NC
NC

NC

NC

NC

AT11

AU14

AU13
AW10
AW11

AT16
AV11
AY10
AV12
AY11
AU16
AV16

AT17
AV13

AW12

AV14

AW13

AU17

AV15
AY13
BA11
AV17
BA10
AT18

AW14

AV18
BA12
AY14

AW7

AU10

AV8

AT14

AY8
BA8

AW8

AU11

AT15

AON_DDR_RESET*

AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_3
AOP_FUNC_4
AOP_FUNC_5
AOP_FUNC_6
AOP_FUNC_7
AOP_FUNC_8
AOP_FUNC_9
AOP_FUNC_10
AOP_FUNC_11
AOP_FUNC_12
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15

AOP_FUNC_16
AOP_FUNC_17
AOP_FUNC_18
AOP_FUNC_19
AOP_FUNC_20
AOP_FUNC_21
AOP_FUNC_22
AOP_FUNC_23
AOP_FUNC_24
AOP_FUNC_25
AOP_FUNC_26

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

SPI SCM

AOP_PDM_CLK4

I2C0 SCM

U1000

TMIT78B0-C4

WLCSP

SYM 7 OF 16

ROOM=SOC

AOP_SWD_TCK_OUT

I2C1 SCM

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

AOP_SWD_TMS0
AOP_SWD_TMS1

SWD_TMS2
SWD_TMS3

AOP_I2CM0_SCL

AOP_I2CM0_SDA

AOP_I2CM1_SCL

AOP_I2CM1_SDA

DOCK_ATTENTION

DOCK_CONNECT

BA16
AW18
AW17

BA18
AV20

AY17
AT21
AC5
AC2

BA9
AV9

AV10
AW9

BA17
AY19

NC

NC

CODEC_TO_AOP_GPIO1
CODEC_TO_AOP_GPIO2

PMU_TO_AOP_CLK32K

SWD_AOP_TO_MANY_SWCLK

OUT

SWD_AOP_BI_RACER_SWDIO

SWD_AOP_BI_BB_SWDIO

SWD_AP_BI_NAND_SWDIO

I2C0_AOP_SCL

OUT

I2C0_AOP_SDA
I2C1_AOP_SCL

OUT

I2C1_AOP_SDA

HYDRA_TO_NUB_INT

HYDRA_TO_NUB_DOCK_CONNECT

38

IN

38

IN

20

IN

50 16 4

50

BI

50

BI

48

48

16 4

36 12

36 12

50 49 41 25 12 4

50 49 41 25 12 4

C

BI

BI

BI

IN

IN

14 4

26 4

26

26 4

48 47 46 38 22 20 17 14 12 10

50 28 21 20 8

26

26 4

35

50

38

20

50 41

50 41

38

49 41 38

36

50

36

AOP_TO_DDR_SLEEP1_READY

OUT

ACCEL_GYRO_TO_AOP_DATARDY

BI

SPI_AOP_TO_ACCEL_GYRO_CS_L

IN

ACCEL_GYRO_TO_AOP_INT

OUT

SPI_AOP_TO_PHOSPHORUS_CS_L

IN

PHOSPHORUS_TO_AOP_INT

OUT

ROMEO_TO_AOP_B2B_DETECT

IN

RACER_TO_AOP_INT_L

IN

AOP_TO_CODEC_RESET_L

OUT

AP_TO_MANY_BSYNC

IN

PMU_TO_AOP_IRQ_L

OUT

AOP_TO_SPKRAMP_BOT_ARC_RESET_L

IN

SPKRAMP_BOT_ARC_TO_AOP_INT_L

OUT

AOP_TO_CODEC_CLP_EN

OUT

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

OUT

PROX_BI_AP_AOP_INT_L

IN

HALL3_TO_AOP_IRQ_L

IN

ALS_TO_AOP_INT_L

IN

R1603

49.9

1/32W

01005

ROOM=SOC

21

1%
MF

R1604

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

50 41 38

R1601

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

49 25 4

50

26 4

26 4

50

50

50

50

50

50

COMPASS_TO_AOP_INT

IN

HALL2_TO_AOP_IRQ_L

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

SPI_IMU_TO_AOP_MISO

IN

SPI_AOP_TO_IMU_MOSI

OUT

SPI_AOP_TO_IMU_SCLK_R

UART_BB_TO_AOP_RXD

IN

UART_AOP_TO_BB_TXD

OUT

AOP_TO_WLAN_CONTEXT_A

OUT

AOP_TO_WLAN_CONTEXT_B

OUT

UART_RACER_TO_AOP_RXD

IN

UART_AOP_TO_RACER_TXD

OUT

B

38

I2S_AOP_TO_CODEC_MCLK2

OUT

R1602

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

38

38

38

38

I2S_AOP_TO_CODEC_ASP2_BCLK

OUT

I2S_CODEC_ASP2_TO_AOP_DIN

IN

I2S_AOP_TO_CODEC_MCLK2_R
I2S_AOP_TO_CODEC_ASP2_LRCLK

OUT

I2S_AOP_TO_CODEC_ASP2_DOUT

OUT

BA14

AT19
AU19
BA15

BA13

AOP_I2S0_BCLK
AOP_I2S0_DIN
AOP_I2S0_MCK
AOP_I2S0_LRCK

AOP_I2S0_DOUT

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: AOP

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

16 OF 80

SHEET

12 OF 51

1

SIZE

D

678

SOC - CPU, GPU & SOC RAILS

1.06V @ 11.0A MAX

0.8V @ 6A MAX

0.575V @ 2.7A MAX

PP_CPU_PCORE

17 4

3 245

1

D

C

B

ROOM=SOC

C1708

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

ROOM=SOC

C1709

14UF

0402-D2X-1

1

0.7V @ 75mA MAX

PP0V7_VDD_LOW_S2

19

1.01V @ 2.1A MAX

0.735V @ 0.6A MAX

PP_CPU_SRAM

17

1.06V @ 1.1A MAX

0.80V @ 0.63A MAX

0.675V @ 0.19A MAX

PP_GPU_SRAM

17

20%
X5R

2

4V

1

C1702

4UF

20%
4V

2

X5R
0201

1

ROOM=SOC

C1704

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1710

14UF

20%

4V

X5R

0402-D2X-1

3

4

1

432

ROOM=SOC

C1705

14UF

20%

4V

X5R

1

432

ROOM=SOC

C1711

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1706

14UF

20%

4V

X5R

0402-D2X-10402-D2X-1

1

432

ROOM=SOC

C1712

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1772

14UF

20%

4V

X5R

0402-D2X-1

1

2

3

4

C1703

4UF

20%
4V

2

X5R
0201

ROOM=SOCROOM=SOC

ROOM=SOC

C1707

0402-D2X-1

1

ROOM=SOC

C1713

14UF

20%
X5R

0402-D2X-1

1

1

C1750

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

ROOM=SOC

C1773

14UF

20%

4V

X5R

0402-D2X-1

1

14UF

20%

4V

X5R

432

4V

432

432

OMIT

XW1701

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

AA14
AA16
AB11
AB13
AB15
AB17
AB19
AC20
AD15
AE14

AF20

AG9
AG15
AH10
AH12
AH14
AH16
AH18
AH20

AM15
AM17
AM19
AM21

AN16
AN18
AN20

AA12
AB18

AC9
AC14
AE20

AF14

U14

VDD_CPU

VDD_LOW

VDD_CPU_SRAM

U1000

TMIT78B0-C4

WLCSP

SYM 8 OF 16

ROOM=SOC

BUCK0_FB

VDD_GPU

VDD_ECPU

OUT

17

F25
J16
F31
G20
G22
G24
G26
J28
H11
H15
H19
H23
H31
J12
J18
J22
J24
J26
J30
L16
K17
K29
L12
L18
L22
L28
M23
L24
N22
N24
N28

AA10
U10
U12
V13
V15
Y13
Y15

1

C1730

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1732

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1737

14UF

20%

4V

X5R

0402-D2X-1

1

432

1

C1731

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1733

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1738

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1791

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1734

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1739

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1792

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1735

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1793

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

XW1731

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

ROOM=SOC

C1736

14UF

20%

4V

X5R

0402-D2X-1

1

432

XW1790

SHORT-20L-0.05MM-SM

2 1

1

C1794

4UF

20%
4V

2

X5R
0201

ROOM=SOC

OMIT

21

ROOM=SOC

OMIT

ROOM=SOC

(Analog)

20 4

AP_CPU_PCORE_SENSE

OUT

AH21

VDD_CPU_SENSE

0.8V @ 6mA MAX

0.8V @ 6mA MAX

0.8V @ 10mA MAX

20 4

ROOM=SOC

C1781

14UF

20%

4V

X5R

0402-D2X-1

1

432

AP_VDD_GPU_SENSE

OUT

ROOM=SOC

C1782

14UF

20%

4V

X5R

0402-D2X-1

1

432

N26
H13
H17
H21
H25
K11
K19

K23
G30
M29

N23

VDD_GPU_SRAM

VDD_GPU_SENSE

VDD_FIXED_CPU

VDD_FIXED_PLL_GPU
VDD_FIXED_PLL_SOC

VDD12_PLL_CPU
VDD12_PLL_GPU
VDD12_PLL_SOC

W14
K21

L20

W16
L21
M20

1

C1720

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1721

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP0V8_SOC_FIXED_S1

(Analog)

1.2V @ 7mA MAX (CPU)

1.2V @ 7mA MAX (GPU)

1.2V @ 20mA MAX (SOC)

PP1V2_SOC

1

C1722

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1723

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

17 14 9 8 7 6

19 14 9 7

1.06V @ 18.3A MAX

0.8V @ 10.6A MAX

0.575V @ 3.4A MAX

PP_GPU

BUCK1_FB

BUCK11_FB

1.06V @ 4.3A MAX

0.8V @ 2.8A MAX

0.575V @ 1.4A MAX

PP_CPU_ECORE

OUT

17 4

18

0.765V @ 4.9A MAX

0.635V @ 2.6A MAX

PP_SOC_S1

1

C1760

4UF

20%
4V

2

X5R
0201

ROOM=SOC

AA9
AA18
AA22
AA24
AA28
AA30
AB21
AB25
AB27

AC22
AC24
AC28
AC30

AD9

AD21
AD25
AD27
AD29

20 18

AE22
AE24
AE28
AF25
AF27

AG22
AG24
AG28
AH25
AH27

AJ16
AJ18
AJ22
AJ24

AJ28
AK13
AK15
AK19
AK21
AK25
AK27

AL12

AL16

AL18

AL22

AL24

AL28

AL30

AM13
AM25

AN12
AN22
AN24

F22

VDD_SOC

1

C1761

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1762

14UF

20%

4V

X5R

0402-D2X-1

1

432

U1000

TMIT78B0-C4

WLCSP

SYM 9 OF 16

ROOM=SOC

ROOM=SOC

C1763

14UF

20%

4V

X5R

0402-D2X-1

1

432

VDD_SOC_SENSE

ROOM=SOC

C1764

14UF

20%

4V

X5R

0402-D2X-1

1

432

G13
J20
L19
M13
M15
M21
N10
N12
N16
N18
N29
P13
P15
P19
P21
P25
P27
R10
R12
R16
R18
R22
R24
R28
T13
T15
T19
T21
T25
T27
U16
U18
U22
U24
U28
U30
V19
V21
V25
V27
W18
W22
W24
W28
W30
Y19
Y25
Y21
Y27

P23

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

OMIT

XW1760

21

ROOM=SOC

TP_SOC_SENSE

OUT

BUCK2_FB

4

17

D

17 17

OUTOUT

C

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Power (1/3)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

17 OF 80

SHEET

13 OF 51

1

SIZE

D

D

C

B

9 8 7 6
17 14 13

34 32

27 17
8 7 6 5
16 14 10
30 29 28

43 35

SOC - POWER SUPPLIES

0.8V @ 0.9A MAX

PP0V8_SOC_FIXED_S1

ROOM=SOC

C1801

1.8V @ 60mA MAX

PP1V8_IO

1

C1810

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=SOC

1

C1802

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

2

1

C1811

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

C1803

4UF

20%
4V
X5R
0201

ROOM=SOC

1

2

1

C1804

4UF

20%
4V

2

X5R
0201

ROOM=SOC

C1812

4UF

20%

6.3V
CER-X5R
0201

ROOM=SOC

0402-D2X-1

1

1

C1805

2

ROOM=SOC

1

C1813

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

14UF

20%

4V

X5R

4UF

20%
4V
X5R
0201

432

AA20
AA26

AB9
AB23
AB29
AC26
AD23
AD31
AE26
AF23
AF29

AG26

AH23
AH29

AJ14
AJ20

AJ26
AK17
AK23

AL14

AL20

AL26

AM11
AM23

AP11
AP21
AP24

F19

F23
M11
M17

N14
N20

P11

P17

P29

R14
R20
R26

T11

T17

T23

T31

U20
U26

AP23
AP25

AB31

V31
Y31

F21

D23

VDD_FIXED

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

678

U1000

TMIT78B0-C4

WLCSP

SYM 10 OF 16

ROOM=SOC

VDD_FIXED_PLL_DDR0
VDD_FIXED_PLL_DDR1
VDD_FIXED_PLL_DDR2
VDD_FIXED_PLL_DDR3

U1000

TMIT78B0-C4

WLCSP

SYM 12 OF 16

ROOM=SOC

VDD18_TSADC_CPU0
VDD18_TSADC_CPU1
VDD18_TSADC_CPU2
VDD18_TSADC_CPU3

VDD18_TSADC_GPU0
VDD18_TSADC_SOC0

VDD18_TSADC_SOC1
VDD18_TSADC_SOC2

LPADC_REF_P

LPADC_REF_M

18 14

V17
V23
V29
W20
W26
Y9
Y17
Y23
Y29

BA19
AY20

AK11
AJ29
D8
R29

T12
AF21
AJ9
Y16

G21
AJ12

AD30
J31

0.6V @ 262mA MAX

PP0V6_VDDQL_S1

1

C1870

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

0.8V @ 8mA MAX

PP0V8_SOC_FIXED_S1

1.06V - 1.17V @ (Inc in VDD2)

42 19 17 14

19 13 9 7

PP1V1_S2

(Analog)

1.2V @ 16mA MAX

PP1V2_SOC

0.875V @ 0.8A MAX

0.730V @ 0.51A MAX

0.600V @ 0.35A MAX

PP_DCS_S1

17

1.8V @ 5.3mA MAX (CPU)

1.8V @ 1.1mA MAX (GPU)

1.8V @ 3.3mA MAX (SOC)

1

C1830

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1831

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

2

Place caps on SoC Corners

PP1V2_LPADC

19

OMIT

XW1870

SHORT-20L-0.05MM-SM

LPADC_GND

(Analog)

VDDQL Voltage Sense ->

1

C1860

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1861

4UF

20%
4V

2

X5R
0201

ROOM=SOC

Place caps on SoC Corners

ROOM=SOC

17 14 13 9 8 7 6

1

C1862

4UF

20%
4V

2

X5R
0201

ROOM=SOC

DCS Voltage Sense ->

PP1V8_IO

43 35 34 32

C1832

4UF

20%
4V
X5R
0201

ROOM=SOC

21

30 29 28 27 17 16 14 10 8 7 6 5

1

C1833

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1863

4UF

20%
4V

2

X5R
0201

ROOM=SOC

NC

NC

AD1
AF1
AH1
AK9
AP9
AT1
AV1

AD39

AF31

AF39
AK31
AP39

AT39
AV39

D1

F1

F9
H1
K9

T1
V1
C4

D39
F39
K31
P31
P39
T39
V39

AR6

AN34

E6

G34

AJ11

AK29

D9

T29

AJ10

AP10

AE30
AK30

F10
L10

A4

K30
R30

VDDQL_DDR0

VDDQL_DDR1

VDDQL_DDR2

VDDQL_DDR3

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3

VDD_DCS_DDR0

VDD_DCS_DDR1

VDD_DCS_DDR2

VDD_DCS_DDR3

U1000

TMIT78B0-C4

WLCSP

SYM 11 OF 16

ROOM=SOC

3 245

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_ZQ
DDR3_ZQ

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

VDD1

VDD2

PP0V6_VDDQL_S1

18 14

AP5
AN35
E5
H35

AR5
AM35
E3
G35

AJ2
N38

AP6
AM34
E4
H34

AB3

AB37

AW3

AW37
B3
B37
Y3
Y37

AA2
AA38
AC39
AH39
AJ1
AK39
AM1
AN39
AP1
AV2
AV37

AW2

AW38
C2
C3
C38
D38
H39
J1
K39
M1
N39
P1
W1

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

1

C1840

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1850

4UF

20%
4V

2

X5R
0201

ROOM=SOC

DDR IMPEDANCE CONTROL

1

R1860

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1861

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1862

240

1%
1/32W
MF
01005

2

ROOM=SOC

AOP_TO_DDR_SLEEP1_READY

SYSTEM_ALIVE

1

C1841

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1851

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1842

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1852

4UF

20%
4V

2

X5R
0201

ROOM=SOC

IN

IN

12 4

23 20 16

1

C1843

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1853

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

R1863

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1870

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1871

240

1%
1/32W
MF
01005

2

ROOM=SOC

1.8V @ 200mA MAX

1.06V - 1.17V @2.2A MAX

1

PP1V8_S2

PP1V1_S2

D

C

50 49

42 19 17 14

48 47 46 38 22 20 17 14 12 10

B

A

8

AF9

V9

VDDIO18_GRP4

VDD18_EFUSE1
VDD18_EFUSE2

VDD18_FMON

VDD18_LPOSC

67

H12
AT6
AN13
AN19

1

C1880

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=SOC

1.8V @ 1mA MAX

PP1V8_IO

PP1V8_LPOSC_S2

1

C1881

0.47UF

20%

6.3V

2

X5R
01005

ROOM=SOC

43 35 34 32

30 29 28 27 17 16 14 10 8 7 6 5

R1880

300

5%

1/32W

MF

01005

ROOM=SOC

1.8V @ 1mA MAX

21

PP1V8_S2

A

SYNC_MASTER=test_mlb

50 49

48 47 46 38 22 20 17 14 12 10

PAGE TITLE

SYNC_DATE=10/17/2016

SOC: Power (2/3)

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02221

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

evt-1

PAGE

18 OF 80

SHEET

14 OF 51

1

SOC - POWER SUPPLIES

678

3 245

1

D

C

B

A1
A2
A3

A5
A11
A18
A27
A29
A31
A33
A35
A36
A37
A38
A39

AA1

AA6
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AA29
AA31
AA34
AA36
AA39

AB1

AB5
AB10
AB12
AB14
AB16
AB20
AB22
AB24
AB26
AB28
AB30
AB35
AB39

AC1

AC3

AC6
AC15
AC21
AC23
AC25
AC27
AC29
AC31
AC34
AC35

AD4

AD6
AD14
AD20
AD22
AD24
AD26
AD28
AD34
AD35
AD37

AE1

AE3

AE5

AE9
AE15
AE21
AE23
AE25
AE27

U1000

TMIT78B0-C4

WLCSP

SYM 13 OF 16

ROOM=SOC

AE29
AE31
AE34
AE39
AF6
AF15
AF22
AF24
AF26
AF28
AF30
AF35
AF37
AG1
AG6
AG14
AG20
AG23
AG25
AG27
AG29
AG34
AG39
AH3
AH5
AH9
AH11
AH13
AH15
AH17
AH19
AH22
AH24
AH26
AH28
AH35
AH37
AJ13

VSSVSS

AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ34
AJ35
AJ39
AK1
AK2
AK6
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK34
AK35
AK36
AL1
AL3
AL5
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL31

AL34
AL35
AL36
AL39

AM2

AM6
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM36
AM37
AM38
AM39

AN1
AN2
AN3
AN4
AN5

AN6
AN11
AN17
AN21
AN23
AN25
AN29
AN31
AN36
AN37
AN38

AP2

AP3

AP4

AP12
AP16
AP18
AP20
AP22
AP28
AP34
AP35
AP36
AP37
AP38

AR1

AR2

AR3

AR4
AR37
AR38
AR39

AT2
AT3
AT4

AT5
AT28
AT29
AT31
AT32
AT33
AT37
AT38

AU1

AU2
AU12
AU15
AU18
AU21
AU24
AU25
AU26
AU27

U1000

TMIT78B0-C4

WLCSP

SYM 14 OF 16

ROOM=SOC

VSS VSS

AU29
AU3
AU4
AU5
AU6
AU9
AU31
AU33
AU34
AU35
AU36
AU37
AU38
AU39
AV3
AV4
AV24
AV26
AV28
AV30
AV32
AV34
AV36
AV38
AW1
AW4
AW24
AW28
AW30
AW32
AW34
AW36
AW39
AY1
AY2
AY3
AY5
AY7
AY9
AY12
AY15
AY18
AY21
AY23
AY25
AY27
AY28
AY29
AY31
AY33
AY35
AY37
AY38
AY39
B1
B2
B4
B5
B11
B18
B27
B35
B36
B38
B39
BA1
BA2
BA3
BA5
BA7
BA23
BA25
BA26
BA29
BA31
BA33
BA35
BA37
BA38

<- DDR Vss V Sense

NC

BA39

C1
C5
C6
C7
C8

C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C29
C31
C33
C35
C36
C37
C39
D10
D14

D2

D3

D4

D5

D6

D7
D22
D24
D25
D26
D27
D34
D35
D36
D37

E1

E2
E34
E35
E36
E37
E38
E39

F12
F14
F18

F2
F3
F4
F5

F6
F20
F24
F26
F30
F34
F35
F36
F37
F38

G1

U1000

TMIT78B0-C4

WLCSP

SYM 15 OF 16

ROOM=SOC

VSSVSS

G2
G3
G6
G11
G15
G17
G19
G23
G25
G31
G36
G37
G38
G39
H2
H4
H5
H14
H16
H18
H20
H22
H24
H26
H30
H36
H37
H38
J2
J3
J6
J11
J17
J19
J21
J23
J25
J27
J29
J34
J35
J36
J37
J38
J39
K1
K2
K5
K6
K10
K12
K16
K18
K20
K22
K24
K28
K35
K37
L1
L2
L3
L6
L9
L11
L17
L23
L29
L34
L38
L39
M10
M12
M14
M16
M18

M19

M2
M5

M6
M22
M24
M28
M34
M36
M38
M39

N1
N2
N3
N4
N5
N6

N9
N11
N13
N15
N17
N19
N21
N25
N27
N34

P3

P5

P10
P12
P14
P16
P18
P20
P22
P26
P28
P30
P35
P37

R1

R6
R11
R13
R15
R17
R19
R21
R23
R25
R27
R31
R34
R39

T6
T10
T14
T16
T18
T20
T22
T24
T26
T28
T30
T34
T36
T38

U1
U3
U5

U9
U11
U13
U15
U17
U19

VSS

U1000

TMIT78B0-C4

WLCSP

SYM 16 OF 16

ROOM=SOC

VSS_CPU_SENSE

VSS_SENSE

U21
U23
U25
U27
U29
U31
U34
U39
V6
V14
V16
V18
V20
V22
V24
V26
V28
V30
V35
V37
W2
W3
W6
W9
W13
W15
W17
W19
W21
W23
W25
W27
W29
W31
W34
W37
W38
W39
Y1
Y5
Y14
Y18
Y20
Y22
Y24
Y26
Y28
Y30
Y35

Y39
AG21
P24

TP_VSS_CPU_SENSE

TP_VSS_SENSE

OUT

OUT

D

C

4

4

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Power (3/3)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

19 OF 80

SHEET

15 OF 51

1

SIZE

D

391mA MAX

678

3 245

1

D

28 27 17 16 14 10 8 7 6 5

43 35 34 32 30 29

1

2

PP1V8_IO

C2624

4UF

20%
4V
X5R
0201

ROOM=NAND

1

C2641

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2643

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2626

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2629

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

1

C2645

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2610

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=NAND

1

C2630

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

1

C2647

4UF

20%
4V

2

X5R
0201

ROOM=NAND

S4E NAND

D

C

932mA MAX

PP0V9_NAND

19

1

C2622

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2627

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2611

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C2602

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=NAND

1

C2640

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2617

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

1

C2605

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=NAND

1

C2642

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2623

68PF

5%

6.3V

2

NP0-C0G
01005

ROOM=NAND

1

C2600

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2644

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2612

47PF

5%
16V

2

CERM
01005

ROOM=NAND

1

C2601

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2646

4UF

20%
4V

2

X5R
0201

ROOM=NAND

1

C2613

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

1

C2616

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

1

C2619

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

1100mA MAX (1us peak power)

PP3V0_NAND

1

C2621

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=NAND

C

19

B

1

C2603

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C2606

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND ROOM=NAND

1

R2604

3.01K

1%
1/32W
MF
01005

2

ROOM=NAND

1

C2609

100PF

5%
16V

2

NP0-C0G
01005

10

7 4

7 4

7

7

1

C2614

68PF

5%

6.3V

2

NP0-C0G
01005

ROOM=NAND

AP_TO_NAND_SYS_CLK

IN

90_PCIE_AP_TO_NAND_REFCLK_P

IN

90_PCIE_AP_TO_NAND_REFCLK_N

IN

7

PCIE_NAND_BI_AP_CLKREQ_L

BI

PCIE_NAND_RESREF

7

7

90_PCIE_AP_TO_NAND_TXD_P

IN

90_PCIE_AP_TO_NAND_TXD_N

IN

90_PCIE_NAND_TO_AP_RXD_P

OUT

90_PCIE_NAND_TO_AP_RXD_N

OUT

1

C2620

47PF

5%
16V

2

CERM
01005

ROOM=NAND

4

4

1

C2628

22PF

5%
16V

2

CERM
01005

ROOM=NAND

NAND_ANI1_VREF

OUT

NAND_ANI0_VREF

OUT

M3

CLK_IN

K11

PCIE_REFCLK_P

J12

PCIE_REFCLK_M

P5

PCIE_CLKREQ_N

H7

PCI_RESREF

M11

PCIE_RX0_P

N12

PCIE_RX0_M

R12

PCIE_TX0_P

T11

PCIE_TX0_M

J8

N8

J6

M9

N6

PCI_VDD_1

PCI_AVDD_H

PCI_AVDD_CLK_1

PCI_AVDD_CLK_2

L2J4G12

PCI_VDD_2

ANI0_VREF

AVDD18_PLL

L6

G8

G6

ANI1_VREF

L8

VDD

K9

J2

E10

E2

R8

R6

VDDIO

U2600

THGBX7G8D2LLFXG

WFLGA

ROOM=NAND

BOMOPTION=OMIT_TABLE

CRITICAL

N2

T5

P9

D3

E12

G4

L12

VCC

R2

NC

F3

R4

VPP

VDD_PLL

1

C2649

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=NAND

1

C2615

22PF

5%
16V

2

CERM
01005

ROOM=NAND

EXT_D2/BOOT2/SPINAND_SCLK

EXT_D3/SWD_UID0/SPINAND_MISO

EXT_D4/UART_RX

EXT_D5/SWD_UID1/SPINAND_MOSI

EXT_D6/UART_TX

EXT_NCE/PERST*

EXT_NRE/JTAG_TMS

EXT_NWE/JTAG_TCK

EXT_RNB/JTAG_TDO

EXT_CLE/JTAG_TDI

EXT_ALE/JTAG_SEL

1

C2618

47PF

5%
16V

2

CERM
01005

ROOM=NAND

EXT_D0/BOOT0
EXT_D1/BOOT1

EXT_D7/SPF

B3
C4
B5
C6
B7
C8
B9
B11

E8
D7
E6
E4
D5
D9

NC

NC

NC

1

C2650

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=NAND

1

C2631

68PF

5%

6.3V

2

NP0-C0G
01005

ROOM=NAND

1

C2651

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=NAND

1

C2632

100PF

5%
16V

2

NP0-C0G
01005

PMU_TO_NAND_LOW_BATT_BOOT_L

AP_TO_NAND_FW_STRAP
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

PCIE_AP_TO_NAND_RESET_L

SWD_AP_BI_NAND_SWDIO

SWD_AOP_TO_MANY_SWCLK

1

C2652

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=NAND

1

C2634

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NANDROOM=NAND

SYSTEM_ALIVE

1

C2635

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

IN
IN
IN

OUT

IN

IN

IN

BI

IN

20

6

7

1

C2636

220PF

5%
10V

2

C0G-CERM
01005

ROOM=NAND

1

C2637

100PF

5%
16V

2

NP0-C0G
01005

ROOM=NAND

B

10 5

10 5 4

10 5

23 20 14

12 4

50 12 4

A

8

U12

T3
G2

PP1V8_IO

43 35 34 32

30 29 28 27 17 16 14 10 8 7 6 5

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

NAND

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

evt-1

PAGE

26 OF 80

SHEET

16 OF 51

1

SIZE

D

DROOP_N

6

AP_TO_NAND_RESET_L

IN

Board trace <= 0.2Ohm

NAND_ZQ_C
NAND_ZQ_N

CKPLUS_WAIVE=MISS_P_DIFFPAIR

1

R2600

100

0.1%
1/32W
MF
01005

2

ROOM=NAND

1

R2601

300

0.1%
1/32
MF
01005

2

ROOM=NAND

L4

G10

K3

C10

RESET*
TRST*
ZQ_C

ZQ_N

A4

A2

A6

A8

A10

A12

B1

B13

C2

C12

D1

D11

D13

F1

F5

F7

F9

F11

F13

H1

H3

H5

H9

H11

H13

VSS

J10

K1

K5

K7

K13

L10

M1

M5

M7

M13

N4

N10

P1

P3

P7

P11

P13

R10

T1

T7

T9

T13

U2

U4

U6

U8

WP_N

U10

67

D

C

B

4.9A MAX

BUCK5BUCK6BUCK7BUCK8 BUCK4

1.7A MAX

2.1A MAX

1.2A MAX 1.2A MAX

BUCK9

1.2A MAX

42 19 14

(Place in TTS)

14 13 9 8 7 6

27 19

13

13

14

PP1V1_S2

1

C2745

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2744

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP0V8_SOC_FIXED_S1

PP1V25_S2

(Place Close to Ansel)

0.80V - 1.06V

PP_CPU_SRAM

0.80V - 0.92V

PP_GPU_SRAM

PP_DCS_S1

1

C2743

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2763

15UF

20%

6.3V

2

X5R
0402-0.1MM-1

ROOM=PMU

1

C2742

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2752

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2762

20%

6.3V

2

X5R
0402-0.1MM-1

ROOM=PMU

1

C2772

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2782

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2792

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2741

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2751

26UF

20%
4V 10V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2761

15UF15UF

20%

6.3V

2

X5R
0402-0.1MM-1

ROOM=PMU

1

C2771

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2781

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2791

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2740

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2750

220PF

5%

2

C0G-CERM
01005

ROOM=PMU

1

C2760

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2770

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2780

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2790

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

678

L2740

1UH-20%-3.2A-0.06OHM

2 1

PIWA20160H-SM

ROOM=PMU

CRITICAL

L2741

0.47UH-20%-3.3A-0.053OHM

PIWA2012FE-SM

ROOM=PMU

OMIT

XW2740

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

L2750

1UH-20%-2.5A-0.052OHM

2 1

PIWA20160H-SM

ROOM=PMU

OMIT

XW2750

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

CRITICAL

L2760

1UH-20%-2.4A-0.06OHM

2 1

PIWA2016FE-SM

ROOM=PMU

OMIT

XW2760

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

L2770

1UH-20%-2.5A-0.052OHM

2 1

PIWA20160H-SM

ROOM=PMU

OMIT

XW2770

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

CRITICAL

L2780

1UH-20%-2.5A-0.078OHM

2 1

PIWA20120H-SM

ROOM=PMU

OMIT

XW2780

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

CRITICAL

L2790

1UH-20%-2.1A-0.1OHM

2 1

PIWA2012FE-SM

ROOM=PMU

OMIT

XW2790

SHORT-20L-0.05MM-SM

21

ROOM=PMU

BUCK4_LX0

21

BUCK4_LX1

BUCK4_FB

BUCK5_LX0

BUCK5_FB

BUCK6_LX0

BUCK6_FB

BUCK7_LX0

BUCK7_FB

BUCK8_LX0

BUCK8_FB

BUCK9_LX

BUCK9_FB

V11

W11

Y11

V9

W9

Y9

T8

V3

W3

Y3

T4

H1
H2

H4

W16
W17
W18

W14

A17
B17

E17

A6
B6

F4

BUCK4_LX0

BUCK4_LX1

BUCK4_FB

BUCK5_LX0

BUCK5_FB

BUCK6_LX0

BUCK6_FB

BUCK7_LX0

BUCK7_FB

BUCK8_LX0

BUCK8_FB

BUCK9_LX0

BUCK9_FB

U2700

D2422B0

WLCSP

SYM 2 OF 5

ROOM=PMU

CRITICAL

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK0_FB

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK1_LX3

BUCK1_FB

BUCK2_LX0

BUCK2_LX1

L17
L18

N16
N17
N18

R16
R17
R18

U16
U17
U18

R13

BUCK0_FB

A15
B15

A13
B13
C13

A11
B11
C11

A9

NC

B9

NC

C9

NC

F15

BUCK1_FB

V5
W5
Y5

V7
W7
Y7

BUCK0_LX0

BUCK0_LX1

BUCK0_LX2

BUCK0_LX3

BUCK1_LX0

BUCK1_LX1

BUCK1_LX2

BUCK2_LX0

BUCK2_LX1

CRITICAL

L2700

1UH-20%-3.2A-0.06OHM

21

PIWA20160H-SM

ROOM=PMU

CRITICAL

L2701

0.47UH-20%-3.3A-0.053OHM

21

PIWA2012FE-SM

ROOM=PMU

CRITICAL

L2702

0.1UH-20%-6.1A-0.031OHM

21

PINA1608-SM

ROOM=PMU

CRITICAL

L2703

0.1UH-20%-6.1A-0.031OHM

21

PINA1608-SM

ROOM=PMU

13

IN

CRITICAL

L2710

1UH-20%-3.6A-0.062OHM

21

0806

ROOM=PMU

L2711

0.47UH-20%-4A-0.048OHM

21

PIWA20120H-SM

ROOM=PMU

CRITICAL

CRITICAL

L2712

0.1UH-20%-7.2A-0.018OHM

21

PINA2012-SM

ROOM=PMU

13

IN

CRITICAL

L2720

1UH-20%-3.2A-0.06OHM

21

PIWA20160H-SM

ROOM=PMU

CRITICAL

L2721

0.47UH-20%-3.3A-0.053OHM

21

PIWA2012FE-SM

ROOM=PMU

3 245

1

C2700

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2710

220PF 26UF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2720

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2701

26UF

2

ROOM=PMU

1

C2706

26UF

2

ROOM=PMU

1

C2711

2

ROOM=PMU

1

C2716

26UF

2

ROOM=PMU

1

2

20%
4V
X5R
0402-0.1MM

20%
4V
X5R
0402-0.1MM

20%
4V
X5R
0402-0.1MM

20%
4V
X5R
0402-0.1MM

C2721

26UF

20%
4V
X5R
0402-0.1MM

ROOM=PMU

1

C2702

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2712

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2722

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2703

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2713

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2723

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2704

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2714

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2724

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

(Place in TTS)

1

C2705

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2715

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

0.625V - 1.06V

PP_CPU_PCORE

0.67V - 0.92V

1.03V for overdrive only

PP_GPU

0.67V/0.80V

PP_SOC_S1

13

1

13 4

13 4

13.8A MAX

BUCK0

13.8A MAX 4.9A MAX

BUCK1

BUCK2

D

C

B

A

BUCK2_FB

BUCK3_LX0

BUCK3_FB

VBUCK3_SW

BUCK3_SW1

SWITCH OUTPUTS

BUCK3_SW2
BUCK3_SW3

T7

BUCK2_FB

F1
F2

G4

C1
C2

A2
B1
B2

D1
D2

BUCK3_LX0

BUCK3_FB

13

IN

L2730

1UH-20%-2.4A-0.06OHM

21

PIWA2016FE-SM

ROOM=PMU

OMIT

XW2730

SHORT-20L-0.05MM-SM

21

ROOM=PMU

PP1V8_TOUCH_RACER_S2

PP1V8_IO

PP1V8_IMU_S2

1

C2730

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

43 35 34

50 42

49 26 25

1

C2731

15UF

20%

6.3V

2

X5R
0402-0.1MM-1

ROOM=PMU

32 30 29 28 27 16 14 10 8 7 6 5

1

C2732

15UF

20%

6.3V

2

X5R
0402-0.1MM-1

ROOM=PMU

SYNC_MASTER=test_mlb

PAGE TITLE

SYSTEM POWER: PMU Bucks (1/4)

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PP1V8_S2

50 49 48

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

27 OF 80

SHEET

17 OF 51

47 46 38 22 20 14 12 10

1.7A MAX

BUCK3

SYNC_DATE=10/13/2016

SIZE

A

D

8

67

35 4

2

1

678

3 245

1

D

C

45 43 42 41 34 31 27 23 21 19

50 46

PP_VDD_MAIN

1

C2854

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2859

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2850

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

1

C2855

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2860

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2851

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

1

C2856

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2861

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

19

IN

1

C2852

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

1

C2857

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2862

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

VDD_MAIN_SNS

1

C2858

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2863

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

P7

VDD_MAIN_SNS

E5

VDD_MAIN_1

K5

VDD_MAIN_2

R7

VDD_MAIN_3

U14

VDD_MAIN_4

L14

VDD_MAIN_5

F14

VDD_MAIN_6

M15
M16
M17
M18

T15
T16
T17
T18

A14

B14
C14
D14

VDD_BUCK0_01

VDD_BUCK0_23

VDD_BUCK1_01

U2700

D2422B0

WLCSP

SYM 3 OF 5

ROOM=PMU

BAT/USBBUCK INPUT

BUCK10_LX0

BUCK10_FB

BUCK11_LX0

BUCK11_LX1

A4
B4

E4

G17
G18

J17
J18

BUCK10_LX

BUCK10_FB

BUCK11_LX0

BUCK11_LX1

CRITICAL

L2800

1UH-20%-2.1A-0.1OHM

21

PIWA2012FE-SM

ROOM=PMU

OMIT

XW2800

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

CRITICAL

L2810

1UH-20%-3.2A-0.06OHM

21

PIWA20160H-SM

ROOM=PMU

CRITICAL

L2811

0.47UH-20%-4A-0.048OHM

21

PIWA20120H-SM

ROOM=PMU

1

C2800

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2810

220PF

5%
10V

2

C0G-CERM
01005

ROOM=PMU

1

C2801

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2811

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2802

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2812

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

1

C2813

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=PMU

PP0V6_VDDQL_S1

PP_CPU_ECORE

14

13

BUCK10

BUCK11

3.0A MAX1.2A MAX

D

C

1

C2864

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2865

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

1

C2866

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=PMU

A10

B10
C10
D10

V6

W6

Y6

E1
E2

V10

W10

Y10

V2

W2

Y2

VDD_BUCK1_23

VDD_BUCK2

VDD_BUCK3

VDD_BUCK4

VDD_BUCK5

BUCK11_FB

J15

BUCK11_FB

IN

20 13

B

J1
J2

Y15

Y16

Y17

B18
C18

A7
B7

A3
B3

H17
H18

VDD_BUCK6

B

VDD_BUCK7

VDD_BUCK8

VDD_BUCK9

VDD_BUCK10

VDD_BUCK11

A

8

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SYSTEM POWER: PMU Bucks (2/4)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

28 OF 80

SHEET

18 OF 51

1

SIZE

D

678

3 245

1

D

43 42 41 34 31 27 23 21 19 18

18

20

20

VDD_MAIN_SNS

OUT

PMU_PRE_UVLO_DET

OUT

50 38 34 27 21 19

OUT

50 46 45

PMU_LDO5_UVLO_DET

PP_VDD_MAIN

XW2990

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

XW2991

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

PP_VDD_BOOST

XW2995

SHORT-20L-0.05MM-SM

2 1

ROOM=PMU

OMIT

OMIT

OMIT

1

C2990

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

OMIT_TABLE

1

C2970

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C2991

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

OMIT_TABLE

1

C2971

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=CAM_PMU

1

C2992

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=PMU

D

C

B

A

A1
A12
A16
A18

A5

A8
B12
B16

B5

B8

C12
C15
C16
C17

C3

C4

C5

C6

C7

C8

D11
D12
D13
D15
D16
D17
D18

D8

D9
E11
E12
E13
E18

E3
F16
F17
F18

F3
F5

G1

G15
G16

G2

G3

G5
H16

H3

H5

J13
J14
J16

J5
K14
K16

U2700

D2422B0

WLCSP

SYM 5 OF 5

ROOM=PMU

VSS VSS

K17
K18
L16
L6
M7
M11
N7
N15
N8
N9
P10
P11
P15
P16
P17
P18
P8
P9
R15
R8
T3
T5
T6
T9
U10
U11
U12
U15
U3
U4
U5
U6
U7
U8
U9
V12
V15
V16
V17
V18
V4
V8
N12
W12
W15
W4
W8
Y1
Y12
Y13
Y14
Y18
Y4
Y8

43 42 41 34 31 27 23 21 19 18

50 38 34 27 21 19

50 46 45

42 17 14

27 17

19

PMU_VSS_RTC

PP_VDD_MAIN
PP_VDD_BOOST

PP1V1_S2

OMIT_TABLE

C2980

2.2UF

X5R-CERM

ROOM=PMU

PP1V25_S2

PP2V5_LDO0_S2

20

20%

6.3V
0201

1

2

OMIT_TABLE

C2981

2.2UF

6.3V

X5R-CERM

0201

ROOM=PMU

20%

U2700

D2422B0

WLCSP

K4

VDD_LDO0

N4

VDD_LDO1

M4

VDD_LDO2

R5

VDD_LDO3

N1

1

2

VDD_LDO4

V1

VDD_LDO5

W1

VDD_LDO5

L1

VDD_LDO6

K1

VDD_BYPASS

M1

VDD_LDO7

R2

VDD_LDO8

M6

VDD_LDO9

R6

VDD_LDO10

R4

VDD_LDO11

L4

VDD_LDO12

R3

VDD_LDO13

T1

VDD_LDO14

M5

VDD_VBUF

J4

VCC_LDOG

E14

VPP_OTP

SYM 1 OF 5

ROOM=PMU

LDO INPUT

LDO

VLDO0
VLDO1
VLDO2
VLDO3
VLDO4
VLDO5

VLDO6

VBYPASS

VLDO7
VLDO8
VLDO9

VLDO10
VLDO11
VLDO12
VLDO13
VLDO14

K3
N3
M3
P5
N2
U1

L2
K2
M2

P2
N6

P6
P4
L3
P3
T2

NC

PP2V5_LDO0_S2

PP3V3_USB

19

6

PP1V8_AUDIO_VA_S2

PP3V0_CONVOY

PP0V7_VDD_LOW_S2

PP3V0_NAND

13

16

PP_ACC_VAR

PP3V0_S2

PP0V9_NAND

16

PP1V8_ALWAYS

PP3V0_DISPLAY

43

PP1V2_SOC

PP1V2_CODEC_S2

PP1V0_DISPLAY_DVDD

38

43

LDO1

50 41 38

LDO2
LDO3
LDO4
LDO5

48 46

50 48 47 45 36

LDO6

LDO7
LDO8

23 20

LDO9

LDO10

14 13 9 7

LDO11
LDO12
LDO13
LDO14

C

B

NC

T14

TP_DET

VBUF_1V2

VPUMP

N5

D3

PMU_VPUMP

1

C2920

47NF

20%

6.3V

2

X5R-CERM
01005

ROOM=PMU

VPUMP: 10nF min. @4.6V

1

2

OMIT_TABLE

1

C2900

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

OMIT_TABLE

C2901

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=PMU

1

C2906

2

OMIT_TABLE

1

C2903

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

OMIT_TABLE

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=PMU

1

C2909

2

OMIT_TABLE

1

C2907

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

1.0UF

20%

6.3V
X5R
0201-1

ROOM=PMU

1

2

OMIT_TABLE

1

C2910

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

OMIT_TABLE

C2911

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=PMU

OMIT_TABLE

1

C2913

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

OMIT_TABLE

1

C2914

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=PMU

SYNC_MASTER=test_mlb

PAGE TITLE

PP1V2_LPADC

1

C2915

0.22UF

20%

6.3V

2

X5R
01005-1

ROOM=PMU

14

VBUF_1V2

SYNC_DATE=10/13/2016

A

SYSTEM POWER: PMU LDOs (3/4)

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

29 OF 80

SHEET

19 OF 51

8

67

35 4

2

1

678

3 245

1

D

C

B

Ansel AMUX

1

C3071

1000PF

10%
10V

2

X5R
01005

ROOM=PMU

CAMPMU_TO_PMU_AMUX

28 20

COLD_RESET & SYSTEM_ALIVE

1

R3061

100K

5%
1/32W
MF
01005

2

ROOM=PMU

PP1V8_S2

50

1

R3062

100K

5%
1/32W
MF
01005

2

ROOM=PMU

SYSTEM_ALIVE

PMU_TO_SYSTEM_COLD_RESET_L

49 48 47 46 38 22 17 14 12 10

23 20 16 14

20 6

NTCs

FOREHEAD NTC

1

5%

16V

5%

16V

5%

16V

1

2

R3041

10KOHM-1%

01005

ROOM=PMU

2

FOREHEAD_NTC_RETURN

REAR CAMERA NTC

1

1

R3042

10KOHM-1%

2

01005

ROOM=PMU

2

RADIO PA NTC on MLB Bottom

AP NTC

1

1

2

R3044

10KOHM-1%

01005

ROOM=PMU

2

REAR_CAMERA_NTC
RCAM_NTC_RETURN

C3041

100PF

NP0-C0G

01005

ROOM=PMU

C3042

100PF

NP0-C0G

01005

ROOM=PMU

C3044

100PF

NP0-C0G

01005

ROOM=PMU

23 20 16 14

FOREHEAD_NTC

AP_NTC

AP_NTC_RETURN

SYSTEM_ALIVE

OUT

OMIT

XW3041

SHORT-20L-0.05MM-SM

21

ROOM=PMU

OMIT

XW3042

SHORT-20L-0.05MM-SM

21

ROOM=PMU

23 20 19

PP1V8_ALWAYS

OMIT

XW3044

SHORT-20L-0.05MM-SM

21

ROOM=PMU

1

C3020

100PF

5%
16V

2

NP0-C0G
01005

ROOM=PMU

1

R3020

3.92K

0.1%
1/20W
MF
0201

2

ROOM=PMU

R3001

0.00

1/32W
01005

0%
MF

21

ROOM=PMU

R3000

100

1/32W
01005

ROOM=PMU

50

OUT

PP1V8_ALWAYS_XO

1

2

21

1%
MF

1

R3011

200K

1%
1/32W
MF
01005

2

ROOM=PMU

C3002

0.1UF

20%

6.3V
X5R-CERM
01005

ROOM=PMU

NC

6

48

6 4

20 6

48 6 4

12

50

50 28 21 12 8

10

12

49 46 10

49 46 10

10

10 4

6

28 20

48 20

46

11

43

50

34 8 4

6 4

50

3

VDD

Y3000

32.768KHZ-10PPM

CSP

1

NC

CLKOUT

CRITICAL

ROOM=PMU

GND

4

AP_TO_PMU_WDOG_RESET

IN

HYDRA_TO_PMU_HOST_RESET

IN

AP_TO_PMU_SOCHOT_L

IN

PMU_TO_SYSTEM_COLD_RESET_L

OUT

PMU_TO_AP_HYDRA_ACTIVE_READY

OUT

PMU_TO_AOP_CLK32K

OUT

PMU_TO_TOUCH_CLK32K_RESET_L

OUT

SYSTEM_ALIVE_R

AP_TO_MANY_BSYNC

IN

PMU_TO_SEP_DOUBLE_CLICK_DET

OUT

PMU_TO_AOP_IRQ_L

OUT

I2C0_AP_SCL

IN

I2C0_AP_SDA

BI

SPMI_PMGR_TO_PMU_SCLK

IN

SPMI_PMU_BI_PMGR_SDATA

OUT

AP_TO_PMU_AMUX_OUT

IN

CAMPMU_TO_PMU_AMUX

IN

HYDRA_TO_PMU_USB_BRICK_ID

IN

ACC_BUCK_TO_PMU_AMUX

IN

PMU_AMUX_AY
ACORN_TO_PMU_ADC

42 20

AP_TO_PMU_AMUX_SYNC

IN

DISPLAY_TO_PMU_AMUX

IN

TOUCH_TO_AMUX_PP1V8

IN

PMU_TO_WLAN_CLK32K

50 20

RIGEL_TO_ISP_INT

IN

AP_TO_PMU_TEST_CLKOUT

IN

PMU_AMUX_BY

OUT

FOREHEAD_NTC

20

REAR_CAMERA_NTC

20

RADIO_PA_NTC

50

AP_NTC

20

CHARGER_NTC

20

PMU_TCAL

2

1

C3030

0.22UF

20%

6.3V

2

X5R
0201

ROOM=PMU

20 19

PMU_VSS_RTC
TCXO_PMU_32K

PMU_VDD_RTC
PMU_VDD_REF

1

C3031

1UF

20%

6.3V

2

X5R
0201

ROOM=PMU

NC

NC

NC
NC

NC

NC

P13

RESET_IN1

P12

RESET_IN2

N13

RESET_IN3

R12

RESET*

H15

SHDN

M12

ACTIVE_RDY

G6

SLEEP_32K

H6

OUT_32K

K13

SYS_ALIVE

M13

FORCE_SYNC

L12

DBL_CLICK_DET

N14

IRQ*

M8

SCL

L8

SDA

K7

SCLK

L7

SDATA

D4

AMUX_A0

D5

AMUX_A1

D6

AMUX_A2

D7

AMUX_A3

F9

AMUX_A4

F10

AMUX_A5

E6

AMUX_A6

E7

AMUX_A7

E8

AMUX_AY

F6

AMUX_B0

G7

AMUX_B1

G8

AMUX_B2

F7

AMUX_B3

E9

AMUX_B4

E10

AMUX_B5

F8

AMUX_B6

H7

AMUX_B7

H8

AMUX_BY

T12

TDEV1

T13

TDEV2

U13

TDEV3

V13

TDEV4

W13

TDEV5

V14

TCAL

R1

XTAL1

P1

XTAL2

L5

VDD_RTC

J3

VDD_REF

CRITICAL

U2700

D2422B0

WLCSP

SYM 4 OF 5

ROOM=PMU

REFSBUTTONS

COMPARATOR

ADC

AMUX

NTC RESETS

GPIO

XTAL

IREF

VREF

PRE_UVLO

VDROOP0
VDROOP1

VDROOP11

VDROOP0_DET
VDROOP1_DET

VDROOP11_DET
PRE_UVLO_DET

LDO5_UVLO_DET

IBAT

VBAT
BRICK_ID1
BRICK_ID2

ADC_IN

BUTTON1
BUTTON2
BUTTON3
BUTTON4

BUTTONO1
BUTTONO2
BUTTONO3

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
GPIO25

FAULT_OUT*

R10

R9

M14

P14
E16
L15

R14
E15
K15

L13
U2

T11
T10
N11
N10
R11

G14
H14
F13
G13

K6
J7
J6

F11
F12
G9
G10
G11
G12
H9
H10
H11
H12
J8
J9
J10
J11
J12
K8
K9
K10
K11
K12
L9
L10
L11
M9
M10

H13

NC
NC

NC

NC

NC
NC

NC

NC

PMU_IREF

PMU_VREF

PMU_TO_AP_BUTTON_POWER_KEY_L

R3010

200K

1/20W

ROOM=PMU

1%
MF

201

21

C3010

0.22UF

21

20%

6.3V
X5R

0201

ROOM=PMU

PMU_TO_AP_PRE_UVLO_L

PMU_TO_AP_THROTTLE_PCORE_L

PMU_TO_AP_THROTTLE_GPU0_L

PMU_TO_AP_THROTTLE_ECORE_L

AP_CPU_PCORE_SENSE

AP_VDD_GPU_SENSE

BUCK11_FB

PMU_PRE_UVLO_DET

PMU_LDO5_UVLO_DET

HYDRA_TO_PMU_USB_BRICK_ID

ACORN_TO_PMU_ADC

BUTTON_VOL_DOWN_L

BUTTON_POWER_KEY_L

BUTTON_VOL_UP_L
BUTTON_RINGER_A

PMU_TO_AP_BUTTON_VOL_DOWN_L

PMU_TO_AP_BUTTON_VOL_UP_L

PMU_TO_NFC_EN_R

PMU_TO_AP_THROTTLE_GPU1_L

TIGRIS_TO_PMU_INT_L

WLAN_TO_PMU_HOST_WAKE

NFC_TO_PMU_HOST_WAKE

PMU_TO_GNSS_EN_R

PMU_TO_WLAN_CLK32K

PMU_TO_BT_REG_ON

BT_TO_PMU_HOST_WAKE

CODEC_TO_PMU_WAKE

PMU_TO_WLAN_REG_ON

PMU_TO_BB_USB_VBUS_DETECT

PMU_TO_AP_FORCE_DFU_R

PMU_TO_CCG2_RESET_L

PMU_TO_BBPMU_RESET_R_L

PMU_TO_NAND_LOW_BATT_BOOT_L

BB_TO_PMU_PCIE_HOST_WAKE_L

PMU_TO_IKTARA_EN_EXT_1P8V

PMU_TO_BOOST_EN

PMU_TO_DISPLAY_PANICB

PMU_TO_IKTARA_RESET_L

OUT

OUT
OUT
OUT

IN
IN
IN

IN
IN

IN

IN

IN

IN
IN

OUT
OUT
OUT

OUT

IN
IN
IN

OUT
OUT

IN
IN

OUT
OUT

OUT

OUT

IN
OUT
OUT
OUT

OUT

6

6

6

19

19

25

25

25

11

11

11

6

23

50

50

50

50

38

50

50

47

16

50

50

21

43

50

D

11 6 4

13 4

13 4

18 13

C

48 20

1

R3074

42 20

31.6K

1%
1/32W
MF
01005

2

ROOM=PMU

R3073

100

5%

1/32W

MF

01005

ROOM=PMU

R3072

100

50 20

5%

1/32W

MF

01005

ROOM=PMU

R3071

20.0K

5%

1/32W

MF

01005

ROOM=PMU

R3070

1.00K

5%

1/32W

MF

01005

ROOM=PMU

PP1V8_ALWAYS

NOSTUFF

21

21

21

21

PMU_HYDRA_TO_AP_FORCE_DFU

23 20 19

PMU_TO_NFC_EN

PMU_TO_GNSS_EN

PMU_TO_BBPMU_RESET_L

OUT

OUT

OUT

33

IN

50

50

B

50

50

48 11

BI

A

CHARGER NTC

1

I609

R3045

10KOHM-1%

01005

ROOM=PMU

2

CHARGER_NTC

CHARGER_NTC_RETURN

C3045

100PF

5%

16V

NP0-C0G

01005

ROOM=PMU

1

2

NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC

8

OMIT

XW3045

SHORT-20L-0.05MM-SM

21

ROOM=PMU

PMU_VSS_RTC

20 19

A

SYNC_DATE=11/01/2016

SIZE

D

1

ROOM=PMU

SHORT-20L-0.05MM-SM

XW3000

2

OMIT

SYNC_MASTER=test_mlb

PAGE TITLE

SYSTEM POWER: PMU (4/4)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

30 OF 80

SHEET

20 OF 51

1

678

3 245

1

D

Boost Enable Pull

PMU_TO_BOOST_EN

21 20

1

R3100

511K

1%
1/32W
MF
01005

2

ROOM=BOOST

D

C

50 47 23 22 10

45 43 42 41 34 31 27 23 19 18

50 46

PP_VDD_MAIN

1

C3190

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

ROOM=BOOST

L3100

0.47UH-20%-4A-0.048OHM

PIWA20120H-SM

2

SYS_BOOST_LX

21 20

R3110

I2C0_SMC_SDA I2C0_SMC_SDA_BOOST

BI

39.2

1/32W
01005

ROOM=BOOST

21

1%
MF

50 47 23 22 10

PMU_TO_BOOST_EN

IN

I2C0_SMC_SCL

IN

BOOST

353S01124

A3

VIN

A4
C3

C4
A1
B2
C2
B1
C1

VIN

SW
SW

EN
SCL
SDA
VSEL
BYP*

U3100

SN61280E

CSP

ROOM=BOOST

CRITICAL

VOUT
VOUT

B3
B4

1

C3110

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

C3111

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

C3112

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

C3113

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

C3114

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=BOOST

1

C3115

220PF

5%
10V

2

C0G-CERM
01005

ROOM=BOOST

When VDD_MAIN < 3.4, boosts to 3.4
Otherwise tracks VDD_MAIN

PP_VDD_BOOST

50 38 34 27 19

C

B

50 28 20 12 8

AP_TO_MANY_BSYNC

IN

A2

GPIO

PGND

D3

D2

D4

AGND

D1

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SYSTEM POWER: Boost

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

31 OF 80

SHEET

21 OF 51

1

SIZE

D

678

3 245

1

D

C

23

VBATT_SENSE

OUT

BATTERY CONNECTOR

Rcpt: 516S00232
Plug: 516S00233

XW3200

SHORT-20L-0.05MM-SM

2 1

ROOM=B2B_BATTERY

PLACE_NEAR=J3200:2mm

NO_XNET_CONNECTION=1

<-- This one on MLB

J3200

B2B-BATT-RCPT

F-ST-SM

9

65

I2C0_SMC_BI_GG_SDA_CONN

CKPLUS_WAIVE=I2C_PULLUP

Gas gauge I2C level translator

Q3200

RV1C002UN

ROOM=B2B_BATTERY

CRITICAL

SM

SYM_VER_1

G

1

S

2

D

3

I2C0_SMC_BI_GG_SDA

1

C3202

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BATTERY

R3202

33

21

5%

1/32W

MF

01005

ROOM=B2B_BATTERY

I2C0_SMC_SDA

D

BI

50 47 23 21 10

C

50 23

PP_BATT_VCC

1

C3292

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BATTERY

1

C3293

330PF

10%
16V

2

CER-X7R
01005

ROOM=B2B_BATTERY

1

C3294

220PF

10%
10V

2

X7R-CERM
01005

ROOM=B2B_BATTERY

1
2

10

ROOM=B2B_BATTERY

3
4

87

1

G

PP1V8_S2

50

49 48 47 46 38 20 17 14 12 10

R3201

I2C0_SMC_TO_GG_SCL_CONN

CKPLUS_WAIVE=I2C_PULLUP

3

D

Q3201

RV1C002UN

SM

ROOM=B2B_BATTERY

CRITICAL

S

SYM_VER_1

2

I2C0_SMC_TO_GG_SCL

1

C3201

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_BATTERY

33

2 1

5%

1/32W

MF

01005

ROOM=B2B_BATTERY

I2C0_SMC_SCL

IN

50 47 23 21 10

B

B

A

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SYSTEM POWER: B2B Battery

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

32 OF 80

SHEET

22 OF 51

1

SIZE

D

TIGRIS2 CHARGER

678

3 245

1

D

TIGRIS_PMID1

DZ3300

BZT52C20LP

DFN10062

K

R3316

A

ROOM=CHARGER

50K

1%

1/32W

MF

01005

1

2

C3316

20%
25V
X5R

0402

ROOM=CHARGER

1

C3317

2

ROOM=CHARGER

D

PP_VDD_MAIN

50 46

1

C3390

18UF

20%

1

C3310

1

4.7UF4.7UF

20%
25V

2

X5R

0402

4.7UF

20%
25V

2

CER-X5R
0402

ROOM=CHARGER

1

C3311

4.7UF

20%
25V

2

CER-X5R
0402

ROOM=CHARGER

1

C3312

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3313

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3314

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3315

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

1

C3391

18UF

20%

6.3V

2

CER-X5R
0402-0.1MM

ROOM=CHARGER

45 43 42 41 34 31 27 21 19 18

C

B

TIGRIS_PMID2

PP1V8_ALWAYS

20 19

20

6

TIGRIS_TO_PMU_INT_L

OUT

USB_VBUS_DETECT

OUT

1

2

PP_VBUS1_E75

49

PP_VBUS2_IKTARA

50

1

R3330

100K

5%
1/32W
MF
01005

2

ROOM=CHARGER

C3320

4.7UF

20%
25V
CER-X5R
0402

ROOM=CHARGER

R3331

100

1%

1/32W

MF

01005

ROOM=CHARGER

R3332

30.1K

1%

1/32W

MF

01005

ROOM=CHARGER

1

C3301

1UF

10%
25V

2

X5R
402

ROOM=CHARGER

1

C3305

1UF

10%
25V

2

X5R
402

ROOM=CHARGER

50 47 22 21 10

50 47 22 21 10

21

21

1

C3322

220PF

5%
25V

2

COG
01005

1

C3302

220PF

5%
25V

2

COG
01005

1

C3306

220PF

5%
25V

2

COG
01005

20 16 14

48 4

1

C3323

220PF

5%
25V

2

COG

ROOM=CHARGER

ROOM=CHARGER

ROOM=CHARGER

I2C0_SMC_SDA

BI

I2C0_SMC_SCL

IN

SYSTEM_ALIVE

IN

HYDRA_TO_TIGRIS_VBUS1_VALID_L

IN

01005

ROOM=CHARGER

1

C3303

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3307

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3324

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3304

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

C3308

220PF

5%
25V

2

COG
01005

ROOM=CHARGER

1

2

TIGRIS_TO_PMU_INT_R_L
TIGRIS_VBUS_DETECT

23

BATTERY_NTC

C3325

220PF

5%
25V
COG
01005

ROOM=CHARGER

F2

E2

D2

C2

B2

A2

VDD_MAIN

VDD_MAIN

VDD_MAIN

VDD_MAIN

VDD_MAIN

A6

PMID1

B6

PMID1

C6

PMID1

D6

PMID1

E6

PMID1

F6

PMID2

G6

PMID2

H6

PMID2

A5

VBUS1

B5

VBUS1

C5

VBUS1

D5

VBUS1

E5

VBUS1

F5

VBUS2

G5

VBUS2

H5

VBUS2

F3

SDA

G2

SCL

F4

SYS_ALIVE

B4

VBUS1_VALID*

B3

VBUS2_VALID*

E3

INT*

C4

VBUS1_DET

D4

TEST

E4 H2

NTC

A8

U3300

SN2500A1YEWR

WCSP

ROOM=CHARGER

CRITICAL

GND

F8

E8

D8

C8

VDD_MAIN5

ACT_DIODE

HDQ_HOST

HDQ_GAUGE

AGND

H8

G8

LDO

BOOT

BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW
BUCK_SW

BATT
BATT
BATT
BATT
BATT

BATT_SNS

AUX1

NC0
NC1
NC2
NC3

B8

H3
H4
A7

B7
C7
D7
E7
F7
G7
H7

A1
B1
C1
D1
E1

F1
A3

G3
G4

A4

D3

G1
H1

TIGRIS_BOOT

NO_XNET_CONNECTION

TIGRIS_LX

TIGRIS_ACTIVE_DIODE

PP_VBUS1_E75_RVP_R

TIGRIS_LDO

1

C3360

220PF

10%
10V

2

X7R-CERM
01005

ROOM=CHARGER

C3340

0.047UF

21

10%
25V
X5R

0201

ROOM=CHARGER

VBATT_SENSE

1

C3361

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=CHARGER

L3340

0.47UH-6.8A-0.046OHM

3225

ROOM=CHARGER

22

IN

R3360

10

2 1

5%

1/32W

MF

01005

ROOM=CHARGER

TIGRIS_LX_MID

21

PP_VBUS1_E75_RVP

CRITICALCRITICAL

L3341

0.47UH-6.8A-0.046OHM

21

3225

ROOM=CHARGER

48 47 45

C3341

220PF

C0G-CERM

01005

ROOM=CHARGER

5%

10V

1

2

C3342

220PF

C0G-CERM

01005

ROOM=CHARGER

NOSTUFF

R3350

100K

1/32W
01005

ROOM=CHARGER

5%

10V

5%
MF

1

2

1

2

C3343

330PF

10%
16V

CER-X7R

01005

ROOM=CHARGER

C

A2

CRITICAL

S

B3

B2

B1

A3

Q3350

A1

G

D

C3

C2

C1

1

2

CSD68841W

BGA

ROOM=CHARGER

PP_BATT_VCC

50 22

B

1

C3350

330PF

10%
16V

2

CER-X7R
01005

ROOM=CHARGER

1

C3351

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=CHARGER

1

C3352

4UF

20%

6.3V

2

CERM-X5R
0201

ROOM=CHARGER

1

C3353

220PF

5%
10V

2

C0G-CERM
01005

ROOM=CHARGER

A

C3370

100PF

5%

16V

NP0-C0G

01005

ROOM=CHARGER

BATTERY NTC

SYNC_MASTER=test_mlb

PAGE TITLE

1

1

2

I251

R3370

10KOHM-1%

01005

ROOM=CHARGER

2

BATTERY_NTC

23

BATTERY_NTC_RETURN

SHORT-20L-0.05MM-SM

8

OMIT

XW3370

21

ROOM=CHARGER

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

SYSTEM POWER: Charger

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

BRANCH

evt-1

PAGE

33 OF 80

SHEET

23 OF 51

1

SYNC_DATE=10/13/2016

SIZE

A

D

678

3 245

1

D

D

C

C

Iktara Components on MLB Bottom

B

B

A

8

A

PAGE TITLE

SYSTEM POWER: Iktara

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

34 OF 80

SHEET

24 OF 51

1

SIZE

D

678

3 245

1

Cyclone + Button Connnector

D

Cyclone Filtering

IKTARA_COIL2

50

MAKE_BASE=TRUE

1

C3500

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

1

C3501

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

IKTARA_COIL2

25

BUTTON_VOL_DOWN_CONN_L

25

IKTARA_COIL2

25

BUTTON_VOL_UP_CONN_L

25

BUTTON_RINGER_A_CONN

25

IKTARA_COIL1

25

PP1V8_IMU_COMPASS_BTN_CONN

25

Rcpt: 516S00289
Plug: 516S00290

<-- This one on MLB

J3500

AA36D-S04VA1

F-ST-SM

PWR

PWR

ROOM=B2B_BUTTON

109

65

21
43

87

1211

COMPASS_TO_AOP_INT_BTN_CONN

I2C1_AOP_TO_COMPASS_SCL_BTN_CONN

I2C1_AOP_BI_COMPASS_SDA_BTN_CONN

25

25

25

D

C

50

IKTARA_COIL1

MAKE_BASE=TRUE

BUTTONS

20

BUTTON_RINGER_A

OUT

1

C3510

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

C3520

27PF

6.3V

NP0-C0G

0201

ROOM=B2B_BUTTON

5%

1

C3511

220PF

2%
50V

2

C0G
0201

ROOM=B2B_BUTTON

IKTARA_COIL1

25

C

R3520

100

21

1

2

5%

1/32W

MF

01005

ROOM=B2B_BUTTON

1

DZ3520

0201

5.5V-6.2PF

ROOM=B2B_BUTTON

2

BUTTON_RINGER_A_CONN

25

B

20

20

BUTTON_VOL_DOWN_L

OUT

5%

10V

5%

10V

1

2

1

2

BUTTON_VOL_UP_L

OUT

C3530

220PF

C0G-CERM

ROOM=B2B_BUTTON

C3540

220PF

C0G-CERM

ROOM=B2B_BUTTON

01005

01005

Compass (Button Flex Location)

R3530

100

5%

1/32W

MF

01005

ROOM=B2B_BUTTON

R3540

100

5%

1/32W

MF

01005

ROOM=B2B_BUTTON

21

1

DZ3530

12V-33PF

01005-1

ROOM=B2B_BUTTON

2

21

1

DZ3540

12V-33PF

01005-1

2

ROOM=B2B_BUTTON

BUTTON_VOL_DOWN_CONN_L

BUTTON_VOL_UP_CONN_L

25

25

B

A

49 26 17

50 49 41 12 4

50 49 41 12 4

49 12 4

PP1V8_IMU_S2

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

BI

COMPASS_TO_AOP_INT

OUT

FL3550

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=B2B_DOCK

R3551

0.00

2 1

0%

1/32W

MF

01005

ROOM=B2B_DOCK

R3552

0.00

2 1

0%

1/32W

MF

01005

ROOM=B2B_DOCK

FL3553

150OHM-25%-200MA-0.7DCR

2 1

01005

ROOM=B2B_DOCK

1

C3550

220PF

5%
10V

2

C0G-CERM
01005

ROOM=B2B_DOCK

1

C3551

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

1

C3552

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=B2B_DOCK

1

C3553

220PF

5%
10V

2

C0G-CERM
01005

ROOM=B2B_DOCK

PP1V8_IMU_COMPASS_BTN_CONN

I2C1_AOP_TO_COMPASS_SCL_BTN_CONN

CKPLUS_WAIVE=I2C_PULLUP

I2C1_AOP_BI_COMPASS_SDA_BTN_CONN

CKPLUS_WAIVE=I2C_PULLUP

COMPASS_TO_AOP_INT_BTN_CONN

25

25

25

25

PAGE TITLE

SYSTEM POWER: B2B Cyclone + Button

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

35 OF 80

SHEET

25 OF 51

SYNC_DATE=10/13/2016SYNC_MASTER=test_mlb

SIZE

D

A

8

67

35 4

2

1