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ART FILM - pdf_top_assem

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Professional.Repairphone

TOP SIDE AS

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

:

NOTES
AR

TWORK

VIEWED FRO

TO STAN

DAR

080-2265 (FLEXIBLE PRI

062-0073 (MULTI- LAYER

SEMBLY

APPLE

DESIGNER

KEN KIPLINGER

DS AS DEFINED IN APPLE SPECIFICATION

M COMPONENT SIDE. PCB SHALL CONFORM

NTED CIRC

BOARD

UIT BOARD

S) AS APPLICABLE.

DAT

03/31/17

S) OR

TITLE

PCBF, X891

TOP MLB

E

SCAL

E

DRAW

ING NUMBER

1:1

NOTICE OF PRO

THE

PRO
THE
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO RE
(III) NOT TO RE

ART FILM - pdf_top_assem

INFORM

PRI

ETARY

POSSESSOR

820-00863-09

PRI

ATION CONTAINED HEREIN IS THE

PRO

ETARY PROPERTY

PERTY OF APPLE

AGREES TO THE FOLLOWING

PRODUCE OR COPY IT

VEAL OR PUBLISH IT

ART FILM - pdf_bot_assem

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Professional.Repairphone

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PCBF, X891

TOP MLB

820-00863-09

ART FILM - pdf_bot_assem

BOTTOM SIDE ASSEMBLY

TITLE

DRAWING NUMBER

SCALE

DATE

1:1

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE

THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

03/31/17

APPLE

DESIGNER

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

KEN KIPLINGER

NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR

062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.

ART FILM - pdf_top_mate

*

*

*

*

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UTAH

*

ROMEO

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FCAM

JULIET

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https://www.facebook.com/
Professional.Repairphone

TOP SIDE AS

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES :
AR

TWORK

VIEWED FRO

TO STAN

DAR

080-2265 (FLEXIBLE PRI

062-0073 (MULTI- LAYER

SEMBLY

APPLE

DESIGNER

KEN KIPLINGER

DS AS DEFINED IN APPLE SPECIFICATION

M COMPONENT SIDE. PCB SHALL CONFORM

NTED CIRC

BOARD

UIT BOARD

S) AS APPLICABLE.

DAT

03/31/17

S) OR

TITLE

PCBF, X891

TOP MLB

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SCAL

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DRAW

1:1

NOTICE OF PRO

THE

PRO
THE
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO RE
(III) NOT TO RE

ART FILM - pdf_top_mate

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INFORM

PRI

ETARY

POSSESSOR

820-00863-09

PRI

ATION CONTAINED HEREIN IS THE

PRO

ETARY PROPERTY

PERTY OF APPLE

AGREES TO THE FOLLOWING

PRODUCE OR COPY IT

VEAL OR PUBLISH IT

ART FILM - pdf_bot_mate

https://www.facebook.com/
Professional.Repairphone

*

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PCBF, X891

TOP MLB

820-00863-09

ART FILM - pdf_bot_mate

BOTTOM SIDE ASSEMBLY

TITLE

DRAWING NUMBER

SCALE

DATE

1:1

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE

THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

03/31/17

APPLE

DESIGNER

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

KEN KIPLINGER

NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR

062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.

ART FILM - pdf_top_assem

*

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L2012_EL2013_E

L2010_E

L1604_E

*

DSM_HB_E

LNA_GPS_E

L2109_EC2101_E

*

R2103_EC2102_E

L1606_E

L1607_E

R2102_E

R1600_E

L2102_E

*

R1612_E

R1615_E

*

R1613_E

*

C7516_S

C7515_S

C7518_S

R1611_E

R1601_E

R1603_E

*

L1605_E

*

C7533_S

*

L1608_E

C1603_E

R1609_E
C1502_E

C1602_E

C1604_E

C7532_S

XW308_E

C7530_S

NFC_DCDC_S

C7531_S

*

Q7502_SQ7501_S

*

*

C7511_S

*

C7512_S

L7502_S

*

C7521_S

C7522_S

C7514_S

C7520_S

*

R7508_S

*

C7517_S

C7507_S

C7510_S

C7526_S

C7506_S

L7503_S

C7523_S

C7503_S

L7500_S

*

T7500_S

NFC_S

L7501_S

C7505_S

*

C7504_S
C7513_S

R7502_S

C7502_S

C7500_S

R3450

C3456

C3452

C3451

C3453

C3455

C3454

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*

C3403

C3402

C3464

C3465

C3461

C3462

C3463

C3466

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U5530

R3460

C5530

MC_E

R703_E

R700_E

R715_E

C701_E

C519_E

R714_E

C532_E

C502_E

C555_E

C515_E

FD0405

FD0411

C514_E C510_EC552_E
C541_E

C536_E

C517_E

C521_E

*

C603_E

C528_E

R7702_W

C535_E

*

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*

C7709_W

C7711_W

R7711_W

C7708_W

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*

C7705_W

L7704

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R7700_WC7701_W

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W2BPF_W

*

*

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*

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R7703_W

*

C7716_W

R5807

FL5809

C5807

C5809

FL5806

FL5810

C200_E

C5806

C5810

*

FL5800

FL5802

C5800

C5802

R201_E

C203_E

FL5805

FL5895

*

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C5805

C5895

C5844

C5804

DZ203_E

R5844

FL580

4

C5890

R5801

C5845

C5803

R202_E

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FL5803

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R5845

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DZ206_E

C5896

C5850

C5894

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FL5893

FL5894

R2105_E

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L2105_E

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R919_E

*

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R5842

R920_E

FL5891

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C5820

R922_E

C5841

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R2412_E

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C2417_E

C2440_E

*

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C2415_E

GPOLAT_E

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C3416

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C5028

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C5016

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R3420

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*

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C1808_E

C1806_E

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*

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C1812_E

*

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C1318_E

R1807_E

R1809_E

C1811_E

FLPDX_E

*

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*

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FL1201_E

*

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C3440

C3417

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C507_E

R702_E

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C516_E

C512_E
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C513_E

R603_E

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C554_E

C530_E

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R801_EC822_E

U_WTR_E

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C1312_EC3043

*

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*

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C1815_E

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C1802_E

*

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*

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C5025

C5006

C5008

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C3413

C4928

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C4909

*

*

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PA_UHB_E

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*

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L4900

*

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C520_E

C4904

R410_E

*

R889_E

*

*

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C539_E

R409_E

C314_E

C888_E

C544_E

*

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C323_E C4907

*

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R888_E

C4905

C547_E

*

C4932

C307_E

*

C550_E

C328_E

C316_E

C303_E

C306_E

*

C322_E

C553_E

R604_E

C533_E

C302_E

*

R422_E

C504_E

XW301_E

*

R401_E

C549_E

C404_E

R402_E

*

C508_E

L304_E

XW302_E

*

C317_E

C534_E

C305_E

*

C501_E

XW404_E

C526_E

U_PMIC_E

XW403_E

Y401_E

XW401_E

C321_EC326_E

*

*

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*

L303_E

*

C540_E

XW305_E

R412_E

C309_E

XW402_E

R411_E

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C401_E

C403_E

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*

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415_E

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*

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*

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XW3043

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*

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*

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*

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*

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C1322_ER1308_ER1304_E

C1201_E

PA_HB_E

C1206_E

C1317_E

C1316_E

R1207_ER1203_EC1205_E

C1311_E

C1211_E

C1306_E

*

C1302_E

C1323_E

https://www.facebook.com/

TOP SIDE AS

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES :
AR

TWORK

VIEWED FRO

TO STAN

DAR

080-2265 (FLEXIBLE PRI

062-0073 (MULTI- LAYER

SEMBLY

APPLE

DESIGNER

GERA

DS AS DEFINED IN APPLE SPECIFICATION

DAN

ILOV

M COMPONENT SIDE. PCB SHALL CONFORM

NTED CIRC

BOARD

UIT BOARD

S) AS APPLICABLE.

Professional.Repairphone

DAT

04/05/17

S) OR

TITLE

E

SCAL

E

DRAW

ING NUMBER

1:1

NOTICE OF PRO

THE

INFORM

PRO

PRI

ETARY

THE

POSSESSOR
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO RE
(III) NOT TO RE

ART FILM - pdf_top_assem

PCBF, X891

BOTTOM MLB

820-00864-06

PRI

ATION CONTAINED HEREIN IS THE

PRO

ETARY PROPERTY

PERTY OF APPLE

AGREES TO THE FOLLOWING

PRODUCE OR COPY IT

VEAL OR PUBLISH IT

ART FILM - pdf_bot_assem

FD0403

FD0413

PP42_E

PP90_E

PP43_E

TP0790

PP39_E

PP37_E

PP7508_S

PP7514_S

PP7511_S

PP7503_S

PP7510_S

PP7505_S

PP7507_S

PP7504_S

P402_E

PP7506_S

PP7512_S

PP7513_S

PP7509_S

PP0700

PP5_E

PP6_E

PP0704

PP7628_W

PP7629_W

TP7505_S

TP7506_S

PP0702

TP0720

PP0703

TP0721

FD0402

FD0414

PP0701

PP101_E

PP106_E

PP95_E

PP99_E

PP58_E

PP88_E

PP100_E

PP104_E

PP87_E

PP98_E

PP28_E

PP32_E

PP57_E

PP31_E

PP26

_E

PP22_E

P601_E PP29_E

PP702_E

PP25_E

PP96_E

PP110_E

PP41_EPP40_E

PP27_E

PP113_E

PP24_E

PP38_E

PP44_E

P501_E

PP77_E

PP18_E

PP20_E

PP94_E

PP93_E

PP36_E

PP108_E

PP111_E

PP46_E

PP112_E

PP45_E

PP109_E

PP85_E

PP81_E

PP50_E

PP30_E

PP48_E

PP23_E

PP47_E

TP0708
PP7622_W

PP7620_W

PP7623_W
PP9

2_E

PP7621_W

TP0713

PP701_E

PP7626_W

PP7607_W

PP7600_W

PP

PP761

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PP 76

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PP

PP7610_W

PP
TP0709

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PP7619_W

PP7613_W

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71 4 TP0715

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TP0751

TP0755

TP0750

PP107_E

PP117_E

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PP82_E

PP55_E

PP54_E

PP56_E

PP78_E

PP53_E

PP80_E

PP127_E
PP12

9_E

PP1301_E

PP1300_E

PP116_E

PP126_E

PP

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8_E

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TP0730

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PP2_E

PP1_E

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TP0731

PP4_E

PP49_E

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PP3_E

P804

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PP51_E

P803_EPP52_E

*

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PP13_E

PP14_E

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J_DEBUG_E

PP7609_W

PP7630_W

PP7617_W
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6_W
1_W
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TP0752

TP0764

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TP0754

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TP0707

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TP0766

PP105_E

TP0760

PP1202_E

PP1201_E

TP0762

PP1203_E

TP0759

PP1200_E

PP1100_E

PP35_E

TP0758

TP0756

TP0771

TP0757

TP0772

TP0767

PP1800_E

PP89_E

https://www.facebook.com/
Professional.Repairphone

PCBF, X891

BOTTOM MLB

820-00864-06

TITLE

DRAWING NUMBER

SCALE

1:1

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE

THE POSSESSOR AGREES TO THE FOLLOWING
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

ART FILM - pdf_bot_assem

BOTTOM SIDE ASSEMBLY

APPLE

DATE

04/05/17

DESIGNER

GERA DANILOV

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR

062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.

ART FILM - pdf_top_mate

*

*

*

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*

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*

*

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*

*

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R

*

*

*

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HB DSM

GPS

*

*

*

*

*

*

*

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*

*

*

*

*

*

*

D

C

­D

*

C

NFC

*

*

*

*

BASE

VINYL

*

*

*

*

*

*

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*

*

*

*

*

*

*

ORB/TOUCH

*

*

COUPLE

J-LAT

*

*

*

LAT-DI

*

*

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SPK

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* *

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*

*

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*

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*

TOP SIDE AS

THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED

ORIG DIV

NOTES :
AR

TWORK

VIEWED FRO

TO STAN

DAR

080-2265 (FLEXIBLE PRI

062-0073 (MULTI- LAYER

SEMBLY

APPLE

DESIGNER

GERA

DS AS DEFINED IN APPLE SPECIFICATION

DAN

ILOV

M COMPONENT SIDE. PCB SHALL CONFORM

NTED CIRC

BOARD

https://www.facebook.com/
Professional.Repairphone

UIT BOARD

S) AS APPLICABLE.

DAT

04/05/17

S) OR

TITLE

PCBF, X891

BOTTOM MLB

E

SCAL

E

DRAW

1:1

NOTICE OF PRO

THE

PRO
THE
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO RE
(III) NOT TO RE

ART FILM - pdf_top_mate

ING NUMBER

INFORM

PRI

ETARY

POSSESSOR

820-00864-06

PRI

ATION CONTAINED HEREIN IS THE

PRO

ETARY PROPERTY

PERTY OF APPLE

AGREES TO THE FOLLOWING

PRODUCE OR COPY IT

VEAL OR PUBLISH IT

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

6543

X891/X893 MLB Top: EVT

LAST_MODIFICATION=Mon Apr 3 13:03:06 2017

2 1

ECNREV DESCRIPTION OF REVISION

CK
APPD

DATE

2017-04-0500084097609 ENGINEERING RELEASED

D

1
2
3
4
5
6
7
8
9
10
11
12

1
2
4
5
6
10
11
12
13
14
15
16

TABLE OF CONTENTS
SYSTEM:BOM Tables
SYSTEM: Mechanical Components
SYSTEM: Testpoints (Top)
BOOTSTRAPPING
SOC: JTAG,USB,XTAL
SOC: PCIE
SOC: MIPI & ISP
SOC: LPDP
SOC: Serial
SOC: GPIO & UART
SOC: AOP

test_mlb

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

10/13/2016

10/13/2016
10/13/2016
10/17/2016
10/17/2016
10/13/2016
10/13/2016
10/17/2016
10/13/2016
10/17/2016

46
47
48
49
50
51

61
62
63
64
65
80

I/O: Accessory Buck
I/O: USB PD
I/O: Hydra
I/O: B2B Dock
I/O: Interposer (Bottom)
RADIOS

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

D

DATESYNCCONTENTSCSAPAGEDATESYNCCONTENTSCSAPAGE

10/17/2016
10/13/2016
10/13/2016
10/13/2016
10/13/2016
06/04/2015

C

13
14
15
16
17
18
19
20
21
22
23
24
25
26

17
18
19
26
27
28
29
30
31
32
33
34
35
36

SOC: Power (1/3)
SOC: Power (2/3)
SOC: Power (3/3)
NAND
SYSTEM POWER: PMU Bucks (1/4)
SYSTEM POWER: PMU Bucks (2/4)
SYSTEM POWER: PMU LDOs (3/4)
SYSTEM POWER: PMU (4/4)
SYSTEM POWER: Boost
SYSTEM POWER: B2B Battery
SYSTEM POWER: Charger
SYSTEM POWER: Iktara
SYSTEM POWER: B2B Cyclone + Button
SENSORS

test_mlb
test_mlb
test_mlb
test_mlb

10/17/2016
10/17/2016
10/17/2016

10/13/2016
test_mlb 10/13/2016
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

test_mlb
test_mlb

10/13/2016

10/13/2016

11/01/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

C

B

27
28
29
30
31
32

34
35
36
37
38
39
40

37
38
39
40
41
42
4333
44
45
46
47 test_mlb
48

CAMERA: PMU (1/2)
CAMERA: PMU (2/2)
CAMERA: B2B Wide (WY)
CAMERA: B2B Tele (MT)
CAMERA: Strobe Drivers
CAMERA: B2B FCAM
CAMERA: B2B Strobe + Hold Button
PEARL: Power
PEARL: B2B Romeo + Juliet
PEARL: B2B Rosaline + Misc
AUDIO: CODEC (1/2)
AUDIO: CODEC (2/2)

test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb
test_mlb

test_mlb

49 AUDIO: Speaker Amp Bottom
50

AUDIO: Speaker Amp Top

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

10/13/2016

B

10/13/2016

10/13/2016

10/13/2016

10/13/2016

08/25/2015

08/25/2015

A

41
42
43
44
45

51
56
57
58
59

ARC: Driver
CG: Power Supplies - Touch & Display
CG: B2B Display
CG: B2B Orb & Touch
I/O: Overvoltage Cut-Off Circuit

BOM:639-04583 (Ultimate)
BOM:639-03409 (Extreme)
MCO:056-04077

1 SCH051-02221 SCH,MLB_TOP,X891 COMMON

820-00863 1 PCB,MLB_TOP,X891

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

NO

BOM OPTIONCRITICAL

COMMONNOPCB

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

test_mlb
test_mlb
test_mlb

sync

10/13/2016

10/13/2016

10/13/2016

08/25/2015

01/10/2017

TABLE OF CONTENTS

DRAWING TITLE

SCH,MLB,TOP,X891

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

1 OF 80

SHEET

1 OF 51

A

SIZEDRAWING NUMBER

D

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

3

124567

678

3 245

1

D

EEEE Codes

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

825-7691

825-7691

1

EEEE FOR (MLB_TOP,639-04583,ULTIMATE)

EEEE FOR (MLB_TOP,639-03409,EXTREME)

1

EEEE_J2WJ

EEEE_HP26

NO

NO

SOC

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

339S00358 CRITICAL1 COMMON

339S00359 DDR-H,3G, B0

SKYE+3GB, B0, M, DEV

PART NUMBER

339S00358

339S00358

339S00358

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

U1000

U1000339S00361 DDR-S-18,3G, B0

U1000

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TABLE_ALT_ITEM

DDR-S-20,3G, B0U1000339S00360

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

ULTIMATE

EXTREME

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

Global Ferrites

TABLE_ALT_HEAD

PART NUMBER

155S0610

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL155S00194

ALL155S0610155S00200

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

FERR BD, 150OHM, TDK

FERR BD, 150OHM, TY

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

155S0610

FERR BD, 150OHM, 01005

Global R/C Alternates

TABLE_ALT_HEAD

PART NUMBER

118S0717

138S0652 ALL138S0648

132S0436 ALL132S0400

138S00049

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL118S0764

ALL138S0706138S0739

ALL138S0831

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

RES, 3.92K, 0.1%, 0201

CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

CAP,CER,X5R,0.22UF,20%,6.3V,20%

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

118S0717

138S0652

138S0706

132S0400

138S0831

RES, 3.92K, 0.1%, 0201

CAP,X5R,4.7UF,6.3V,0.65MM,0402

CAP,CER,X5R,0.22UF,20%,6.3V,20%

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,2.2UF,20%,6.3V,0201

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

Soft-Term Cap Sub BOMs

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

SUBBOM,MLB,TOP,CAP,TYPICAL,X891

1685-00155

SUBBOM_CAP CRITICAL COMMON

Agnes Input

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

Agnes Output

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

9

138S00159

138S0831 TYPICAL_CAPCRITICAL

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

9

C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914

C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914

Sensors

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

138S00159 SOFT_CAPCRITICALC3602,C3622

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

2

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

BOM OPTIONCRITICAL

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC2970,C2971,C2980,C29814138S00159

TYPICAL_CAPCRITICALC2970,C2971,C2980,C2981138S0831 4

BOM OPTIONCRITICAL

SOFT_CAPCRITICAL

BOM OPTIONCRITICAL

TYPICAL_CAPCRITICALC3602,C36222138S0831

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

D

C

B

A

NAND

Ultimate

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CRITICAL ULTIMATE1335S00287 HYNIX, 3DV3, ULTIMATE U2600

TABLE_ALT_HEAD

PART NUMBER

335S00284 335S00287

335S00287335S00288 U2600

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

U2600BOM_TABLE_ALTS

U2600335S00285 335S00287

U2600335S00286 335S00287

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TOSHIBA, 1Z, ULTIMATE

TABLE_ALT_ITEM

TOSHIBA, BICS3, ULTIMATE

TABLE_ALT_ITEM

SANDISK, BICS3, ULTIMATE

TABLE_ALT_ITEM

SAMSUNG, 3DV4, ULTIMATE

Extreme

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1335S00240 EXTREMECRITICALHYNIX, 3DV3, EXTREME U2600

TABLE_ALT_HEAD

PART NUMBER

335S00228 335S00240

335S00247 335S00240

335S00276 335S00240

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

U2600

U2600

U2600

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

TOSHIBA, BICS3, EXTREME

TABLE_ALT_ITEM

SANDISK, BICS3, EXTREME

TABLE_ALT_ITEM

SAMSUNG, 3DV4, EXTREME

Global Capacitors

TABLE_ALT_HEAD

PART NUMBER

BOM_TABLE_ALTS

138S00150 138S00149 ALL

138S00151

PART NUMBER

138S00143 ALL138S00144

138S00163

138S00144

PART NUMBER

138S00139138S00138 ALL

138S00164 ALL138S00139

PART NUMBER

138S00145 138S00146 ALL

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

PART NUMBER

138S00140

138S00142

138S00166

138S00141

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL138S00148 138S00149

ALL138S00149

ALL

ALL138S00146138S00165

ALL138S00141

ALL

ALL138S00141

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, Kyocera

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, SEMCO

TABLE_ALT_ITEM

0402-3T,10.5uF@1V, TY

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402,16uF@1V, Kyocera

TABLE_ALT_ITEM

0402,16uF@1V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0201,3uF@1V, Kyocera

TABLE_ALT_ITEM

0201,3uF@1V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0402,5.1uF@3V, Kyocera

TABLE_ALT_ITEM

0402,5.1uF@3V, Taiyo

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

0201,1.1uF@3V, Kyocera

TABLE_ALT_ITEM

0201,1.1uF@3V, SEMCO

TABLE_ALT_ITEM

0201,1.1uF@3V, Taiyo

CRITICAL PART# COMMENT

138S00149

CRITICAL PART# COMMENT

138S00144

CRITICAL PART# COMMENT

138S00139

CRITICAL PART# COMMENT

138S00146

CRITICAL PART# COMMENT

138S00141

RCAM B2Bs

TABLE_5_HEAD

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

Global Inductors

TABLE_ALT_HEAD

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

152S00710 152S00617

152S00712 ALL

152S00713 ALL

152S00714 ALL

152S00720

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

152S00649 152S00650

PART NUMBER

152S00620

152S00621

152S00622

152S00626

152S00631

152S00623152S00715

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

BOM_TABLE_ALTS

ALL

ALL152S00716

ALL152S00717

ALL152S00632152S00718

ALL152S00640

ALL152S00641152S00721

ALL

ALL152S00651152S00653

L3340,L3341

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608

IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012

IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012

IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012

IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012

IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012

IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016

IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012

IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012

IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016

IND,1.2UH,3A,2016,0.65Z

IND,0.47UH,6.6A,3225,0.8Z

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL PART# COMMENT

152S00617

152S00620

152S00621

152S00622

152S00626

152S00631

152S00632

152S00640

152S00641

152S00623

152S00651

152S00650

IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608

IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012

IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012

IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012

IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012

IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012

IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016

IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012

IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012

IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016

IND,1.2UH, 3A, 2016, 0.65Z

IND,0.47UH,6.6A,3225,0.8Z

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

138S0831 TYPICAL_CAPCRITICALC3909,C3925,C4025

Strobe B2B

Audio

Pearl B2B

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

3 SOFT_CAPCRITICALC3909,C3925,C4025138S00159

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

3

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

1138S00159

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

1138S0831

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

2138S00159

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

2138S0831

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA

1138S0831

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

BOM OPTIONCRITICAL

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC4303

TABLE_5_ITEM

C

TYPICAL_CAPCRITICALC4303

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC4809,C4805

TABLE_5_ITEM

TYPICAL_CAPCRITICALC4809,C4805

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

SOFT_CAPCRITICALC46131138S00159

TABLE_5_ITEM

TYPICAL_CAPCRITICALC4613

Acorn

TABLE_5_HEAD

0402-3T,10.5uF@1V

0402,16uF@1V

0201,3uF@1V

0402,5.1uF@3V

0201,1.1uF@3V

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEADTABLE_ALT_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

XTAL Alternate

TABLE_ALT_HEAD

PART NUMBER

197S0612 197S0446

BOM_TABLE_ALTS

Y1000

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

XTAL, 24M, 1612

CRITICAL PART# COMMENT

TABLE_ALT_ITEM

197S0446

XTAL, 24M, 1612

Multi-Vendor Criticals

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEMTABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM

CRITICAL PART# COMMENT

377S0106

197S0446

155S0576

155S00168

138S0979

138S0692

138S0683

138S0652

138S00070

138S00014

132S0664

132S0663

132S0534

132S0436

132S0396

132S0316

132S0304

132S0296

132S0318

SUPPR,TRANS,VARISTOR,12V,33PF,01005

XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612

FERR BD,10 OHM,50%,750MA,0.07 DCR,01005

FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605

CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM

CAP,CER,X5R,1UF,20%,6.3V,0201

CAP,CER,X5R,1UF,10%,25V,0402

CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402

CAP,X5R,4.7UF,20%,25V,0402

CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM

CAP,CER,0.047UF,10%,25V,X5R,0201

CAP,CER,X5R,1UF,10%,25V,0402

CAP,CER,X5R,0.1UF,10%,25V,0201

CAP,CER,X5R,0.22UF,20%,6.3V,01005

CAP,CER,X5R,1000PF,10%,10V,01005 CAP,CER,C0G,220PF,5%,10V,01005

CAP,CER,X5R,0.1UF,20%,6.3V,01005

CAP,CER,X5R,0.22UF,20%,6.3V,0201

CAP,CER,X5R,1000PF,10%,6.3V,01005

CAP,CER,X5R,820PF,10%,10V,01005

TABLE_CRITICAL_HEAD

CRITICAL PART# COMMENT

TABLE_CRITICAL_ITEM

132S0288

TABLE_CRITICAL_ITEM

132S0275

TABLE_CRITICAL_ITEM

132S0249

TABLE_CRITICAL_ITEM

132S0245

TABLE_CRITICAL_ITEM

132S00093

TABLE_CRITICAL_ITEM

132S00025

TABLE_CRITICAL_ITEM

132S00008

TABLE_CRITICAL_ITEM

131S0883

TABLE_CRITICAL_ITEM

131S0804

TABLE_CRITICAL_ITEM

131S0307

TABLE_CRITICAL_ITEM

131S0225

TABLE_CRITICAL_ITEM

131S0223

TABLE_CRITICAL_ITEM

131S0220

131S0216

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

CAP,CER,X5R,0.1UF,10%,16V,0201

CAP,CER,X5R,470PF,10%,10V,01005

CAP,CER,X7R,220PF,10%,10V,01005

CAP,CER,X5R,0.01UF,10%,6.3V,01005

CAP,X5R,0.022UF,20%,6.3V,01005

CAP,CER,X5R,0.047UF,20%,6.3V,01005

CAP,CER,0.1UF,10%,50V,X7R,0402

CAP,CER,NP0/C0G,220PF,2%,50V,0201

CAP,CER,27PF,5%,C0G,25V,0201

CAP,CER,NP0/C0G,100PF,5%,16V,01005

CAP,CER,NP0/C0G,15PF,5%,16V,01005

CAP,CER,NP0/C0G,27PF,5%,16V,01005

CAP,CER,NP0/C0G,12PF,5%,16V,01005

CAP,CER,NP0/C0G,47PF,5%,16V,01005

131S00053

TABLE_CRITICAL_ITEM

118S00068

TABLE_CRITICAL_ITEM

117S0055

TABLE_CRITICAL_ITEM

107S0257

TABLE_CRITICAL_ITEM

RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201

RES,MF,1/20W,2M OHM,5,0201,SMD

THERMISTOR,NTC,10K OHM,1%,B=3435,01005

TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM

CODEC

Ansel

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,10UF,10V,0402,MURATA

2138S00160

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

2138S0979

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,10UF,10V,0402,MURATA

2138S00160

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

2138S0979

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

CAP,SOFT-TERM,10UF,10V,0402,MURATA

1138S00160

CAP,TYPICAL,10UF,10V,0402,MUR/KYO

1138S0979 CRITICAL

PART NUMBER

685-00155685-00156

BOM_TABLE_ALTS

SYNC_MASTER=test_mlb

PAGE TITLE

SUBBOM_CAP

C4811,C4808 SOFT_CAPCRITICAL

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

SUBBOM,MLB,TOP,CAP,SOFT,X891

SYSTEM:BOM Tables

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC5641,C5653

TYPICAL_CAPCRITICALC5641,C5653

BOM OPTIONCRITICAL

TYPICAL_CAPCRITICALC4811,C4808

BOM OPTIONCRITICAL

SOFT_CAPCRITICALC3710

TYPICAL_CAPC3710

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

051-02221

9.0.0

evt-1
2 OF 80
2 OF 51

SYNC_DATE=10/13/2016

SIZE

D

B

A

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

67

35 4

2

1

678

3 245

1

FIDUCIALS

FD0401

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

D

CL0400

2.10R1.60-NSP

1

FD0402

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0403

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0404

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0420

FID

0P5SQ-CROSS-NSP

1

ROOM=ASSEMBLY

FD0405

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

D

C

CRITICAL

SB0400

STDOFF-2.9OD1.4ID-0.77H-SM

1

CL0401

2.10R1.60-NSP

1

FD0410

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0411

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

FD0412

0P5SQ-SMP3SQ-NSP

FID

1

ROOM=ASSEMBLY

C

B

CRITICAL

SB0402

STDOFF-MLB-TUBE

1

CL0402

2.10R1.60-NSP

1

B

CRITICAL

1

SH0401

SM

SHLD-EMI-HARD-X891

A

https://www.facebook.com/
Professional.Repairphone

CRITICAL

SB0401

STDOFF-2.9OD1.4ID-0.77H-SM

1

CRITICAL

1

SH0400

SM

SHIELD-EMI-TOP-X891

CL0403

2.10R1.60-NSP

1

PAGE TITLE

SYSTEM: Mechanical Components

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

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SHEET

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A

SIZE

D

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67

35 4

2

1

678

3 245

1

D

C

PP_ROMEO_DENSE_ANODE

34 35

PP_ROMEO_CATHODE

34 35

POWER

TP0540

P2MM-NSM

SM

1

TP0543

P2MM-NSM

1

PP

SM

PP

ROOM=TEST

ROOM=TEST

Test Points

20

XW0510

SHORT-10L-0.05MM-SM

XW0511

SHORT-10L-0.05MM-SM

17 13

PP_GPU

20 6

11 5

32 8

11

11 6

20 6

Probe Points

SOC Debug

PP0500

P2MM-NSM

AP_TO_PMU_TEST_CLKOUT

IN

BOARD_ID0

IN

AP_TO_FCAM_SHUTDOWN_L

IN

8

AP_DEBUG3

IN

DFU_STATUS

IN

PMU_TO_AP_PRE_UVLO_L

IN

AP_TO_PMU_SOCHOT_L

IN

SOC CPU/GPU

21

21

PP_GPU_LVCC

PP_CPU_PCORE_LVCCPP_CPU_PCORE

SM

1

PP

ROOM=TEST

PP0501

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0502

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0503

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0504

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0505

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0506

P2MM-NSM

SM

1

PP

ROOM=TEST

50

50 17 13

26 12

26 12

26 12

26 12

26 12

49 25 12

26 12

48 23

Sensors

SPI_AOP_TO_IMU_SCLK

IN

SPI_AOP_TO_IMU_MOSI

IN

SPI_IMU_TO_AOP_MISO

IN

ACCEL_GYRO_TO_AOP_DATARDY

IN

ACCEL_GYRO_TO_AOP_INT

IN

COMPASS_TO_AOP_INT

IN

PHOSPHORUS_TO_AOP_INT

IN

Hydra VBUS

HYDRA_TO_TIGRIS_VBUS1_VALID_L

IN

PP0540

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0541

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0542

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0544

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0545

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0546

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0547

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0550

P2MM-NSM

SM

1

PP

ROOM=TEST

41 37

41 37

47 10

47 10

50 49 41 25 12

50 49 41 25 12

PDM_CODEC_TO_ARC_CLK

IN

PDM_CODEC_TO_ARC_DATA

IN

AP_BI_CCG2_SWDIO

IN

AP_TO_CCG2_SWCLK

IN

SOC I2C1_AOP

I2C1_AOP_SCL

IN

I2C1_AOP_SDA

IN

PP0582

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0583

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0586

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0587

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0590

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0591

P2MM-NSM

SM

1

PP

ROOM=TEST

D

C

B

20 13

20 13

13

15

15

AP_CPU_PCORE_SENSE

IN

AP_VDD_GPU_SENSE

IN

TP_SOC_SENSE

IN

TP_VSS_CPU_SENSE

IN

TP_VSS_SENSE

IN

PMU

PP0512

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0513

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0514

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0515

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0516

P2MM-NSM

SM

1

PP

ROOM=TEST

16 12

50 16 12

16 10 5

16

16

NAND CCG2

PP0560

P2MM-NSM

SWD_AP_BI_NAND_SWDIO

IN

SWD_AOP_TO_MANY_SWCLK

IN

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

IN

NAND_ANI1_VREF

IN

NAND_ANI0_VREF

IN

SM

1

PP

ROOM=TEST

PP0561

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0562

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0563

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0564

P2MM-NSM

SM

1

PP

ROOM=TEST

47 10

CCG2_TO_SMC_INT_L

IN

PP0592

P2MM-NSM

SM

1

PP

ROOM=TEST

B

14 12

20 10

48 20 6

16 7

16 7

AOP_TO_DDR_SLEEP1_READY

IN

SPMI_PMU_BI_PMGR_SDATA

IN

PMU_TO_AP_HYDRA_ACTIVE_READY

IN

PCIE Refclk

90_PCIE_AP_TO_NAND_REFCLK_P

IN

90_PCIE_AP_TO_NAND_REFCLK_N

IN

PP0520

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0521

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0522

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0530

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0531

P2MM-NSM

SM

1

PP

ROOM=TEST

34 28

34 20 8

Rigel

CAMPMU_TO_RIGEL_ENABLE

IN

RIGEL_TO_ISP_INT

IN

PP0570

P2MM-NSM

SM

1

PP

ROOM=TEST

PP0571

P2MM-NSM

SM

1

PP

ROOM=TEST

A

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SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SYSTEM: Testpoints (Top)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

5 OF 80

SHEET

4 OF 51

1

SIZE

D

678

3 245

1

D

11

11

BOARD_REV3

OUT

BOARD_REV2

OUT

R0623

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0622

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

NOSTUFF

BOOTSTRAPPING:BOARD REV

BOARD ID
BOOT CONFIG

PP1V8_IO

43 35 34 32

30 29 28 27 17 16 14 10 8 7 6

D

C

11

11

11

BOARD_REV1

OUT

BOARD_REV0

OUT

BOARD_ID4

OUT

CKPLUS_WAIVE=SINGLE_NODENET

R0621

1.00K

1/32W
01005

ROOM=SOC

21

5%
MF

R0620

1.00K

1/32W
01005

ROOM=SOC

No connect

21

5%
MF

C

SELECTED -->

B

50 10

11

11

11 4

BOARD_ID3

OUT

CKPLUS_WAIVE=SINGLE_NODENET

PP1V8_IO

OUT

PP1V8_IO

OUT

BOARD_ID0

OUT

On mlb_bot

MAKE_BASE=TRUE

No connect

SELECTED -->

D221 Baseband Selected on RF Board

B

A

16 10 4

16 10

16 10

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

OUT

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

No connect

R0601

4.7K

1/32W
01005

ROOM=SOC

21

1%
MF

R0600

4.7K

1/32W
01005

ROOM=SOC

21

1%
MF

NOSTUFF

SELECTED -->

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Professional.Repairphone

SYNC_MASTER=test_mlb

PAGE TITLE

BOOTSTRAPPING

DRAWING NUMBER

051-02221

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

REVISION

BRANCH

PAGE

6 OF 80

SHEET

5 OF 51

9.0.0
evt-1

SYNC_DATE=10/13/2016

SIZE

D

A

8

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67

35 4

2

1

SOC - USB, JTAG, XTAL

678

3 245

1

VDD11_XTAL:1.06-1.17V @ 2mA MAX

VDD18_USB: 1.62V - 1.98V @ 20mA MAX

D

PP1V8_XTAL

1

C1090

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

FL1092

240-OHM-25%-0.20A-0.9DCR

1

C1092

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1095

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

01005

ROOM=SOC

PP1V8_IO

43 35 34 32

30 29 28 27 17 16 14 10 8 7 5

D

21

1

C1093

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

3.14-3.46V @ 12mA MAX

PP3V3_USB

19

AP_USB_REXT

6

USB Reference

1

R1000

200

1%
1/32W
MF
01005

2

ROOM=SOC

C

NC
NC

BA4
AY4

AT7

VDD12_UH1_HSIC0

UH1_HSIC0_DATA
UH1_HSIC0_STB

AP14

OMIT_TABLE

U1000

TMIT78B0-C4

WLCSP

SYM 1 OF 16

ROOM=SOC

CRITICAL

AU28

VDD18_USB

VDD18_XTAL

AN15

AN14

VDD33_USB

VDD_FIXED_USB

ANALOGMUX_OUT

AT27

(Analog)

0.765V - 0.84V @ 5mA MAX

PP0V8_SOC_FIXED_S1

AP_TO_PMU_AMUX_OUT

OUT

17 14 13 9 8 7

C

20

B

20

PMU_TO_SYSTEM_COLD_RESET_L

IN

MAKE_BASE=TRUE

R1020

10K

21

5%

1/32W

MF

01005

MAKE_BASE=TRUE

48

48

48 20 4

20 4

16

16

GND

SWD_DOCK_BI_AP_SWDIO

BI

SWD_DOCK_TO_AP_SWCLK

IN

PMU_TO_SYSTEM_COLD_RESET_R_L
PMU_TO_AP_HYDRA_ACTIVE_READY

IN

AP_TO_PMU_TEST_CLKOUT

OUT

AP_TO_NAND_RESET_L

OUT

OUT

AP_TO_NAND_FW_STRAP
GND
GND

NC
NC
NC

AT8

AV6

AT9
AT12
AT10
AT13

AU7
AT34

AV5

V2

AF34

AG38

W5
W4

JTAG_SEL

JTAG_TRST*
JTAG_TDO
JTAG_TDI
JTAG_TMS
JTAG_TCK

COLD_RESET*
CFSB

CFSB_AON
TST_CLKOUT
SSD_RESET*

SSD_BFH

HOLD_RESET
TESTMODE

USB_DP

USB_DM

USB_VBUS

USB_ID

USB_REXT

CPU_TRIGGER0
CPU_TRIGGER1

GPU_TRIGGER0
GPU_TRIGGER1

SOCHOT1

DROOP

WDOG

XI0

XO0

AY6
BA6

AV7

AW6

AU8

AT22
AW21

AD2
AD3

A30
B31

AW5
BA28

BA27

NC

90_USB_AP_DATA_P
90_USB_AP_DATA_N

USB_VBUS_DETECT

AP_USB_REXT

PMU_TO_AP_THROTTLE_PCORE_L
PMU_TO_AP_THROTTLE_ECORE_L

PMU_TO_AP_THROTTLE_GPU0_L
PMU_TO_AP_THROTTLE_GPU1_L

AP_TO_PMU_SOCHOT_L
PMU_TO_AP_PRE_UVLO_L
AP_TO_PMU_WDOG_RESET

XTAL_AP_24M_IN

XTAL_AP_24M_OUT

6

BI
BI

IN

IN
IN

IN
IN

OUT

IN

OUT

23

20

20

20

20

20

48

48

B

20 4

20 11 4

NOSTUFF

1

R1010

511K

1%
1/32W
MF
01005

2

ROOM=SOC

R1011

1.00K

5%

1/32W

MF

01005

ROOM=SOC

24.000MHZ-30PPM-9.5PF-60OHM

21

SOC_24M_O

1

C1010

12PF

5%
16V

2

CERM
01005

ROOM=SOC

ROOM=SOC

Y1000

1.60X1.20MM-SM

31

42

1

C1011

12PF

5%
16V

2

CERM
01005

ROOM=SOC

A

8

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SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: JTAG,USB,XTAL

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

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2

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10 OF 80

SHEET

6 OF 51

1

SIZE

D

SOC - PCIE INTERFACES

678

3 245

1

D

C

PCIe BB CLKREQ PU on BB domain

PCIe Clock Request Pull-Ups

29 28 27 17 16 14 10 8 7 6 5

PCIE_NAND_BI_AP_CLKREQ_L

16 7

PCIE_WLAN_BI_AP_CLKREQ_L

50 7

43 35 34 32 30

PP1V8_IO

R1100

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1130

PCIe Reset Pull-Downs

PCIE_AP_TO_WLAN_RESET_L

50 7

PCIE_AP_TO_BB_RESET_L

50 7

PCIE_AP_TO_NAND_RESET_L

16 7

R1101

100K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1121

100K

1/32W
01005

ROOM=SOC

100K

1/32W
01005

ROOM=SOC

5%
MF

5%
MF

(Analog)

R1198

19 14 13 9

1

2

1

2

R1131

ROOM=SOC

100K

5%

1/32W

MF

01005

1

2

PP1V2_SOC

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX

1

C1198

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

AM31

AP26

AN26

VDD12_PCIE_REFBUF

VDD12_PCIE_REFBUF

AM29

VDD18_PCIE

VDD18_PCIE

ROOM=SOC

U1000

AP29

AN30

VDD_FIXED_PCIE_ANA

VDD_FIXED_PCIE_ANA

AP31

VDD_FIXED_PCIE_ANA

AP27

AM27

VDD_FIXED_PCIE_REFBUF

VDD_FIXED_PCIE_REFBUF

1

C1199

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

PP0V8_SOC_FIXED_PCIE_REFBUF

1

C1194

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

R1194

0.00

1/32W
01005

ROOM=SOC

21

0%
MF

VDD_FIXED_PCIE_REFBUF:0.765V - 0.84V @ 9mA MAX

VDD_FIXED_PCIE_ANA:0.765V - 0.84V @ 131mA MAX

1

C1193

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1192

1.0UF

20%

6.3V

2

X5R
0201-1

ROOM=SOC

1.62V - 1.98V @ 81mA MAX

PP1V8_IOPP1V2_SOC_PCIE_REFBUF

(Analog)

PP0V8_SOC_FIXED_S1

1

C1191

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

43 35 34 32 30

17 14 13 9 8 6

29 28 27 17 16 14 10 8 7 6 5

TMIT78B0-C4

WLCSP

D

C

B

16

IN

16

IN

16

OUT

16

PCIE LINK 0

OUT

90_PCIE_NAND_TO_AP_RXD_P
90_PCIE_NAND_TO_AP_RXD_N

90_PCIE_AP_TO_NAND_TXD_P
90_PCIE_AP_TO_NAND_TXD_N

0.22UF

0.22UF

0.22UF

0.22UF

2 1

6.3V

01005

ROOM=SOC

2 1

6.3V 20%

01005

ROOM=SOC

2 1

6.3V 20%

01005

ROOM=SOC

2 1

6.3V

01005

ROOM=SOC

20%
X5R

C1101

X5R

C1102

X5R

C1103

20%
X5R

C1100

GND_VOID

GND_VOID

GND_VOID

GND_VOID

16 7

16 4

16 4

16 7

PCIE_NAND_BI_AP_CLKREQ_L

BI

90_PCIE_AP_TO_NAND_REFCLK_P

OUT

90_PCIE_AP_TO_NAND_REFCLK_N

OUT

90_PCIE_NAND_TO_AP_RXD_C_P
90_PCIE_NAND_TO_AP_RXD_C_N

90_PCIE_AP_TO_NAND_TXD_C_P
90_PCIE_AP_TO_NAND_TXD_C_N

PCIE_AP_TO_NAND_RESET_L

OUT

NC
NC

NC

AL38

AW27

AV27

AV29

AW29

AY30
BA30

AJ37

AL37

AW26

AY26

PCIE_CLKREQ0*
PCIE_REF_CLK0_P

PCIE_REF_CLK0_N

PCIE_RX0_P
PCIE_RX0_N

PCIE_TX0_P
PCIE_TX0_N

PCIE_PERST0*

PCIE_CLKREQ1*
PCIE_REF_CLK1_P

PCIE_REF_CLK1_N

SYM 2 OF 16

LINK3LINK0

PCIE_CLKREQ3*

PCIE_REF_CLK3_P
PCIE_REF_CLK3_N

PCIE_RX3_P
PCIE_RX3_N

PCIE_TX3_P

PCIE_TX3_N

PCIE_PERST3*

PCIE_CLKREQ2*

PCIE_REF_CLK2_P
PCIE_REF_CLK2_N

AJ36
AY24

BA24

BA36
AY36

AV35
AW35

AH36

AK37
AV25

AW25

PCIE_WLAN_BI_AP_CLKREQ_L

90_PCIE_AP_TO_WLAN_REFCLK_P
90_PCIE_AP_TO_WLAN_REFCLK_N

90_PCIE_WLAN_TO_AP_RXD_C_P
90_PCIE_WLAN_TO_AP_RXD_C_N

90_PCIE_AP_TO_WLAN_TXD_C_P
90_PCIE_AP_TO_WLAN_TXD_C_N

PCIE_AP_TO_WLAN_RESET_L

PCIE_BB_BI_AP_CLKREQ_L

BI

OUT
OUT

OUT

BI

50

50

50

50 7

6.3V

ROOM=SOC

6.3V

ROOM=SOC

6.3V

ROOM=SOC

6.3V20%

ROOM=SOC

21

0.1UF

01005

21

0.1UF

01005

21

0.1UF

01005

21

0.1UF

01005

1

C1124

4.7PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=SOC

1

C1125

4.7PF

+/-0.1PF
16V

2

NP0-C0G
01005

ROOM=SOC

90_PCIE_WLAN_TO_AP_RXD_P
90_PCIE_WLAN_TO_AP_RXD_N

90_PCIE_AP_TO_WLAN_TXD_P
90_PCIE_AP_TO_WLAN_TXD_N

90_PCIE_AP_TO_BB_REFCLK_P
90_PCIE_AP_TO_BB_REFCLK_N

IN
IN

OUT
OUT

OUT
OUT

50

50

50

50

50

50

B

C1130

GND_VOID

20%

X5R-CERM

C1131

GND_VOID

20%

X5R-CERM

C1132

GND_VOID

20%

X5R-CERM

C1133

50 7

GND_VOID

X5R-CERM

A

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Professional.Repairphone

NC
NC

NC
NC

NC

AV31

AW31

AY32
BA32

AK38

AU30
AT30

PCIE_RX1_P
PCIE_RX1_N

PCIE_TX1_P
PCIE_TX1_N

PCIE_PERST1*

PCIE_EXT_REF_CLK_P
PCIE_EXT_REF_CLK_N

LINK1 LINK2

PCIE_RX2_P
PCIE_RX2_N

PCIE_TX2_P
PCIE_TX2_N

PCIE_PERST2*

PCIE_REXT

BA34
AY34

AV33
AW33

AJ38

AU32

90_PCIE_BB_TO_AP_RXD_C_P
90_PCIE_BB_TO_AP_RXD_C_N

90_PCIE_AP_TO_BB_TXD_C_P
90_PCIE_AP_TO_BB_TXD_C_N

AP_PCIE_RCAL

PCIE_AP_TO_BB_RESET_L

1

R1150

200

1%
1/32W
MF
01005

2

ROOM=SOC

OUT

21

6.3V
01005

21

6.3V
01005

21

6.3V
01005

21

6.3V
01005

0.1UF

0.1UF

0.1UF

0.1UF

PAGE TITLE

90_PCIE_BB_TO_AP_RXD_P
90_PCIE_BB_TO_AP_RXD_N

90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_TXD_N

IN
IN

OUT
OUT

50

50

50

50

PCIE LINK 2 PCIE LINK 3

SYNC_DATE=10/17/2016SYNC_MASTER=test_mlb

A

C1120

GND_VOID

20%

X5R-CERM

ROOM=SOC

C1121

GND_VOID

20%

X5R-CERM

ROOM=SOC

C1122

GND_VOID

20%

X5R-CERM

ROOM=SOC

C1123

50 7

GND_VOID

20%

X5R-CERM

ROOM=SOC

SOC: PCIE

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

11 OF 80

SHEET

7 OF 51

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

67

35 4

2

1

678

3 245

1

D

SOC - MIPI & ISP INTERFACES

MIPI Lane & Polarity Swapping

17 14 13 9 7 6

(Analog)

0.765V - 0.84V @ 40mA MAX

PP0V8_SOC_FIXED_S1

20%

6.3V

1

2

C1290

0.1UF 2.2UF

X5R-CERM

01005

ROOM=SOC

C1291

2.2UF

20%

6.3V

X5R-CERM

0201

ROOM=SOC

ISP I2C0

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

1.62V - 1.98V @ 10mA MAX

PP1V8_IO

43 35 34 32

1

2

G14

G12

F13

F11

VDD18_MIPI

1

C1295

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1296

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

30 29 28 27 17 16 14 10 8 7 6 5

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

29 8

I2C0_ISP_SCL

29 8

I2C0_ISP_SDA

ISP I2C1

PP1V8_IO

1

R1201

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1211

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1202

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1212

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

D

C

35

35

35

35

35

35

32

32

32

32

FCAM MIPI Juliet MIPI

32

32

43

43

43

43

43

43

43

43

90_MIPI_JULIET_TO_AP_DATA0_P

BI

90_MIPI_JULIET_TO_AP_DATA0_N

BI

90_MIPI_JULIET_TO_AP_DATA1_P

IN

90_MIPI_JULIET_TO_AP_DATA1_N

IN

90_MIPI_JULIET_TO_AP_CLK_N

IN

90_MIPI_JULIET_TO_AP_CLK_P

IN

90_MIPI_FCAM_TO_AP_DATA0_N

BI

90_MIPI_FCAM_TO_AP_DATA0_P

BI

90_MIPI_FCAM_TO_AP_DATA1_N

IN

90_MIPI_FCAM_TO_AP_DATA1_P

IN

90_MIPI_FCAM_TO_AP_CLK_P

IN

90_MIPI_FCAM_TO_AP_CLK_N

IN

90_MIPI_AP_TO_DISPLAY_DATA0_P

BI

90_MIPI_AP_TO_DISPLAY_DATA0_N

BI

90_MIPI_AP_TO_DISPLAY_DATA1_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA1_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_P

OUT

90_MIPI_AP_TO_DISPLAY_DATA3_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_N

OUT

90_MIPI_AP_TO_DISPLAY_DATA2_P

OUT

Display MIPI

43

43

90_MIPI_AP_TO_DISPLAY_CLK_N

OUT

90_MIPI_AP_TO_DISPLAY_CLK_P

OUT

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

MAKE_BASE
MAKE_BASE

90_MIPI_JULIET_TO_AP_DATA0_P
90_MIPI_JULIET_TO_AP_DATA0_N

90_MIPI_JULIET_TO_AP_DATA1_P
90_MIPI_JULIET_TO_AP_DATA1_N

90_MIPI_JULIET_TO_AP_CLK_N
90_MIPI_JULIET_TO_AP_CLK_P

MIPI0C_REXT

8

MIPI1C_REXT

8

90_MIPI_FCAM_TO_AP_DATA0_N
90_MIPI_FCAM_TO_AP_DATA0_P

90_MIPI_FCAM_TO_AP_DATA1_N
90_MIPI_FCAM_TO_AP_DATA1_P

90_MIPI_FCAM_TO_AP_CLK_P
90_MIPI_FCAM_TO_AP_CLK_N

90_MIPI_AP_TO_DISPLAY_DATA1_P
90_MIPI_AP_TO_DISPLAY_DATA1_N

90_MIPI_AP_TO_DISPLAY_DATA3_P
90_MIPI_AP_TO_DISPLAY_DATA3_N

90_MIPI_AP_TO_DISPLAY_DATA2_N
90_MIPI_AP_TO_DISPLAY_DATA2_P

90_MIPI_AP_TO_DISPLAY_CLK_N
90_MIPI_AP_TO_DISPLAY_CLK_P

B12
A12

B14
A14

A13
B13

D12
D13

B17
A17

B15

A15

A16
B16

A10

B10

B9

A9

A7

B7

A6
B6

A8
B8

MIPI0C_DPDATA0
MIPI0C_DNDATA0

MIPI0C_DPDATA1
MIPI0C_DNDATA1

MIPI0C_DPCLK
MIPI0C_DNCLK

MIPI0C_REXT
MIPI1C_REXT

MIPI1C_DPDATA0
MIPI1C_DNDATA0

MIPI1C_DPDATA1
MIPI1C_DNDATA1

MIPI1C_DPCLK
MIPI1C_DNCLK

MIPID_DPDATA0
MIPID_DNDATA0

MIPID_DPDATA1
MIPID_DNDATA1

MIPID_DPDATA2
MIPID_DNDATA2

MIPID_DPDATA3
MIPID_DNDATA3

MIPID_DPCLK
MIPID_DNCLK

VDD_FIXED_MIPI

U1000

TMIT78B0-C4

WLCSP

SYM 3 OF 16

ROOM=SOC

ISP_I2C0_SCL

ISP_I2C0_SDA

ISP_I2C1_SCL

ISP_I2C1_SDA

ISP_I2C2_SCL

ISP_I2C2_SDA

ISP_I2C3_SCL

ISP_I2C3_SDA

SENSOR_INT

SENSOR0_CLK
SENSOR1_CLK
SENSOR2_CLK

SENSOR0_RST
SENSOR1_RST
SENSOR2_RST
SENSOR3_RST
SENSOR4_RST

SENSOR0_ISTRB
SENSOR1_ISTRB

W35
V38

W36
Y36

Y34
Y38

AA37
AB38

AB36

U38
R38
R37

V34
U35
AB34
AC37
AA35

V36
U36

NC

NC

I2C0_ISP_SCL
I2C0_ISP_SDA

I2C1_ISP_SCL
I2C1_ISP_SDA

I2C2_ISP_SCL
I2C2_ISP_SDA

I2C3_ISP_SCL
I2C3_ISP_SDA

RIGEL_TO_ISP_INT

AP_TO_WIDE_CLK_R
AP_TO_TELE_CLK_R

AP_TO_FCAM_JULIET_RIGEL_CLK_R

AP_TO_JULIET_SHUTDOWN_L

AP_TO_TELE_SHUTDOWN_L
AP_TO_WIDE_SHUTDOWN_L

AP_TO_FCAM_SHUTDOWN_L

AP_DEBUG3

OUT

BI

OUT

BI

OUT

BI

OUT

BI

IN

OUT
OUT
OUT

OUT

OUT

35

30

29

4

30 8

I2C1_ISP_SCL

30 8

I2C1_ISP_SDA

29 8

29 8

29 28 27 17 16 14 10 8 7 6 5

30 8

30 8

32 8

32 8

35 34 31 28 8

35 34 31 28 8

43 35 34 32 30

ISP I2C2

PP1V8_IO

32 8

I2C2_ISP_SCL

32 8

I2C2_ISP_SDA

1

R1221

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1222

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

C

R1240

33.2

34 20 4

1/32W
01005

ROOM=SOC

21

1%
MF

R1241

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

R1242

33.2

1/32W
01005

32 4

ROOM=SOC

21

1%
MF

AP_TO_FCAM_JULIET_CLK

AP_TO_WIDE_CLK

AP_TO_TELE_CLK

OUT

OUT

OUT

29

29 28 27 17 16 14 10 8 7 6 5

30

35 32

43 35 34 32 30

35 34 31 28 8

35 34 31 28 8

ISP I2C3

PP1V8_IO

I2C3_ISP_SCL
I2C3_ISP_SDA

1

R1231

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1232

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

R1243

33.2

1%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_RIGEL_CLK

OUT

34

B

50 28 21 20 12

43

AP_TO_MANY_BSYNC

OUT

DISPLAY_TO_AP_ALIVE

IN

MIPID_REXT

8

NC

NC
NC

NC

AA3

AB4

AB6

D11

AA4
AA5

Y4

DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1

DISP_TOUCH_EB

MIPID_REXT

DISP_I2C_SCL
DISP_I2C_SDA

DISP_POL

SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN

U37
T37

NC

ISP_TO_DISPLAY_FLASH_INT

OUT

43

B

A

MIPI Reference

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1252

200

1%

1/32W

MF

01005

ROOM=SOC

R1250

200

1%

1/32W

MF

01005

ROOM=SOC

1

2

R1251

8

MIPI0C_REXT
MIPI1C_REXT

MIPID_REXT

1

8

8

8

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SOC: MIPI & ISP

DRAWING NUMBER

2

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

12 OF 80

SHEET

8 OF 51

1

SIZE

D

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

SOC - LPDP

19 14 13 7

678

VDD12_PLL_LPDP 1.14V - 1.26V @ 10mA MAX
VDD12_LPDP 1.14V - 1.26V @ 72mA MAX

PP1V2_SOC

3 245

(Analog)
VDD_FIXED_PLL_LPDP 0.765V - 0.84V @ 3mA MAX
VDD_FIXED_LPDP_TX 0.765V - 0.84V @ 16mA MAX
VDD_FIXED_LPDP_RX 0.765V - 0.84V @ 30mA MAX

PP0V8_SOC_FIXED_S1

1

17 14 13 9 8 7 6

D

1

C1390

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1391

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1392

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1393

0.01UF

10%

6.3V

2

X5R
01005

ROOM=SOC

1

C1394

15PF2.2UF

5%
16V

2

NP0-C0G-CERM
01005

ROOM=SOC

Desense for Wifi frequencies

M9

VDD12_LPDP_TX

F16

F17

F15

VDD12_LPDP_RX

T9

VDD12_PLL_LPDP

R9

P9

VDD_FIXED_LPDP_TX

VDD_FIXED_PLL_LPDP

G18

G16

VDD_FIXED_LPDP_RX

1

C1395

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1396

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

D

C

29

29

29

29

29

29

30

30

30

30

90_LPDP_WIDE_TO_AP_D0_P

IN

90_LPDP_WIDE_TO_AP_D0_N

IN

90_LPDP_WIDE_TO_AP_D1_P

IN

90_LPDP_WIDE_TO_AP_D1_N

IN

90_LPDP_WIDE_TO_AP_D2_P

IN

90_LPDP_WIDE_TO_AP_D2_N

IN

90_LPDP_TELE_TO_AP_D0_P

IN

90_LPDP_TELE_TO_AP_D0_N

IN

90_LPDP_TELE_TO_AP_D1_P

IN

90_LPDP_TELE_TO_AP_D1_N

IN

A26
B26

A25
B25

A24
B24

A21
B21

A20
B20

LPDPRX_RX_D0_P
LPDPRX_RX_D0_N

LPDPRX_RX_D1_P
LPDPRX_RX_D1_N

LPDPRX_RX_D2_P
LPDPRX_RX_D2_N

LPDPRX_RX_D3_P
LPDPRX_RX_D3_N

LPDPRX_RX_D4_P
LPDPRX_RX_D4_N

U1000

TMIT78B0-C4

WLCSP

SYM 4 OF 16

LPDP_TX0P
LPDP_TX0N

LPDP_TX1P
LPDP_TX1N

LPDP_TX2P
LPDP_TX2N

LPDP_TX3P
LPDP_TX3N

M3
M4

L4
L5

K3
K4

J4
J5

NC
NC

NC
NC

NC
NC

NC
NC

C

B

17 14 13 9 8 7 6

30

IN

30

IN

29

BI

30

BI

MAKE_BASE=TRUE

PP0V8_SOC_FIXED_S1

300

1%

1/32W

MF

1

2

R1300

01005-1

ROOM=SOC

90_LPDP_TELE_TO_AP_D2_P
90_LPDP_TELE_TO_AP_D2_N

LPDP_WIDE_BI_AP_AUX

LPDP_TELE_BI_AP_AUX

GND
GND

AP_LPDPRX_RCAL_NEG

NC
NC

NC
NC

A19
B19

D21
D20
D19
D17
D16
D15

A22
B22

B23

A23

LPDPRX_RX_D5_P
LPDPRX_RX_D5_N

LPDPRX_AUX_D0_P
LPDPRX_AUX_D1_P
LPDPRX_AUX_D2_P
LPDPRX_AUX_D3_P
LPDPRX_AUX_D4_P
LPDPRX_AUX_D5_P

LPDPRX_BYP_CLK_P
LPDPRX_BYP_CLK_N

LPDPRX_RCAL_P

LPDPRX_RCAL_N

LPDP_AUX_P
LPDP_AUX_N

LPDP_CAL_DRV_OUT

LPDP_CAL_VSS_EXT

EDP_HPD

DP_WAKEUP

G4
G5

H3
H6

Y6
Y2

NC
NC

NC
NC

NC
NC

B

A

C1301

100PF

5%

16V

NP0-C0G

01005

ROOM=SOC

1

D18

NC

2

LPDPRX_EXT_C

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE

A

SOC: LPDP

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

13 OF 80

SHEET

9 OF 51

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

67

35 4

2

1

SOC - SERIAL INTERFACES

678

3 245

1

AP I2C0

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

R1400

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1401

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

D

C

B

R1460

38

I2S_AP_TO_CODEC_MCLK1

OUT

33.2

1%

1/32W

MF

01005

ROOM=SOC

R1464

50

I2S_AP_TO_SPKRAMP_TOP_MCLK

OUT

33.2

1%

1/32W

MF

01005

ROOM=SOC

R1465

16 5

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0

OUT

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1461

50

SPI_AP_TO_RACER_SCLK

OUT

0.00

0%

1/32W

MF

01005

ROOM=SOC

R1462

38

SPI_AP_TO_CODEC_SCLK

OUT

SPI: Route as Daisy-Chain. No T's Allowed

Place series terminations close to SoC Pins

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

21

21

21

21

38

38

38

38

47 4

47 4

38

50

50

50

50

16 5 4

16 5

50 5

50

50

50

38

38

38

I2S_AP_TO_CODEC_MCLK1_R
I2S_AP_TO_CODEC_ASP3_BCLK

OUT

I2S_AP_TO_CODEC_ASP3_LRCLK

OUT

I2S_CODEC_ASP3_TO_AP_DIN

IN

I2S_AP_TO_CODEC_ASP3_DOUT

OUT

I2S_AP_TO_SPKRAMP_TOP_MCLK_R

AP_BI_CCG2_SWDIO

BI

AP_TO_CCG2_SWCLK

OUT

CODEC_TO_AP_INT_L CCG2_TO_SMC_INT_L

IN

I2S_BB_TO_AP_BCLK

OUT

I2S_BB_TO_AP_LRCLK

OUT

I2S_BB_TO_AP_DIN

IN

I2S_AP_TO_BB_DOUT

OUT

SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

IN

SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1

OUT

SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R
BOARD_ID3

IN

SPI_RACER_TO_AP_MISO

IN

SPI_AP_TO_RACER_MOSI

OUT

SPI_AP_TO_RACER_SCLK_R
SPI_AP_TO_RACER_CS_L

OUT

SPI_CODEC_TO_AP_MISO

IN

SPI_AP_TO_CODEC_MOSI

OUT

SPI_AP_TO_CODEC_SCLK_R
SPI_AP_TO_CODEC_CS_L

OUT

NC
NC
NC
NC
NC

NC

NC

NC
NC
NC
NC

AV23

AW23

AT24
AT25
AT26

AH34
AG36
AG35
AH38
AG37

AT35

AT36

AR36

AR34

AR35

AG4
AG5
AH2
AH6
AH4

AV22

BA21

BA22

AU22

AU23

AY22

AW22

AT23

AE4
AE2

AD5

AE6

AE38

AE35

AF38

AE37

I2S0_MCK
I2S0_BCLK
I2S0_LRCK
I2S0_DIN
I2S0_DOUT

I2S1_MCK
I2S1_BCLK
I2S1_LRCK
I2S1_DIN
I2S1_DOUT

I2S2_MCK
I2S2_BCLK
I2S2_LRCK
I2S2_DIN
I2S2_DOUT

I2S3_MCK
I2S3_BCLK
I2S3_LRCK
I2S3_DIN
I2S3_DOUT

SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_SSIN

SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_SSIN

SPI2_MISO
SPI2_MOSI
SPI2_SCLK
SPI2_SSIN

SPI3_MISO
SPI3_MOSI
SPI3_SCLK
SPI3_SSIN

U1000

TMIT78B0-C4

WLCSP

SYM 6 OF 16

ROOM=SOC

I2C0_SCL

I2C0_SDA

I2C1_SCL

I2C1_SDA

I2C2_SCL

I2C2_SDA

I2C3_SCL

I2C3_SDA

SMC_I2CM0_SCL

SMC_I2CM0_SDA

SMC_I2CM1_SCL

SMC_I2CM1_SDA

SMC_UART0_RXD

SMC_UART0_TXD

SEP_SPI0_SCLK
SEP_SPI0_MISO
SEP_SPI0_MOSI

SEP_I2C_SCL

SEP_I2C_SDA

SPMI_SCLK

SPMI_SDATA

DWI_CLK

DWI_DO

CLK24M_OUT

NAND_SYS_CLK

AG3
AG2

AD38
AD36

A34
B34

AC36
AC38

AY16
AW16

AT20
AU20

AW19
AW15

AL6

NC

AM5

NC

AM4

AL2

CKPLUS_WAIVE=I2C_PULLUP

AM3

CKPLUS_WAIVE=I2C_PULLUP

AV21
AW20

AE36

NC

AF36

NC

AV19

BA20

IKTARA_TO_SMC_INT

PMU_TO_SEP_DOUBLE_CLICK_DET

SPMI_PMGR_TO_PMU_SCLK_R SPMI_PMGR_TO_PMU_SCLK

SPMI_PMU_BI_PMGR_SDATA

AP_TO_RACER_REF_CLK_R

AP_TO_NAND_SYS_CLK_R

I2C0_AP_SCL
I2C0_AP_SDA

I2C1_AP_SCL
I2C1_AP_SDA

I2C2_AP_SCL
I2C2_AP_SDA

I2C3_AP_SCL
I2C3_AP_SDA

I2C0_SMC_SCL
I2C0_SMC_SDA

I2C1_SMC_SCL
I2C1_SMC_SDA

I2C4_AP_SCL
I2C4_AP_SDA

49 46 20 10

49 46 20 10

I2C0_AP_SCL
I2C0_AP_SDA

D

AP I2C1

PP1V8_IO

R1410

2.2K

5%

1/32W

MF

01005

ROOM=SOC

AP I2C2

PP1V8_IO

R1420

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

R1411

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1421

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

BI

OUT

IN

IN
IN

50

29 28 27 17 16 14 10 8 7 6 5

49 46 20 10

49 46 20 10

49 33 10

49 33 10

49 33 10

50 10

50 10

50 42 10

50 42 10

50 47 23 22 21 10

50 47 23 22 21 10

48 10

48 10

47 4

49 33 10

I2C1_AP_SCL
I2C1_AP_SDA

29 28 27 17 16 14 10 8 7 6 5

I2C2_AP_SCL

50 10

I2C2_AP_SDA

50 10

43 35 34 32 30

43 35 34 32 30

AP I2C3

PP1V8_IO

R1430

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

R1431

2.2K

5%

1/32W

MF

01005

ROOM=SOC

1

2

C

10

10

29 28 27 17 16 14 10 8 7 6 5

20

IN

50 42 10

50 42 10

I2C3_AP_SCL
I2C3_AP_SDA

43 35 34 32 30

SMC I2C

48 47 46 38 22 20 17 14 12 10

R1482

0.00

BI

20 4

1/32W
01005

21

0%
MF

ROOM=SOC

OUT

20

50 47 23 22 21 10

50 47 23 22 21 10

I2C0_SMC_SCL
I2C0_SMC_SDA

48 47 46 38 22 20 17 14 12 10

R1481

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_RACER_REF_CLK

OUT

50

I2C1_SMC_SCL

48 10

I2C1_SMC_SDA

48 10

R1480

0.00

0%

1/32W

MF

01005

ROOM=SOC

21

AP_TO_NAND_SYS_CLK

OUT

16

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_S2

50 49

PP1V8_S2

50 49

AP I2C4

PP1V8_IO

R1440

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1450

4.7K

5%

1/32W

MF

01005

ROOM=SOC

R1470

4.7K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

1

2

R1441

2.2K

5%

1/32W

MF

01005

ROOM=SOC

R1451

4.7K

5%

1/32W

MF

01005

ROOM=SOC

R1471

4.7K

5%

1/32W

MF

01005

ROOM=SOC

1

2

1

2

B

1

2

A

335S00234

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

1 CRITICAL COMMON

WLCSP U1490

TABLE_ALT_HEAD

PART NUMBER

335S00234

BOM_TABLE_ALTS

U1490 U1490335S00233

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

BOM OPTIONCRITICAL

TABLE_5_HEAD

TABLE_5_ITEM

29 28 27 17 16 14 10 8 7 6 5

43 35 34 32 30

PP1V8_IO

1

C1490

0.47UF

20%

6.3V

2

X5R
01005

ROOM=SOC

VCC

U1490

SCL SDA

WLCSP

OMIT_TABLE

VSS

ROOM=SOC

CRITICAL

B2 A1

I2C4_AP_SCL

10

I2C4_AP_SDA

10

A2B1

I2C4_AP_SDA
I2C4_AP_SCL

10

10

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Serial

SIZE

D

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

051-02221

REVISION

9.0.0

BRANCH

evt-1

PAGE

14 OF 80

SHEET

10 OF 51

8

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67

35 4

2

.

1

678

3 245

1

D

C

43

28

50

50

50

50

28

50

50

50

50

50

5 4

50

20

50

50

50 48 20

20

50

50

D

SOC - GPIO INTERFACES

U1000

TMIT78B0-C4

WLCSP

SYM 5 OF 16

ROOM=SOC

TMR32_PWM0
TMR32_PWM1
TMR32_PWM2

UART0_RXD

UART0_TXD

UART1_CTS*
UART1_RTS*

UART1_RXD

UART1_TXD

UART2_CTS*
UART2_RTS*

UART2_RXD

UART2_TXD

UART3_CTS*
UART3_RTS*

UART3_RXD

UART3_TXD

UART4_CTS*
UART4_RTS*

UART4_RXD

UART4_TXD

UART6_RXD

UART6_TXD

UART7_RXD

UART7_TXD

D28
C30
A28

AF3
AF2

P34
L36
P36
M37

B28
B29
C28
B30

D30
B32
C32
D31

K36
M35
N36
N35

AF5
AF4

R5
P2

NC
NC

PMU_TO_AP_PRE_UVLO_L

JULIET_PMU_TO_RIGEL_STROBE_R

WLAN_TO_AP_TIME_SYNC

UART_AP_DEBUG_RXD
UART_AP_DEBUG_TXD

UART_BT_TO_AP_CTS_L
UART_AP_TO_BT_RTS_L

UART_BT_TO_AP_RXD
UART_AP_TO_BT_TXD

UART_GNSS_TO_AP_CTS_L
UART_AP_TO_GNSS_RTS_L

UART_GNSS_TO_AP_RXD
UART_AP_TO_GNSS_TXD

UART_NFC_TO_AP_CTS_L
UART_AP_TO_NFC_RTS_L

UART_NFC_TO_AP_RXD
UART_AP_TO_NFC_TXD

UART_WLAN_TO_AP_CTS_L
UART_AP_TO_WLAN_RTS_L

UART_WLAN_TO_AP_RXD
UART_AP_TO_WLAN_TXD

UART_ACCESSORY_TO_AP_RXD
UART_AP_TO_ACCESSORY_TXD

IN

IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

20 6 4

50

48

48

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

48

48

NC

NC

NC

NC

NC

NC

NC
NC

NC

AL4

T35
R36
P38
R35
N37

L37
K38
K34

L35
D33
C34
D32
D29

B33

A32

P6

P4
R4
R3
R2

T5

T4

T3

T2
U6
U4
U2

V5

V4

V3

AJ3
AJ4
AJ5

AJ6
AK3
AK4
AK5

GPIO_0
GPIO_1
GPIO_2
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_7
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37

AP_TO_DISPLAY_RESET_L

OUT

AP_TO_CAMPMU_RESET_L

OUT

AP_TO_NFC_DEV_WAKE

OUT

AP_TO_BB_COREDUMP

OUT

AP_TO_BB_RESET_L

OUT

AP_TO_BB_IPC_GPIO1

OUT

CAMPMU_TO_AP_IRQ_L

IN

AP_TO_GNSS_WAKE

OUT

AP_TO_BT_WAKE

OUT

AP_TO_SPKRAMP_TOP_RESET_L

OUT

AP_TO_NFC_FW_DWLD_REQ

OUT

AP_TO_RACER_RESET_L

OUT

BOARD_ID0

IN

SPKRAMP_TOP_TO_AP_INT_L

IN

PMU_TO_AP_BUTTON_VOL_UP_L

IN

AP_TO_BBPMU_RADIO_ON_L

OUT

AP_TO_WLAN_DEVICE_WAKE

OUT

5

4

5

5

5

5

5

5

PP1V8_IO

IN

PMU_HYDRA_TO_AP_FORCE_DFU

IN

DFU_STATUS

OUT

PP1V8_IO

IN

BOARD_ID4

IN

AP_TO_PMU_AMUX_SYNC

IN

AP_TO_BB_TIME_MARK

OUT

BB_TO_AP_RESET_DETECT_L

IN

BOARD_REV3

IN

BOARD_REV2

IN

BOARD_REV1

IN

BOARD_REV0

IN

NOSTUFF

R1500

200K

1%

1/32W

MF

01005

ROOM=SOC

21

JULIET_PMU_TO_RIGEL_STROBE

OUT

35 34

C

B

20

20

PMU_TO_AP_BUTTON_POWER_KEY_L

IN

PMU_TO_AP_BUTTON_VOL_DOWN_L

IN

AB2
AC4

B

REQUEST_DFU1
REQUEST_DFU2

A

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Professional.Repairphone

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SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/13/2016

A

SOC: GPIO & UART

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

15 OF 80

SHEET

11 OF 51

1

SIZE

D

SOC - AOP

678

3 245

1

1.8V @ 15mA MAX

D

C

AOP I2C Pull-Ups

1

R1620

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

1

R1621

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

50 49 41 38

50 49 41 38

1

R1622

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

IN

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK

I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK

PP1V8_S2

1

R1623

1.00K

5%
1/32W
MF
01005

2

ROOM=SOC

I2C1_AOP_SCL
I2C1_AOP_SDA
I2C0_AOP_SCL
I2C0_AOP_SDA

26 4

50 49

50 49 41 25 12 4

50 49 41 25 12 4

36 12

36 12

SPI_AOP_TO_IMU_SCLK

OUT

48 47 46 38 22 20 17 14 12 10

50 49

PP1V8_S2

1

C1690

4UF

20%

6.3V

2

CER-X5R
0201

1

C1691

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOCROOM=SOC

D

AP19

AP17

AP15

AP13

VDDIO18_AOP

VDDIO18_AOP

VDDIO18_AOP

VDDIO18_AOP

NC
NC

NC

NC

NC

AT11

AU14

AU13
AW10
AW11

AT16
AV11
AY10
AV12
AY11
AU16
AV16

AT17
AV13

AW12

AV14

AW13

AU17

AV15
AY13
BA11
AV17
BA10
AT18

AW14

AV18
BA12
AY14

AW7

AU10

AV8

AT14

AY8
BA8

AW8

AU11

AT15

AON_DDR_RESET*

AOP_FUNC_0
AOP_FUNC_1
AOP_FUNC_2
AOP_FUNC_3
AOP_FUNC_4
AOP_FUNC_5
AOP_FUNC_6
AOP_FUNC_7
AOP_FUNC_8
AOP_FUNC_9
AOP_FUNC_10
AOP_FUNC_11
AOP_FUNC_12
AOP_FUNC_13
AOP_FUNC_14
AOP_FUNC_15

AOP_FUNC_16
AOP_FUNC_17
AOP_FUNC_18
AOP_FUNC_19
AOP_FUNC_20
AOP_FUNC_21
AOP_FUNC_22
AOP_FUNC_23
AOP_FUNC_24
AOP_FUNC_25
AOP_FUNC_26

AOP_SPI_MISO
AOP_SPI_MOSI
AOP_SPI_SCLK

AOP_UART0_RXD
AOP_UART0_TXD

AOP_UART1_RXD
AOP_UART1_TXD

AOP_UART2_RXD
AOP_UART2_TXD

SPI SCM

AOP_PDM_CLK4

I2C0 SCM

U1000

TMIT78B0-C4

WLCSP

SYM 7 OF 16

ROOM=SOC

AOP_SWD_TCK_OUT

I2C1 SCM

AOP_PDM_CLK0
AOP_PDM_DATA0
AOP_PDM_DATA1

RT_CLK32768

AOP_SWD_TMS0
AOP_SWD_TMS1

SWD_TMS2
SWD_TMS3

AOP_I2CM0_SCL

AOP_I2CM0_SDA

AOP_I2CM1_SCL

AOP_I2CM1_SDA

DOCK_ATTENTION

DOCK_CONNECT

BA16
AW18
AW17

BA18
AV20

AY17
AT21
AC5
AC2

BA9
AV9

AV10
AW9

BA17
AY19

NC

NC

CODEC_TO_AOP_GPIO1
CODEC_TO_AOP_GPIO2

PMU_TO_AOP_CLK32K

SWD_AOP_TO_MANY_SWCLK

SWD_AOP_BI_RACER_SWDIO

SWD_AOP_BI_BB_SWDIO

SWD_AP_BI_NAND_SWDIO

I2C0_AOP_SCL
I2C0_AOP_SDA

I2C1_AOP_SCL
I2C1_AOP_SDA

HYDRA_TO_NUB_INT

HYDRA_TO_NUB_DOCK_CONNECT

IN
IN

IN

OUT

BI
BI
BI

OUT

BI

OUT

BI

IN

IN

38

38

20

48

48

50

50

50 16 4

16 4

36 12

36 12

50 49 41 25 12 4

50 49 41 25 12 4

C

14 4

26 4

26

26 4

48 47 46 38 22 20 17 14 12 10

50 28 21 20 8

26

26 4

35

50

38

20

50 41

50 41

38

49 41 38

36

50

36

AOP_TO_DDR_SLEEP1_READY

OUT

ACCEL_GYRO_TO_AOP_DATARDY

BI

SPI_AOP_TO_ACCEL_GYRO_CS_L

IN

ACCEL_GYRO_TO_AOP_INT

OUT

SPI_AOP_TO_PHOSPHORUS_CS_L

IN

PHOSPHORUS_TO_AOP_INT

OUT

ROMEO_TO_AOP_B2B_DETECT

IN

RACER_TO_AOP_INT_L

IN

AOP_TO_CODEC_RESET_L

OUT

AP_TO_MANY_BSYNC

IN

PMU_TO_AOP_IRQ_L

OUT

AOP_TO_SPKRAMP_BOT_ARC_RESET_L

IN

SPKRAMP_BOT_ARC_TO_AOP_INT_L

OUT

AOP_TO_CODEC_CLP_EN

OUT

I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT

OUT

PROX_BI_AP_AOP_INT_L

IN

HALL3_TO_AOP_IRQ_L

IN

ALS_TO_AOP_INT_L

IN

R1603

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

R1604

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

50 41 38

R1601

49.9

1/32W
01005

ROOM=SOC

21

1%
MF

49 25 4

50

26 4

26 4

50

50

50

50

50

50

COMPASS_TO_AOP_INT

IN

HALL2_TO_AOP_IRQ_L

IN

I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN

IN

SPI_IMU_TO_AOP_MISO

IN

SPI_AOP_TO_IMU_MOSI

OUT

SPI_AOP_TO_IMU_SCLK_R

UART_BB_TO_AOP_RXD

IN

UART_AOP_TO_BB_TXD

OUT

AOP_TO_WLAN_CONTEXT_A

OUT

AOP_TO_WLAN_CONTEXT_B

OUT

UART_RACER_TO_AOP_RXD

IN

UART_AOP_TO_RACER_TXD

OUT

B

38

I2S_AOP_TO_CODEC_MCLK2

OUT

R1602

33.2

1/32W
01005

ROOM=SOC

21

1%
MF

38

38

38

38

I2S_AOP_TO_CODEC_ASP2_BCLK

OUT

I2S_CODEC_ASP2_TO_AOP_DIN

IN

I2S_AOP_TO_CODEC_MCLK2_R
I2S_AOP_TO_CODEC_ASP2_LRCLK

OUT

I2S_AOP_TO_CODEC_ASP2_DOUT

OUT

BA14

AT19
AU19
BA15

BA13

AOP_I2S0_BCLK
AOP_I2S0_DIN
AOP_I2S0_MCK
AOP_I2S0_LRCK

AOP_I2S0_DOUT

B

A

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SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: AOP

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

16 OF 80

SHEET

12 OF 51

1

SIZE

D

678

SOC - CPU, GPU & SOC RAILS

1.06V @ 11.0A MAX

0.8V @ 6A MAX

0.575V @ 2.7A MAX

PP_CPU_PCORE

17 4

3 245

1

D

C

B

ROOM=SOC

C1708

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

ROOM=SOC

C1709

14UF

0402-D2X-1

1

0.7V @ 75mA MAX

PP0V7_VDD_LOW_S2

19

1.01V @ 2.1A MAX

0.735V @ 0.6A MAX

PP_CPU_SRAM

17

1.06V @ 1.1A MAX

0.80V @ 0.63A MAX

0.675V @ 0.19A MAX

PP_GPU_SRAM

17

20%
X5R

2

4V

1

C1702

4UF

20%
4V

2

X5R
0201

1

ROOM=SOC

C1704

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1710

14UF

20%

4V

X5R

0402-D2X-1

3

4

1

432

ROOM=SOC

C1705

14UF

20%

4V

X5R

1

432

ROOM=SOC

C1711

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1706

14UF

20%

4V

X5R

0402-D2X-10402-D2X-1

1

432

ROOM=SOC

C1712

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1772

14UF

20%

4V

X5R

0402-D2X-1

1

2

3

4

C1703

4UF

20%
4V

2

X5R
0201

ROOM=SOCROOM=SOC

ROOM=SOC

C1707

0402-D2X-1

1

ROOM=SOC

C1713

14UF

20%
X5R

0402-D2X-1

1

1

C1750

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

ROOM=SOC

C1773

14UF

20%

4V

X5R

0402-D2X-1

1

14UF

20%

4V

X5R

432

4V

432

432

OMIT

XW1701

SHORT-20L-0.05MM-SM

2 1

ROOM=SOC

AA14
AA16
AB11
AB13
AB15
AB17
AB19
AC20
AD15
AE14

AF20

AG9

AG15

AH10
AH12
AH14
AH16
AH18
AH20

AM15
AM17
AM19
AM21

AN16
AN18
AN20

AA12
AB18

AC9
AC14
AE20

AF14

U14

VDD_CPU

VDD_LOW

VDD_CPU_SRAM

U1000

TMIT78B0-C4

WLCSP

SYM 8 OF 16

ROOM=SOC

BUCK0_FB

VDD_GPU

VDD_ECPU

OUT

17

F25
J16
F31
G20
G22
G24
G26
J28
H11
H15
H19
H23
H31
J12
J18
J22
J24
J26
J30
L16
K17
K29
L12
L18
L22
L28
M23
L24
N22
N24
N28

AA10
U10
U12
V13
V15
Y13
Y15

1

C1730

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1732

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1737

14UF

20%

4V

X5R

0402-D2X-1

1

432

1

C1731

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1733

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1738

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1791

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1734

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1739

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1792

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1735

14UF

20%

4V

X5R

0402-D2X-1

1

432

ROOM=SOC

C1793

14UF

20%

4V

X5R

0402-D2X-1

1

3

4

2

XW1731

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

ROOM=SOC

C1736

14UF

20%

4V

X5R

0402-D2X-1

1

432

XW1790

SHORT-20L-0.05MM-SM

2 1

1

C1794

4UF

20%
4V

2

X5R
0201

ROOM=SOC

OMIT

21

ROOM=SOC

OMIT

ROOM=SOC

(Analog)

20 4

AP_CPU_PCORE_SENSE

OUT

AH21

VDD_CPU_SENSE

0.8V @ 6mA MAX

0.8V @ 6mA MAX

0.8V @ 10mA MAX

20 4

ROOM=SOC

C1781

14UF

20%

4V

X5R

0402-D2X-1

1

432

AP_VDD_GPU_SENSE

OUT

ROOM=SOC

C1782

14UF

20%

4V

X5R

0402-D2X-1

1

432

N26
H13
H17
H21
H25
K11
K19

K23
G30
M29

N23

VDD_GPU_SRAM

VDD_GPU_SENSE

VDD_FIXED_CPU

VDD_FIXED_PLL_GPU
VDD_FIXED_PLL_SOC

VDD12_PLL_CPU
VDD12_PLL_GPU
VDD12_PLL_SOC

W14
K21

L20

W16
L21
M20

1

C1720

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1721

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

PP0V8_SOC_FIXED_S1

(Analog)

1.2V @ 7mA MAX (CPU)

1.2V @ 7mA MAX (GPU)

1.2V @ 20mA MAX (SOC)

PP1V2_SOC

1

C1722

0.1UF

20%

6.3V

2

X5R-CERM
01005

ROOM=SOC

1

C1723

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

17 14 9 8 7 6

19 14 9 7

1.06V @ 18.3A MAX

0.8V @ 10.6A MAX

0.575V @ 3.4A MAX

PP_GPU

BUCK1_FB

BUCK11_FB

1.06V @ 4.3A MAX

0.8V @ 2.8A MAX

0.575V @ 1.4A MAX

PP_CPU_ECORE

OUT

17 4

18

0.765V @ 4.9A MAX

0.635V @ 2.6A MAX

PP_SOC_S1

1

C1760

4UF

20%
4V

2

X5R
0201

ROOM=SOC

AA9
AA18
AA22
AA24
AA28
AA30
AB21
AB25
AB27
AC22
AC24
AC28
AC30

AD9
AD21
AD25
AD27
AD29

20 18

AE22
AE24
AE28
AF25
AF27

AG22
AG24
AG28

AH25
AH27

AJ16
AJ18
AJ22
AJ24

AJ28
AK13
AK15
AK19
AK21
AK25
AK27

AL12

AL16

AL18

AL22

AL24

AL28

AL30

AM13
AM25

AN12
AN22
AN24

F22

VDD_SOC

1

C1761

4UF

20%
4V

2

X5R
0201

ROOM=SOC

ROOM=SOC

C1762

14UF

20%

4V

X5R

0402-D2X-1

1

432

U1000

TMIT78B0-C4

WLCSP

SYM 9 OF 16

ROOM=SOC

ROOM=SOC

C1763

14UF

20%

4V

X5R

0402-D2X-1

1

432

VDD_SOC_SENSE

ROOM=SOC

C1764

14UF

20%

4V

X5R

0402-D2X-1

1

432

G13
J20
L19
M13
M15
M21
N10
N12
N16
N18
N29
P13
P15
P19
P21
P25
P27
R10
R12
R16
R18
R22
R24
R28
T13
T15
T19
T21
T25
T27
U16
U18
U22
U24
U28
U30
V19
V21
V25
V27
W18
W22
W24
W28
W30
Y19
Y25
Y21
Y27

P23

SHORT-20L-0.05MM-SM

NO_XNET_CONNECTION

OMIT

XW1760

21

ROOM=SOC

TP_SOC_SENSE

OUT

BUCK2_FB

4

17

D

17 17

OUTOUT

C

B

A

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Power (1/3)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

35 4

2

BRANCH

evt-1

PAGE

17 OF 80

SHEET

13 OF 51

1

SIZE

D

D

C

B

9 8 7 6
17 14 13

34 32

27 17
8 7 6 5
16 14 10
30 29 28

43 35

SOC - POWER SUPPLIES

0.8V @ 0.9A MAX

PP0V8_SOC_FIXED_S1

ROOM=SOC

C1801

1.8V @ 60mA MAX

PP1V8_IO

1

C1810

26UF

20%
4V

2

X5R
0402-0.1MM

ROOM=SOC

1

C1802

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

2

1

C1811

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

C1803

4UF

20%
4V
X5R
0201

ROOM=SOC

1

2

1

C1804

4UF

20%
4V

2

X5R
0201

ROOM=SOC

C1812

4UF

20%

6.3V
CER-X5R
0201

ROOM=SOC

0402-D2X-1

1

1

C1805

2

ROOM=SOC

1

C1813

4UF

20%

6.3V

2

CER-X5R
0201

ROOM=SOC

14UF

20%

4V

X5R

4UF

20%
4V
X5R
0201

432

AA20
AA26

AB9
AB23
AB29
AC26
AD23
AD31
AE26

AF23
AF29

AG26

AH23
AH29

AJ14
AJ20

AJ26
AK17
AK23

AL14

AL20

AL26

AM11
AM23

AP11
AP21
AP24

F19

F23
M11
M17

N14
N20
P11
P17
P29
R14
R20
R26

T11

T17

T23

T31

U20
U26

AP23
AP25

AB31

V31
Y31

F21

D23

VDD_FIXED

VDDIO18_GRP1

VDDIO18_GRP2

VDDIO18_GRP3

678

U1000

TMIT78B0-C4

WLCSP

SYM 10 OF 16

ROOM=SOC

VDD_FIXED_PLL_DDR0
VDD_FIXED_PLL_DDR1
VDD_FIXED_PLL_DDR2
VDD_FIXED_PLL_DDR3

U1000

TMIT78B0-C4

WLCSP

SYM 12 OF 16

ROOM=SOC

VDD18_TSADC_CPU0
VDD18_TSADC_CPU1
VDD18_TSADC_CPU2

VDD18_TSADC_CPU3
VDD18_TSADC_GPU0
VDD18_TSADC_SOC0

VDD18_TSADC_SOC1
VDD18_TSADC_SOC2

LPADC_REF_P

LPADC_REF_M

18 14

V17
V23
V29
W20
W26
Y9
Y17
Y23
Y29

BA19
AY20

AK11
AJ29
D8
R29

T12
AF21
AJ9
Y16

G21
AJ12

AD30
J31

0.6V @ 262mA MAX

PP0V6_VDDQL_S1

1

C1870

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

0.8V @ 8mA MAX

PP0V8_SOC_FIXED_S1

1.06V - 1.17V @ (Inc in VDD2)

42 19 17 14

19 13 9 7

PP1V1_S2

(Analog)

1.2V @ 16mA MAX

PP1V2_SOC

0.875V @ 0.8A MAX

0.730V @ 0.51A MAX

0.600V @ 0.35A MAX

PP_DCS_S1

17

1.8V @ 5.3mA MAX (CPU)

1.8V @ 1.1mA MAX (GPU)

1.8V @ 3.3mA MAX (SOC)

1

C1830

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1831

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

2

Place caps on SoC Corners

PP1V2_LPADC

19

OMIT

XW1870

SHORT-20L-0.05MM-SM

LPADC_GND

(Analog)

VDDQL Voltage Sense ->

1

C1860

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1861

4UF

20%
4V

2

X5R
0201

ROOM=SOC

Place caps on SoC Corners

ROOM=SOC

17 14 13 9 8 7 6

1

C1862

4UF

20%
4V

2

X5R
0201

ROOM=SOC

DCS Voltage Sense ->

PP1V8_IO

43 35 34 32

C1832

4UF

20%
4V
X5R
0201

ROOM=SOC

21

30 29 28 27 17 16 14 10 8 7 6 5

1

C1833

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1863

4UF

20%
4V

2

X5R
0201

ROOM=SOC

NC

NC

AD1
AF1
AH1
AK9
AP9
AT1
AV1

AD39

AF31

AF39
AK31
AP39

AT39
AV39

D1

F1

F9
H1
K9

T1
V1
C4

D39
F39
K31
P31
P39
T39
V39

AR6

AN34

E6

G34

AJ11

AK29

D9

T29

AJ10

AP10

AE30
AK30

F10
L10

A4

K30
R30

VDDQL_DDR0

VDDQL_DDR1

VDDQL_DDR2

VDDQL_DDR3

VDDIO11_RET_DDR0
VDDIO11_RET_DDR1
VDDIO11_RET_DDR2
VDDIO11_RET_DDR3

VDDIO12_PLL_DDR0
VDDIO12_PLL_DDR1
VDDIO12_PLL_DDR2
VDDIO12_PLL_DDR3

VDD_DCS_DDR0

VDD_DCS_DDR1

VDD_DCS_DDR2

VDD_DCS_DDR3

U1000

TMIT78B0-C4

WLCSP

SYM 11 OF 16

ROOM=SOC

3 245

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_RET*
DDR1_RET*
DDR2_RET*
DDR3_RET*

DDR0_ZQ
DDR3_ZQ

DDR0_SYS_ALIVE
DDR1_SYS_ALIVE
DDR2_SYS_ALIVE
DDR3_SYS_ALIVE

VDD1

VDD2

PP0V6_VDDQL_S1

18 14

AP5
AN35
E5
H35

AR5
AM35
E3
G35

AJ2
N38

AP6
AM34
E4
H34

AB3

AB37

AW3

AW37
B3
B37
Y3
Y37

AA2
AA38
AC39
AH39
AJ1
AK39
AM1
AN39
AP1
AV2
AV37

AW2

AW38
C2
C3
C38
D38
H39
J1
K39
M1
N39
P1
W1

DDR0_RREF
DDR1_RREF
DDR2_RREF
DDR3_RREF

DDR0_ZQ
DDR3_ZQ

1

C1840

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1850

4UF

20%
4V

2

X5R
0201

ROOM=SOC

DDR IMPEDANCE CONTROL

1

R1860

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1861

240

1%
1/32W
MF
01005

2

ROOM=SOC

AOP_TO_DDR_SLEEP1_READY

SYSTEM_ALIVE

1

C1841

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1851

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

C1842

2.2UF

20%

6.3V

2

X5R-CERM
0201

ROOM=SOC

1

C1852

4UF

20%
4V

2

X5R
0201

ROOM=SOC

1

R1862

240

1%
1/32W
MF
01005

2

ROOM=SOC

IN

IN

1

2

1

2

1

R1863

240

1%
1/32W
MF
01005

2

ROOM=SOC

12 4

23 20 16

C1843

2.2UF

20%

6.3V
X5R-CERM
0201

ROOM=SOC

C1853

4UF

20%
4V
X5R
0201

ROOM=SOC

1

R1870

240

1%
1/32W
MF
01005

2

ROOM=SOC

1

R1871

240

1%
1/32W
MF
01005

2

ROOM=SOC

1.8V @ 200mA MAX

PP1V8_S2

1.06V - 1.17V @2.2A MAX

PP1V1_S2

1

D

C

50 49

42 19 17 14

48 47 46 38 22 20 17 14 12 10

B

AF9

A

V9

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

VDDIO18_GRP4

VDD18_EFUSE1
VDD18_EFUSE2

VDD18_FMON

VDD18_LPOSC

67

H12
AT6
AN13
AN19

1

C1880

56PF

5%
25V

2

NP0-C0G-CERM
01005

ROOM=SOC

1.8V @ 1mA MAX

PP1V8_IO

PP1V8_LPOSC_S2

1

C1881

0.47UF

20%

6.3V

2

X5R
01005

ROOM=SOC

43 35 34 32

30 29 28 27 17 16 14 10 8 7 6 5

R1880

300

5%

1/32W

MF

01005

ROOM=SOC

1.8V @ 1mA MAX

21

PP1V8_S2

A

SYNC_MASTER=test_mlb

50 49

48 47 46 38 22 20 17 14 12 10

PAGE TITLE

SYNC_DATE=10/17/2016

SOC: Power (2/3)

SIZE

D

Apple Inc.

DRAWING NUMBER

051-02221

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

35 4

2

BRANCH

evt-1

PAGE

18 OF 80

SHEET

14 OF 51

1

SOC - POWER SUPPLIES

678

3 245

1

D

C

B

A1
A2
A3

A5
A11
A18
A27
A29
A31
A33
A35
A36
A37
A38
A39

AA1

AA6
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AA29
AA31
AA34
AA36
AA39

AB1

AB5
AB10
AB12
AB14
AB16
AB20
AB22
AB24
AB26
AB28
AB30
AB35
AB39

AC1
AC3

AC6
AC15
AC21
AC23
AC25
AC27
AC29
AC31
AC34
AC35

AD4

AD6
AD14
AD20
AD22
AD24
AD26
AD28
AD34
AD35
AD37

AE1
AE3
AE5

AE9
AE15
AE21
AE23
AE25
AE27

U1000

TMIT78B0-C4

WLCSP

SYM 13 OF 16

ROOM=SOC

AE29
AE31
AE34
AE39
AF6
AF15
AF22
AF24
AF26
AF28
AF30
AF35
AF37
AG1
AG6
AG14
AG20
AG23
AG25
AG27
AG29
AG34
AG39
AH3
AH5
AH9
AH11
AH13
AH15
AH17
AH19
AH22
AH24
AH26
AH28
AH35
AH37
AJ13

VSSVSS

AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ34
AJ35
AJ39
AK1
AK2
AK6
AK10
AK12
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK34
AK35
AK36
AL1
AL3
AL5
AL11
AL13
AL15
AL17
AL19
AL21
AL23
AL25
AL27
AL29
AL31

AL34
AL35
AL36
AL39

AM2

AM6
AM12
AM14
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM36
AM37
AM38
AM39

AN1
AN2
AN3
AN4
AN5

AN6
AN11
AN17
AN21
AN23
AN25
AN29
AN31
AN36
AN37
AN38

AP2

AP3

AP4
AP12
AP16
AP18
AP20
AP22
AP28
AP34
AP35
AP36
AP37
AP38

AR1

AR2

AR3

AR4
AR37
AR38
AR39

AT2
AT3
AT4

AT5
AT28
AT29
AT31
AT32
AT33
AT37
AT38

AU1

AU2
AU12
AU15
AU18
AU21
AU24
AU25
AU26
AU27

U1000

TMIT78B0-C4

WLCSP

SYM 14 OF 16

ROOM=SOC

VSS VSS

AU29
AU3
AU4
AU5
AU6
AU9
AU31
AU33
AU34
AU35
AU36
AU37
AU38
AU39
AV3
AV4
AV24
AV26
AV28
AV30
AV32
AV34
AV36
AV38
AW1
AW4
AW24
AW28
AW30
AW32
AW34
AW36
AW39
AY1
AY2
AY3
AY5
AY7
AY9
AY12
AY15
AY18
AY21
AY23
AY25
AY27
AY28
AY29
AY31
AY33
AY35
AY37
AY38
AY39
B1
B2
B4
B5
B11
B18
B27
B35
B36
B38
B39
BA1
BA2
BA3
BA5
BA7
BA23
BA25
BA26
BA29
BA31
BA33
BA35
BA37
BA38

<- DDR Vss V Sense

NC

BA39

C1
C5
C6
C7
C8

C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C29
C31
C33
C35
C36
C37
C39
D10
D14

D2

D3

D4

D5

D6

D7
D22
D24
D25
D26
D27
D34
D35
D36
D37

E1

E2
E34
E35
E36
E37
E38
E39
F12
F14
F18

F2

F3

F4

F5

F6
F20
F24
F26
F30
F34
F35
F36
F37
F38

G1

U1000

TMIT78B0-C4

WLCSP

SYM 15 OF 16

ROOM=SOC

VSSVSS

G2
G3
G6
G11
G15
G17
G19
G23
G25
G31
G36
G37
G38
G39
H2
H4
H5
H14
H16
H18
H20
H22
H24
H26
H30
H36
H37
H38
J2
J3
J6
J11
J17
J19
J21
J23
J25
J27
J29
J34
J35
J36
J37
J38
J39
K1
K2
K5
K6
K10
K12
K16
K18
K20
K22
K24
K28
K35
K37
L1
L2
L3
L6
L9
L11
L17
L23
L29
L34
L38
L39
M10
M12
M14
M16
M18

M19

M2
M5

M6
M22
M24
M28
M34
M36
M38
M39

N1
N2
N3
N4
N5
N6

N9
N11
N13
N15
N17
N19
N21
N25
N27
N34

P3

P5

P10
P12
P14
P16
P18
P20
P22
P26
P28
P30
P35
P37

R1

R6
R11
R13
R15
R17
R19
R21
R23
R25
R27
R31
R34
R39

T6
T10
T14
T16
T18
T20
T22
T24
T26
T28
T30
T34
T36
T38

U1
U3
U5

U9
U11
U13
U15
U17
U19

VSS

U1000

TMIT78B0-C4

WLCSP

SYM 16 OF 16

ROOM=SOC

VSS_CPU_SENSE

VSS_SENSE

U21
U23
U25
U27
U29
U31
U34
U39
V6
V14
V16
V18
V20
V22
V24
V26
V28
V30
V35
V37
W2
W3
W6
W9
W13
W15
W17
W19
W21
W23
W25
W27
W29
W31
W34
W37
W38
W39
Y1
Y5
Y14
Y18
Y20
Y22
Y24
Y26
Y28
Y30
Y35
Y39

AG21
P24

TP_VSS_CPU_SENSE

TP_VSS_SENSE

OUT

OUT

D

C

4

4

B

A

8

PDF Watermark Remover DEMO : Purchase from www.PDFWatermarkRemover.com to remove the watermark

SYNC_MASTER=test_mlb

PAGE TITLE

SYNC_DATE=10/17/2016

A

SOC: Power (3/3)

DRAWING NUMBER

051-02221

Apple Inc.

REVISION

9.0.0

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

67

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BRANCH

evt-1

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SIZE

D