How it Works
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IMG5
User Manual
74 pgs2.64 Mb0

Apple IMG5 User Manual

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
78
6
5
4
12/13/04
3
ECN
ZONE
I
REV
355571
DESCRIPTION OF CHANGE
PRODUCTION RELEASED
12
CK APPD
DATE
12/13/04
ENG APPD
?
DATE
D
PAGE
10 11 11 13*
C
14 16 17 18 21* 22 23 24 25* 26 27 28 29
B
30 31 32 33 34 35 36 37 38 40 44 45 46
A
48 49 50
8
PDF
1 2 3 4 55 6 7 8 9
1 2 3 4
6 7 8 9
10
TABLE OF CONTENTS SYSTEM BLOCK DIAGRAM POWER BLOCK DIAGRAM REVISION HISTORY TABLE ITEMS FUNC TEST POWER CONNECTOR / POWER ALIAS SIGNAL ALIAS
2.5V VREG
1.2V VREG
CIRCUIT
3.3V/5V PWRON SWITCHING 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
SMU CPU LOGIC ANALYZER CONNECTOR FAN 1, 2 AND SYSTEM TEMP SENSOR FAN 3 AND HARD DRIVE TEMP SENSOR I2C CONNECTIONS INDICATOR LED U3LITE CORE SHASTA CORE U3LITE MISC SHASTA SERIAL PULSAR POWER PULSAR CLOCKS U3LITE APPLE PI NEO APPLE PI CPU STRAPS NEO POWER & BYPASS CPU BYPASS CPU VREG CPU VREG CPU VREG OUTPUT CAPS CPU DIODE CONDITIONER U3LITE MEMORY SERIES TERMINATION DIMMS PARALLEL TERMINATION PARALLEL TERMINATION VTT VREG U3LITE AGP GPU AGP GRAPHICS VREGS (GPU CORE & 1.5V)
* PAGES WHERE MASTER PAGE IS IN A DIFFERENT SCHEMATIC
67
BLOCK
TOP
PROCESSOR
MEMORY
GRAPHICS
5
PAGE51PDF
42 52 53 54 55 56 57 58 59 60 62* 64 73 74* 75* 76 77* 80* 83 84* 87 88* 90 91* 92 94 95* 96* 98*
100* 101* 102* 103*
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
4
CIRCUIT
EXTERNAL TMDS TRANSMITTER GPU FRAME BUFFER FRAME BUFFER TERMINATION GRAPHICS DDR SDRAM A GRAPHICS DDR SDRAM B GPU STRAPS GPU DAC & CLOCKS GPU DVI & STRAPS EXT VGA & TMDS U3LITE HYPERTRANSPORT SHASTA HYPERTRANSPORT HYPERTRANSPORT LA CONNECTORS PCI SERIES TERMINATION SHASTA PCI BOOT ROM AIRPORT EXTREME USB2 PCI SHASTA DISK DISK CONNECTORS SHASTA ETHERNET ETHERNET PHY & CONNECTORS SHASTA FIREWIRE FIREWIRE A PHY & CONNECTORS USB HOST INTERFACE USB DEVICE INTERFACE MODEM CONNECTOR PCM3052 AUDIO CODEC LINE IN AMP LINE OUT AMP SPEAKER AMP AUDIO CONNECTORS AUDIO POWER SUPPLIES S/PDIF TRANSMITTER
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
DRAFTER
ENG APPD
QA APPD
RELEASE
3
METRIC
MATERIAL/FINISH
NOTED AS
APPLICABLE
DESIGN CK
MFG APPD
DESIGNER
NONE
SIZE
2
Apple Computer Inc.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SCH,MLB,IMG5
DRAWING NUMBER
D
051-6482
BLOCK
GRAPHICS
HT
PCI
DISK
ETHERNET
FIREWIRE
USB
MODEM
AUDIO
SHT
1
REV.
1
I
OF
D
C
B
A
103
FREQUENCIES LISTED ARE MAXIMUM DATA TRANSFER RATES SUPPORTED BY U3LITE
D
U5400, U5401
FRAME
BUFFER A
PAGE 54
U2600
PULSAR
POWER
C
PAGE 26
B
CLOCKS
PAGE 27
EDUCATION: NOT USED GOOD,BETTER,BEST: HARD DRIVE
FOR DEVELOPMENT ONLY
EDUCATION: HARD DRIVE
GOOD,BETTER,BEST: OPTICAL
78
64-BIT
FRAME BUFFER
2.6V/540MHZ
JXXXX
SATA
CONNECTOR
PAGE 83
J8302
SATA DEV
CONNECTOR
PAGE 83
J8301
UATA
CONNECTOR
PAGE 83
J5900, J5901
J5902, J5903
17",20" INVERTER
TMDS
EXT VGA
PAGE 59
U4900
GPU
NV18B/NV34
PAGE 49
U5500, U5501
FRAME
BUFFER B
PAGE 55
SATA/150
1.2V/1.5GHZ
SATA/150
1.2V/1.5GHZ
UATA/133
3.3V/133MHZ
64-BIT
FRAME BUFFER
2.6V/540MHZ
6
32-BIT
8X AGP
0.8V/533MHZ
4X = 1.5V I/O = 1.5V
U2900
CPU
NEO 10S
PAGE 29
APPLE PI
PAGE 28
U3
AGP
U3LITE
PAGE
48
HYPERTRANSPORT
MISC
PAGE 24
I2C
PAGE 18
SATA1 SATA2
PAGE 80 PAGE 80
ETHERNET FIREWIRE
PAGE 84
GMII (3.3V/125MHz)
8-bit TX & 8-bit RX
HYPERTRANSPORT
SATA
U2300
UATA
CORE
PAGE 23
PAGE 88
32-BIT
APPLE PI
ELASTIC INTERFACE
1.2V/900MHZ
CORE
PAGE 22
PAGE 60
J6400
J6401
J6402
HT DEBUG
PAGE 64
PAGE 62
SHASTA
NCs
PAGE 91
1394 OHCI (3.3V/98MHz)
8-bit TX/RX
5
64/128-BIT MAIN MEMORY
2.6V/400MHZ
PAGE 37
MAIN MEMORY
8-BIT
HYPERTRANSPORT
1.2V/400MHZ
CONTROL = 2.5V
I2S
PAGE 25
SCCA SCCB I2S1
PCI
PAGE 74
PAGE 25
GPIO/PCI64
I2S2I2S0
SERIES
TERM
PAGE 38
U7500
BOOTROM
32-bit PCI (5V-3.3V/33MHz)
4
J4000 J4001
DIMMS
PAGE 40
J7600
AIRPORT EXTREME
CONNECTOR
PAGE 76
J9401
CTL-LESS / SOFT MODEM CONNECTOR
PAGE 94
PARALLEL
PAGES 44&45
123
PAGE 91
U7700
USB 2.0
uPD720101
PAGE 77PAGE 75
TERM
USB
PCI
3
45
J9210/J9220/J9230
USB
CONNECTORS
PAGE 92
J9400
MICRODASH MODEM
CONNECTOR
PAGE 94
J9240
BLUETOOTH CONNECTOR
PAGE 92
U1300
SMU
PAGE 13
To Shasta
SCCA
12
U1301
RTC
PAGE 13
D
C
B
U9500
S/PDIF
AUDIO CODEC
U8700
10/100 ETHERNET
BCM5221
A
4 Diff pairs
8
PAGE 87
J8700
ETHERNET CONNECTOR
PAGE 87
67
U9000
FIREWIRE A
802A
PAGE 90 0
J9000, J9001
FIREWIRE A CONNECTORS
PAGE 90
1
2 Diff pairs
5
PCM3052
LINE IN
AMP
PAGE 97
J9800
LINE IN
CONNECTOR
PAGE 98
PAGE 95
J9802
MIC
CONNECTOR
PAGE 98
LINE OUT
AMP
PAGE 97
SPEAKER
AMP
PAGE 97
4
OPTICAL OUT J9803
COMBO OUT CONNECTOR
PAGE 98
LINE OUT
J9801
SPEAKER
CONNECTOR
PAGE 98
SYSTEM BLOCK DIAGRAM
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
APPLE COMPUTER INC.
3
2
D
NONE
SHT
2
1
REV.
OF
103
A
I
78
6
5
4
3
12
D
C
J700 PAGE 7
PP24V_RUN
FW CONN
20" LCD INVERTER
PP5V_RUN_AUDIO
LINEAR
PAGE 99
5V
HP/LINEOUT AMP
PP4V5_RUN_AUDIO
LINEAR
PAGE 99
4.5V
AUDIO CODEC
PP12V_RUN
20" PANEL POWER
20" LCD INVERTER
PAGE 33
0.8~1.2V
CPU CORE SWITCHER
SC2643VX*1 SC1211*4
POWER CONNECTOR
PP5V_RUN
HDD & OPTICAL
31
8 7
ALIAS
6
CPU_AVDD_EN
PP2V5_RUN_CPU_AVDD
31
LINEAR
PAGE 31
2.8V
=PP5V_RUN_CPU
GPUL
CPU AVDD
U3LITE CORE
SWITCHER
PAGE 22
1.53V
IRU3037CS
U3LITE CORE
PP5V_ALL
PP5V_PWRON FET SWITCH
PAGE 11
5V
USB CONN
UDASH MODEM
PP2V5_PWRON
SWITCHER
PAGE 9
2.62V
IRU3037CS
PAGE 11
3.3V
PP3V3_PWRON
PAGE 11
3.3V
SHASTA HT
DDR DIMM
PP3V3_ALL
LINEAR
FW PHY
SMU
FET SWITCH
ENET PHY
USB2 HOST MODEM & BT
PP2V5_PWRON
IN
SYS_POWERUP_L
PP3V3_RUN
GPU CORE SWITCHER
PAGE 50
1.6/1.4V
PCI BUS
AUDIO CODEC
IRU3037CS
NV18B/NV34
PP1V2_PWRON
FET SWITCH
PAGE 10
10
10 10
PP1V2_SHASTA_CORE
SWITCHER
PAGE 10
1.2V
PWRON_SD
PWRON_DISK_SB
PULSAR_POWER_DOWN MAKE_BASE=TRUE
TURN_ON_SHASTA_CORE_L
TURN_ON_PP1V2_L
=PULSAR_POWER_DOWN
27
5V
IRU3037ACS
SHASTA CORE
IN IN
IN
PPVCORE_PWRON_SB
6
10
PP1V2_RUN FET SWITCH
PAGE 10
IN
HT BUS API BUS
SYS_POWERUP_L
POWER SEQUENCE PIN
SMU_PWRSEQ_P1_4
SMU_PWRSEQ_P1_0
SMU_PWRSEQ_P1_1
SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6
SMU_PWRSEQ_P1_2
11
R330
100K
21
COMPARE_SB_CORE
5%
1
402
C330
MF
0.01UF
20% 16V
2
CERM 402
13
13
13
13
13
13
RAIL_CTL_NEG
SMU
PP3V3_ALL
(PWR_GOOD_SB_CORE)
(PWR_GOOD_PP2V5)
(TURN_ON_VTT)
1
R331
10K
5% 1/16W MF 402
2
PWR_GOOD_SB_CORE
3
8
V+
U1100
GND
9
12
LM339A
SOI
14
D
C
PP2V5_RUN FET SWITCH
PAGE 9
B
RAM TERM
GRAPHIC FB
PP1V25_RAM_VTT
LINEAR
PAGE 46
1.25V
46
IN
RAM VTT
TURN_ON_VTT
PP1V5_PWRON
LINEAR
PAGE 50
1.5V
PP1V5_RUN
POWER SW
PAGE 50
PULSAR CORE
AGP BUS
R340
100K
5%
MF
402
PP5V_ALL
1
R342
150K
5% 1/16W MF 402
2
PS_2V_REF
21
1
C340
0.01UF
20% 16V
2
CERM 402
COMPARE_PP2V5
1
R343
100K
5% 1/16W MF 402
2
6
U1100
7
GND
3
LM339A
SOI
V+
12
PP3V3_ALL
1
R341
10K
5% 1/16W MF 402
1
2
PWR_GOOD_PP2V5
B
POWER BLOCK DIAGRAM
A
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
D
DRAWING NUMBER
NONE
051-6482
SHT
3
REV.
OF
103
A
I
8
67
5
4
3
2
1
78
6
5
4
3
12
DATE
02/27/04
03/05/04
D
03/24/04
04/12/04
04/12/04
04/13/04
C
04/14/04
04/21/04
04/21/04
B
04/26/04
04/27/04
04/29/04
04/30/04
05/03/04
A
05/05/04
DESCRIPTION
EVT3 RELEASE (REV 20)
GPU XTAL - C5700 AND C5719 -> 27PF FROM 22PF
I2C A - U1800 MOVED BACK TO PWRON RAIL HEATSINK ASSEMBLY - NEW PART NUMBERS
FAN 3 - STUFFING ON ALL CONFIGS FIREWIRE POWER DU JOUR
EVT3 - BOM REV 21 RELEASE
MASTER PAGE SYNC
EVT3 REWORKS
NOSTUFF R807 - SMU_BOOT_SCLK IS ALSO CPU_VID<5>
NOSTUFF R3691 & R828 - DIODE CAL RETURN PATH
MOVED MARTY SERIAL 0 OHM RESISTORS TO COMMON BOM SMU - ADDED QREQ
GPU - ADDED DECOUPLING TO GPU_VTT FOR NV36 INVERTER CONTROL - ADDED AND GATES U5850 & U5851 TO CONTROL LCD_PWM AND FPD_PWR_ON
CHECKIN 21001
CPU - CHANGED CPU SYMBOL TO NEO-10S-REV2-76C (OLD IS OBSOLETE)
SCHEMATIC REUSE - NETS THAT NEED ALIASES START WITH = (DOES NOT EFFECT NETLIST) 3PHASE CPU POWER SUPPLY - ADDED TABLE FOR R3328
INVERTER - ADDED RESISTORS R5860-1 AND CHANGED R5808-9 TO 47OHM
TMDS POWER - ADDED R5960 AND D5914 DIODE CAL - ADDED OPTION TO POWER FROM PP5V_ALL AND PP3V3_ALL RAILS
CHECKIN 21002
MASTER PAGE SYNC - IN SYNC ON ALL PAGES EXCEPT PAGE 13 EMI - REMOVED EMI700 & EMI9400
QREQ_L HACK - ADDED U2850, C2850, R2850, R2851
VOLTAGE SENSE FROM 12V - ADDED R3360, R3361 CHECKIN 21003
MAIN MEMORY DQS PARALLEL TERM - CHANGED TO 100 OHM (LIKE EVT3)
I/O ALIGNMENT FIXTURE - ADDED 815-8008 TO MLB BOM
DIMM CONNECTORS - UPDATED 30 DEGREE SYMBOL GREEN LED - ADDED KINGBRIGHT AS ALTERNATE
VTT - NO LONGER POWER SEQUENCED - NO STUFFED R4610 AND R4603
HD TEMP SENSOR - STUFFED ON ALL CONFIGS SMU PULLUPS CHANGES - R1312 -> 2K; R1311 -> 10K
SDF804 -> ZH804 CHECKIN 21004
RAM PARALLEL TERM - DQ RPAKS CHANGED TO 68 OHM
STROBE RESISTORS CHANGED TO 120 OHM
EVT3A RELEASE (REV 22) CHECKIN 22001 - FIXING DIMM SYMBOL
CHECKIN 22002 - FIXING DIMM SYMBOL AGAIN
MASTER PAGE SYNC - NOW IN SYNC ON ALL SHAREABLE PAGES
MAIN MEMORY - DQ SERIES TERM CHANGED TO 22 OHM MAIN MEMORY - DQ PARALLEL TERM CHANGED TO 82 OHM
FIREWIRE POWER - NEW CURRENT LIMITING RESISTOR NOSTUFFING FIREWIRE PORT POWER "CHOICE A" CIRCUIT
INPUT VOLTAGE SENSE - CHANGED DIVIDER VALUES
INPUT CURRENT SENSE - CHANGED R3343 TO 0.025 OHM 1% RESISTOR CHECKIN 22003
SMU_SUSPENDREQ - STUFFED LEVEL SHIFTER
CPU POWER SUPPLY - NOSTUFFED R3305
CHANGED R3304 TO 116S1000 CHANGED C3304-7 TO 132S4733
EVT3A BOM RELEASE REV 23
USB POWER CAPS - NOSTUFFED C9211, C9221, C9231 PULSAR_POWER_DOWN CONNECTED TO SMU_PWRSEQ_P1_4
SW703 CHANGED TO 516S0221
MASTER PAGE SYNC CHECKIN 23001
MASTER PAGE SYNC - AUDIO AND SMU CHANGES
SUSPENDACK LEVEL SHIFTER - REPLACED Q2407 AND Q2408 WITH Q2420 SN7002DW
I2C_CPU_A - ADDED Q1801 TO LEVEL SHIFTER ADDED POWER SUPPLY TEMP SENSOR
Q3000 ADDED TO LEVEL SHIFT / INVERT CPU_BYPASS AND CPU_HRESET CURRENT SENSE - CHANGED R3345 FROM 121K TO 73.2K
CHECKIN 23002
QREQ CIRCUITS MOVED TO PWRON RAIL
I2C UPDATE NB_SUSPENDACK_L NOW USED U700 TO LEVEL SHIFT - OLD CIRCUIT REMOVED
DIMMS - UPDATED TO 25/28 DEGREE CONNECTORS
MASTER PAGE SYNC CHECKIN 23003
SOFT MODEM - ADDED DECOUPLING CAPS TO POWER RAIL
REMOVED OLD OVERTEMP CIRCUIT ADDED DIAG LED
MASTER PAGE SYNC
CHECKIN 23004
CPU POWER SUPPLY - ON SEMI FETS ONLY ADDED 1.6GHZ CPU PART NUMBER
UPDATED PLATING FOR ZH702
CHECKIN 23005
CPU AVDD - ADDED 2.7V BOM OPTION POWER_FAIL - RESISTOR DIVIDED TO 3.3V
ADDED BOMS OPTIONS FOR ON_SEMI AND VISHAY FETS FOR 3PHASE AND 4PHASE CPU PS AVP CHANGES
CPU VREG - ADDED BOM OPTION ’EXTRA_C’ FOR CAPS WE WOULD LIKE TO NOSTUFF
CHECKIN 23006 CPU VREG AVP - C3304, C3305, C3306, C3307 CHANGED TO 8.2NF
TMDS TERM - STUFFING CHANGES
CHECKIN 23007
05/06/04
05/07/04
05/10/04
05/11/04
06/10/04
06/11/04
06/21/04
06/22/04
06/22/04
06/23/04
06/24/04
06/28/04
06/28/04
07/01/04
07/02/04
07/06/04
07/08/04
07/12/04
07/13/04
07/14/04
DVT RELEASE (REV 24)
TMDS - NEW PARALLEL TERMINATION RESISTORS R5869-R5872
CHECKIN 24001
FRAME BUFFER CLOCKS - ADDED DIFF PAIR PROPERTIES
PCI_RESET - UPDATES FOR SCHEMATIC REUSE
MASTER PAGE SYNC - ADDED S/PDIF XMITTER AND BITCLK DELAY CHECKIN 24002
AUDIO UPDATES
CHECKINS 24003-24005
DVT RELEASE (REV 25)
LAST MINUTE BOM CHANGES FOR DVT:
SUSPENDREQ LEVEL SHIFTER - R2419, R2420 CHANGED TO 330 OHM
I2C A BUS PULLUPS - R1816,R1817 CHANGED TO 200 OHM USB PULL-DOWNS - R9403,R9404 MOVED TO COMMON BOM
SMU CRYSTAL CAPS - C1304,C1305 CHANGED TO 18PF FROM 12PF
SMU RESET - CHANGED R1322 TO 150K FROM 100K CPU HEATSINK ASSEMBLIES - NEW PART NUMBERS
TMDS POWER - CHANGED D5914 TO SURFACE MOUNT PART FROM THROUGH HOLE
MOVED R714 TO R1303 FOR SCHEMATIC REUSE U1600,U1601,U1700 CHANGED TO 353S0890 FOR MORE SOURCES
MOVED CPU LOGIC ANALYZER RESISTORS TO DEVELOPMENT BOM
CHECKIN 25001
MASTER PAGE SYNC - NOSUFFED EXTERNAL S/PDIF TRANSMITTER ADDED TABLES FOR:
PATA CONN J8301 CHANGED TO 516S0235 (ADDED VENDOR) NEW SATA CONNECTER SOURCES J8300, J8302
NEW TMDS CONNECTOR W/ BOSS J5902
REMOVED COIN CELL BATTERY AND I/O ALIGNMENT FIXTURE FROM MLB BOM (FATP ITEMS) NEW BACKUP SMU_RESET CIRCUIT (SAME AS Q78)
CHECKIN 25003
REPLACED Q5006 (FET FOR 1.5V) WITH 376S0254
FAN OPAMPS - REPLACED U1600 W/ SECOND OPAMP IN U1700
TIED INPUTS IN UNUSED OPAMP IN U1601
NOSTUFFED CPU VREG ELECTROLYTIC CAPS C3332, C3427, C3421 NOSTUFFED R2775/6 (UNUSED CLOCKS)
CHECKIN 25004
"PROPERLY" TERMINATED UNUSED OPAMP IN U1601
BOM RELEASE REV 26
"PROPERLY" TERMINATED UNUSED OPAMP IN U2100 R5010 REMOVED TO DECREASE DROOP ON 1.5V RAIL
ADDED CONNECTOR J1701 TO SUPPORT REMOTE HD TEMP SENSOR
CHECKIN 26001
MASTER PAGE SYNC - PICKED UP AUDIO CHANGES RELATED TO BITCLK CHECKIN 26002
SUPPORT FOR 2GB DIMMS - SWAPPED PINS 103 & 167 ON DIMM CONNECTOR
CHECKIN 26003
ADDED SECOND SOURCE VTT REGULATOR (PAGE 46) NO STUFF POWER SUPPLY TEMP SENSOR
CHANGED HD TEMP SENSOR CONN J1701 TO 4 PIN
MASTER PAGE SYNC - AUDIO CHANGES CHECKIN 26004
UPDATED LINE AND NECK WIDTH CONSTRAINTS THROUGHOUT SCHEMATIC
NOSTUFFED ON BOARD HD TEMP SENSOR CHANGED U3LITE CORE TO 1.53V
FEEDBACK RESISTORS CHANGED TO 603
CHECKIN 26005
REMOVED ON BOARD HARD DRIVE TEMP SENSOR AUDIO DETECT PULLUPS - CHANGED FROM 47K TO 4.7K
CHANGED AUDIO I2S_BITCLK SERIES RESISTER TO 0 OHM
U3LITE FEEDBACK RESISTORS CHANGED TO 0.5% TOLERANCE CHECKIN 26006
REPLACED MAXIM ANALOG SWITCH U2850 WITH TI ANALOG SWITCH
PERICOM ADDED AS AN ALTERNATE ALL I/O CONNECTORS CHANGED
POWER CONNECTOR CHANGED
POWER SWITCH CHANGED SMU DOWNLOAD CONNECTOR - PRODUCTION P/N
CPU PART NUMBERS - UPDATED WITH ACTUAL PART NUMBERS
CHECKIN 26007 BOM RELEASE REV 27
CPU VREG DROOP - R3327 CHANGED TO 1.5K; R3326 CHANGED TO 301
PULSAR_POWER_DOWN - R2750 CHANGED TO 47 OHM FOR ICT
AUDIO DETECT PULLUPS - CHANGED BACK TO 47K FROM 4.7K AUDIO MUTE PULLDOWNS R9815 & RA012 - CHANGED FROM 47K TO 4.7K
MIC BIAS - NOSTUFFED CA210 TO HELP NOISE FLOOR
1.5V_RUN FET - ADDED (N/S) C5060 FOR POSSIBLE SOFT-START
2.5V VREG SOFT START - CHANGED C915 TO 1UF FOR U3L POWER SEQUENCING
MLB CARCODE - CHANGED TO 825-6447 I/O CONNECTOR SYMBOL UPDATES
CHECKIN 27001
POWER_FAIL_L R DIVIDE - ADJUSTED FOR 2K PULLUP THAT WILL BE IN PVT POWER SUPPLIES
ORIGIN HOLE ZH702 - CHANGED TO 4.15MM CHECKIN 27002
FIREWIRE CRYSTAL - ADDED R9060 & R9061
CHECKIN 27003 FIREWIRE CRYSTAL R - FIXED REF DES
ANALOG SWITCH U2850 - ADDED PERICOM & AND MAXIM AS ALTERNATES TO TI
STUFFED P/S TEMP SENSOR NAMED SOME UNNAMED NETS
CHECKIN 27004
NEW 1.5V FET - LOWER RDS(ON) - Q5006
07/15/04
07/28/04
08/03/04
08/20/04
08/27/04
09/14/04
09/30/04
11/15/04
12/13/04
U3LITE PWR SEQ - CHANGED C915 TO 0.22UF
P/S TEMP SENSOR - NOSTUFF REMOTE HD TEMP SENSOR CONNECTOR - NOSTUFF
PVT / PRODUCTION RELEASE 820-1540:A (SCH 051-6482 REV A)
STUFFED TMDS CONNECTOR J5902 (ACCIDENTALLY OMITTED) FIREWIRE CRYSTAL - CHANGED R9061 TO 470 OHM
2.5V VREG - CHANGED SOFT START CAP TO 0.68UF
NEW P/N FOR HEATSINK ASSEMBLIES NOSTUFFED OPTICAL TEMP SENSOR
STUFFED REMOTE HD TEMP SENSOR CONNECTOR
BOM RELEASE (REV B)
2.5V VREG - CHANGED SOFT START CAP TO 0.47UF I/O CONNECTOR SHIELD CHANGE P/N TO 805-5664
NEW CPU P/N AND BINCODES FOR 1.10V VMIN BOM RELEASE (REV C)
TMDS VCC - CHANGED C5918 TO 0.022UF TO LOWER INRUSH CURRENT
POWER SWITCH SW703 - MADE FOXCONN 516S0248 AND SUYIN 516S0249 ALTERNATES
PATA CONNECTOR J8301 - CHANGED TO 516S0264 TO MATCH REVERSED BOSSES ON FAB BOM RELEASE (REV D)
NOSTUFF SDF700
SW703 - SUYIN WAS REMOVED AS ALTERNATE
BOM RELEASE (REV E)
CPU - WAVE5 PROCESSORS ADDED AS ALTERNATES (ARL, BPL, BRL) CPU P/S CAPS - AIR CHANNEL BY STUFFING C3427, C3332 AND NOSTUFFING C3327, C3428
SATABR RESET - STUFFED PULLDOWN R2565 CPU_INT_L - CHANGED R2578 TO 47 OHM TO CURRENT LIMIT
BOM RELEASE (REV F)
CPU - 1.6GHZ 1.20V PROCESSORS ADDED AS ALTERNATES (APA, APL)
REMOTE HD TEMP SENSOR CONN - CHANGED J1701 TO BLACK 518S0193
KEPT 518S0084 AS ALTERNATE
FW SURGE RESISTORS - CHANGED R9056 & R9002 TO 1.3 OHM 107S0060
BOM RELEASE (REV G)
CPU - ADDED HP PROCESSORS AS ALTERNATES (ANA, BNA) AUDIO GROUND - CHANGED R9813 & R9814 TO 0 OHM
HD TEMP CONN - REMOVED ALTERNATE CONNECTOR BOM RELEASE (REV H)
CPU DECOUPLING - NOSTUFFED EXTRA_C BOM OPTION
U3LITE - ADDED NEW LAMINATE PART AS ALTERNATE
BOM RELEASE (REV I)
REVISION HISTORY
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
APPLE COMPUTER INC.
D
NONE
D
C
B
A
REV.
I
SHT
OF
4
103
8
67
5
4
3
2
1
78
6
5
4
3
12
PROCESSORS
QTY
QUALIFIED
QTY
D
WAVE3
WAVE3
WAVE3
WAVE5
WAVE5
WAVE5 HP
WAVE3
WAVE5
WAVE5 HP
337S2969
1
PART NUMBER
337S2995
337S2980
337S2997 337S2968
337S2981
337S2982
337S2998
ALTERNATE FOR PART NUMBER
337S2968337S2994
337S2968
337S2968
337S2969337S2970
337S2969
337S2969
337S2969
DEVICE
PROCESSOR
PROCESSOR
PACKAGE
CBGA-576-1MM
CBGA-576-1MM
DESCRIPTION
IC,GPUL,10S,DD3,1.6G,85C,ARA
IC,GPUL,10S,DD3,1.8G,85C,BPA
BOM OPTION
CPU_DD30_1_6GHZ
CPU_DD30_1_6GHZ
CPU_DD30_1_6GHZ
CPU_DD30_1_6GHZ
CPU_DD30_1_8GHZ IC,GPUL,DD3,1.8G,BRA
CPU_DD30_1_8GHZ
REF DES
COMMENTS:
IC,GPUL,DD3,1.6G,APA
IC,GPUL,DD3,1.6G,APL
IC,GPUL,DD3,1.6G,ARL
IC,GPUL,DD3,1.6G,ANA
IC,GPUL,DD3,1.8G,BPLCPU_DD30_1_8GHZ
IC,GPUL,DD3,1.8G,BRL
IC,GPUL,DD3,1.8G,BNACPU_DD30_1_8GHZ
1.6GHZ337S2968
1.8GHZ
VALUE VOLT. WATT.
42W
42W
TABLE_ALT_HEAD
VOLTAGE
TABLE_ALT_ITEM
1.20V
TABLE_ALT_ITEM
1.20V
TABLE_ALT_ITEM
1.25V
TABLE_ALT_ITEM
1.20V
TABLE_ALT_ITEM
1.25V
TABLE_ALT_ITEM
1.20V
TABLE_ALT_ITEM
1.25VWAVE5
TABLE_ALT_ITEM
1.20V
REFERENCE DESIGNATOR(S)
TOL.PART #
?1
?
BOM OPTION
CPU_DD30_1_6GHZ
CPU_DD30_1_8GHZ
TABLE_11_HEAD
TABLE_11_HEAD
TABLE_11_HEAD
343S0283
820-1540 MLB1
825-6447
051-6482
341T1366
341T1395
CRITICAL
C
337S2865
337S2866
337S2787
QTY
1 ?
1
DEVICE
PROCESSOR
PROCESSOR
PROCESSOR
PACKAGE
CBGA-576-1MM
CBGA-576-1MM
CBGA-576-1MM
DESCRIPTION
IC,GPUL,10S,DD2.11,1.8GHZ,85C
IC,GPUL,10S,DD2.11,2.0GHZ,85C
IC,GPUL,10S,REV3,2.0G,85C,CJA
NOT QUALIFIED
VALUE VOLT. WATT.
1.8GHZ
2.0GHZ
2.0GHZ
REFERENCE DESIGNATOR(S)
TOL.PART #
45W
45W
?1
?
45W
BOM OPTION
CPU_DD211_1_8GHZ
CPU_DD211_2_0GHZ
CPU_DD30_2_0GHZ
TABLE_11_HEAD
TABLE_11_HEAD
TABLE_11_HEAD
TABLE_11_HEAD
603-6015
CRITICAL1603-6016
DESCRIPTION
1
IC,U3LITE,V1.1,300MM,PBGA
PART NUMBER
343S0282
QTY
1
QTY
1
1
1
1
1
1
1
ALTERNATE FOR PART NUMBER
343S0284 U3343S0321
DESCRIPTION
IC,ASIC,SHASTA,V1.1,PBGA
DESCRIPTION
SPEC,VENDOR PACKAGING PROCEDURE
PCB,FAB,MLB
BARCODE LABEL, MLB, Q45
PCB,SCHEM,MLB
IC,FLASH,1MX8,3.3V,90NS
PURCH ASSY, SMU BIG
HEAT SINK ASSEMBLY 17 IN
HEAT SINK ASSEMBLY 20 IN
PART NUMBER
378S0119
ASICS
BOM OPTION
MISC PARTS
ALTERNATE FOR PART NUMBER
378S0114
REFERENCE DESIGNATOR(S)
U3343S0284
REF DES
U3343S0284
U3343S0284343S0320
REFERENCE DESIGNATOR(S)
REFERENCE DESIGNATOR(S)
VPP1062-2082
LBL1
SCH1
U7500
U1300
MECH17
MECH20
ALTERNATES
BOM OPTION
REF DES
LED700,LED702,LED5900
BOM OPTION
COMMENTS:
U3L,V1.1,200MM,PBGA
U3L,NEW LAM,200MM
U3L,NEW LAM,300MM
BOM OPTION
BOM OPTION
17_INCH_LCD
20_INCH_LCD
COMMENTS:
KINGBRIGHT LED
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_ALT_HEAD
TABLE_ALT_ITEM
D
C
B
B
TABLE ITEMS
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
5
1
REV.
OF
103
A
I
PP5V_ALL
PP5V_PWRON
SHT
12
PP5V_RUN
6
PP24V_RUN
PP3V3_RUN
PP1V2_PWRON
PP3V3_PWRON
OF
D
C
B
A
REV.
I
103
78
6
5
4
3
PP12V_RUN
NO_TEST=YES NO_TEST=YES NO_TEST=YES
I3
NO_TEST=YES
I4
NO_TEST=YES
I5
NO_TEST=YES
I6
NO_TEST=YES
I7
NO_TEST=YES
I8
NO_TEST=YES
I9
NO_TEST=YES
I10
NO_TEST=YES
I295
NO_TEST=YES
D
C
B
A
I296
I297
I298
I300
I299
I302
I307
I311
I314
I315
I316
I317
I320
I319
I322
I323
I321
I336
I337
I338
I340
I339
I342
I343
I341
I344
I345
I346
I347
I348
I350
I349
I354
I355
I356
I357
I358
I360
I359
I362
I363
I361
I364
I365
I372
I373
I371
I374
I375
I376
I377
I378
I380
I379
I382
I383
I381
I384
I385
I386
I388
I387
I390
I389
I391
I393
I392
I395
I394
I396
I398
I397
I399
I401
I400
I403
I402
I404
I405
I406
I408
I407
I426
I429
I428
I431
I430
I432
NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES NO_TEST=YES
TP_BUF_RST TP_DFPCLK
TP_DFPCLK_L
TP_DFPD0 TP_DFPD1
TP_DFPD2
TP_DFPD3 TP_DFPD5
TP_DFPD6
TP_EXT_TMDS_CKM TP_EXT_TMDS_CKP
TP_EXT_TMDS_D0M TP_EXT_TMDS_D0P
TP_EXT_TMDS_D1M
TP_EXT_TMDS_D1P TP_EXT_TMDS_D2M
TP_EXT_TMDS_D2P
TP_FBBCS1_L
TP_GPU_INTB_L
TP_GPU_THERMA TP_GPU_THERMC
TP_IFP1VREF TP_NVAGP_TDO
TP_TMDS_TXD3M TP_TMDS_TXD3P
TP_TMDS_TXD7M
TP_TMDS_TXD7P TP_VIPHCLK
TP_FRWRLPS
TP_AGP_MB_AGP8X_DET_L TP_ATTENTION
TP_ENET_CLK125M_GTX TP_ENET_TXD<7>
TP_ENET_TXD<4>
TP_ENET_TXD<5> TP_FW_CLK98M_LCLK
TP_AFN
TP_PSRO1 TP_PSRO2
TP_PSYNCOUT
TP_USB2_PWREN<2> TP_USB2_PWREN<3>
TP_USB2_PWREN<4>
TP_NEC_AMC
TP_NEC_NANDTEST TP_NEC_NTEST1
TP_NEC_SMC
TP_NEC_SMI_L TP_NEC_SRCLK
TP_NEC_SRDATA
TP_NEC_SRMOD TP_NEC_TEB
TP_NEC_TEST TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1
TP_PLS_REF_CML TP_PLS_TEST1
TP_PLS_TEST2
TP_PLS_TEST3 TP_SB_FSTEST
TP_SB_PLLTEST
TP_VREF_CG TP_SB_NC_P7
TP_SB_NC_P8 TP_SB_NC_R3
TP_SB_NC_R4
TP_SB_NC_R5 TP_SB_NC_R6
TP_SB_NC_R7
TP_SB_NC_R8 TP_SB_NC_T1
TP_SB_NC_T2
TP_SB_NC_T3 TP_SB_NC_T4
TP_SB_NC_T5 TP_SB_NC_T6
TP_SB_NC_T7
TP_SB_NC_T8 TP_SB_NC_U1
TP_SB_NC_U2
TP_SB_NC_U3 TP_SB_NC_U4
TP_SB_NC_U5
TP_SB_NC_U6 TP_SB_NC_V1
TP_SB_NC_V2 TP_SB_NC_V3
TP_SB_NC_V4
TP_SB_NC_W1 TP_SB_NC_W3
TP_SB_NC_Y1
TP_SB_NC_Y3 TP_SATA_CLK25M
TP_ENET_TCK
TP_USB2_PWREN<0> TP_USB2_PWREN<1>
TP_DUMMY_A TP_DUMMY_B
TP_RAM_CKE_R<2>
57
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
58
52
49
58
58
58
49
58
58
58
58
57
58
48
29
87
87
87
87
90
29
29
29
29
92
92
92
77
77
77
77
77
77
77
77
77
77
27
27
27
27
27
27
25
25
48
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
91
27
87
92
92
24
24
8
NO_TEST=YES
I434
NO_TEST=YES
I433
NO_TEST=YES
I436
NO_TEST=YES
I435
NO_TEST=YES
I437
NO_TEST=YES
I439
NO_TEST=YES
I438
NO_TEST=YES
I440
NO_TEST=YES
I441
NO_TEST=YES
I442
NO_TEST=YES
I444
NO_TEST=YES
I443
NO_TEST=YES
I445
NO_TEST=YES
I446
NO_TEST=YES
I781
NO_TEST=YES
I809
NO_TEST=YES
I810
GENZ SHOULD USE J1400 FOR THE FOLLOWING NETS:
NO_TEST=TRUE
I782
NO_TEST=YES
I784
NO_TEST=YES
I785
NO_TEST=TRUE
I786
NO_TEST=TRUE
I787
NO_TEST=TRUE
I789
NO_TEST=YES
I788
NO_TEST=YES
I790
NO_TEST=TRUE
I792
NO_TEST=TRUE
I791
NO_TEST=YES
I793
NO_TEST=YES
I794
NO_TEST=YES
I795
NO_TEST=YES
I796
NO_TEST=YES
I797
NO_TEST=YES
I798
NO_TEST=YES
I799
NO_TEST=YES
I800
NO_TEST=YES
I801
NO_TEST=YES
I802
NO_TEST=YES
I803
NO_TEST=YES
I804
NO_TEST=YES
I805
NO_TEST=YES
I806
NO_TEST=YES
I807
NO_TEST=YES
I808
TP_RAM_CKE_R<3> TP_RAM_CKE_R<6>
TP_RAM_CKE_R<7>
TP_RAM_CS_L_R<10> TP_RAM_CS_L_R<11>
TP_RAM_CS_L_R<2>
TP_RAM_CS_L_R<3> TP_RAM_MUXEN0
TP_RAM_MUXEN4
TP_NB_PM_SLEEP0 TP_J4000_SJRESET_L
TP_J4001_SJRESET_L TP_CMP_SPARE
TP_ENET_TXD<6>
U2100_UNUSED PLS_CLK_66M_0_R
PLS_CLK_66M_1_R
EI_CPU_TO_NB_AD<0..43>
EI_CPU_TO_NB_CLK_N EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_SR_N<0..1>
EI_CPU_TO_NB_SR_P<0..1> EI_NB_TO_CPU_AD<0..43>
EI_NB_TO_CPU_CLK_N
EI_NB_TO_CPU_CLK_P EI_NB_TO_CPU_SR_N<0..1>
EI_NB_TO_CPU_SR_P<0..1> CHKSTOP_L
CPU_HRESET_L
CPU_INT_L CPU1_HTBEN
EI_CPU1_CLK_N
EI_CPU1_CLK_P EI_QACK_L
EI_QREQ_L
EI_SE I2C_SMU_A_SCL_OUT_L
I2C_SMU_A_SDA_OUT_L MCP_L
RI_L
SYNCENABLE TP_PROC_TRIGGER_OUT
EI_CPU1_SYNC
8
8
8
8
8
8
8
8
8
24
40
40
87
21
27
27
29
28
14
29
28
14
29
28
14
28
29
14
29
28
14
28
29
14
29
28
14
29
28
14
28
29
14
28
29
14
14
29
8
29
30
14
30
25
29
14
14
27
14
27
14
28
29
14
28
29
30
14
28
29
30
14
14
18
13
14
18
13
29
14
29
30
14
29
30
14
29
14
27
14
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
90
IN
73 74 75 76 77
IN
73 74 76 77
IN
8
IN
74 76
IN
74 76
IN
25 76
IN
8
51 58 74
IN
73 74 76 77
IN
73 74 76 77
IN
73 74 76 77
IN
73 74 76 77
IN
73 74 76 77
IN
73 74 76 77
IN
76
IN
74 75 76
IN
74 75 76
IN
74 75 76
IN
75 76
IN
76
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
92
IN
25 76 94
IN
25 94
IN
25 94
IN
25 76 94
IN
25 76 94
IN
25 94
IN
25 94
IN
18 94
IN
18 94
IN
94
IN
94
IN
25 94
IN
25 94
IN
94
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
7
59
IN
59
IN
59
IN
59
IN
56 57 59
IN
56 57 59
IN
59
IN
59
IN
58 59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
59
IN
8
33
IN
36
IN
36
IN
36
IN
36
IN
33 36
IN
33 36
IN
FW_VP_PORT1 FW_TPO1P
FW_TPO1N
FW_TPI1P FW_TPI1N
FW_VP_PORT2
FW_TPO2P FW_TPO2N
FW_TPI2P
FW_TPI2N FW_VGND
PCI_AD<31..0>
PCI_CBE_L<3..0>
PCI_CLK33M_AIRPORT PCI_SLOTA_REQ_L
PCI_SLOTA_GNT_L
PCI_SLOTA_INT_L PCI_RESET_L
PCI_FRAME_L
PCI_TRDY_L PCI_IRDY_L
PCI_STOP_L PCI_DEVSEL_L
PCI_PAR
PCI_SLOTA_IDSEL ROM_CS_L
ROM_OE_L
ROM_WE_L ROM_ONBOARD_CS_L
AIRPORT_CLKRUN_L_PD
USB_BT_N
USB_BT_P
USB2_PORT1_N_F
USB2_PORT1_P_F USB2_PORT2_N_F
USB2_PORT2_P_F
USB2_PORT3_N_F USB2_PORT3_P_F
PP5V_USB2_PORT1_F
PP5V_USB2_PORT2_F PP5V_USB2_PORT3_F
I2S1_DEV_TO_SB_DTI
I2S1_SYNC
I2S1_BITCLK I2S1_MCLK
I2S1_SB_TO_DEV_DTO
I2S1_RESET_L MODEM_RING2SYS_L
I2C_UDASH_SDA
I2C_UDASH_SCL USB_UDASH_N
USB_UDASH_P UDASH_SDOWN
UDASH_RESET_L
UDASH_I2C_A1_PU
PPVCC_TMDS
PP3V3_DDC TD0M
TD0P
TD1M TD1P
TD2M TD2P
TCKM
TCKP TMDS_DDC_DAT
TMDS_DDC_CLK
GND_CHASSIS_TMDS
FILT_ANALOG_RED
FILT_ANALOG_GRN FILT_ANALOG_BLU
ANALOG_HSYNC_L ANALOG_VSYNC_L
VGA_IIC_CLK
VGA_IIC_DAT MON_DETECT
DDC_VCC_5
PP24V_INV
GND_20_INV
INV_20_LCD_PWM_ INV_20_CUR_HI_F
PP12V_INV GND_17_INV
PP5V_AGP_RL
INV_17_LCD_PWM_F LAMP_STS_F
INV_17_CUR_HI_F
CPU_VID_R<5..0>
KPVDD2_FMAX
KPGND2_FMAX TDIODE_POS_FMAX
TDIODE_NEG_FMAX CORE_ISNS_M
CORE_ISNS_P
2 TEST POINTS
2 TEST POINTS
2 TEST POINTS 2 TEST POINTS
2 TEST POINTS
2 TEST POINTS 2 TEST POINTS
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
10 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
5 TEST POINTS
12 TEST POINTS
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
FUNC_TEST=YES
7
11
11 18
11 18
7
83
7
83
PP12V_RUN
IN
PP5V_ALL
IN
PP5V_RUN
IN
PP3V3_RUN
IN
PP24V_RUN
IN
=PP5V_DISK
IN
=PP12V_DISK
IN
GND
IN
PP2V5_RUN
PP2V5_RUN
IN
PP1V5_RUN
IN
PP5V_PWRON
11 18
IN
PP3V3_PWRON
11 18 27
IN
PP1V2_PWRON
IN
PPVCORE_PWRON_SB
3
10
IN
=PP3V3_ALL_SMU
7 8
13
IN
=PP5V_RUN_CPU
3 7 8
31
IN
PPVCORE_NB
7
22
IN
PPVCORE_CPU
7
33 34 35
IN
PP12V_CPU
33 34
IN
VCORE_SENSE_GND
33
IN
VCORE_SENSE_VOUT
33
IN
SMU_MANUAL_RESET_L
7 8
IN
SYS_POWER_BUTTON_L
7
13
IN
POWER_BUTTON_L
7
IN
RESET_BUTTON_L
7
IN
SMU_RESET_L
13
8
IN
SYS_POWERUP_L
7
10 11 13 33
IN
SYS_SLEEP
8 9
10 11 46 50
IN
SYS_POWERFAIL_L
8
13
IN
EXT_POWER_BUTTON_L
IN
U900_FEEDBACK
9
IN
U2200_FEEDBACK
22
IN
ANALOG_RED
57 59
IN
ANALOG_GRN
57 59
IN
ANALOG_BLU
57 59
IN
AUDIO_LI_DETECT_L
IN
25
IN
75
IN
80 83
IN
80 83
IN
80 83
IN
80 83
IN
80 83
IN
83
IN
80 83
IN
6
6
80 83
IN
80 83
83
IN
80 83
IN
83
IN
83
IN
83
IN
31 36
IN
76
IN
76
IN
AUDIO_LO_DET_L
ROM_WP_L
UATA_DD<15..0>
UATA_DA<2..0>
UATA_CS0_L UATA_CS1_L
UATA_RESET_L UATA_DSTROBE_R
UATA_HSTROBE
UATA_STOPUATA_STOP UATA_DMARQ_R
UATA_DMACK_L
UATA_INTRQ_R UATA_IOCS16_PU
UATA_CSEL_PD
TDIODE_NEG
TP_AIRPORT_PME_L TP_AIRPORT_RF_DISABLE
101
2 TEST POINTS 2 TEST POINTS
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=TRUE FUNC_TEST=TRUE FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
FUNC_TEST=YES FUNC_TEST=YES FUNC_TEST=YES
PP1V5_RUN
FUNC TEST
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
APPLE COMPUTER INC.
D
NONE
8
67
5
4
3
2
1
78
PP12V_RUN
D
POWER_GOOD
8
SYS_POWERUP_L
33
13
10
6
11
C
PP5V_ALL
R710
330
5%
1/16W
MF
603
13
21
ITS_PLUGGED_IN
LED702
GREEN
2.0X1.25A
SILKSCREEN:1
SYS_POWER_BUTTON_L
7
6
B
SYS_POWER_BUTTON_L
7
6
13
DEVELOPMENT
R712
1/16W
8
6
1K
402
5% MF
SYS_RESET_BUTTON_L
13
A
PP5V_RUN
PP5V_ALL
90
59
1
2
21
SMU_MANUAL_RESET_L
PP3V3_RUN
CRITICAL
J700
HM96110-P2
F-RT-TH
1
2
3
4
5
6
7
8
9
10
11
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PIN 13,19,11,22 ARE DIFFERENCE FROM ATX .
PP3V3_ALL
11
7
PP3V3_PWRON
FERR-EMI-100-OHM
1
C703
0.1UF
20% 10V
2
CERM
PART NUMBER
516S0249
R713
1K
1/16W
402
DEVELOPMENT
RESET
P/N 518-0159
CRITICAL
U700
74LCX125
14
2
3
125
17
R700
330
21
ITS_ALIVE
5%
1/16W
MF
603
LED700
2.0X1.25A
SILKSCREEN:2
L700
21
SYS_PWR_BTN_FILT
SM
402
L701
FERR-EMI-100-OHM
21
5%
MF
SW701
SPST
SM
21
SM
ALTERNATE FOR PART NUMBER
516S0248
SUYIN WILL NOT BE USED FOR INITIAL RAMP
SW702
21
43
POWER
SW700
SPST
SM
SMU RESET
PP24V_RUN
PP12V_RUN
12
13
14
15
16
17
18
19
20
21
22
VOLTAGE=0V
1
C700
0.1UF
20% 10V
2
CERM 402
SYS_POWERUP_L_BUF
PP3V3_RUN
1
GREEN
2
GND_SYS_PWR_BTN_FILT
BOM OPTION
SPST
SM
21
1
2
43
21
43
PP5V_RUN
DEVELOPMENT
R701
330
5%
1/16W
MF
603
CRITICAL
SW703
PWR-BUTT
ST-SM3
1
2
54
REF DES
SW703
POWER_BUTTON_L
RESET_BUTTON_L
C705
0.1UF
20% 10V CERM 402
21
ITS_RUNNING
DEVELOPMENT
LED701
GREEN
2.0X1.25A
SILKSCREEN:RUN
SILKSCREEN:POWER
3
516S0248 FOXCONN
COMMENTS:
POWER SWITCH - SUYIN
6
6
1
C704
0.1UF
20% 10V
2
CERM 402
35
31
=PP1V2_EI_CPU
18 18
14 14
30
29 28
8
6
PP24V_RUN
VOLTAGE=24V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
MAKE_BASE=TRUE
PP12V_RUN
VOLTAGE=12V
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
PP5V_RUN
PP3V3_RUN
1
2
TABLE_ALT_HEAD
PP2V5_RUN
PP1V5_RUN
35
XW700
XW704
XW701
XW705
VOLTAGE=5V MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL MAKE_BASE=TRUE
VOLTAGE=2.5V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=1.5V MAKE_BASE=TRUE MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PPVCORE_CPU
6
34
33
MAKE_BASE=TRUE
EI OVDD POWER OPTIONS
5
RUN RAILS
ONLY ON IN RUN
SM
21
PP12V_AUDIO_CODEC
SM
21
SM
21
PP12V_AUDIO_SPKRAMP
SM
21
ALIAS
ALIAS
ALIAS
PP1V5_RUN
=PP24V_GRAPHICS
=PP12V_AGP =PP12V_RUN_CPU =PP12V_DISK
=PP5V_PATA =PP5V_DISK
=PP5V_AGP
=PP5V_RUN_CPU
PP5V_AUDIO
=PP5V_RUN_RAM
=PP3V3_AGP
PP3V3_AUDIO
=PP3V3_RUN_CPU =PP3V3_PATA
=PP3V3_SB_PCI
=PP3V3_PCI =PPVIO_PCI_USB2
=PP3V3_DISK
PP2V5_GPU
=PP2V5_RUN_CPU =PP2V5_RUN_RAM
=PP1V5_AGP =PPVCORE_PULSAR
=PPVCORE_CPU
59
50
59
33
6
83
102
100
83
83
6
49
50
59
31
8
6
3
101
46
49
48
50
52
51
102
101
100
95
33
83
74
25
77
76
75
74
77
83
55
54
52
50
31
46
45
44
48
49
26
7
31
36
32
29
VOLTAGE=1.2V MAKE_BASE=TRUE MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
=PP1V2_HT
=PP1V2_PULSAR
1
5%
FF
805
5%
FF
805
0
0
R715
21
21
1
R711
0
0
5%
5%
FF
805
805
2
2
NOSTUFF
R708
1
0
5%
FF
805
2
NOSTUFF
1
R709
0
5% 1/10W FF 805
2
PP1V2_EI_NB
VOLTAGE=1.2V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
36
32
31
PP1V2_EI_CPU
VOLTAGE=1.2V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
67
=PPVCORE_CPU
29
7
NOSTUFF
R705
1
1
R718
0
0
5%
5%
FF
805
805
2
2
R703
R719
NOSTUFF
1
1
R706
0
0
5%
5% 1/10W
FF
FF
805
805
2
2
R704
5
4
PWRON RAILS
ON IN RUN AND SLEEP
PP5V_PWRON
VOLTAGE=5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
PP3V3_PWRON
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
PP2V5_PWRON
VOLTAGE=2.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
PP1V5_PWRON
59 58 57
56
103
PP1V2_RUN
NOSTUFF
R716
0
5%
FF
805
NOSTUFF
R717
0
5%
FF
805
MAKE_BASE=TRUE
VOLTAGE=1.5V MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
PP1V2_PWRON
MAKE_BASE=TRUE MIN_LINE_WIDTH=25MIL
MIN_NECK_WIDTH=10MIL VOLTAGE=1.2V
24
60
26
21
PP1V25_RAM_VTT
21
=PP1V2_EI_NB
44
45
46
ALIAS
R707
21
2512
4
3
_PP5V_PWRON_USB _PP5V_PWRON_UDASH
=PP5V_PWRON_CPU
=PP5V_PWRON_AIRPORT
=PP3V3_PWRON_SB =PPPCI64_PWRON_SB
=PPPCI32_PWRON_SB
_PP3V3_PWRON_MODEM =PP3V3_PWRON_USB
PP3V3_PWRON_ENET
_PP3V3_PWRON_BT _PP3V3_PWRON_UDASH
=PP3V3_PWRON_CPU =PP3V3_PWRON_EI
=PP2V5_PWRON_SB
=PP2V5_PWRON_RAM =PP2V5_HT
=PP2V5_PWRON_HT
=PP1V5_PWRON_NB_AVDD =PPVCORE_PWRON_PULSAR
0
PPVCORE_NB
5% 1W FF
=PP1V2_PWRON_HT
=PP1V2_PWRON_DISK_SB =PP1V2_PWRON_SB
=PP3V3_ALL_RTC
13
3
92
94
36
76
23
74
25
23
23
94
91
87
92
94
36
28
23
25
74
26
37
40
60
64
62
28
60
37
48
26
22
6
62
80
25
PP3V3_ALL_RTC VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
ALL RAILS
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
PP3V3_ALL
59
7
11
90
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PP5V_ALL
11
6
VOLTAGE=5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL MAKE_BASE=TRUE
PP5V_ALL
=PP3V3_ALL_SMU
=PP3V3_ALL_EI
=PP3V3_ALL_CPU
=PP5V_ALL_CPU
GND RAILS
XW702
SM
XW706
SM
XW703
SM
XW707
SM
21
21
21
21
GND_AUDIO
102
88
GND_AUDIO_SPKRAMP
102
100
CHASSIS GND
GND_CHASSIS_AUDIO_EXTERNAL
102
101
MIN_NECK_WIDTH=15MIL MAKE_BASE=TRUE VOLTAGE=0 MIN_LINE_WIDTH=25MIL
GND_CHASSIS_VGA
59
GND_CHASSIS_USB
92
GND_CHASSIS_FIREWIRE
90
GND_CHASSIS_TMDS
6
59
MIN_NECK_WIDTH=15MIL MIN_LINE_WIDTH=25MIL VOLTAGE=0
GND_CHASSIS_RJ45
87
MIN_NECK_WIDTH=15MIL MIN_LINE_WIDTH=25MIL VOLTAGE=0
GND_CHASSIS_AUDIO_INTERNAL
101
MAKE_BASE=TRUE
GND_CHASSIS_LED
21
GND_CHASSIS_17_INCH_INVERTER
59
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL VOLTAGE=0
GND_CHASSIS_20_INCH_INVERTER
59
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL VOLTAGE=0
SDF700 IS USED FOR CPU HEATSINK MOUNTING
ALIAS
ZH701
315R138
1
ALIAS
ZH703
6.00MM-PTH
1
NOSTUFF
SDF700
HSK-NUT-6.5MM
TH
1
RTC BATTERY
ALWAYS ON (TRICKLE)
DS700
SM
21
PP3V3_ALL_BATT_SAFETY
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
MBR0530
R702
1K
5%
MF
402
21
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
POWER CONN / ALIAS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
APPLE COMPUTER INC.
2
D
NONE
12
SH700
1
SHLD-IO-CONN
Q45-TH1
805-5664
PP3V3_ALL_BATT
SHT
7
1
8
6
13
36
36
ZH700
315R138
1
4
32
CRITICAL
J702
BB10209-A5
OF
ZH702
7R4.15
1
12
TH
REV.
103
D
C
B
A
I
78
6
5
4
3
12
PCI CLOCKS
TP_NB_THMI
MAKE_BASE=TRUE
TP_THMO
MAKE_BASE=TRUE
TP_RAM_CKE_R<2>
6
MAKE_BASE=TRUE
TP_RAM_CKE_R<3>
6
MAKE_BASE=TRUE
TP_RAM_CKE_R<6>
6
MAKE_BASE=TRUE
TP_RAM_CKE_R<7>
6
MAKE_BASE=TRUE
TP_RAM_MUXEN0
6
MAKE_BASE=TRUE
TP_RAM_MUXEN4
D
6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<2>
6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<3>
6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<10>
6
MAKE_BASE=TRUE
TP_RAM_CS_L_R<11>
6
MAKE_BASE=TRUE
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
DIAG LED
LED850P1
1
LED850
RED
SM
2
LED850P2
R851
1K
DIAG_LED
13
MAKE_BASE=TRUE
5%
MF
402
21
DIAG_LED_R
RAM_CKE_R<2>
RAM_CKE_R<3>
RAM_CKE_R<6>
RAM_CKE_R<7>
RAM_MUXEN0
RAM_MUXEN4
RAM_CS_L_R<2>
RAM_CS_L_R<3>
RAM_CS_L_R<10>
RAM_CS_L_R<11>
PP5V_ALL
1
R850
180
5% 1/16W MF 402
2
3
1
2
NB_THMI
NB_THMO
Q850
2N3904
SM
24
24
37
37
37
37
37
37
37
37
37
PCI_CLK33M_USB2 MAKE_BASE=TRUE
TP_PCI_CLK_GP1 MAKE_BASE=TRUE
PCI_CLK33M_AIRPORT
6
MAKE_BASE=TRUE
TP_PCI_CLK_P4 MAKE_BASE=TRUE
PCI_CLK33M_SB_EXT
74
27 27
MAKE_BASE=TRUE
TP_ALS0_OUT
MAKE_BASE=TRUE
TP_ALS1_OUT
MAKE_BASE=TRUE
TP_ALS_GAIN_BOOST
MAKE_BASE=TRUE
TP_SMU_ONEWIRE
MAKE_BASE=TRUE
TP_SYS_SLOT_PWR
MAKE_BASE=TRUE
TP_SMU_PWRSEQ_P1_3
MAKE_BASE=TRUE
TP_SYS_DOOR_AJAR_L
MAKE_BASE=TRUE
TP_FAN_PWM8
MAKE_BASE=TRUE
TP_SYS_DRIVE_BAY_INT_L
MAKE_BASE=TRUE
SMU_WARM_RESET_L
13
8
MAKE_BASE=TRUE
PCI_RESET_L
6
74
58
51
MAKE_BASE=TRUE
C
CPU VID<0:5>
VID CONTROLLED BY SMU
R819
0
20% 10V
402
5%
MF
402
R821
0
5%
MF
402
R823
0
5%
MF
402
1
2
21
R820
0
21
5%
MF
21
402
R822
0
21
5%
MF
21
402
R824
0
21
5%
MF
402
14
NOSTUFF
F-ST-SM
J803
BM12B-SRSS-TB
5
VOLTAGE DETECTOR
MC33465N_30ATR
R810
0
21
5%
MF
402
2
1
NOTE:PULL UP CPU_VID<5>TO
2.2V FOR CPU VRM10.
2
VCC
U890
SM
RESETDELAY
NOSTUFF
GND
3
CPU_VID<0>
13
CPU_VID<1>
13
CPU_VID<2>
13
CPU_VID<3>
13
CPU_VID<4>
13
CPU_VID<5>
13
B
=PP3V3_ALL_SMU
13
6
7
NOSTUFF
C800
0.1uF
CERM
SMU_MANUAL_RESET_L
6
8
7
NOSTUFF
1
C890
0.01UF
10%
A
16V
CERM
402
2
CPU_VID_R<0>
CPU_VID_R<1>
CPU_VID_R<2>
CPU_VID_R<3>
CPU_VID_R<4>
CPU_VID_R<5>
9876543
1
2
1
NOSTUFF
R890
1K
5% 1/16W MF 402
121110
NOSTUFF
1
C891
1uF
10%
6.3V
2
CERM 402
1
R814
10K
5% 1/16W MF 402
2
NOSTUFF
1
R832
1K
13
2
SMU_RESET_L
5% 1/16W MF 402
1
R816
10K
5% 1/16W MF 402
2
NOSTUFF
1
R831
1K
5% 1/16W MF 402
2
PULSAR ERROR_L LEDBACKUP SMU RESET CIRCUIT
13
6
CLOCK_ERROR_L
27
DEVELOPMENT
ALIAS
ALIAS
ALIAS
SMU
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
1
R817
10K
5% 1/16W MF 402
2
NOSTUFF
1
R830
1K
5% 1/16W MF 402
2
R801
4.7K
5%
MF
402
PCI_CLK_GP0
=PCI_CLK33M_USB2
PCI_CLK_GP1
PCI_CLK_P3
_PCI_CLK33M_AIRPORT
PCI_CLK_P4
PCI_CLK_P1
ALS0_OUT
ALS1_OUT
ALS_GAIN_BOOST
SMU_ONEWIRE
SYS_SLOT_PWR
SMU_PWRSEQ_P1_3
SYS_DOOR_AJAR_L
FAN_PWM8
SYS_DRIVE_BAY_INT_L
NB_WARM_RESET_L
PCI_AIRPORT_RESET_L
GPU_RESET_L
=PCI_ROM_RESET_L =PCI_USB2_RESET_L
1
2
PP3V3_RUN
1
2
R808
10K
5% 1/16W MF 402
NOSTUFF
1
R829
1K
5% 1/16W MF 402
2
DEVELOPMENT
1
R800
330
5% 1/16W MF 402
2
ERROR_LED
1
2
1
R809
10K
5% 1/16W MF 402
2
NOSTUFF
1
2
DEVELOPMENT
D810
RED
SM
PP3V3_RUN
R827
1K
5% 1/16W MF 402
27
77
27
27
76
27 37
13
13
13
13
13
13
13
13
13
24
76
49
75
77
1
R804
10K
2
5% 1/16W MF 402
6
6
6
6
6
6
1
R811
20K
5% 1/16W MF 402
2
ELECTRICAL_CONSTRAINT_SET
SMU_RESET
I246
SMU_RESET
I247
PP2V5_PWRON
SMU_WARM_RESET_L SYS_WARM_RESET_L
13 25
8 8
SMU_SLEEP
13
NB_SUSPEND_ACK_L
24
SMU_BOOT_SCLK
13
SMU_BOOT_CE
33
33
33
33
33
33
13
SMU_BOOT_CNVSS
13
NET_SPACING_TYPE
10 MIL SPACING
10 MIL SPACING
1
R870
4.7K
5% 1/16W
U700
MF 402
2
R806
10K
1/16W
74LCX125
14
9
8
125
7
10
U700
74LCX125
14
5
6
125
47
U700
74LCX125
14
11
12
125
7
13
PP3V3_ALL
NOSTUFF
1
1
R807
10K
5%
5%
1/16W MF
MF
402
402
2
2
J802 & R826 CAN MOVE TO DEVELOPMENT BOM POST RAMP
PLL LOCK LED
=PP5V_RUN_CPU
31
8
7
6
3
DEVELOPMENT
1
R837
DEVELOPMENT
180
5%
Q802
2N3906
29
PLLLOCK
DEVELOPMENT
R839
180
5%
MF
402
21
Q803_B
MF 402
2
Q803_C
1
Q802_B
DEVELOPMENT
1
R838
1K
5% 1/16W MF 402
2
3
DEVELOPMENT
Q803
2N3904
SM
2
SM
1
DIFFERENTIAL_PAIR
SYS_SLEEP
NB_SUSPENDACK_L
DOWNLOAD CONNECTOR
J802
HC17051
M-ST-TH
1
2
J802_2
43
65
J802_6
87
9
10
R835
180
5% 1/16W MF 402
DEVELOPMENT
LED802
GREEN
2.0X1.25A
NOSTUFF
R805
1/16W
518-0158
2
3
Q802_E
DEVELOPMENT
1
2
LED802_1
1
2
402
10
9
6
13
1
0
5%
MF
2
14
6
29
SYS_COLD_RESET_L
SYS_WARM_RESET_L
87
77
74
46
50
11
R826
100
21
5%
MF
402
SMU_MANUAL_RESET_L
1
R803
10K
5% 1/16W MF 402
2
CHKSTOP_L
NB_PMR_OBSV
24
SMU_BOOT_BUSY
SMU_BOOT_RXD
(SMU_BOOT_EPM)
SMU_BOOT_TXD
=PP5V_RUN_CPU
3
31
8
7
6
DEVELOPMENT
R836
180
21
5%
Q801_B
MF
402
24
13
8
77
74
25
87
U.FL-R_SMT
13
13
13
6
8
7
13
NOSTUFF
C801
2.2UF
CHKSTOP LED
DEVELOPMENT
1
R834
180
5% 1/16W MF 402
2
Q800_G
3
DEVELOPMENT
1
Q801
2N3904
SM
2
DEVELOPMENT
J800
F-ST-SM
3
1
2
518S0104
PP3V3_ALL_SMU_AVCC
1
20% 10V
2
CERM
805
DEVELOPMENT
1
R833
180
5% 1/16W MF 402
2
LED801_1
1
2
Q800_D
3
DEVELOPMENT
D
Q800
2N7002
1
SM
G
S
2
SMU ANALOG VREF
NOSTUFF
1
R818
200
1% 1/16W MF 402
NOSTUFF
2.5V
SSOT-23
VR801
DEVELOPMENT
LED801
RED
SM
2
12
3
PPVREF_SMU MAKE_BASE=TRUE
R802
0
5%
MF
402
NOSTUFF
1
C802
0.47UF
20% 10V
2
CERM 603
NOSTUFF
R828
0
5%
MF
402
21
PPVREF_SMU_ADC_REF
GND_SMU_AVSS
21
GND_SMU_AVSS_DAGND
HS_SDF800 HS_SDF801 HS_SDF802
1
2
HS_SDF803
1
2
=PPVREF_SMU
SDF800
HSK-NUT-6.5MM
1
C880
0.01UF
20% 16V CERM 402
SDF803
HSK-NUT-6.5MM
1
C883
0.01UF
20% 16V CERM 402
POWER_FAIL_L CONNECTION
POWER_GOOD
7
13
36
33
13
36
STDOFF-6MMOD1MMH-TH
36
CPU HEATSINK SMT NUTS
NOSTUFF
TH
1
2
NOSTUFF
TH
HS_SDF804
1
2
PP3V3_ALL
NOSTUFF
1
1
R812
R813
10K
430
5%
5% 1/16W
1/16W MF
MF 402
2
1
2
402
2
SYS_POWERFAIL_L
R860
4.7K
POWER_GOOD IS A 5V DRIVEN
5%
SIGNAL FROM POWER SUPPLY
2K PULLUP INSIDE P/S
AIRPORT CARDGUIDE
SMT NUTS
SDF890
1
HSK-NUT-6.5MM
C881
0.01UF
20% 16V CERM 402
6P15R5P4
C884
0.01UF
20% 16V CERM 402
STDOFF-6MMOD1MMH-TH
NOSTUFF
SDF801
TH
1
1
C882
0.01UF
20% 16V
2
CERM 402
OMIT
ZH804
1
SDF700 IS ALSO
USED FOR HEATSINK
MOUNTING
13
6
SDF891
1
NOSTUFF
SDF802
HSK-NUT-6.5MM
TH
1
D
C
B
SIGNAL ALIAS
A
I
SHASTA JTAG
TP_JTAG_SB_TCK
MAKE_BASE=TRUE
TP_JTAG_SB_TDI
MAKE_BASE=TRUE
TP_JTAG_SB_TDO
MAKE_BASE=TRUE
TP_JTAG_SB_TMS
MAKE_BASE=TRUE
PULL DOWN
25
THESE PINS HAVE INTERNAL PULLUPS
ALIAS
ALIAS
ALIAS
ALIAS
JTAG_SB_TRST_L
JTAG_SB_TCK
JTAG_SB_TDI
JTAG_SB_TDO JTAG_SB_TMS
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1
25
25
25
25
R825
10K
5% 1/16W MF 402
2
APPLE COMPUTER INC.
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
REV.
OF
8
103
8
67
5
4
3
2
1
78
6
5
4
3
12
D
D
2.5V VOLTAGE REGULATOR
1
1
PP5V_PWRON
G
G
U900_VC_D
4
D
Q901
NTD70N03R
CASE369
S
3
Q902_DRAIN
4
D
Q902
NTD70N03R
CASE369
S
3
1
D902
MBR0520L
SM
2
1
C917
1UF
20% 10V
2
CERM 603
NOSTUFF
1
R904
1.1K
5% 1/8W FF 1206
2
R904_P2
1
2
NOSTUFF
C912
1UF
20% 25V CERM 1206
1
C901
10UF
20%
6.3V
2
CERM 1206
CRITICAL
L901
1.6UH
TH
1
2
21
CRITICAL
C902
390UF
20%
6.3V ELEC 8X11.5-TH
NOSTUFF
1
C907
3300PF
10% 50V
2
CERM 603
1
C903
390UF
20%
6.3V
2
ELEC 8X11.5-TH
1
R903
11K
1% 1/16W MF 402
2
1
R905
10K
1% 1/16W MF 402
2
1
2
PP5V_PWRON
D900
21
1
R900
4.7
5% 1/10W FF 805
2
26
VCC
VC
U900
SOI
GND
4
U900_VC
HD
LD
FB
1
C904
1UF
C
20% 25V
2
CERM 805
IRU3037CS
1
C915
0.47UF
20% 10V
2
CERM 603
U900_SS
U900_COMP
1
R901
27.4K
1% 1/16W MF 402
2
R901_P2
1
C914
3900PF
5% 50V
2
CERM
603
1
C913
2
8
7
56PF
5% 50V CERM 402
SS
COMP
5
U900_GATE_H
3
U900_GATE_L
1
U900_FEEDBACK
6
U900_VC_R
1
C916
1UF
20% 25V
2
CERM 805
1
C906
220PF
5% 25V
2
CERM 402
MBR0520L
D901
21
MBR0520L
R902
0
5%
FF
805
SM
SM
21
Q901_GATE
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
NOSTUFF
1
C905
0.022UF
10% 50V
2
CERM 603
NOTE: SET OUTPUT=2.62V FOR FRAMEBUFFER. IRU3037CS VREF=1.25VDC VOUT=VREF*(R903+R905)/R905=2.62VDC
PEAK CURRENT OF TOTAL RAILS
12.68A WITH DIMM TERMINATION
9.24A WITHOUT DIMM TERMINATION
PP2V5_PWRON
VOLTAGE=2.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
C908
1800UF
20%
6.3V ELEC TH-KZJ
1
2
C909
1800UF
20%
6.3V ELEC TH-KZJ
3
2
1
Q903
IRF7410
SO-8
S
G
4
8
7
D
6
5
LOW TO ENABLE
SYS_SLEEP
PP2V5_RUN
8 6
C
50 46 11 10
U900_FEEDBACK
B
B
2.5V VREG
A
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
9
REV.
OF
103
A
I
8
67
5
4
3
2
1
78
6
5
4
3
12
SHASTA CORE VOLTAGE REGULATOR
D
PP5V_ALL
D1000
21
1
R1002
4.7
5% 1/10W FF 805
2
26
VCC
VC
U1000
SOI
GND
4
U1000_VC
HD
LD
FB
1
C1004
1UF
20% 25V
2
CERM 805
8
7
1
C1013
68PF
5% 50V
2
CERM 603
SS
COMP
IRU3037ACS
PP3V3_ALL
U1000_SS
1
R1007
100K
5%
MF
402
2
C
TURN_ON_SHASTA_CORE_L
3
NOSTUFF
SYS_POWERUP_L
6
11
10
13
33
7
R1011
R1010
0
21
Q1000_G
5%
MF
402
0
21
5%
MF
3
D
Q1000
2N7002
1
SM
G
S
2
1
C1015
0.1UF
20% 16V
2
CERM 603
U1000_COMP
1
R1001
27.4K
1% 1/16W MF 402
2
R1001_P2
1
C1014
3900PF
5% 50V
2
CERM 603
U1000_VC_R U1000_VC_D
1
C1000
1UF
20% 25V
2
CERM 805
5
U1000_GATE_H
3
U1000_GATE_L
1
U1000_FEEDBACK
1
C1006
220PF
5% 25V
2
CERM 402
MBR0520L
D1001
21
MBR0520L
R1000
0
5%
FF
805
SM
SM
21
Q1001_GATE
MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL
NOSTUFF
1
C1005
0.022UF
10% 50V
2
CERM 603
1
PP5V_ALL
D
1
G
S
G
4
Q1001
NTD60N02R
CASE369
3
Q1002_DRAIN
4
D
Q1002
NTD70N03R
CASE369
S
3
1
D1002
MBR0520L
SM
2
1
C1017
1UF
20% 10V
2
CERM 603
NOSTUFF
1
R1004
1.1K
5%
1/8W FF 1206
2
R1004_P2
1
2
NOSTUFF
C1012
1UF
20% 25V CERM 1206
1
C1001
10UF
20%
6.3V
2
CERM 1206
L1001
1.6UH
TH
U1000_FEEDBACK
1
C1002
390UF
20%
6.3V
2
ELEC 8X11.5-TH
21
NOSTUFF
1
C1007
3300PF
10% 50V
2
CERM 603
1
C1003
390UF
20%
6.3V
2
ELEC 8X11.5-TH
MAKE_BASE=TRUE VOLTAGE=1.2V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=15MIL
1
R1003
5.11K
1% 1/16W MF 402
2
1
R1005
10K
1% 1/16W MF 402
2
NOTE: SET OUTPUT=1.2V IRU3037ACS VREF=0.8VDC VOUT=VREF*(R1003+R1005)/R1005=1.206VDC
PEAK CURRENT OF TOTAL RAILS
5.96A
1
C1008
1800UF
20%
6.3V
2
ELEC TH-KZJ
1
C1009
1800UF
20%
6.3V
2
ELEC TH-KZJ
PPVCORE_PWRON_SB
=PPVCORE_PWRON_SB
10
6
3
23
D
C
PP1V2_PWRON FET SWITCH
PEAK CURRENT 0.6A
PP1V2_PWRON
B
Q1006
21
SI3446DV
TSOP
R1009
100K
21
5%
MF
402
Q1005_G
NOSTUFF
R1013
0
5%
MF
PP5V_ALL
21
R1012
0
5%
MF
402
PP3V3_ALL
1
R1014
100K
5%
MF
402
TURN_ON_PP1V2_L
3
SYS_POWERUP_L
6
11
10
13
33
7
2
Q1006_G
1
521
RDSON=0.06 OHM @ VGS=2.5 V
4
36
3
D
Q1005
2N7002
SM
G
S
2
PP1V2_RUN FET SWITCH
PEAK CURRENT 4.43A
PPVCORE_PWRON_SBPPVCORE_PWRON_SB
3 3
10 10
PP5V_ALL
6 6
R1008
100K
21
5%
MF
402
Q1004
2N7002DW
SOT-363
8765
Q1003_G
5
G
Q1003
SI9426DY
SOI
I70
4
3
D
S
4
6
D
S
1
321
RDSON=0.016 OHM @ VGS=2.5 V
Q1004
2N7002DW
SOT-363
2
G
PP1V2_RUN
SYS_SLEEP
B
6
11
46
50
9
8
1.2V VREG
A
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
10
REV.
OF
103
A
I
8
67
5
4
3
2
1
3
7
6
6
PP5V_ALL
5
78
11
4
12
D
PP5V_RUN
18
6
100K
5%
MF
402
R1100
100K
21
R1103
100K
RAIL_CTL_POS
RAIL_CTL_NEG
3
5%
MF
402
5%
MF
402
R1102
47.0K
21
21
1
1%
MF
603
2
10
11
4
5
V+
U1100
GND
12
V+
U1100
GND
12
3
CRITICAL
3
LM339A
SOI
LM339A
SOI
13
2
RUN -> FLOAT SLEEP -> LOW SHUTDOWN -> FLOAT
RAIL_RUN_FET MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
RUN -> LOW SLEEP -> FLOAT SHUTDOWN -> FLOAT
RAIL_SLEEP_FET MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
FET ON IN SLEEP
Vpwr >= Vout+0.35V
Vctrl >= Vout+1.25V
PP3V3_ALL
59
90
11
7
R1104
50 46
SYS_POWERUP_L
10
33
13
7
6
SYS_SLEEP
10
9
8
6
C
PP5V_ALL
11
7
6
CRITICAL
Q1100
SI4467DY
8
7
D
6
5
FET ON IN RUN
G
1
2
3
P-CHANNEL Ron=11mOhm
SM-1
CRITICAL
Q1101
4
SI4467DY
SM-1
S
G
4
DS
1
C1102
100UF
2
3
2
1
5
6
7
8
CRITICAL
VR1100
5
4
VCTRL
20%
6.3V ELEC SM
1
R1107
1K
1% 1/16W MF 402
2
1
SENSE
CS5253
SM
VOUTVPWR VOUT
TAB
ADJ
2
3_3V_ALL_ADJ MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
1
C1101
0.1UF
N20P80% 16V
2
CERM 603
PP5V_PWRON
VOLTAGE=5V
PP5V_PWRON
1
R1101
1K
1% 1/16W MF 402
2
3
6
R1
R2
1
R1105
124
1% 1/16W MF 603
2
1
R1106
210
1% 1/16W MF 603
2
PP3V3_RUN
18
6
FET ON IN RUN
FET ON IN SLEEP
PROCESS SWING
3.30V - 3.45V
Vout=Vref(1+R2/R1)+Iadj(R2)
Vref=1.250V typ Iadj=50uA typ
1
C1100
150UF
20% 10V
2
ELEC SM
8
7
6
5
1
2
3
Q1102
SI4467DY
SM-1
D
Q1103
4
SI4467DY
SM-1
G
P-CHANNEL Ron=11mOhm
S
G
4
DS
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
PP3V3_PWRON
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL
3
MIN_NECK_WIDTH=10MIL
2
1
5
6
7
8
PP3V3_ALL
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
18
6
27
18
6
59
11
90
7
D
C
B
B
5V & 3.3V VREGS
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
11
1
REV.
OF
103
A
I
ELECTRICAL_CONSTRAINT_SET
SMU_CLK10M_XTAL
RTC_CLK32K_XTAL
Page Notes
Power aliases required by this page:
D
- _PP3V3_ALL_SMU
- _PP3V3_ALL_RTC
- _PP3V3_PWRON_SMU
- _PPVREF_SMU (SMU AVCC or 2.5V reference)
Signal aliases required by this page: (NONE)
BOM options provided by this page: (NONE)
NOTE: CPU current/voltage monitoring (CPU_SENSE_I/CPU_SENSE_V) requires 100K/10uF RC filter at SMU pins. Caps should connect to GND_SMU_AVSS. SMU_VREF should be same signal or reference used by monitoring circuit, but be aware that this will affect other analog inputs such as AC adapter ID.
NOTE: All analog inputs to SMU should have a 100pF capacitor to the SMU AVSS signal (GND_SMU_AVSS). None of those capacitors are provided on this page.
NOTE: Some primary and alternate functions reuire pull-ups that are not.
C
provided on this page. Please. review the latest SMU specification to ensure missing pull-ups are provided on another page.
NOTE: Pinout matches SMU pinout v1.51.
B
NET_SPACING_TYPE
15 MIL SPACING
15 MIL SPACING
15 MIL SPACING
15 MIL SPACING 15 MIL SPACING
78
DIFFERENTIAL_PAIR
SMU_CLK10M_XIN
SMU_CLK10M_XOUT
SMU_CLK10M_XOUT_R
RTC_CLK32K_X1 RTC_CLK32K_X2
=PP3V3_ALL_SMU
6
7
8
13
SMU_TO_SB_INT_L
25
D1310
1N914
C1310
0.22uF
SMU_CLK10M_XOUT
13
13
13
13
13
13
3
1
20%
6.3V CERM
402
C1304
6
NO_SMU_I2C_D
R1399
1
R1322
150K
5% 1/16W MF 402
2
1
2
R1317
18pF
50V
CERM
402
5%
MF
402
0
5%
MF
402
5%
0
21
NO STUFF
R1316
1
CRITICAL
Y1300
2
10.0000M
8X4.5MM-SM
1
C1305
2
5
4
System Management Unit
=PP3V3_ALL_SMU
6 8
8
7
13
C1300
Y = Primary function N = Alternate function
(see aliases below) S = Spare
CPU_SENSE_I
33
CPU_SENSE_V
33
CPU_TEMP
36
CPU_BYPASS
30
FAN_RPM3
13
FAN_RPM4
13
FAN_RPM5
13
SMU_ONEWIRE
8
SMU_PWRSEQ_P1_0
3
SMU_PWRSEQ_P1_1
3
SMU_PWRSEQ_P1_2
3
SMU_PWRSEQ_P1_3
8
SMU_PWRSEQ_P1_4
3
SYS_POWERFAIL_L
8
6
13
SYS_DRIVE_BAY_INT_L
13
8
SYS_DOOR_AJAR_L
13
8
I2C_SMU_E_SDA
18
I2C_SMU_E_SCL
18
FAN_TACH0
16
FAN_TACH1
16
FAN_TACH2
17
FAN_TACH3
13
FAN_TACH4
13
FAN_TACH5
13
I2C_SMU_A_SDA_IN
18
I2C_SMU_A_SDA_OUT_L
14
6
18
I2C_SMU_A_SCL_IN
18
I2C_SMU_A_SCL_OUT_L
14
6
18
18
I2C_SMU_D_SDA
I2C_SMU_D_SCL
18
SMU_CHARGE_BATT
13
SYS_OVERTEMP_L
25
16
27
=PPVREF_SMU
8
SMU_BOOT_CNVSS
8
6
8
SMU_RESET_L
13
SMU_CLK10M_XOUT_R
13
SMU_CLK10M_XIN
10M
21
5%
MF
402
21
Keep crystal subcircuit close to SMU.
Y1300’s load capacitance is 12pF
1
18pF
5%
50V
2
CERM
402
10uF
6.3V CERM
20%
805
R1325
1
2
10K
C1301
0.1uF
CERM
1
5%
MF
402
2
1
20% 10V
2
402
Portable
Consumer
Y
Y
YYY
YYY
Y
Y
Y
Y
N
S S
N
YYY
N
YYY YY
Y
Y
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
Y
Y
Y
YN
S
S
N
S
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SSN
Y Y
N
Y
N
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
SS
Y
S
Y
S
1
C1325
1uF
10%
6.3V
2
CERM 402
C1302
0.1uF
CERM
Server
Desktop
Entry Desktop
S
S
67
S
S
66
SS
65
SS
64
Y
63
Y
62
Y
YYY
61 60
Y
Y
59
Y
Y
58
Y
Y
57
Y
Y
56
YSY
Y
55
Y
Y
54
Y
S
53
Y
YY
52
Y
Y
51
Y
Y
50
Y
YYY
49
Y
Y
48
Y
Y
47
Y
Y
46
Y
Y
45
Y
Y
44
Y
YYYY
39
Y
38
Y
Y
37
Y
Y
36
Y
Y
35
Y
Y
34
S
S
33
S
S
32
6
9 10 12 77
20% 10V
402
P0[0] P0[1] P0[2] P0[3] P0[4] P0[5] P0[6] P0[7]
P1[0] P1[1] P1[2] P1[3] P1[4] P1[5] P1[6] P1[7]
P2[0] P2[1] P2[2] P2[3] P2[4] P2[5] P2[6] P2[7]
P3[0] P3[1] P3[2] P3[3] P3[4] P3[5] P3[6] P3[7]
PCNVSS RESET* XOUT XIN VREF
R1315
4.7
21
5%
1
2
402
MF
13
VCC
U1300
M30280F8
QFP-80
AN00
AN01
OMIT
AN02 AN03
AN04
AN05 AN06
AN07
AN20
AN21 AN22
AN23
INT3*
INT4*
INT5*
SDAmm SCLmm
IOC2
IOC3 IOC4
IOC5
IOC6 IOC7
CLK3 Sin3
Sout3
VSS
11
XW1300
SM
(BUSY)
TA1out
TA2out
TA3out
TA4out
21
PP3V3_ALL_SMU_AVCC
VOLTAGE=3.3V MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
1
C1303
1uF
10%
6.3V
2
CERM 402
GND_SMU_AVSS
78
AVCC
RTS0*/ CTS0*
P6[0] P6[1]
CLK0
P6[2]
RXD0 TXD0
P6[3]
RTS1*
P6[4] P6[5]
CLK1
P6[6]
RXD1
P6[7]
TXD1
P7[0]
SDA
P7[1]
SCL
P7[2] P7[3]
TA1in
P7[4]
TA2in
P7[5] P7[6] P7[7]
TA3in
P8[0]
TA4in
P8[1] P8[2]
INT0*
P8[3]
INT1* INT2*
P8[4]
NMI*
P8[5] P8[6]
CE*
P8[7]
P9[0]
TB0in
P9[1]
TB1in
P9[2]
TB2in
AN24
P9[3]
AN25
P9[5]
AN26
P9[6]
AN27
P9[7]
AN0
P10[0] P10[1]
AN1
P10[2]
AN2
P10[3]
AN3
P10[4]
KI0* KI1*
P10[5] P10[6]
KI2*
P10[7]
KI3*
AVSS
75
GND_SMU_AVSS
VOLTAGE=0V MIN_LINE_WIDTH=15 mil MIN_NECK_WIDTH=10 mil
43 42 41 40 31 30 29 28
27 26 25 24 23 22 21 20
19 18 17 16 15 14 8 7
5 4 3 2 1 80 79
76 74 73 72 71 70 69 68
Consumer
Portable
Y
Y
Y
Y
YYYY
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y Y
Y
Y
Y
Y
Y
YSSNN
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
S
S
S
Y
Y
Y
Y
YYYY Y
Y
Y
Y
Y
Y
Y
YYYY
Y
Y
Y
Y
YYY
Y
Y
Y
Y
Y
Y
SSYYY
SYYS
S
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
8
13
33
13
8
36
Server
Desktop
Entry Desktop
N
N
N
N N
N
SS
S
S
S
S
Y
Y
Y
Y
Y
YYYY
Y
N
N
Y
Y
Y
Y
YY
Y
Y
Y
Y
Y
Y
Y
Y
S
S
Y
Y
S
S
Y
Y
Y
Y
Y
Y
S
S
Y
Y
Y
Y
Y
Y
Y
S
S
S
Y
Y
Y
Y
YY
Y
Y
Y
Y
Y
Y
SS
1
R1327
10K
5% 1/16W MF 402
2
36
33
SMU_BOOT_BUSY SMU_BOOT_SCLK
SMU_BOOT_CE
CPU_VID<0>
CPU_VID<1>
CPU_VID<2> CPU_VID<3>
CPU_VID<4>
CPU_VID<5> SMU_BOOT_RXD
SMU_BOOT_TXD
I2C_SMU_B_SDA
I2C_SMU_B_SCL I2C_SMU_CPU_SDA_IN
FAN_RPM0
I2C_SMU_CPU_SCL_IN FAN_RPM1
FAN_PWM8
FAN_RPM2
SYS_LED
SYS_COLD_RESET_L SYS_PME_L
SMU_QREQ SYS_SLEWING_L
I2C_SMU_CPU_SDA_OUT_L
SYS_POWERUP_L
MAKE_BASE=TRUE
SMU_SLEEP
CLOCK_RESET_L CPU_HRESET
SB_TO_SMU_INT_L
SB_STOPXTALS_L SMU_PWRSEQ_P9_5
SMU_PWRSEQ_P9_6 SYS_SLOT_PWR
TP_SMU_SPARE_P10_0
SMU_WARM_RESET_L
NB_SUSPENDACK_L SB_SUSPENDACK_L
SMU_SUSPENDREQ_L
SYS_POWER_BUTTON_L SYS_RESET_BUTTON_L
I2C_SMU_CPU_SCL_OUT_L
3
12
Real Time Clock
=PP3V3_ALL_RTC
7
=PP3V3_ALL_SMU
6
8
7
13
C1308
I2C_RTC_SDA
18
I2C_RTC_SCL
18
8
8
8
13
8
13
8
13
8
8
8
8
8
8
18
18
18
13
16
18
13
16
13
8
17
21
13
8
24
77
25
13
28
27
25
33
13
18
6
10
7
33
13
11
8
13
27
30
25
25
3
3
8
8
8
25
25
24
28
13
7
6
13
13
7
18
SMU Pull-ups / pull-down
PP3V3_PWRON
PP3V3_RUN
PP2V5_PWRON
1
0.1uF
20% 10V
2
CERM
402
NC
=PP3V3_ALL_SMU
R1302
10K
21
5%
MF
402
R1313
100K
21
5%
MF
402
5
6
7
R1300
10K
5%
MF
402
R1303
10K
5%
MF
402
R1304
10K
5%
MF
402
R1312
2K
5%
MF
402
NO STUFF
R1311
2K
5%
MF
402
R1310
100K
5%
MF
402
VCC
U1301
DS1338
MSOP
SDA
SCL SQW/
OUT
GND
8
7
6
13
21
21
12
21
21
21
8
1
X1
2
X2
3
VBAT
4
SYS_POWERUP_L
SYS_POWER_BUTTON_L
SYS_RESET_BUTTON_L
SYS_PME_L
SYS_SLEWING_L
SMU_SUSPENDREQ_L
SYS_COLD_RESET_L
SMU_SLEEP
1
C1309
0.1uF
20% 10V
2
CERM 402
RTC_CLK32K_X1
CRITICAL
1
Y1301
32.768K
SM-1
4
RTC_CLK32K_X2
6
11
10
7
13
6
7
7
13
13
25
77
13
25
33
27
13
24
28
25
8
13
24
8
13
13
D
13
C
33
13
B
Master: Link
A
Portable
FAN_RPM3 ALS0_OUT
13
FAN_RPM4 ALS1_OUT
13
FAN_RPM5
13
SYS_POWERFAIL_L
8
6
13
SYS_DRIVE_BAY_INT_L
8
13
SYS_DOOR_AJAR_L
8
13
FAN_PWM8
8
13
Port
0.4
0.5
0.6
1.5
1.6
1.7
7.6
ALS_GAIN_BOOST SMU_ACIN
SMU_BATT_DET_L
SYS_LID_OPEN SYS_KBDLED
8
8
8
8
Alternate Functions
Consumer
FAN_TACH3
13 21
FAN_TACH4
13 21
FAN_TACH5 SMU_CHARGE_BATT
13
Port
2.5
2.6
2.7
3.6
SYS_LED_RED
SYS_LED_GREEN
SYS_LED_BLUE DIAG_LED
67
Tower & Server
CPU_VID<0>
13
8
CPU_VID<1>
13
8
CPU_VID<2>
13
21 13
8
8
I2C_SMU_CPU_SDA_IN
13
18
I2C_SMU_CPU_SCL_IN
13
18
Port
6.0
6.1
6.2
7.2
7.4
FAN_TACH6
FAN_TACH7
FAN_TACH8 FAN_PWM6
FAN_PWM7
APPLE COMPUTER INC.
5
4
3
System Management Unit
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6482
NONE
SHT
2
A
REV.
I
OF
13 103
1
78
6
5
4
3
12
DEVELOPMENT
R1400
0
EI_CPU1_CLK_P_R
27
EI_CPU1_CLK_N_R
27
D
27
27
CPU1_HTBEN_R
EI_CPU1_SYNC_R
5% MF
DEVELOPMENT
R1401
0
5% MF
DEVELOPMENT
R1402
0
5% 402
DEVELOPMENT
0
R1403
4025%
21
21
21
21
EI_CPU1_CLK_P
EI_CPU1_CLK_N
CPU1_HTBEN
EI_CPU1_SYNC
6
27
14
14
6
27
D
6
14
6
27
14
=PP1V2_EI_CPU
EI_CPU1_SYNC
14
6
27
CHKSTOP_L
8
6
29
C
EI_NB_TO_CPU_AD<13>
6
29
28
EI_NB_TO_CPU_AD<15>
6
29
28
EI_NB_TO_CPU_AD<17>
6
29
28
EI_NB_TO_CPU_AD<21>
6
29
28
EI_NB_TO_CPU_AD<20>
6
29
28
EI_NB_TO_CPU_AD<25>
6
29
28
EI_NB_TO_CPU_AD<29>
6
29
28
EI_NB_TO_CPU_AD<28>
6
29
28
EI_NB_TO_CPU_AD<40>
6
29
28
EI_NB_TO_CPU_AD<10>
6
29
28
EI_NB_TO_CPU_AD<39>
6
29
28
EI_NB_TO_CPU_AD<36>
29
RI_L
30
EI_QREQ_L
30
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
H30
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 G25
G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24
G26H26 G27H27 G28H28 G29H29 G30H30
G1
G1
G2
G2
G3
G3
NC
G4
G4
G5
G5
G6
G6
G7
G7
G8
G8
G9
G9
G10
G11
G12
NC
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
G29
G30
EI_CPU1_CLK_P
EI_CPU_TO_NB_AD<3>
EI_CPU_TO_NB_AD<4>
EI_CPU_TO_NB_AD<7> EI_CPU_TO_NB_AD<11>
EI_CPU_TO_NB_CLK_N EI_CPU_TO_NB_CLK_P
EI_CPU_TO_NB_SR_N<1>
EI_CPU_TO_NB_SR_P<1>
EI_CPU_TO_NB_AD<17>
EI_CPU_TO_NB_AD<14> EI_CPU_TO_NB_AD<24>
EI_CPU_TO_NB_AD<28>
EI_NB_TO_CPU_AD<14> EI_NB_TO_CPU_AD<12>
EI_NB_TO_CPU_AD<18> EI_NB_TO_CPU_AD<19>
EI_NB_TO_CPU_AD<27>
EI_NB_TO_CPU_AD<26> EI_NB_TO_CPU_AD<30>
EI_NB_TO_CPU_AD<42>
EI_NB_TO_CPU_AD<41>
EI_NB_TO_CPU_SR_N<0> EI_NB_TO_CPU_SR_P<0>
I2C_SMU_A_SCL_OUT_L
14
14
6
27
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
28
6
29
28
6
29
28
6
29
28
6
29
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6 6
28 28
29
6 6
29
28 29
29
6 6
18 29
28
13 28
EI_CPU1_CLK_N
6 27
EI_NB_TO_CPU_AD<5>
6 29
EI_NB_TO_CPU_AD<37> EI_NB_TO_CPU_SR_N<1>
EI_NB_TO_CPU_SR_P<1>
6 29
F1
F1
F2
F2
F3
F3
F4
F4
F5
F5
F6
F6
F7
F7
F8
F8
F9
F9
F10
F10
F11
F11
F12
F12
F13
F13
F14
F14
F15
F15
F16
F16
F17
F17
F18
F18
F19
F19
F20
F20
F21
F21
F22
F22
F23
F23
F24
F24
F25
F26
F27
F28
F29
F30
E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25F25 E26F26 E27F27 E28F28 E29F29 E30F30
E1
E1
E2
E2
E3
E3
E4
E4
E5
E5
E6
E6 E7 E8 E9
EI_CPU_TO_NB_AD<8>
E7
EI_CPU_TO_NB_AD<13>
E8
NC
E9
EI_CPU_TO_NB_AD<12>
E10
EI_CPU_TO_NB_AD<5>
E11
EI_CPU_TO_NB_AD<36>
E12
EI_CPU_TO_NB_AD<35>
E13
EI_CPU_TO_NB_AD<18>
E14
EI_CPU_TO_NB_AD<43>
E15
EI_CPU_TO_NB_AD<42>
E16
EI_CPU_TO_NB_AD<38>
E17
EI_CPU_TO_NB_AD<40>
E18
EI_NB_TO_CPU_AD<9>
E19
EI_NB_TO_CPU_AD<11>
E20
EI_NB_TO_CPU_AD<0>
E21
EI_NB_TO_CPU_AD<1>
E22
E23
EI_NB_TO_CPU_AD<22>
E24
EI_NB_TO_CPU_AD<33>
E25
EI_NB_TO_CPU_AD<43>
E26
EI_NB_TO_CPU_AD<2>
E27
EI_NB_TO_CPU_AD<38>
E28
E29
TP_PROC_TRIGGER_OUT
E30
SYNCENABLE
18
7
30
35 31
29
NOSTUFF
J1400
YFS-30-03-H-08-SB
28
6
6
6
28
6
6
6
6
6
6
6
6
28
6
6
28
6
6
28
6
6
6
6
28
29
6 29
6 6
29 28
6 6
F-ST-BGA
30
29
29
28
29
28
29
29
28
29
28
29
28
29
28
29
28
29
28
29
28
29
29
28
29
29
29
29
28
29
28
29
28
29
29
28
30 29
29 28
29
25
28
28
28
28
28
CPU_INT_L
6
EI_CPU_TO_NB_AD<15>
6 29
EI_NB_TO_CPU_AD<8>
6
EI_NB_TO_CPU_AD<24>
6
EI_NB_TO_CPU_AD<7>
6 29
EI_NB_TO_CPU_AD<6>
EI_QACK_L
6
=PP1V2_EI_NB
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
D16
D16
D17
D17
D18
D18
D19
D19
D20
D20
D21
D21
D22
D22
D23
D23
D24
D24
D25
D26
D27
D28
D29
D30
=PP1V2_EI_NB
7
28
18
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
6
29
28
28
6
29
6
29
28
28
6
29
29
29
29
29
29
29
29
29
29
6 6
29 29
28 28
30
18
14
EI_NB_TO_CPU_AD<4>
29
EI_NB_TO_CPU_AD<3>
28
6
EI_NB_TO_CPU_AD<16>
28
6
EI_NB_TO_CPU_AD<35>
6
28
EI_NB_TO_CPU_AD<34>
6
28
EI_NB_TO_CPU_AD<31>
6
28
EI_NB_TO_CPU_AD<32>
6
28
EI_NB_TO_CPU_AD<23>
6
28
EI_NB_TO_CPU_CLK_N
6
28
EI_NB_TO_CPU_CLK_P
6
28
MCP_L
6
29
I2C_SMU_A_SDA_OUT_L
6
13
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
B10
B10
B11
B11
B12
B12
B13
B13
B14
B14
B15
B15
B16
B16
B17
B17
B18
B18
B19
B19
B20
B20
B21
B21
B22
B22
B23
B23
B24
B24
B25
B25
B26
B27
B28
B29
B30
7
28
18
14
C1
C1 B1 A1
C2
C2
C3
C3
C4
C4
C5
C5
C6
EI_CPU_TO_NB_AD<6>
C7
EI_CPU_TO_NB_AD<21>
C8
EI_CPU_TO_NB_AD<20>
C9
EI_CPU_TO_NB_AD<25>
C10
EI_CPU_TO_NB_AD<26>
C11
EI_CPU_TO_NB_SR_P<0>
C12
EI_CPU_TO_NB_SR_N<0>
C13
EI_CPU_TO_NB_AD<27>
C14
EI_CPU_TO_NB_AD<23>
C15
EI_CPU_TO_NB_AD<39>
C16
EI_CPU_TO_NB_AD<16>
C17
EI_CPU_TO_NB_AD<19>
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
EI_SE
C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25D25 C26D26 C27D27 C28D28 C29D29 C30D30
C6 C7 C8 C9
A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26B26 A27B27 A28B28 A29B29 A30B30
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
CPU_HRESET_L
CPU1_HTBEN
EI_CPU_TO_NB_AD<0> EI_CPU_TO_NB_AD<2>
EI_CPU_TO_NB_AD<1> EI_CPU_TO_NB_AD<9>
EI_CPU_TO_NB_AD<10> EI_CPU_TO_NB_AD<22>
EI_CPU_TO_NB_AD<31>
EI_CPU_TO_NB_AD<37> EI_CPU_TO_NB_AD<30>
EI_CPU_TO_NB_AD<34>
EI_CPU_TO_NB_AD<33> EI_CPU_TO_NB_AD<32>
EI_CPU_TO_NB_AD<41>
EI_CPU_TO_NB_AD<29>
29
6
30
14
6
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28
6
29
28 28
6 6
29
C
B
B
CPU LOGIC ANALYZER
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
14
1
REV.
OF
103
A
I
78
6
5
4
3
12
OPTICAL TEMP SENSOR
FAN 1 - Q37 STYLE CPU FAN CONTROL CIRCUIT
CPU FAN 2
R1645
4.7
21
5%
21
5%
1/16W
MF
402
D1604
C1616
4700PF
21
10% 50V
CERM
603
R1644
4.7K
FAN_0_GATE
1N914
31
C1617
1
5%
MF
402
2
3
1
GDS
4
1
1
10UF
CERM 1210
10% 16V
C1618
10UF
10%
2
16V
2
CERM 1210
Q1601
IRF5505
SM
2
1
C1619
D1605
1
47UF
20% 16V
2
ELEC
SM
MAX FAN CURRENT=0.5A
FAN_0_PWR
MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
CRITICAL
SM
MBR0530
PP12V_FAN_0_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
1
R1640
D
R1605
0
21
FAN_RPM0
13
NOSTUFF
R1600
PP3V3_RUN
C
R1606
0
13
FAN_TACH0
5%
1/16W
MF
402
21
5%
1/16W
MF
402
0
5%
1/16W
MF
402
1
2
FAN_0_CNTL
21
R1604
10K
1% 1/16W MF 402
FAN_0_TACH
10K
1% 1/16W MF 402
2
FAN_0_DRV
3
D
Q1600
2N7002
1
SM
G
S
2
MIN_NECK_WIDTH=10MIL
FAN_0_DRV_F
R1641
100K
1%
MF
402
1
R1639
10K
1% 1/16W MF 402
2
NOSTUFF
1
R1603
0
5% 1/16W MF 402
2
21
R1642
1
C1613
0.1UF
20% 16V
2
CERM 603
C1614
100K
1%
MF
402
10UF
21
1
20% 16V
2
ELEC
SM
6
5
FAN_0_OPP
R1601
10K
1%
MF
402
FAN_0_OPM
CRITICAL
U1700
8
LM358-SOI1
7
4
1
2
1
C1601
0.47UF
20% 16V
2
CERM 805
C1615
100PF
FAN_0_GT
R1643
10K
1%
1/16W
MF
402
50V
CERM
402
21
PP12V_RUN
NOSTUFF
1
C1600
10UF
10% 16V
2
CERM 1210
CRITICAL
J1600
HF28040-B
M-ST-TH
1
MOTOR CONTROL
2
TACH
3
GND
4
12V DC
17" SYSTEM FAN 603-5518
20" SYSTEM FAN 603-5521
I2C ADDR:94(1001010)
18
18
I2C ADDR:90(1001000)
I2C_OPTICAL_SDA
18
I2C_OPTICAL_SCL
18
POWER SUPPLY TEMP SENSOR
I2C_PS_TEMP_SDA
I2C_PS_TEMP_SCL
PP3V3_PWRON
U1602
7
A0
6
A1
5
A2
1
SDA
2
SCL
PP3V3_PWRON
VS+
U1650
SOP
LM75
7
A0
6
A1
5
A2
CRITICAL
1
SDA
2
SCL
GND
VS+
SOP
LM75
CRITICAL
GND
NOSTUFF
8
OS
4
NOSTUFF
8
NOSTUFF
3
TEMP_SENSOR_OS SYS_OVERTEMP_L
OS
4
3
PS_SENSOR_OS
R1621
NOSTUFF
R1650
0
5%
MF
402
0
21
5%
MF
402
21
SYS_OVERTEMP_L
D
27
25
16
13
C
27
25
16
13
FAN 2 - Q37 STYLE CPU FAN CONTROL CIRCUIT
SYSTEM FAN 1
R1611
4.7
21
5%
21
5%
1/16W
MF
402
D1602
C1608
4700PF
21
10% 50V
CERM
603
R1610
4.7K
FAN_1_GATE
1N914
31
C1607
1
5%
MF
402
2
3
1
GDS
4
1
1
C1606
10UF
CERM 1210
10% 16V
10UF
10% 16V
2
2
CERM 1210
C1604
47UF
Q1603
IRF5505
SM
MAX FAN CURRENT=0.5A
FAN_1_PWR
CRITICAL
2
D1601
SM
MBR0530
1
ELEC
20% 16V
SM
U1601_UNUSED
6
5
R1636
0
5%
1/16W
MF
402
21
LM358-SOI1
4
R1635
0
5%
1/16W
MF
402
NOSTUFF
R1619
0
5%
1/16W
MF
402
PP3V3_RUN
1
R1623
10K
1% 1/16W MF 402
2
7
21
21
FAN_1_CNTL
FAN_1_TACH
13
PP3V3_RUN
FAN_RPM1
B
A
FAN_TACH1
13
U1601
8
1
R1616
10K
1% 1/16W MF 402
2
FAN_1_DRV
3
D
Q1602
2N7002
1
SM
G
S
2
PP12V_FAN_1_ANALOG
VOLTAGE=12V
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
FAN_1_DRV_F
R1615
100K
1%
MF
402
1
R1620
10K
1% 1/16W MF 402
2
NOSTUFF
1
R1618
0
5% 1/16W MF 402
2
21
R1614
1
C1611
0.1UF
20% 16V
2
CERM 603
C1610
100K
1%
MF
402
10UF
21
1
20% 16V
2
ELEC
SM
2
3
FAN_1_OPP
R1617
10K
1%
MF
402
1
2
FAN_1_OPM
CRITICAL
8
U1601
LM358-SOI1
1
4
1
2
C1609
0.47UF
20% 16V CERM 805
C1605
100PF
FAN_1_GT
R1613
10K
1%
1/16W
MF
402
50V
CERM
402
21
PP12V_RUN
1
2
MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
1
2
FERR-EMI-100-OHM
NOSTUFF
C1603
10UF
10% 16V CERM 1210
FERR-EMI-100-OHM
FERR-EMI-100-OHM
L1602
SM
C1602
0.01UF
L1600
SM
L1601
SM
21
PP12V_RUN_FAN_1_LC VOLTAGE=12V MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
1
20% 16V
2
CERM
402
21
FAN_1_PWR_FILT
21
FAN_1_TACH_FILT
L1604
FERR-EMI-100-OHM
FERR-EMI-100-OHM
CRITICAL
J1601
10-89-7062
TACH
21
M-ST-TH
4
65
FAN_1_GND_FILT VOLTAGE=0V MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
MOTOR CONTROL
SM
17" CPU FAN 603-5519
20" HD FAN 603-5487
L1603
21
SM
1
PP12V_RUN_FAN_1_LCL VOLTAGE=12V MIN_LINE_WIDTH=20MIL MIN_NECK_WIDTH=10MIL
GND
APPLE COMPUTER INC.
FAN 1, 2 & SYSTEM TEMP
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6482
NONE
SHT
16
OF
103
B
A
REV.
I
8
67
5
4
3
2
1
78
6
5
4
3
12
FAN 3 - Q37 STYLE SYSTEM FAN CONTROL CIRCUIT
PP12V_RUN
R1745
4.7
21
5%
21
5%
1/16W
MF
402
C1716
4700PF
21
10% 50V
CERM
603
R1744
4.7K
FAN_2_GATE
D1704
1N914
31
1
5%
MF
402
2
C1717
10UF
CERM 1210
NOSTUFF
C1719
3
4
1
C1718
10UF
10% 16V
2
CERM 1210
Q1701
IRF5505
SM
2
1
1
GDS
1
10% 16V
2
1
47UF
20% 16V
2
ELEC
SM
MAX FAN CURRENT=0.5A
FAN_2_PWR
MIN_LINE_WIDTH=20MIL
MIN_NECK_WIDTH=10MIL
D1705
SM
MBR0530
CRITICAL
1
C1700
10UF
10% 16V
2
CERM 1210
MOTOR CONTROL
TACH
CRITICAL
J1700
10-89-7062
M-ST-TH
4
65
+12V DC
1
GND
17" HD FAN 603-5520
D
C
20" CPU FAN 603-5459
PP12V_FAN_2_ANALOG VOLTAGE=12V MIN_LINE_WIDTH=20MIL
1
R1740
D
R1705
0
21
FAN_RPM2
13
NOSTUFF
R1700
PP3V3_RUN
C
R1706
0
13
FAN_TACH2
5%
1/16W
MF
402
21
5%
1/16W
MF
402
0
5%
1/16W
MF
402
1
2
FAN_2_CNTL
21
R1704
10K
1% 1/16W MF 402
FAN_2_TACH
10K
1% 1/16W MF 402
2
FAN_2_DRV
3
D
Q1700
2N7002
1
SM
G
S
2
MIN_NECK_WIDTH=10MIL
FAN_2_DRV_F
R1741
100K
1%
MF
1
R1739
10K
1% 1/16W MF 402
2
NOSTUFF
1
R1703
0
5% 1/16W MF 402
2
402
21
R1742
1
C1713
0.1UF
20% 16V
2
CERM 603
C1714
100K
1%
MF
402
10UF
21
20% 16V
ELEC
SM
2
3
FAN_2_OPP
R1701
1
2
10K
1%
MF
402
1
C1701
0.47UF
20% 16V
2
CERM 805
FAN_2_OPM
CRITICAL
U1700
8
LM358-SOI1
1
4
1
2
C1715
100PF
FAN_2_GT
R1743
10K
1%
1/16W
MF
402
50V
CERM
402
21
REMOTE HARD DRIVE TEMP SENSOR
REMOTE HD TEMP SENSOR
B
PP3V3_PWRON
I2C_HD_TEMP_SDA
18
I2C_HD_TEMP_SCL
18
I2C ADDR:92(1001001)
CRITICAL
J1701
53261-0498
M-RT-SM 5
1
2
3
4
6
518S0193
B
FAN 3 & HD TEMP
A
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
17
REV.
OF
103
A
I
8
67
5
4
3
2
1
1
R1802
2K
5% 1/16W MF 402
2
SHT
12
18
D
C
B
A
REV.
I
OF
103
78
NOSTUFF
1
1
R1831
2K
5% 1/16W MF 402
2
2
0K
5%
SM1
CPU JTAG
JTAG_CPU_TDO
JTAG_CPU_TDI
JTAG_CPU_TMS
JTAG_CPU_TCK
R1832
0
603
NOSTUFF
R1833
0
603
27
8
SMU_CPU_JTAG_OR_I2C
7
I2C_CPU_A_SCL
6
I2C_CPU_A_SDA_TO_SMU
5
I2C_CPU_A_SDA_TO_CPU
PP5V_PWRON
6
11
PP5V_RUN
6
D
G
S
11
PP3V3_RUN
6
11
NOSTUFF
R1830
RP1800
1
2
3
4
6
Q1801
2N7002DW
SOT-363
1
I2C_CPU_SCL_LS
NOSTUFF
RP1801
0K
5%
1
2
3
4
SM1
2K
5%
MF
402
8
7
6
5
I2C A BUS
SMU
D
C
PP2V5_PWRON
MASTER
U1300
I2C_SMU_A_SDA_IN
13
MAKE_BASE=TRUE I2C_SMU_A_SDA_OUT_L
14
6
13
MAKE_BASE=TRUE I2C_SMU_A_SCL_IN
13
MAKE_BASE=TRUE I2C_SMU_A_SCL_OUT_L
13
14
6
MAKE_BASE=TRUE
PINS 36-39
SMU
MASTER
U1300
I2C_SMU_CPU_SCL_IN
13
MAKE_BASE=TRUE I2C_SMU_CPU_SCL_OUT_L
13
MAKE_BASE=TRUE I2C_SMU_CPU_SDA_IN
13
MAKE_BASE=TRUE I2C_SMU_CPU_SDA_OUT_L
13
MAKE_BASE=TRUE PINS 14,25,23,68
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
I2C
I2C
I2C
I2C
2
I2C C BUS
B
R1805
A
1
1
R1804
2K
2K
5%
5%
MF
402
402
2
2
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
ALIAS
ALIAS
U3LITE
MASTER
U3
I2C_NB_C_SDA MAKE_BASE=TRUE
I2C_NB_C_SCL MAKE_BASE=TRUE
PINS C21, E21
DIMMS
J4000 = A0 J4001 = A2
I2C_DIMM_SDA
I2C_DIMM_SCL
PINS 91, 92
OF EACH DIMM
24
24
24
40
40
6
21
PP5V_U1800
MIN_LINE_WIDTH=12MIL MIN_NECK_WIDTH=8MIL
21
PP3V3_PWRON
18
27
6
11
R1800
PP3V3_PWRON
18
6
11
R1819
29
30
29
30
29
30
29
30
2K
402
1
5%
MF
2
1
2K
5%
MF
402
2
C1800
0.1UF
20% 10V
1
R1801
2K
5% 1/16W MF 402
2
1
2
CERM
402
LM339A
14
LM339A
1
R1818
2K
5% 1/16W MF
LM339A
402
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
13
LM339A
2
C1801
0.1UF
1
2
SOI
U1800
SOI
U1800
SOI
U1800
SOI
U1800
20% 10V
CERM
402
3
V+
GND
12
3
V+
GND
12
3
V+
GND
12
3
V+
GND
12
1
2
NOSTUFF
R1809
I2C_0V6_REF
R1811
4.7K
8
9
6
7
10
11
4
5
4.7K
5
1
0.1UF
20% 10V CERM 402
R1808
200
NOSTUFF
R1820
5%
MF
402
2
1
0
5%
MF
402
2
1
1
R1828
4.7K
5%
5%
MF
402
402
2
2
1
5%
MF
402
2
1
C1802
2
6
D
Q1800
2N7002DW
2
5
5
SOT-363
G
S
1
3
D
Q1800
2N7002DW
SOT-363
G
S
4
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
3
D
Q1801
2N7002DW
SOT-363
G
S
4
USE 576 OHM FOR R1811 IF 5V RAIL IS USED FOR REFERENCE
I2C D & E BUS
PP2V5_PWRON
1
1
R1813
2K
2K
5%
5% 1/16W
MF
MF
402
402
2
2
NOSTUFF
1
1
R1823
0
0
5%
5% 1/16W
MF
MF
402
402
2
2
R1824
21
R1825
21
SMU ’D’ AND RTC CAN MAKE AN I2C ’D’ BUS
R1812
U3LITE ’B’
U3
I2C_NB_B_SDA I2C_NB_B_SCL
PINS C20, B21
I2C
I2C
NOSTUFF
R1822
SMU ’E’
MASTER U1300
I2C_SMU_E_SDA
13
I2C_SMU_E_SCL
13
PINS 50, 51
STANDARD CONFIGURATION: SMU IS MASTER OF BUS E WITH RTC AS SLAVE; U3LITE ’B’ AND SMU ’D’ ARE NOT USED
TO IMPROVE LATENCY WITH RGB LED - U3LITE ’B’ AND SMU ’E’ CAN MAKE AN I2C ’E’ BUS
I2C
I2C
R1807
0
5%
MF
402
0
5%
MF
402
PP3V3_ALL
2K
5%
1/16W
MF
402
1
2
1
R1806
2K
5% 1/16W MF 402
2
NOSTUFF
R1826
0
21
5%
MF
402
NOSTUFF
R1827
0
21
5%
MF
402
I2C
I2C
I2C
I2C
I2C_RTC_SDA I2C_RTC_SCL
PINS 5, 6
SMU ’D’
I2C_SMU_D_SDA
I2C_SMU_D_SCL
PINS 34, 35
1
2
1
2
RTC
U1301
MASTER U1300
R1810
200
5% 1/16W MF 402
NOSTUFF
R1821
0
5% 1/16W MF 402
R1816
4
=PP1V2_EI_NB
=PP1V2_EI_CPU
1
200
5%
MF
402
2
13
13 24
13
13
7
14
1
R1817
200
5% 1/16W MF 402
2
28
29
30
7
14
I2C_CPU_A_SCL
I2C_CPU_A_SDA
SHASTA
MASTER
U2300
I2C_SB_SDA
25
MAKE_BASE=TRUE
I2C_SB_SCL
25
MAKE_BASE=TRUE
PINS Y9, AB7
MICRODASH
J9400
I2C_UDASH_SDA
94
6
I2C_UDASH_SCL
94
6
PINS 21, 24
AUDIO
U9500 / AU300
I2C_AUDIO_SDA
103
95
I2C_AUDIO_SCL
103
95
PINS 18, 19
U3LITE
U3
I2C_NB_A_SDA I2C_NB_A_SCL
PINS A20, B20
35 31
CPU
U2900
PINS AA20, Y21
I2C SB BUS
3
PP3V3_PWRON
I2C B BUS
1
R1803
2K
5%
SMU
MASTER
U1300
I2C_SMU_B_SDA
13
MAKE_BASE=TRUE I2C_SMU_B_SCL
13
MAKE_BASE=TRUE
24
24
29
29
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
ALIAS
ALIAS
PINS 26, 27
PULSAR
U2600
I2C_CLOCK_SDA
27
I2C_CLOCK_SCL
27
PINS C1, B1
OPTICAL TEMP SENSOR
U1602
I2C_OPTICAL_SDA
16
I2C_OPTICAL_SCL
16
PINS 1, 2
I2C ADDR:90
PS TEMP SENSOR
U1650
I2C_PS_TEMP_SDA
16
I2C_PS_TEMP_SCL
16
PINS 1, 2
I2C ADDR:94
HD TEMP SENSOR
U1702
I2C_HD_TEMP_SDA
17
I2C_HD_TEMP_SCL
17
PINS 1, 2
I2C ADDR:92
PP3V3_RUN
1
R1815
1K
5%
MF
402
2
1
R1814
1K
5% 1/16W MF 402
2
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
ALIAS
NET_SPACING_TYPE=I2C
NET_SPACING_TYPE=I2C
MF
402
2
I2C CONNECTIONS
ALIAS
ALIAS
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
8
67
5
4
3
2
1
TOTAL CURRENT EXCLUDING LEDS CURRENT < 170 MICRO AMPS
78
6
5
4
3
12
RGB_LED
C2105
220PF
21
GND_CHASSIS_LED
PLACE THESE PARTS CLOSE TO SMU IC
RGB_LED
G_PWM_IN_H
RGB_LED
R2104
953K
402
RGB_LED
R2105
200K
402
RGB_LED
R2102
1
953K
1%
MF
402
2
1
200K
1%
MF
402
2
R2109
1
1%
MF
2
1
1%
MF
2
953K
402
R_PWM_DC
D
SYS_LED_GREEN
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU
C
PLACE THESE PARTS CLOSE TO SMU IC
SYS_LED_RED
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU
RGB_LED
C2106
0.47UF
RGB_LED
R2115
21
RGB_LED
C2112
0.47UF
CERM
RGB_LED
R2101
0
21
5%
MF
402
1
20% 10V
2
CERM
603
100% DUTY CYCLE OF 3V-PP PWM = 0.5V
0
R_PWM_IN_H
5%
RGB_LED
R2110
MF
402
RGB_LED
R2111
1
20% 10V
2
603
953K
1%
MF
1%
MF
402
G_PWM_DC
1
2
PP5V_PWRON
1
2
4
12
+
13
-
11
G_IN_OFFSET
5MV INPUT OFFSET
PP5V_PWRON
RGB_LED
U2100
4
LP324
5
+
6
-
11
R_IN_OFFSET
RGB_LED
U2100
LP324
14
RGB_LED
C2104
0.022UF
7
R_BASE_DRV
RGB_LED
C2101
0.022UF
G_BASE_DRV
21
20% 16V
CERM
402
21
20% 16V
CERM
402
RGB_LED
R2112
1K
21
1%
MF
402
RGB_LED
R2114
1K
21
1%
MF
402
1
1
B
PLACE THESE PARTS CLOSE TO SMU IC
RGB_LED
R2118
953K
953K
402
200K
402
1
1%
MF
2
1
1%
MF
2
RGB_LED
R2130
0
SYS_LED_BLUE
13
MAKE_BASE=TRUE
PWM INPUT FROM SMU
A
21
RGB_LED
C2118
0.47UF
CERM
20% 10V
603
B_PWM_IN_H
5%
RGB_LED
R2116
MF
402
RGB_LED
R2117
1
2
1
1%
MF
402
2
B_PWM_DC
PP5V_PWRON
3
+
2
-
B_IN_OFFSET
RGB_LED
U2100
4
LP324
1
11
C2102
0.022UF
B_BASE_DRV
RGB_LED
21
20% 16V
CERM
402
RGB_LED
R2127
1K
21
1%
MF
402
1
5%
25V
CERM
402
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
1
RGB_LED
L2100
400-OHM-EMI
SM-1
2
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
3
RGB_LED
Q2102
2N3904
SM
2
G_DRV_FB MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
RGB_LED
1
R2100
25.5
1% 1/16W MF 402
2
MAX LED CURRENT = 0.5 / R
R_DRV_K MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
1
L2101
400-OHM-EMI
SM-1
2
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
3
RGB_LED
Q2108
2N3904
SM
2
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
RGB_LED
1
R2113
25.5
1% 1/16W MF 402
2
B_DRV_K MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
1
RGB_LED
L2102
400-OHM-EMI
SM-1
2
B_DRV MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
3
RGB_LED
Q2114
2N3904
SM
2
B_DRV_FB MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
RGB_LED
1
R2126
25.5
1% 1/16W MF 402
2
G_DRV_K
G_DRV
<-- 17 INCH
CHANGE R2100 VALUE TO SET LED CURRENT
RGB_LED
R_DRV
R_DRV_FB
<-- 17 INCH
<-- 17 INCH
21
7
RGB_LED
LED2100
LATBG66B
AMB-GRN-BLUE
PLCC
1
AMB
3
GRN
4
BLUE
RGB_LED
C2108
220PF
21
CERM
RGB_LED
C2109
220PF
21
CERM
SM-1
21
7
PP5V_PWRON
21
RGB_LED
L2104
6
2
5
5%
25V
402
5%
25V
402
RGB_LED_A MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
RGB_LED
1
C2107
220PF
5% 25V
2
CERM 402
GND_CHASSIS_LED
400-OHM-EMI
RGB_LED
C2103
LED2101
2
WHITE
SM6
SYS_DRV_K
WHITE_LED
MIN_NECK_WIDTH=10MIL
MIN_LINE_WIDTH=25MIL
C2110
220PF
PLACE THESE PARTS CLOSE TO SMU IC
PP3V3_PWRON
NOSTUFF
R2119
953K
21
1%
MF
402
NOSTUFF
R2132
1K
SYS_LED
13
PWM INPUT FROM SMU
20 INCH -->
21
5%
MF
402
(STUFF WHEN SYS_LED_L = ACTIVE HIGH)
(AND NO STUFF R2132, R2119 & Q2100)
114S3921
114S1821
NOSTUFF
Q2100
FDV302P
SOT-23
S
2
G
1
SYS_LED_IN
WHITE_LED
R2107
0
21
5%
MF
402
QTY
DESCRIPTION
1
RES, 39.2 OHM, 1%, 402
RES, 18.2 OHM, 1%, 402
3
D
3
SYS_LED_H
WHITE_LED
R2129
4.7K
1
5%
MF
402
2
REFERENCE DESIGNATOR(S)
WHITE_LED
R2106
1K
21
5%
MF
402
R2100,R2113,R2126
SYS_GATE
BOM OPTION
20_INCH_LCD
NOSTUFF
1
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
21
5%
25V
CERM
1
2
17_INCH_LCD
1
R2103
56.2
1% 1/16W MF 402
2
3
2
402
WHITE_LED
L2103
400-OHM-EMI
SM-1
SYS_LED_DRV_K MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
SYS_LED_DRV_C MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
WHITE_LED
Q2101
FDV301N
SM
APPLE COMPUTER INC.
PP3V3_PWRON
PP5V_PWRON
RGB_LED
U2100
4
LP324
10
+
9
-
11
6
U2100_UNUSED
WHITE_LED
L2105
21
SM-1
GND_CHASSIS_LED
8
PP5V_PWRON
7
0.1UF
CERM
1
1
20% 10V
2
402
SYS_DRV_A MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
400-OHM-EMI
WHITE_LED
1
C2111
220PF
5% 25V
2
CERM 402
INDICATOR LED
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6482 I
SHT
NONE
D
C
21
B
A
REV.
OF
10321
8
67
5
4
3
2
1
78
6
5
D
4
NOTE: SET OUTPUT=1.5VDC FOR U3LITE CORE IRU3037CS VREF=1.25VDC VOUT=VREF*(R2203+R2205)/R2205=1.53VDC
7.73A OF PEAK CURRENT DRAW ON PCORE_NB
3
12
D
PPVCORE_NB
VOLTAGE=1.2V MIN_NECK_WIDTH=10MIL MIN_LINE_WIDTH=25MIL MAKE_BASE=TRUE
=PPVCORE_NB
22
D2200
21
MBR0520L
SM
D2201
21
SM
R2202
PP5V_PWRON
1
D2202
MBR0520L
SM
2
0
21
Q2201_GATE
5%
FF
805
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
NOSTUFF
1
C2205
0.022UF
10%
50V
2
CERM 603
PP5V_PWRON
1
R2200
4.7
5% 1/10W FF 805
2
26
VCC
VC
U2200
SOI
GND
4
U2200_VC
HD
LD
FB
1
2
5
U2200_GATE_H
3
U2200_GATE_L
1
6
U2200_FEEDBACK
1
2
C2216
1UF
C2206
220PF
1
C2204
1UF
20% 25V
2
CERM 805
IRU3037CS
U2200_SS
U2200_COMP
1
C
1
C2214
0.1UF
20% 16V
2
CERM 603
R2201
27.4K
1% 1/16W MF 402
2
R2201_P2
1
C2215
3900PF
5% 50V
2
CERM 603
8
7
1
C2213
68PF
5% 50V
2
CERM 603
SS
COMP
20% 25V CERM 805
5% 25V CERM 402
MBR0520L
PP5V_PWRON
D
G
S
Q2202_DRAIN
D
4
1
G
S
3
U2200_FEEDBACK
CHECK FETS
U2200_VC_DU2200_VC_R
Q2201
NTD60N02R
CASE369
Q2202
NTD60N02R
CASE369
1
C2217
1UF
20% 25V
2
CERM 805
NOSTUFF
1
R2204
1.1K
1% 1/16W MF 402
2
R2204_P2
NOSTUFF
1
C2212
1UF
20% 25V
2
CERM 1206
1
C2201
10UF
20%
6.3V
2
CERM 1206
L2201
1.6UH
TH
1
C2202
390UF
20%
6.3V
2
ELEC 8X11.5-TH
21
NOSTUFF
1
C2207
1UF
20% 10V
2
CERM 603
1
C2203
390UF
20%
6.3V
2
ELEC 8X11.5-TH
1
R2203
2.21K
0.5% 1/16W MF-LF 603
2
1
R2205
10K
0.5% 1/16W MF-LF 603
2
1
C2208
1800UF
20%
6.3V
2
ELEC TH-KZJ
1
C2209
1800UF
20%
6.3V
2
ELEC TH-KZJ
B
7 6
R14
T16
T11
U18
U13
U10
AG13
AG16
AG22
AE10
AE19
AE25
AC13
AC16
AC22
AB23
AB27
AA10
AA19
AG7
AE4
AC7
AB2
AB6
Y12
Y15
Y20
W13
W18
W21
W25
V11
V16
V19
U14
U17
T12
T15
T20
T23
T27
R10
R13
V15
V12
W17
W14
GND
W4
W8
U9
T2
T6
R17
VDD
OMIT
U3
U3LITE
V1.0-300MM
PBGA
(SYM 6 OF 7)
P12
P15
N13
N18
M11
M16
L14
L17
K12
GND
K15
R18
P11
P16
P19
N4
N8
N9
N14
N17
N23
N27
M12
M15
M20
L10
L13
L18
K2
K6
K11
K16
K21
K25
J9
J14
H10
H19
G4
G23
G27
F13
F16
F22
D2
D7
D10
D19
D25
B4
B13
B16
B22
C
B
=PPVCORE_NB
22
1
C2222
0.1UF
20% 10V
2
CERM 402
1
C2223
0.1UF
20% 10V
2
CERM 402
1
C2225
0.1UF
20% 10V
2
CERM 402
1
C2227
0.1UF
20% 10V
2
CERM 402
1
C2228
0.1UF
20% 10V
2
CERM 402
1
C2229
0.1UF
20% 10V
2
CERM 402
1
C2230
0.1UF
20% 10V
2
CERM 402
1
C2231
0.1UF
20% 10V
2
CERM 402
1
C2232
0.1UF
20% 10V
2
CERM 402
1
C2233
0.1UF
20% 10V
2
CERM 402
1
C2234
0.1UF
20% 10V
2
CERM 402
1
C2235
0.1UF
20% 10V
2
CERM 402
1
C2236
0.1UF
20% 10V
2
CERM
402
1
C2237
0.1UF
20% 10V
2
CERM 402
1
C2238
0.1UF
20% 10V
2
CERM 402
1
C2239
0.1UF
20% 10V
2
CERM 402
1
C2240
0.1UF
20% 10V
2
CERM 402
1
C2242
0.1UF
20% 10V
2
CERM 402
1
C2243
0.1UF
20% 10V
2
CERM 402
1
C2244
0.1UF
20% 10V
2
CERM 402
1
C2245
0.1UF
20% 10V
2
CERM
402
1
C2246
0.1UF
20% 10V
2
CERM
402
1
C2247
0.1UF
20% 10V
2
CERM
402
U3LITE CORE POWER
A
APPLE COMPUTER INC.
8
67
5
4
3
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
22
1
REV.
OF
103
A
I
Page Notes
Power aliases required by this page:
- _PPPCI64_PWRON_SB (to 5V or 3.3V)
- _PPPCI32_PWRON_SB (to 5V or 3.3V)
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PPVCORE_PWRON_SB (1.2V) NOTE: PCI pads use the VIO supply to meet different drive timing characteristics required by the PCI spec for 5V vs. 3.3V operation.
D
Connect _PPPCI32_PWRON_SB to appropriate PCI bus voltage and _PPPCI64_PWRON_SB to same if 64-bit PCI, otherwise 3.3V.
Signal aliases required by this page: (NONE)
BOM options provided by this page: (NONE)
Power Sequencing:
Must power Shasta VCore rail before any other Shasta supplies.
C
B
78
10
74
=PPVCORE_PWRON_SB
=PP3V3_PWRON_SB
25
7
1
C2300
0.1uF
20% 10V
2
CERM 402
1
C2305
0.1uF
20% 10V
2
CERM 402
1
C2310
0.1uF
20% 10V
2
CERM 402
1
C2320
0.1uF
20% 10V
2
CERM 402
1
C2325
0.1uF
20% 10V
2
CERM 402
1
C2330
0.1uF
20% 10V
2
CERM 402
1
C2335
0.1uF
20% 10V
2
CERM 402
6
1
C2301
0.1uF
20% 10V
2
CERM 402
1
C2306
0.1uF
20% 10V
2
CERM 402
1
C2311
0.1uF
20% 10V
2
CERM 402
1
C2321
0.1uF
20% 10V
2
CERM 402
1
C2326
0.1uF
20% 10V
2
CERM 402
1
C2331
0.1uF
20% 10V
2
CERM 402
1
C2336
0.1uF
20% 10V
2
CERM 402
1
C2302
0.1uF
20% 10V
2
CERM 402
1
C2307
0.1uF
20% 10V
2
CERM 402
1
C2312
0.1uF
20% 10V
2
CERM 402
1
C2322
0.1uF
20% 10V
2
CERM 402
1
C2327
0.1uF
20% 10V
2
CERM 402
1
C2332
0.1uF
20% 10V
2
CERM 402
1
C2337
0.1uF
20% 10V
2
CERM 402
1
C2303
0.1uF
20% 10V
2
CERM 402
1
C2308
0.1uF
20% 10V
2
CERM 402
1
C2313
0.1uF
20% 10V
2
CERM 402
1
C2323
0.1uF
20% 10V
2
CERM 402
1
C2328
0.1uF
20% 10V
2
CERM 402
1
C2333
0.1uF
20% 10V
2
CERM 402
1
C2338
0.1uF
20% 10V
2
CERM 402
1
C2304
0.1uF
20% 10V
2
CERM 402
1
C2309
0.1uF
20% 10V
2
CERM 402
1
C2314
0.1uF
20% 10V
2
CERM 402
1
C2324
0.1uF
20% 10V
2
CERM 402
1
C2329
0.1uF
20% 10V
2
CERM 402
1
C2334
0.1uF
20% 10V
2
CERM 402
1
C2339
0.1uF
20% 10V
2
CERM 402
5
4
3
12
D
H8
J15
J12
H15
AA1
AA2
AA3
AB10
AB2
AB6
B1
B2
B5
D1
F4
VDDO33
F8
H1
L7
M1
R2
U12
Shasta max (est 06/30/03) current:
U9
V7
DIGITAL - 1.2V - 950 mA (1175 mW)
W4
ANALOG12 - 1.2V - 600 mA ( 760 mW) VDDPs - 2.5V - 100 mA ( 250 mW)
A1
I/O 2.5 - 2.5V - 20 mA ( 60 mW)
A2
I/O 3.3 - 3.3V - 220 mA ( 770 mW)
A22
Total: 3015 mW
AA10
AA6
AB1
AB22
C19
D2
GND
E22
F3
F7
H2
H9
J10
J11
J13
J14
J16
K7
K13
K12
K11
K10
J22
K8
L15
U2300
SHASTA
POWER
K9
L10
L8
M15
VDDC
V1.0
BGA
(1 OF 8)
OMIT
GND
L11
=PP2V5_PWRON_SB
1
C2350
0.1uF
20% 10V
2
N8
R9
P15
L14
L13A5L12
R10
L16
R12
L9
M10
T10
M11
T15
VDDO25
VDDP_KL
M13
M12
VIO1
VIO2
M14
GND
D19
G15
H18
H17
K21
L21
W22
Y19
V8
W5
W19
U22
U13
U10
T12
R19
P9
P4
P14
P13
P12
P10
N9
N22
N13
N12
N11
N10
M2
1
C2355
0.1uF
20% 10V
2
CERM 402
For PCI_AD<63..32>
1
C2360
0.1uF
20% 10V
2
CERM 402
For PCI_AD<31..0>
CERM 402
1
C2356
0.1uF
20% 10V
2
CERM 402
1
C2361
0.1uF
20% 10V
2
CERM 402
1
C2351
0.1uF
20% 10V
2
CERM 402
=PPPCI64_PWRON_SB
1
C2357
0.1uF
20% 10V
2
CERM 402
=PPPCI32_PWRON_SB
1
C2362
0.1uF
20% 10V
2
CERM 402
=PP2V5_PWRON_SB
1
C2365
0.1uF
20% 10V
2
CERM 402
88
74
25
23
7
7
C
7
88
74
25
23
7
B
A
DRAWING
LAST_MODIFIED=Mon Dec 13 20:01:04 2004
8
Master: Link
Shasta Core Power
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE COMPUTER INC.
67
5
4
3
2
NONE
051-6482
SHT
23 103
1
REV.
I
OF
A
78
6
5
4
3
12
D
=PP1V2_HT
60
7
PP2V5_PWRON
U3LITE REQUIRES ALL JTAG SIGNALS
HIGH FOR NORMAL OPERATION
1
R2424
10K
2
JTAG_NB_TCK
JTAG_NB_TDI JTAG_NB_TDO
JTAG_NB_TMS
C
JTAG_NB_TRST_L
5% 1/16W MF 402
1
R2426
10K
5% 1/16W MF 402
2
1
R2429
10K
5% 1/16W MF 402
2
1
R2431
10K
5% 1/16W MF 402
2
1
R2433
10K
5% 1/16W MF 402
2
1
R2444
10K
5% 1/16W MF 402
2
1
R2436
10K
5% 1/16W MF 402
2
1
R2443
10K
5% 1/16W MF 402
2
1
2
1
R2442
10K
5% 1/16W MF 402
2
NOSTUFF
C2401
1000PF
5% 25V CERM 603
1
R2400
100
1% 1/16W MF 402
2
1
R2403
100
1% 1/16W MF 402
2
VSP_NB_CLK_P
27
VSP_NB_CLK_N
27
JTAG_NB_TCK
JTAG_NB_TDI JTAG_NB_TDO
JTAG_NB_TMS
JTAG_NB_TRST_L NB_RI_PU
NB_TEST_PD
NB_MC_PD
NB_RE_PD
NB_VSP_CLK_VREF VOLTAGE=0.6V
1
C2400
0.1UF
20% 10V
2
CERM 402
TP_NB_PM_SLEEP0
6
1
R2402
121
1% 1/16W MF 402
2
MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
1
R2401
121
1% 1/16W MF 402
2
P4
VSP_CLKP
R4
VSP_CLKN
R25
CE1_LT_TCK
V25
CE1_A_TDI
AA25
CE1_B_TDO
M26
CE1_DI1_TMS
F20
CE1_DI2_TRST
AC2
CE1_RI
AH3
CEO_TEST
AD5
CE0_MC
AD3
CE0_RE
D15
PM_SLEEP0
U3
U3LITE
V1.0-300MM
PBGA
(SYM 7 OF 7)
OMIT
HRESET*
PURESET*
SUSPENDACK*
SUSPENDREQ*
API0_ISCL
API_ISCA
SYS_ISCL0
SYS_ISCA0
SYS_ISCL1
SYS_ISCA1
DUMMY_A
DUMMY_B
IRQ0
PMR_OBSV
THMI
THMO
A21
E20
D20
D21
A20
B20
C20
B21
C21
E21
AC28
AB28
E9
Y9
J17
J18
NB_WARM_RESET_L NB_COLD_RESET_L
NB_SUSPEND_ACK_L NB_SUSPEND_REQ_L
I2C_NB_A_SCL
I2C_NB_A_SDA
I2C_NB_B_SCL I2C_NB_B_SDA
I2C_NB_C_SCL
I2C_NB_C_SDA
TP_DUMMY_A TP_DUMMY_B
NB_INT_L
NB_PMR_OBSV
NB_THMI
NB_THMO
SMU_SUSPENDREQ_L
13
28 25
8
24
8
24
18
18
18
18
18
18
6
6
25
8
8
8
PP3V3_PWRON PP2V5_PWRON
1
R2420
330
5% 1/16W MF 402
2
PMU_SUSPEND_REQ
6
D
Q2404
2N7002DW
2
SOT-363
G
S
1
NOSTUFF
R2408
5%
MF
402
5
G
0
21
1
R2419
330
5% 1/16W MF 402
2
3
D
Q2404
2N7002DW
SOT-363
S
4
NB_SUSPEND_REQ_L
24
D
C
PP3V3_PWRON
PP2V5_PWRON
NOSTUFF
1
B
SYS_COLD_RESET_L
8
13
R2405
4.7K
5% 1/16W MF 402
2
NOSTUFF
1
R2438
10K
5% 1/16W MF 402
2
NB_PU_RESET
6
NOSTUFF
D
Q2412
2N7002DW
2
SOT-363
G
S
1
R2406
0
5%
MF
402
1
R2435
4.7K
5% 1/16W MF 402
2
3
NOSTUFF
D
Q2412
2N7002DW
5
21
SOT-363
G
S
4
NB_COLD_RESET_L
24
LAST MODIFIED: JUNE 10, 04
MASTER: GILA
B
U3LITE MISC
A
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
24
REV.
OF
103
A
I
8
67
5
4
3
2
1
ELECTRICAL_CONSTRAINT_SET
I2S0_TO_SB
I2S0_TO_DEV
I2S0_TO_DEV I2S0_BIDIR
I2S0_BIDIR
I2S1_TO_SB I2S1_TO_DEV
I2S1_TO_DEV
I2S1_BIDIR
D
I2S1_BIDIR
I2S2_TO_SB
I2S2_TO_DEV
I2S2_TO_DEV I2S2_BIDIR
I2S2_BIDIR
SB_CLK25M_ATA
Page Notes
Power aliases required by this page:
- _PP3V3_PCI
- _PP3V3_PWRON_SB
- _PP2V5_PWRON_SB
- _PP1V2_PWRON_SB
Signal aliases required by this page: (NONE)
BOM options provided by this page:
- PCI_64BIT Configures Shasta for 64-bit PCI NOTE: XGC required for Shasta GPIOs
- MPIC_NB/MPIC_SB
C
Selects whether NorthBridge or SouthBridge MPIC will be used for interrupt controller.
NorthBridge / SouthBridge MPIC Routing
-> From NorthBridge NB_INT_L
24
B
<- To CPU CPU_INT_L
29
30
14
6
=PP3V3_PCI
R2551
10K
5%
MF
402
R2553
10K
5%
MF
402
R2557
A
10K
5%
MF
402
R2559
10K
5%
MF
402
DRAWING
LAST_MODIFIED=Mon Dec 13 20:01:12 2004
21
21
21
21
MPIC_NB
R2579
75
74
7
R2550
10K
5%
MF
402
R2552
10K
5%
MF
402
R2556
10K
5%
MF
402
R2558
10K
5%
MF
402
76
77
0
5%
MF
402
21
21
21
21
1
2
PCI_SLOTE_REQ_L
PCI_SLOTE_GNT_L
PCI_SLOTF_REQ_L
PCI_SLOTF_GNT_L
PCI_SLOTA_INT_L
PCI_SLOTD_INT_L
PCI_SLOTE_INT_L
PCI_SLOTG_INT_L
MPIC_SB
R2575
10K
5%
MF
402
MPIC_SB
R2578
47
5%
MF
402
NET_SPACING_TYPE
AUDIO
10 MIL SPACING
10 MIL SPACING
15 MIL SPACINGSB_CLK18M_XTAL 15 MIL SPACING
15 MIL SPACING
15 MIL SPACING
21
NB_INT_L_R
21
25
25
25
25
76
25
6
25
25
77
25
78
DIFFERENTIAL_PAIR
PP3V3_RUN
1
R2576
10K
5% 1/16W MF 402
2
3
MPIC_SB
1
Q2576
2N3904
SM
2
I2S0_DEV_TO_SB_DTI
I2S0_SB_TO_DEV_DTO
I2S0_MCLK I2S0_BITCLK
I2S0_SYNC
I2S1_DEV_TO_SB_DTI
I2S1_SB_TO_DEV_DTO I2S1_MCLK
I2S1_BITCLK
I2S1_SYNC
I2S2_DEV_TO_SB_DTI
I2S2_SB_TO_DEV_DTO
I2S2_MCLK I2S2_BITCLK
I2S2_SYNC
SB_CLK18M_XTALI
SB_CLK18M_XTALO SB_CLK18M_XTALO_R
SB_CLK25M_ATA
To SouthBridge -> NB_TO_SB_INT
From SouthBridge <­SB_INT_L
25
25
6
95
25
103
95
25
102
25
103
102
25
103
95
25
76
25
6
94
25
94
76
6
6
76
94
25
6
94
25
94
25
6
102
25
102
25
102
25
102
25
25
102
25
25
25
27
25
95
95
103
102
102
103
95
103
I2S0: Audio DAC
25
94
76
76
25
94
76
25
94
94
25
94
25
25
94
I2S1: Soft Modem
102
102
102
102
102
I2S2: S/P-DIF
23
74
25
PCI 32-bit select
1 = 32-bit PCI & GPIOs 0 = 64-bit PCI & XGC
=PP2V5_PWRON_SB
7
74
88
23
Re-pin within each RPAK as necessary DO NOT swap between RPAKs
I2S0_DEV_TO_SB_DTI
25
I2S0_SB_TO_DEV_DTO
25
I2S0_MCLK
25
I2S0_BITCLK
25
I2S0_SYNC
25
I2S1_DEV_TO_SB_DTI
6
I2S1_SB_TO_DEV_DTO
6
I2S1_MCLK
6
I2S1_BITCLK
6
I2S1_SYNC
6
I2S1_RESET_L
6
I2S2_DEV_TO_SB_DTI
25
I2S2_SB_TO_DEV_DTO
25
I2S2_MCLK
25
I2S2_BITCLK
25
I2S2_SYNC
25
I2S2_RESET_L
102
AUDIO GPIO - see note on right
=PP3V3_PWRON_SB
7
R2500
10K
5%
MF
402
PCI_64BIT
R2501
1K
5%
MF
402
1
R2580
4.7K
5%
MF
402
2
C2590
22pF
5%
50V
CERM
402
1
2
1
2
1
2
R2511
4
RP2510
3
1
2
2
RP2520
1
4
3
4
RP2530
3
2
1
CRITICAL
Y2590
18.432M
8X4.5MM-SM
33 5%
SM1
33 5%
SM1
33 5%
SM1
21
5
R2505
3.3
5%
FF
805
R2510
3.3
5%
FF
805
0
21
5%
MF
402
87
1
R2590
200
2
SB_CLK18M_XTALO
1
2
PP2V5_PWRON_SB_XTAL18VDD
21
1
C2500
10uF
20%
6.3V
2
CERM 1206
PP2V5_PWRON_SB_XTALVDD
21
1
C2510
10uF
20%
6.3V
2
CERM 1206
(I2S0_DEV_TO_SB_DTI)
5
I2S0_SB_TO_DEV_DTO_R
6
I2S0_MCLK_R
8
I2S0_BITCLK_R
7
I2S0_SYNC_R
(I2S1_DEV_TO_SB_DTI)
7
I2S1_SB_TO_DEV_DTO_R
8
I2S1_MCLK_R
5
I2S1_BITCLK_R
6
I2S1_SYNC_R
(I2S1_RESET_L)
(I2S2_DEV_TO_SB_DTI)
5
I2S2_SB_TO_DEV_DTO_R
6
I2S2_MCLK_R
7
I2S2_BITCLK_R
8
I2S2_SYNC_R
(I2S2_RESET_L)
SB_INT_L
25
MODEM_RING2SYS_L
6
25
94
SB_PCI_SEL32BIT
I2C_SB_SCL
18
I2C_SB_SDA
18
SYS_WARM_RESET_L
77
74
8
SB_STOPXTALS_L
13
SMU_SUSPENDREQ_L
24
28
13
SB_SUSPENDACK_L
13
SYS_PME_L
77
13
TP_SB_WATCHDOG
JTAG_SB_TDI
8
JTAG_SB_TDO
8
JTAG_SB_TCK
8
JTAG_SB_TMS
8
JTAG_SB_TRST_L
8
SB_TEST_MODE_PD TP_SB_PLLTEST
6
TP_SB_FSTEST
6
25
SB_CLK18M_XTALI
SB_CLK18M_XTALO_R
25
SB_CLK25M_ATA
27
25
1% 1/16W MF 402
C2591
22pF
5% 50V CERM 402
VOLTAGE=2.5V MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=15 mil
1
C2501
1uF
10%
6.3V
2
CERM 402
VOLTAGE=2.5V MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=15 mil
1
C2511
1uF
10%
6.3V
2
CERM 402
W10
U11
V11
W18
V12
AA11
AB11
W12
NC
25
W14
VDD VDD
W7
I2S0DTI_H
Y5
I2S0DTO_H
U8
I2S0MCLK_H
AA4
I2S0BITCLK_H
Y6
I2S0SYNC_H
V10
I2S1DTI_H
AB5
I2S1DTO_H
V9
I2S1MCLK_H
AA8
I2S1BITCLK_H
AA7
I2S1SYNC_H
V5
GPIO_H_0
AA5
I2S2DTI_H
Y8
I2S2DTO_H
Y7
I2S2MCLK_H
AB4
I2S2BITCLK_H
W9
I2S2SYNC_H
Y2
GPIO_H_1
AB3
GPIO_H_2
W8
GPIO_H_3
W6
PCI_SEL32BIT_H
Y9
I2CCLK_H
AB7
I2CDATA_H
E9
RESET_L
STOPXTALS_L
SUSPENDREQ_L
SUSPENDACK_L
PCI1PME_L
INTRWD_H
TDI
W11
TDO
TCK
Y11
TMS
TRST_L
A3
TEST_MODE_H
U14
PLLTEST
V14
FSTEST
W13
XTAL_18_I
V13
XTAL_18_O
U15
XTALI
V15
XTALO
XTAL_18 PLL_45
GND
AB12
XTAL_18XTAL
4
Y13
AA13AB13
PLL_45
VDD
U2300
SHASTA
V1.0
BGA
(2 OF 8)
(SCCA)(SCCB)
I2S2 I2S1 I2S0
GPIO
I2C
PWR_MGT
TEST
XTALS
GND
PP1V2_PWRON_SB_PLL45VDD
PP1V2_PWRON_SB_PLL49VDD
Y12
PLL_49
VDD
OMIT
GPIO
PCI1REQ_3_L
6
PCI1GNT_3_L
7
PCI1REQ_4_L
8
PCI1GNT_4_L
9
PCI1REQ_5_L
10
PCI1GNT_5_L
11
PCI1AD_32_H
12
PCI1AD_33_H
13
PCI1AD_34_H
14
PCI1AD_35_H
15
PCI1AD_36_H
16
PCI1AD_37_H
17
PCI1AD_38_H
18
PCI1AD_39_H
19
PCI1AD_40_H
20
PCI1AD_41_H
21
PCI1AD_42_H
22
PCI1AD_43_H
23
PCI1AD_44_H
24
PCI1AD_45_H
25
PCI1AD_46_H
26
PCI
PCI1AD_47_H
27
PCI1AD_48_H
28
PCI1AD_49_H
29
30
PCI1AD_50_H
31
PCI1AD_51_H
32
PCI1AD_52_H
33
PCI1AD_53_H
34
PCI1AD_54_H
PCI1AD_55_H
35 36
PCI1AD_56_H
PCI1AD_57_H
37
PCI1AD_58_H
38 39
PCI1AD_59_H
40
PCI1AD_60_H
PCI1AD_61_H
41
PCI1AD_62_H
42
43
PCI1AD_63_H
PCI1C_BE_4_L
44
PCI1C_BE_5_L
45
PCI1C_BE_6_L
46
PCI1C_BE_7_L
47
PCI1REQ64_L
48
PCI1ACK64_L
49
PCI1PAR64_H
50
XGI_CLK_H
51
XGI_DTO0_H
52
XGI_DTO1_H
53
XGI
XGI_DTI_H
54
PLL_49
GND
AA12
VOLTAGE=1.2V MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=15 mil
1
C2521
VOLTAGE=1.2V MIN_LINE_WIDTH=20 mil MIN_NECK_WIDTH=15 mil
C2531
W17
VIO PME
C2520
1uF
10%
6.3V 2
CERM
402
1
C2530
1uF
10%
6.3V 2
CERM
402
1
C2540
0.1uF
20% 10V
2
CERM 402
"Slot E" - AD21
U17
PCI_SLOTE_REQ_L
AA19
PCI_SLOTE_GNT_L "Slot F" - AD22
AB21
PCI_SLOTF_REQ_L
AA20
PCI_SLOTF_GNT_L
U16
SB_TO_SMU_INT_L
Y20
CPU_SRESET_L
D18
SB_GPIO12
A20
SYS_OVERTEMP_L
F18
UDASH_SDOWN
F17
UDASH_RESET_L
G16
AGP_INT_L
F16
PCI_SLOTA_INT_L
A21
PCI_SLOTB_INT_L
B21
PCI_SLOTC_INT_L
C20
PCI_SLOTD_INT_L
G17
PCI_SLOTE_INT_L
G18
PCI_SLOTF_INT_L
E19
SB_GPIO23
F19
SB_GPIO24
D20
SB_GPIO25
E20
SB_SATABR_RESET_L
C21
PCI_SLOTG_INT_L
F20
FW_LOWPWR
G19
ENETFW_RESET
C22
SB_GPIO30
D21
ENET_ENERGYDET
G20
AUDIO_LO_DET_L
D22
AUDIO_LO_OPTICAL_PLUG_L
K18
AUDIO_LI_DET_L
H19
AUDIO_LI_OPTICAL_PLUG_L
J17
AUDIO_HP_DET_L
F21
AUDIO_SPKR_DET_L
G21
AUDIO_LO_MUTE_L
H20
AUDIO_HP_MUTE_L
J19
AUDIO_SPKR_MUTE_L
F22
AUDIO_EXT_MCLK_SEL
G22
AUDIO_GPIO_11
H21
AUDIO_GPIO_12
J20
I2S0_RESET_L
H22
SB_GPIO45
K22
SB_GPIO46
K20
SB_GPIO47
K17
SYS_SLEWING_L
L17
SB_GPIO49
E18
SB_GPIO50
Y4
SB_GPIO51
U7
SB_GPIO52
T9
NB_TO_SB_INT
W2
SMU_TO_SB_INT_L
3
1
10uF
20%
6.3V 2
CERM 1206
1
10uF
20%
6.3V 2
CERM 1206
=PP3V3_PWRON_SB
R2520
3.3
5%
FF
805
R2530
3.3
5%
FF
805
7
21
21
25
23
=PP1V2_PWRON_SB
74
25
25
25
25
25
13
29
30
25
25
16
25
27
13
6
94
6
25
94
49
6
25
76
25
25
25
25
25
25
25
25
25
77
25
90
25
87
25
25
87
25
101
6
101
101
102
102
102
98
102
100
102
103
102
101
95
25
25
25
27
33
25
13
25
25
25
25
25
25
13
7
REDUNDANT - NEED TO ADDRESS THIS
REDUNDANT - NEED TO ADDRESS THIS
AUDIO GPIOS
the audio circuit to provide the
necessary pull-ups & pull-downs.
NOTE: It is the responsibility of
APPLE COMPUTER INC.
12
=PP3V3_PWRON_SB
25
74
23
7
R2554
1K
SB_TO_SMU_INT_L
13
25
CPU_SRESET_L
25
30
29
SYS_OVERTEMP_L
13
27
25
16
UDASH_RESET_L
6
94
25
SYS_SLEWING_L
13
27
33
25
MODEM_RING2SYS_L
94
25
6
I2S1_RESET_L
94
25
6
SB_SATABR_RESET_L
25
FW_LOWPWR
25
90
ENETFW_RESET
25
87
ENET_ENERGYDET
25
87
SB_GPIO12
25
PCI_SLOTB_INT_L
25
PCI_SLOTC_INT_L
25
PCI_SLOTF_INT_L
25
SB_GPIO23
25
SB_GPIO24
25
SB_GPIO25
25
SB_GPIO30
25
SB_GPIO45
25
SB_GPIO46
25
SB_GPIO47
25
SB_GPIO49
25
SB_GPIO50
25
SB_GPIO51
25
SB_GPIO52
25
SMU_TO_SB_INT_L
13
25
Shasta Serial / Misc
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
051-6482
NONE
21
NO STUFF
5%
R2555
MF
402
R2560
1K
21
5%
R2561
MF
402
NO STUFF
R2562
1K
21
5%
R2563
MF
402
R2564
10K
21
5%
MF
402
R2565
R2566
10K
21
5%
R2567
MF
402
R2568
10K
21
5%
MF
402
=PP3V3_PWRON_SB
25
74
23
7
RP2550
10K
54
5%
RP2550
SM1
RP2550
10K
81
5%
RP2551
SM1
RP2551
10K
63
5%
RP2551
SM1
RP2550
10K
63
5%
RP2551
SM1
RP2552
10K
81
5%
RP2552
SM1
RP2552
10K
63
5%
RP2552
SM1
RP2553
10K
54
5%
RP2553
SM1
RP2553
10K
63
5%
RP2553
SM1
Master: Link
SHT
10K
5%
MF
402
10K
5%
MF
402
10K
5%
MF
402
10K
5%
MF
402
10K
5%
MF
402
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
10K
5%
SM1
OF
21
D
21
21
21
21
C
72
81
72
54
B
72
54
72
81
A
REV.
I
10325
8
67
5
4
3
2
1
78
6
5
4
3
12
C2_VDD
C3_VDD
C4_VDD
VDD_PLL1
VDD_PLL2
VDD_PLL3
VDD_PLL4
VDD_I2C
VDD_NBSYNC
VDD_PCLK
VDD25
VDD25
VDD33
VDD33_BC
VDD33_BC1
VDD_HCLK0
VDD_HCLK0
VDD_HCLK1
VDD_HCLK2
VDD_HCLK2
VDD_HSYNC
VDD_HSYNC
VDD15_HSYNC
VDD15_PCLK
VDD_VCLK
VDD_XTAL
C2637
0.1UF
20% 10V CERM 402
SYM 2 OF 2
OMIT
U2600
PULSAR
FSBGA
1
C2638
0.1UF
20% 10V
2
CERM 402
C1_VSSC1_VDD
C2_VSS
C3_VSS
C4_VSS
VSS_PLL1
VSS_PLL2
VSS_PLL3
VSS_PLL4
VSS_CML
VSS_I2C
VSS_NBSYNC
VSS_PCLK
VSS25
VSS25
VSS33
VSS33_BC
VSS33_BC1
VSS_HCLK0
VSS_HCLK0
VSS_HCLK1
VSS_HCLK2
VSS_HCLK2
VSS_HSYNC
VSS_HSYNC
VSS_VCLK
VSS_XTAL
G1F1
M4L3
E10E12
C9B9
D12
D1
K8
M2
A6
C2
F11
L12
L2
H2
E2
L7
M5
C10
B11
B7
A4
A7
H10
K12
A3
C12
D
C
B
L2601
=PPVCORE_PWRON_PULSAR
7
26
D
C
PP3V3_PWRON
B
180-OHM-1.5A
0603
R2601
4.7
5%
1/16W
MF
402
1
C2611
0.1UF
20% 10V
2
CERM 402
L2603
180-OHM-1.5A
0603
R2609
4.7
5%
1/16W
MF
402
1
C2613
0.1UF
20% 10V
2
CERM 402
L2605
180-OHM-1.5A
0603
R2603
4.7
5%
1/16W
MF
402
1
C2615
0.1UF
20% 10V
2
CERM 402
L2607
180-OHM-1.5A
0603
R2605
4.7
5%
1/16W
MF
402
1
C2619
0.1UF
20% 10V
2
CERM 402
L2609
180-OHM-1.5A
0603
R2607
4.7
5%
1/16W
MF
402
1
C2620
0.1UF
20% 10V
2
CERM 402
21
21
1
C2645
2.2UF
20%
6.3V
2
PLACE NEAR PIN D10 D12
21
21
1
C2669
2.2UF
20%
6.3V
2
PLACE NEAR PIN D2 D1
21
21
1
C2603
2.2UF
20%
6.3V
2
PLACE NEAR PIN L8 K8
21
21
1
C2607
2.2UF
20%
6.3V
2
PLACE NEAR PIN M3 M2
21
21
1
C2621
2.2UF
20%
6.3V
2
PP1V5_PSL_PLL1
1
C2609
0.1UF
20% 10V
2
CERM 402
PP1V5_PSL_PLL2
1
C2617
0.1UF
20% 10V
2
CERM 402
PP1V5_PSL_PLL3
1
C2601
0.1UF
20% 10V
2
CERM 402
PP1V5_PSL_PLL4
1
C2605
0.1UF
20% 10V
2
CERM 402
PP3V3_PSL_XTAL
1
C2622
0.1UF
20% 10V
2
CERM 402
402 CAPS NOT NEEDED
IF 603 CAN BE PLACED CLOSE TO PULSAR
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=1.5V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
VOLTAGE=3.3V MIN_LINE_WIDTH=25MIL MIN_NECK_WIDTH=10MIL
=PP2V5_PWRON_RAM
40
37
7
26
=PPVCORE_PULSAR
7
26
=PPVCORE_PWRON_PULSAR
7
26
PP3V3_PWRON
1
C2665
0.1UF
20% 10V
2
CERM 402
1
C2639
0.1UF
20% 10V
2
CERM 402
1
C2631
0.1UF
20% 10V
2
CERM 402
1
C2627
0.1UF
20% 10V
2
CERM 402
1
C2667
0.1UF
20% 10V
2
CERM 402
1
C2640
0.1UF
20% 10V
2
CERM 402
1
C2632
0.1UF
20% 10V
2
CERM 402
1
C2628
0.1UF
20% 10V
2
CERM 402
40
=PPVCORE_PWRON_PULSAR
7
26
=PP1V2_PULSAR
7
26
=PP2V5_PWRON_RAM
37
7
26
PP3V3_PWRON
PP3V3_RUN
=PPVCORE_PULSAR
7
26
=PP1V2_PULSAR
7
26
=PPVCORE_PULSAR
7
26
PP3V3_RUN
1
C2651
0.1UF
20% 10V
2
CERM 402
1
C2633
0.1UF
20% 10V
2
CERM 402
1
C2629
0.1UF
20% 10V
2
CERM 402
PP3V3_PWRON
1
C2634
0.1UF
20% 10V
2
CERM 402
1
C2630
0.1UF
20% 10V
2
CERM 402
1
C2671
0.1UF
20% 10V
2
CERM 402
1
C2635
2
D10
D2
L8
M3
B2
G12
M12
H3
K1
E1
L5
M9
A11
A9
A8
C5
B4
K10
H12
J11
M11
A1
A12
PINS G12, M12, H3, K1, L5, M9, A11, A9
A8, C5, B4, K10, H12 J11, M11, A1 CAN BE TURNED OFF IN SLEEP
0.1UF
20% 10V CERM 402
1
C2636
0.1UF
20% 10V
2
CERM 402
1
2
=PP1V2_PULSAR
7
26
1
C2623
0.1UF
20% 10V
2
CERM 402
359S0076
QTY
1
DESCRIPTION
PULSAR, PBGA
REFERENCE DESIGNATOR(S)
BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
A
8
67
5
4
1
C2624
0.1UF
20% 10V
2
CERM 402
1
C2625
0.1UF
20% 10V
2
CERM 402
1
C2626
0.1UF
20% 10V
2
CERM 402
LAST MODIFIED: APR 09, 04
MASTER: GILA
PULSAR POWER
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
DRAWING NUMBER
D
APPLE COMPUTER INC.
3
2
051-6482
NONE
SHT
26
1
REV.
I
OF
103
A
78
6
5
4
3
12
ELECTRICAL_CONSTRAINT_SET
EI_CPU_CLK_P
27
29
EI_CPU_CLK_N
27
29
EI_CPU1_CLK_P
14
6
EI_CPU1_CLK_N
14
6
EI_NB_CLK_P
27
28
EI_NB_CLK_N
27
28
EI_CPU_SYNC
27
29
EI_NB_SYNC
27
28
EI_CPU1_SYNC
14
D
6
VSP_NB_CLK_P
24
27
VSP_NB_CLK_N
24
27
AGP_CLK66M_NB
27
48
AGP_CLK66M_GPU
27
49
HT_CLK66M_NB
27
60
HT_CLK66M_SB
27
62
PCI_CLK66M_SB_INT
27
74
PCI_CLK33M_SB_EXT
8
74
PLS_EXTCLK
27
EI_CPU_CLK EI_CPU_CLK
EI_CPU_CLK EI_CPU_CLK
EI_NB_CLK EI_NB_CLK
EI_SYNC
EI_CPU1_SYNC
VSP_NB_CLK VSP_NB_CLK
AGP_NB_CLK
AGP_GPU_CLK
HT_NB_CLK
HT_SB_CLK
CLOCKS_PCI
CLOCKS_PCI
PLS_XTAL
DIFFERENTIAL SIGNALS SHOULD HAVE 5 MIL SPACING TO EACH OTHER
ALL SPACING GROUPS SHOULD HAVE 15 MIL SPACING TO SIGNALS NOT IN THEIR GROUP
EI_NB_SYNC IS PART OF EI_CPU_SYNC TOPOLOGY
NET_SPACING_TYPE
CLOCKS
CLOCKS
CLOCKS CLOCKS
CLOCKS CLOCKS
CLOCKS
CLOCKS CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
C
CLOCK_RESET_L
13
0=IIC ADDR D2/D3
1=IIC ADDR D4/D5
PP3V3_PWRON
18
6
11
1
R2722
1K
5% 1/16W MF
21
25.0000M
402
2
NO STUFF
R2752
0
5%
1/16W
MF
402
NO STUFF
R2758
330K
5%
1/16W
MF
402
CRITICAL
Y2701
8X4.5MM-SM
21
21
21
R2754
1/16W
R2756
1/16W
PLS_X_OUT_B
402
402
0
21
5%
MF
0
21
5% MF
NOSTUFF
R2748
PLS_X_IN_B
5%
MF
402
0
SYS_OVERTEMP_L
25
16
B
13
=PULSAR_POWER_DOWN
3
NOSTUFF
J2700
U.FL-R_SMT
F-ST-SM
3
1
2
27
PLS_EXTCLK
NOSTUFF
1
R2762
24
5% 1/16W MF 402
2
PLS_INTERM
NOSTUFF
1
R2764
24
5% 1/16W MF 402
2
R2706
R2744
R2740 R2746
R2742
R2750
R2724
249
1K
1K
681
806
DIFFERENTIAL_PAIRNET_PHYSICAL_TYPE
EI_CPU1_CLKEI_CPU1_CLK EI_CPU1_CLKEI_CPU1_CLK
EI_NB_CLK EI_NB_CLK
VSP_NB_CLKVSP_NB_CLK
NOSTUFF
NOSTUFF
R2704
0
5% 402
R2738
1K
4025%
21
21
21
21
21
21
21
21
21
402
402 1% 402 1%
4021K1%
402
402 5%
18
18
PLS_RESET_L
PLS_X_IN
PLS_X_OUT
PLS_X_ADDRSEL
TP_PLS_TEST1
6
TP_PLS_TEST2
6
TP_PLS_TEST3
6
1%
PLS_SCAN_MODE
PLS_REF15 PLS_REF25
PLS_REF33
TP_PLS_REF_CML
6
1%
PLS_PRES_CML
PLS_FORCE_P0_L_R
5%47402
PULSAR_POWER_DOWN_R
I86
I87
I116
I117
I96
I97
I98
I99
I118
I94
I95
I100
I101
I102
I103
I90
I91
I119
I2C_CLOCK_SCL
I2C_CLOCK_SDA
C11
B12
E11
D11
G11
C1
B1
D3
E3
K3
M1
J2
M6
A5
B6
F2
C3
U2600
PULSAR
SCLK
SDATA
RESET*
XIN
XOUT
ADDRSEL
TEST1
TEST2
TEST3
SCAN_MODE
REF15
REF25
REF33
REF_CML
PRES_CML
FORCESPO*
PD
SYM 1 OF 2
OMIT
FSBGA
GPCLK33_0
GPCLK33_1
VCLKN
VCLKP
HCLKN_0
HCLKN_1
HCLKN_2
HCLKP_0
HCLKP_1
HCLKP_2
GPCLK25_0
GPCLK25_1
PCLK25_0
PCLK25_1
PCLK33_0
PCLK33_1
PCLK33_2
PCLK33_3
PCLK33_4
HTBEN_0
HTBEN_1
NBSYNC
HSYNC_0
HSYNC_1
REFCLK_0
REFCLK_1
SLEWING*
ERROR*
PCLK12
PCLK15
L4
PCI_CLK_GP0_R
K4
PCI_CLK_GP1_R
A2
VSP_NB_CLK_N_C
B3
VSP_NB_CLK_P_C
B10
EI_CPU_CLK_N_C
C8
EI_CPU1_CLK_N_R
C4
EI_NB_CLK_N_C
A10
EI_CPU_CLK_P_C
B8
EI_CPU1_CLK_P_R
B5
EI_NB_CLK_P_C
J3
PLS_CLK_66M_0_R
6
J1
6
PLS_CLK_66M_1_R
K2
HT_CLK66M_NB_R
L1
RAM_CLK66M_NB_R
K5
PCI_CLK66M_SB_INT_R
L6
PCI_CLK_P1_R
M7
AGP_CLK66M_GPU_R
L9
PCI_CLK_P3_R
M10
PCI_CLK_P4_R
K11
CPU_HTBEN_R
J12
CPU1_HTBEN_R
F12
EI_NB_SYNC_R
J10
EI_CPU_SYNC_R
H11
EI_CPU1_SYNC_R
G2
SB_CLK25M_ATA_R
H1
SATA_CLK25M_R
K9
SLEWING_L_R
M8
CLOCK_ERROR_L
L11
HT_CLK66M_SB_R
L10
AGP_CLK66M_NB_R
R2701
5%
0
21
R2761
21
5%0402
C2708
0.001UF
CERM
50V
21
10% 402
C2710
0.001UF
50V
CERM
21
40210%
C2713
0.001UF
50V
CERM
21
40210%
C2715
0.001UF
CERM
50V
21
10% 402
NET SPACING
TYPE
CLOCKS
CLOCKS
CLOCKS CLOCKS
CLOCKS
CLOCKS
14
CLOCKS
CLOCKS
CLOCKS
14
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS
CLOCKS CLOCKS
CLOCKS CLOCKS
CLOCKS
CLOCKS
CLOCKS
14
CLOCKS
CLOCKS CLOCKS
14
CLOCKS
CLOCKS
CLOCKS
8
CLOCKS
CLOCKS
R2720
5%0402
21
SYS_SLEWING_L
33
13
25
NOSTUFF
0
R2775
4025%
20
R2709
4025%
0
R2707
4025%
0
R2715
5% 402
0
R2772
4025%
NOSTUFF
R2700
402225%
0
R2717
4025%
C2700
0.001UF
50V
C2702
0.001UF
50V
21
21
21
21
21
21
21
21
21
10% 402
NOSTUFF
0
5%
CERM
40210%
CERM
R2776
40205%
R2705
402
R2702
40205%
R2719
40205%
21
21
21
21
20
R2703
4025%
R2711
40205%
R2779
5%0402
0
R2768
4025%
20
R2770
5% 402
3.3V
33MHZ
3.3V
33MHZ
66MHZ
2.5V
66MHZ
2.5V
21
21
21
21
21
2.5V
2.5V
3.3V
3.3V
3.3V
3.3V
1.2V
1.2V
1.2V
2.5V
2.5V
1.2V
1.5V
66MHZ
66MHZ
66MHZ 33MHZ
66MHZ 33MHZ
33MHZ
25MHZ
25MHZ
66MHZ
66MHZ
PCI_CLK_GP0
PCI_CLK_GP1
VSP_NB_CLK_P
VSP_NB_CLK_N
EI_CPU_CLK_P
EI_CPU_CLK_N
EI_NB_CLK_P EI_NB_CLK_N
TP_PLS_CLK_66M_0
TP_PLS_CLK_66M_1
HT_CLK66M_NB
RAM_CLK66M_NB
PCI_CLK66M_SB_INT PCI_CLK_P1
AGP_CLK66M_GPU
PCI_CLK_P3 PCI_CLK_P4
CPU_HTBEN
EI_NB_SYNC
EI_CPU_SYNC
SB_CLK25M_ATA
TP_SATA_CLK25M
HT_CLK66M_SB
AGP_CLK66M_NB
8
8
24
27
24
27
27
29
27
29
27
28
27
28
6
6
27
60
37
27
74
8
27
49
8
8
29
30
27
28
27
29
25
6
27
62
27
48
LAST MODIFIED: JULY 12, 04
MASTER: GILA
D
C
B
PULSAR CLOCKS
A
C2707
33PF
CERM
50V
402
1
5%
2
1
C2705
33PF
5% 50V
2
CERM 402
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
APPLE COMPUTER INC.
NOTICE OF PROPRIETARY PROPERTY
SIZE
DRAWING NUMBER
051-6482
D
NONE
SHT
27
REV.
OF
103
A
I
8
67
5
4
3
2
1
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