Analog Devices OP297FS-REEL7, OP297FS-REEL, OP297FS, OP297EZ, OP297EP Datasheet

8/21/97 4:00 PM

a

Dual Low Bias Current

Precision Operational Amplifier

OP297

FEATURES
Precision Performance in Standard SO-8 Pinout
Low Offset Voltage: 50 ␮V max
Low Offset Voltage Drift: 0.6 ␮V/ⴗC max
Very Low Bias Current:
␣ ␣ +25ⴗC (100 pA max)
␣␣–55ⴗC to +125ⴗC (450 pA max)
Very High Open-Loop Gain (2000 V/mV min)
Low Supply Current (Per Amplifier): 625 ␮A max
Operates From 62 V to 620 V Supplies
High Common-Mode Rejection: 120 dB min
Pin Compatible to LT1013, AD706, AD708, OP221,
␣ ␣ LM158, and MC1458/1558 with Improved Performance

APPLICATIONS
Strain Gauge and Bridge Amplifiers
High Stability Thermocouple Amplifiers
Instrumentation Amplifiers
Photo-Current Monitors
High-Gain Linearity Amplifiers
Long-Term Integrators/Filters
Sample-and-Hold Amplifiers
Peak Detectors
Logarithmic Amplifiers
Battery-Powered Systems

GENERAL DESCRIPTION

The OP297 is the first dual op amp to pack precision perfor­mance into the space-saving, industry standard 8-pin SO pack­age. Its combination of precision with low power and extremely
low input bias current makes the dual OP297 useful in a wide
variety of applications.

Precision performance of the OP297 includes very low offset,

under 50 µV, and low drift, below 0.6 µV/°C. Open-loop gain

exceeds 2000 V/mV insuring high linearity in every application.

PIN CONNECTIONS

Plastic Epoxy-DIP (P Suffix)

8-Pin Cerdip (Z Suffix)

8-Pin Narrow Body SOIC (S Suffix)

OUT A V+

–IN A OUT B
+IN A –IN B

1

A

2

+

–

3
45

V– +IN B

8

B

7

–

+

6

Errors due to common-mode signals are eliminated by the
OP297’s common-mode rejection of over 120 dB. The
OP297’s power supply rejection of over 120 dB minimizes
offset voltage changes experienced in battery powered systems.

Supply current of the OP297 is under 625 µA per amplifier and
it can operate with supply voltages as low as ±2 V.

The OP297 utilizes a super-beta input stage with bias current
cancellation to maintain picoamp bias currents at all tempera­tures. This is in contrast to FET input op amps whose bias

currents start in the picoamp range at 25°C, but double for
every 10°C rise in temperature, to reach the nanoamp range
above 85°C. Input bias current of the OP 297 is under 100 pA
at 25°C and is under 450 pA over the military temperature

range.

Combining precision, low power and low bias current, the
OP297 is ideal for a number of applications including instru­mentation amplifiers, log amplifiers, photodiode preamplifiers
and long-term integrators. For a single device, see the OP97;
for a quad, see the OP497.

60

40

20

0

20

INPUT CURRENT (pA)

–40

–60

–75 –50 –25 0 25 50 75 100 125

I

–

B

+

I

B

I

OS

TEMPERATURE (°C)

V

S

V

CM

= ±15V

= 0V

400

1200 UNITS

300

200

NUMBER OF UNITS

100

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

INPUT OFFSET VOLTAGE (µV)

Figure 1. Low Bias Current Over Temperature Figure 2. Very Low Offset

REV. D

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1997

T

A

V

S

V

CM

= +25°C

= ±15V

= 0V

8/21/97 4:00 PM

OP297–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VS = ⴞ15 V, TA = +25ⴗC, unless otherwise noted.)

␣␣␣␣OP297A/E ␣␣␣␣ OP297F ␣␣␣␣␣ OP297G

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Input Offset Voltage V

OS

25 50 50 100 80 200 µV

Long-Term Input

␣ ␣ Voltage Stability 0.1 0.1 0.1 µV/mo

Input Offset Current I
Input Bias Current I
Input Noise Voltage e
Input Noise e
␣ ␣ Voltage Density e
Input Noise Current Density i

OS

B

p-p 0.1 Hz to 10 Hz 0.5 0.5 0.5 µV p-p

n

n

n

n

VCM = 0 V 20 100 35 150 50 200 pA
V

= 0 V 20 ±100 35 ±150 50 ±200 pA

CM

f

= 10 Hz 20 20 20 nV/√Hz

O

f

= 1000 Hz 17 17 17 nV/√Hz

O

f

= 10 Hz 20 20 20 fA√Hz

O

Input Resistance
␣ ␣ Differential Mode R

IN

30 30 30 MΩ

Input Resistance
␣ ␣ Common-Mode R

INCM

Large-Signal V
␣ ␣ Voltage Gain A

VO

= ±10 V

O

R

= 2 kΩ 2000 4000 1500 3200 1200 3200 V/mV

L

500 500 500 GΩ

Input Voltage Range IVR (Note 1) ±13 ±14 ±13 ±14 ±13 ±14 V

Common-Mode Rejection CMR V
Power Supply Rejection PSR V
Output Voltage Swing V

Supply Current Per Amplifier I
Supply Voltage V

O

V

O

SY

S

= ±13 V 120 140 114 135 114 135 dB

CM

= ±2 V to ±20 V 120 130 114 125 114 125 dB

S

R

= 10 kΩ±13 ±14 ±13 ±14 ±13 ±14 V

L

R

= 2 kΩ±13 ±13.7 ±13 ±13.7 ±13 ±13.7 V

L

No Load 525 625 525 625 525 625 µA
Operating Range ±2 ±20 ±2 ±20 ±2 ±20 V

Slew Rate SR 0.05 0.15 0.05 0.15 0.05 0.15 V/µs

Gain Bandwidth Product GBWP AV = [phone] kHz
Channel Separation CS VO = 20 V p–p 150 150 150 dB

fO = 10 Hz

Input Capacitance C

NOTES

1

Guaranteed by CMR test.

Specifications subject to change without notice.

IN

333pF

(@ V

= ⴞ15 V, –55ⴗC ≤ TA ≤ +125ⴗC for OP297A, unless otherwise noted.)

ELECTRICAL CHARACTERISTICS

S

␣␣␣␣␣ OP297A

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage V

OS

Average Input Offset Voltage Drift TCV
Input Offset Current I
Input Bias Current I
Large-Signal Voltage Gain A

OS

B

VO

OS

VCM = 0 V 60 450 pA
V

= 0 V 60 ±450 pA

CM

V

= ±10 V, RL = 2 kΩ 1200 2700 V/mV

O

45 100 µV

0.2 0.6 µV/°C

Input Voltage Range IVR (Note 1) ±13 ±13.5 V

Common-Mode Rejection CMR V
Power Supply Rejection PSR V
Output Voltage Swing V
Supply Current Per Amplifier I
Supply Voltage V

NOTES

1

Guaranteed by CMR test.

Specifications subject to change without notice.

O

SY

S

= ±13 114 130 dB

CM

= ±2.5 V to ±20 V 114 125 dB

S

R

= 10 kΩ±13 ±13.4 V

L

No Load 575 750 µA
Operating Range ±2.5 ±20 V

–2–

REV. D

8/21/97 4:00 PM

OP297

(@ V

ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Units

Input Offset Voltage V
Average Input Offset

Voltage Drift TCV
Input Offset Current I
Input Bias Current I
Large-Signal Voltage Gain A

Input Voltage Range IVR (Note 1) ±13 ±13.5 ±13 ±13.5 ±13 ±13.5 V

Common-Mode Rejection CMR V
Power Supply Rejection PSR V

Output Voltage Swing V
Supply Current Per Amplifier I
Supply Voltage V

NOTES

1

Guaranteed by CMR test.

Specifications subject to change without notice.

OS

B

SY

OS

VO

O

S

OS

VCM = 0 V 50 450 80 750 80 750 pA
V

= 0 V 50 ±450 80 ±750 80 ±750 pA

CM

V

= ±10 V,

O

= 2 kΩ 1200 3200 1000 2500 700 2500 V/mV

R

L

= ±13 114 130 108 130 108 130 dB

CM

= ±2.5 V

S

to ±20 V 114 0.15 108 0.15 108 0.3 dB

R

= 10 kΩ±13 ±13.4 ±13 ±13.4 ±13 ±13.4 V

L

No Load 550 750 550 750 550 750 µA
Operating Range ±2.5 ±20 ±2.5 ±20 ±2.5 ±20 V

= ⴞ15 V, –40ⴗC ≤ TA ≤ +85ⴗC for OP297E/F/G, unless otherwise noted.)

S

␣␣␣␣OP297E ␣␣␣␣ OP297F ␣␣␣␣␣ OP297G

35 100 80 300 110 400 µV

0.2 0.6 0.5 2.0 0.6 2.0 µV/°C

Wafer Test Limits

(@ VS = ⴞ15 V, TA = +25ⴗC, unless otherwise noted.)

Parameter Symbol Conditions Limit Units

Input Offset Voltage V
Input Offset Current I

Input Bias Current I
Large-Signal Voltage Gain A

OS

B

OS

VO

VCM = 0 V 200 pA max

V

= 0 V ±200 pA max

CM

V

= ±10 V, RL = 2 kΩ 1200 V/mV min

O

200 µV max

Input Voltage Range IVR (Note 1) ±13 V min

Common-Mode Rejection CMR V
Power Supply PSR V
Output Voltage Swing V
Supply Current Per Amplifier I

NOTES

1. Guaranteed by CMR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

O

SY

= ±13 V 114 dB min

CM

= ±2 V to ±l 8 V 114 dB min

S

R

= 2 kΩ±13 V min

L

No Load 625 µA max

DICE CHARACTERISTICS

Dimension shown in inches and (mm).

Contact factory for latest dimensions

OUTPUT A

–INPUT A

+INPUT A

+V

S

0.118 (3.00)

OUTPUT B

–V

S

0.074 (1.88)

–INPUT B
+INPUT B

–3–REV. D

8/21/97 4:00 PM

WARNING!

ESD SENSITIVE DEVICE

OP297

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V

Input Voltage
Differential Input Voltage

2

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V

2

. . . . . . . . . . . . . . . . . . . . . . . . 40 V

1

Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Storage Temperature Range

Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Operating Temperature Range

OP297A (Z) . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

OP297E, F (Z) . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

OP297F, G (P, S) . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Junction Temperature

Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +175°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

OP297AZ –55°C to +125°C 8-Pin Cerdip Q-8
OP297EZ –40°C to +85°C 8-Pin Cerdip Q-8
OP297EP –40°C to +85°C 8-Pin Plastic DIP N-8
OP297FP –40°C to +85°C 8-Pin Plastic DIP N-8
OP297FS –40°C to +85°C 8-Pin SO SO-8
OP297FS-REEL –40°C to +85°C 8-Pin SO SO-8
OP297FS-REEL7 –40°C to +85°C 8-Pin SO SO-8
OP297GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP297GS –40°C to +85°C 8-Pin SO SO-8
OP297GS-REEL –40°C to +85°C 8-Pin SO SO-8

OP297GS-REEL7

2

–40°C to +85°C 8-Pin SO SO-8

Package Type ␪

3

JA

␪

JC

Units

8-Pin Cerdip (Z) 134 12 °C/W
8-Pin Plastic DIP (P) 96 37 °C/W
8-Pin SO (S) 150 41 °C/W

NOTES

1

Absolute maximum ratings apply to both DICE and packaged parts, unless

otherwise noted.

2

For supply voltages less than ±20 V, the absolute maximum input voltage is equal

to the supply voltage.

3

θJA is specified for worst case mounting conditions, i.e., θ

socket for cerdip and P-DIP, packages; θ
circuit board for SO package.

1

is specified for device soldered to printed

JA

is specified for device in

JA

1

NOTES

1

Burn-in is available on extended industrial temperature range parts in cerdip, and plastic DIP

packages. For outline information see Package Information section.

2

For availability and burn-in information on SO packages, contact your local sales office.

–

50Ω

1/2
OP-297

+

50kΩ

–

1/2
OP-297

2kΩ

V1 20V

V

2

p-p

@ 10Hz

+

V

CHANNEL SEPARATION = 20 log

Figure 3. Channel Separation Test Circuit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP297 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

1

)

V2/10000

)

–4–

REV. D

8/21/97 4:00 PM

400

1200 UNITS

300

200

NUMBER OF UNITS

100

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

INPUT OFFSET VOLTAGE (µV)

T

A

V

S

V

CM

= +25°C

= ±15V

= 0V

Figure 4. Typical Distribution of Input
Offset Voltage

60

40

20

0

20

INPUT CURRENT (pA)

–40

–60

–75 –50 –25 0 25 50 75 100 125

I

–

B

+

I

B

I

OS

TEMPERATURE (°C)

V

S

V

CM

= ±15V

= 0V

Typical Performance Characteristics–

250

1200

UNITS

200

150

100

NUMBER OF UNITS

50

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

INPUT BIAS CURRENT (pA)

Figure 5. Typical Distribution of Input
Bias Current

60

= +25°C

T

A

= ±15V

V

S

40

20

0

–20

INPUT CURRENT (pA)

–40

–60

–15 –10 –5 0 5 10 15

COMMON-MODE VOL T A GE (VOL TS)

= +25°C

T

A

V

= ±15V

S

V

CM

= 0V

I
I

I

–

B

+

B

OS

OP297

400

1200 UNITS

300

200

NUMBER OF UNITS

100

0

–100 –80 –60 –40 –20 0 20 40 60 80 100

INPUT OFFSET CURRENT (pA)

Figure 6. Typical Distribution of In­put Offset Current

±3

T

= +25°C

A

= ±15V

V

S

= 0V

V

CM

±2

±1

DEVIATION FROM FINAL VALUE (µV)

0

012345

TIME AFTER POWER APPLIED (MINUTES)

= +25°C

T

A

= ±15V

V

S

V

CM

= 0V

Figure 7. Input Bias, Offset Current
vs. Temperature

10000

BALANCED OR UNBALANCED

= ±15V

V

S

V

= 0V

CM

1000

100

–55°C

≤

T

≤

125°C

A

EFFECTIVE OFFSET VOLTAGE (µV)

T

= +25°C

A

10

10 100 1k 10k 100k 1M 10M

SOURCE RESISTANCE (Ω)

Figure 10. Effective Offset Voltage
vs. Source Resistance

Figure 8. Input Bias, Offset Current
vs. Common-Mode Voltage

100

BALANCED OR UNBALANCED
VS = ±15V

= 0V

V

CM

10

1

0.1

EFFECTIVE OFFSET VOLTAGE DRIFT (µV/°C)

100 100M1k 10k 100k 1M 10M

SOURCE RESISTANCE (Ω)

Figure 11. Effective TCVOS vs. Source
Resistance

Figure 9. Input Offset Voltage Warm­Up Drift

35
30
25
20
15
10

5

= ±15V

V

S

OUTPUT SHORTED

0

TO GROUND

–5
–10
–15
–20

SHORT-CIRCUIT CURRENT (mA)

–25
–30
–35

01 2 34

TIME FROM OUTPUT SHORT (MINUTES)

T

= –55°C

A

= +25°C

T

A

= +125°C

T

A

= +125°C

T

A

= +25°C

T

A

= –55°C

T

A

Figure 12. Short Circuit Current vs.
Time, Temperature

–5–REV. D