Analog Devices FIFOA Datasheet
High Speed ADC USB FIFO Evaluation Kit
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
FEATURES
Buffer memory board for capturing digital data
Used with high speed ADC evaluation boards
32 kB FIFO Depth at 133 MSPS (upgradeable to 256 kB)
Simplifies evaluation of high speed ADCs
Measures performance with ADC Analyzer™
Real-time FFT and time domain analysis
Analyze SNR, SINAD, SFDR, and harmonics
Import raw text data for analysis
Virtual ADC eval board support using ADIsimADC™
Simple USB port interface
nd
Compatible with Windows® 98 (2
Ed), Windows 2000,
Windows Me, or Windows XP
EQUIPMENT NEEDED
3.3 V power supply
Analog signal source and anti-aliasing filter
Low jitter clock source
High speed ADC evaluation board and ADC data sheet
nd
PC running Windows 98 (2
Ed), Windows 2000,
Windows Me, or Windows XP
USB 2.0 port recommended (USB 1.1 compatible)
Available ADIsimADC product model files
PRODUCT DESCRIPTION
The high speed ADC FIFO evaluation kit includes the latest
version of ADC Analyzer and a memory board to capture
blocks of digital data from Analog Devices’ high speed analogto-digital converter (ADC) evaluation boards. This FIFO board
can be connected to a PC through a USB port and used with
ADC Analyzer to evaluate the performance of high speed ADCs
quickly. Users can view an FFT for a specific analog input and
encode rate and analyze SNR, SINAD, SFDR, and harmonic
information.
The evaluation kit is easy to set up. Additional equipment
needed includes an Analog Devices’ high speed ADC evaluation
board, a power supply, a signal source, and a clock source. Once
the kit is connected and powered, the evaluation is enabled
instantly on the PC.
Two versions of the FIFO are available. The HSC-ADC-EVALADC is used with dual ADCs and converters with demultiplexed
digital outputs. The HSC-ADC-EVALA-SC evaluation board is
used with single-channel ADCs. See Table 1, to choose the FIFO
appropriate for your high speed ADC evaluation board.
FILTERED
ANALOG
INPUT
PRODUCT HIGHLIGHTS
1. Easy to set up—Connect the power supplies and signal
2. ADIsimADC – The software supports virtual ADC
3. USB Port Connection to PC—PC interface is a USB 2.0
4. 32 kB FIFO(s)—This FIFO(s) stores data from the ADC(s)
5. Up to 133 MSPS encode rate on each channel—Single-
FUNCTIONAL BLOCK DIAGRAM
ADC ANALYZER
USB CABLE
SINGLE OR DUAL
HIGH SPEED ADC
EVALUATION BOARD
POWER
SUPPLY
LOGIC
ADC
CLOCK
CIRCUIT
CLOCK INPUT
Figure 1. Functional Block Diagram (Simplified)
n
HSC-ADC-EVALA-SC
OR
HSC-ADC-EVALA-DC
FIFO2
32K
TIMING
FIFO1
CIRCUIT
32K
80-PIN CONNECTOR
sources to the two evaluation boards. Then connect to the
PC and evaluate the performance instantly.
evaluation using ADI proprietary behavioral modeling
technology. This allows rapid comparison between multiple
ADCs, with or without hardware evaluation boards.
connection (1.1 compatible) to PC. A USB cable is
provided in the kit.
for processing. A pin compatible FIFO family is used for
easy upgrading.
channel ADCs with encode rates up to 133 MSPS can be
used with the FIFO board. Dual and demultiplexed output
ADCs also can be used with the FIFO board (with clock
rates up to 133 MSPS on each output channel).
TM
3.3V
04750-0-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
TABLE OF CONTENTS
FIFO Evaluation Board Quick Start............................................... 4
Requirements ................................................................................ 4
Quick Start Steps ...................................................................... 4
Virtual Evaluation Board Quick Start With ADIsimADC.......... 5
Requirements ................................................................................ 5
Quick Start Steps ...................................................................... 5
FIFO 4 Data Capture Board............................................................ 6
FIFO 4 Supported ADC Evaluation Boards.............................. 6
Te r m in o l o g y ...................................................................................... 8
Single Tone FFT............................................................................ 8
Two-Tone FFT .............................................................................. 9
Theory of Operation ...................................................................... 10
Clocking Description................................................................. 10
Clocking with Interleaved Data................................................ 10
Installing ADC Analyzer................................................................11
Average FFT................................................................................ 17
Continuous Average FFT .......................................................... 17
Two Tone ..................................................................................... 18
Continuous Two Tone ............................................................... 18
Average Two Tone...................................................................... 18
Stop............................................................................................... 18
Zooming and Exporting Data .................................................. 18
Importing Data ........................................................................... 19
.csv and ASCII files ................................................................ 19
Printing ........................................................................................ 20
Saving Files.................................................................................. 21
Additional Functions (Virtual ADC only) .............................. 21
Amplitude Sweep (Virtual ADC only) .................................... 21
Analog Frequency Sweep (Virtual ADC only)....................... 22
Troubleshooting.............................................................................. 23
Installation................................................................................... 11
Configuration File ...................................................................... 11
Configuring an Evaluation Board ............................................ 11
Additional Configuration Options .......................................... 14
Windowing ..............................................................................14
Power Supply........................................................................... 14
Y- Ax i s .......................................................................................14
Installing ADC Analyzer With ADIsimADC.............................. 15
Installation................................................................................... 15
Configuration File ...................................................................... 15
Configuring a Model.................................................................. 15
ADC Analyzer Functions .............................................................. 17
Time Domain .............................................................................. 17
Continuous Time Domain........................................................ 17
FFT ...............................................................................................17
Flat Line Signal Displayed......................................................... 23
Displayed Signal Unlike Analog Input .................................... 23
FFT Noise Floor Higher Than Expected................................. 24
Large Spur In FFT (Image Problem) ....................................... 24
MSBs Missing From Time Domain ......................................... 25
Upgrading FIFO Memor y ......................................................... 25
Jumpers ............................................................................................ 26
Default Settings........................................................................... 26
FIFO Schematices and PCB Layout ............................................. 28
FIFO Connector ......................................................................... 28
PCB Schematic............................................................................ 29
Assembly—Primary Side........................................................... 35
Assembly—Secondary Side....................................................... 36
Layer 1— Primary Side.............................................................. 37
Layer 2—Ground Plane............................................................. 38
Continuous FFT .........................................................................17
Rev. 0 | Page 2 of 44
Layer 3—Power Plane................................................................ 39
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
Layer 4—Secondary Side............................................................40
Windowing Functions................................................................43
ESD Caution ................................................................................40
Bill of Materials................................................................................41
Appendix: Sampling and FFT Fundamentals..............................43
Coherent Sampling .....................................................................43
REVISION HISTORY
5/04—Revision 0: Initial Version
FFT Calculations.........................................................................43
Ordering Guide ...........................................................................44
Rev. 0 | Page 3 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
FIFO EVALUATION BOARD QUICK START
Install ADC Analyzer from the CD provided in the FIFO
evaluation kit. See the Installing ADC Analyzer section for more
details. For the latest updates to the software, check the Analog
Devices website at
REQUIREMENTS
Requirements include
• FIFO evaluation board, ADC Analyzer, and USB cable
• High speed ADC evaluation board and ADC data sheet
• 3.3 V power supply for FIFO evaluation board
• Power supply for ADC evaluation board
• Analog signal source and appropriate filtering
• Low jitter clock source applicable for specific ADC
evaluation, typically < 1 ps rms
• PC running Windows 98 (2nd Ed), Windows 2000,
Windows Me, or Windows XP
• PC with a USB 2.0 port recommended (USB 1.1
compatible)
Quick Start Steps
1. Connect the FIFO evaluation board to the ADC evaluation
board. If an adapter is required, insert the adapter between
the ADC evaluation board and the FIFO board. If using the
HSC-ADC-EVALA-SC model, connect the evaluation
board to the bottom half of the 80-pin connector (closest
to the installed IDT FIFO chip).
2. Connect the provided USB cable to the FIFO evaluation
board and to an available USB port on the computer.
3. Refer to Table 4 for any jumper changes. Most evaluation
boards can be used with the default settings.
4. After verification, connect the appropriate power supplies
to the FIFO and ADC evaluation boards. The FIFO
evaluation board requires a single 3.3 V power supply with
1 A current capability. Refer to the instructions included in
the ADC data sheet for more information about the ADC
evaluation board setup.
www.analog.com/hsc-FIFO.
5. Once the cable is connected to both the computer and
FIFO and power is supplied, the USB drivers start to install.
To complete the total installation of the FIFO drivers, you
need to complete the new hardware sequence two times.
The first Found New Hardware Wizard opens with the text
message This wizard helps you install software for…Pre-
FIFO 4. Click the recommended install, and go to the next
screen. A Hardware Installation warning window should
then be displayed. Click Continue Anyway. The next
window that opens should finish the Pre-FIFO 4
installation. Click Finish to complete. Your computer
should go through a second Found New Hardware Wizard,
and the text message, This wizard helps you install
software for…Analog Devices FIFO 4, should be
displayed Continue as you did in the previous installation
and click Continue Anyway, then click Finish on the next
two windows. This should complete the installation.
6. (Optional) Verify in the device manager that “Analog
Devices, FIFO4” is listed under the USB hardware.
7. Apply power to the evaluation board and check the voltage
levels at the board level.
8. Connect the appropriate analog input (which should be
filtered with a band-pass filter) and low jitter clock signal.
Make sure the evaluation boards are powered before
connecting the analog input and clock.
9. Start ADC Analyzer (see the Installation section for
installing the software).
10. Choose a configuration file for the ADC evaluation board
used or create one (see the Configuring an Evaluation
Board section for more information).
11. Click Time Domain (left-most button under the pull-
down menus). A reconstruction of the analog input is
displayed. If the expected signal does not appear, or if there
is only a flat red line, refer to the Troubleshooting section
for more information.
Rev. 0 | Page 4 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
VIRTUAL EVALUATION BOARD QUICK START WITH ADIsimADC
REQUIREMENTS
Requirements include
• Completed installation of ADC Analyzer version 4.5.0 or
later.
• ADIsimADC product model files for the desired converter.
Models are not installed with the software, but may be
downloaded from the website at no charge. Go to
www.analog.com/ADIsimADC or look under Design
To o l s for the product of interest.
• No hardware is required. However, if you wish to compare
results of a real evaluation board and the model, you may
switch easily between the two, as outlined below.
Quick Start Steps
1. To obtain ADC model files, go to
www.analog.com/ADIsimADC or look under Design
To o l s for the product of interest. Download the files of
interest to a local drive. The default location is c:\program
files\adc_analyzer\models.
5. On the ADC Modeling form, select the Device tab and
click the
file browser and displays all of the models found in the
default directory: c:\program files\adc_analyzer\models. If
no model files are found, follow the on-screen directions or
see Step 1 to install available models. If you have saved the
models somewhere other than the default location, use the
browser to navigate to that location and select the file of
interest.
6. From the menu choose Config > FFT. In the FFT
Configuration form, ensure that the Encode Frequency is
set for a valid rate for the simulated device under test. If set
too low or too high, the model will not run.
7. Once a model has been selected, information about the
model displays on the Device tab. After ensuring that you
have selected the right model, select the Input tab. This lets
you configure the input to the model. From the drop down
menu, select either Sine Wave or Two Tone for the input
signal.
… button, adjacent to the dialog box. This opens a
2. Start ADC Analyzer (see the Installation section for
installing the software).
3. From the menu choose Config > Buffer and select Model
from the drop down menu as the buffer memory. In effect,
the model functions in place of the ADC and data capture
hardware.
4. After selecting the Model, a small button, Model, is
displayed next to the Stop button. Click Model to select
and configure which converter will be modeled. This places
a small form in the workspace where you can select and
configure how the model will behave.
8. Click Time Domain (left-most button under the pull-
down menus). A reconstruction of the analog input is
displayed. The model may now be used just as a standard
evaluation board would be.
9. The model supports additional features not found when
testing a standard evaluation board. When using the
modeling capabilities, it is possible to sweep either the
analog amplitude or the analog frequency. See the
Installing ADC Analyzer With ADISIMADC section for
additional features.
Rev. 0 | Page 5 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
FIFO 4 DATA CAPTURE BOARD
JUMPERS UNUSED
PINS TO GROUND
ADC EVALUATION
BOARD CONNECTION:
40 PIN INTERFACE FOR
DATA AND CLOCK INPUT
FOR TOP CHANNEL
IDT72V283 32K
×
16-BIT FIFO
OPTIONAL SMA
CLOCK INPUTS
JUMPERS TIE TOP
AND BOTTOM CLOCK
INPUTS TOGETHER =
IN FOR SINGLE
CHANNEL OPTION,
OUT FOR DUAL
CHANNEL OPTION
JUMPERS UNUSED
PINS TO GROUND
OPTIONAL FINE
TUNING ADJUST
ADC EVALUATION
BOARD CONNECTION:
40 PIN INTERFACE
FOR DATA AND
CLOCK INPUT FOR
BOTTOM CHANNEL
IDT72V283 32K
×
16- BIT FIFO
×
CYPRESS F
SPEED USB 2.0
MICROCONTROLLER
2 HIGH
Figure 2. FIFO Components Description
MICROCONTROLLER
CRYSTAL CLOCK =
24MHz. OFF DURING
DATA CAPTURE
EEPROM TO LOAD
USB FIRMWARE
+3.3V POWER
CONNECTION
INVERT WRITE
CLOCK OPTIONS
ADDITIONAL
TIMING DELAYS
FOR WRITE CLOCK
WRITE CLOCK
SELECT TO
GENERATE WEN
SIGNAL
INVERT WRITE
CLOCK OPTIONS
SET WEN TIMING
FOR INTERLEAVE
MODES
USB CONNECTION
TO COMPUTER
04750-0-002
FIFO 4 SUPPORTED ADC EVALUATION BOARDS
The evaluation boards in Table 1 can be used with the high speed ADC FIFO Evaluation Kit1. Some evaluation boards require an adapter
between the ADC evaluation board connector and the FIFO connector. If an adapter is needed, send an email to
highspeed.converters@analog.com with the part number of the adapter and a mailing address.
Table 1 HSC-ADC-EVALA-DC: and HSC-ADC-EVALA-SC Compatible Evaluation Boards
Evaluation Board Model Description of ADC FIFO Board Version Comments
AD6640ST/PCB 12-Bit, 65 MSPS ADC SC Requires AD664xFFA
AD6644ST/PCB 14-Bit, 65 MSPS ADC SC Rev. C Requires AD664xFFA
AD6645/PCB 14-Bit, 80 MSPS ADC SC Rev. C Requires AD664xFFA
AD9051/PCB 10-Bit, 60 MSPS ADC SC Requires AD9051FFA
AD9057/PCB 8-Bit, 80 MSPS ADC SC Requires AD9283FFA
AD9059/PCB Dual 8-Bit, 60 MSPS ADC DC Requires AD9059FFA
AD9071/PCB 10-Bit, 100 MSPS ADC SC Requires AD9071FFA
AD9200SSOP-EVAL 10-Bit, 20 MSPS ADC SC Requires AD922xFFA
AD9200TQFP-EVAL 10-Bit, 20 MSPS ADC SC Requires AD922xFFA
AD9201-EVAL Dual 10-Bit, 20 MSPS ADC
4
SC Requires AD922xFFA
AD9203-EB 10-Bit, 40 MSPS ADC SC Requires AD922xFFA
AD9214-65PCB 10-Bit, 65 MSPS ADC SC
AD9214-105PCB 10-Bit, 105 MSPS ADC SC
AD9215BCP-65EB 10-Bit, 65 MSPS ADC SC
AD9215BCP-80EB 10-Bit, 80 MSPS ADC SC
AD9215BCP-105EB 10-Bit, 105 MSPS ADC SC
AD9215BRU-65EB 10-Bit, 65 MSPS ADC SC
AD9215BRU-80EB 10-Bit, 80 MSPS ADC SC
AD9215BRU-105EB 10-Bit, 105 MSPS ADC SC
2
3
Rev. 0 | Page 6 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
Evaluation Board Model Description of ADC FIFO Board Version Comments
AD9218-65PCB Dual 10-Bit, 65 MSPS ADC DC
AD9218-105PCB Dual 10-Bit, 105 MSPS ADC DC
AD9220-EB 12-Bit, 10 MSPS ADC SC Requires AD922xFFA
AD9221-EB 12-Bit, 1.25 MSPS ADC SC Requires AD922xFFA
AD9223-EB 12-Bit, 3 MSPS ADC SC Requires AD922xFFA
AD9224-EB 12-Bit, 40 MSPS ADC SC Requires AD922xFFA
AD9225-EB 12-Bit, 25 MSPS ADC SC Requires AD922xFFA
AD9226-EB 12-Bit, 65 MSPS ADC SC Requires AD922xFFA
AD9226QFP-EB 12-Bit, 65 MSPS ADC SC Requires AD922xFFA
AD9235BRU-20EB 12-Bit, 20 MSPS ADC SC
AD9235BRU-40EB 12-Bit, 40 MSPS ADC SC
AD9235BRU-65EB 12-Bit, 65 MSPS ADC SC
AD9235BCP-20EB 12-Bit, 20 MSPS ADC SC
AD9235BCP-40EB 12-Bit, 40 MSPS ADC SC
AD9235BCP-65EB 12-Bit, 65 MSPS ADC SC
AD9235-20PCB 12-Bit, 20 MSPS ADC SC
AD9235-40PCB 12-Bit, 40 MSPS ADC SC
AD9235-65PCB 12-Bit, 65 MSPS ADC SC
AD9236BCP-80EB 12-Bit, 80 MSPS ADC SC
AD9236BRU-80EB 12-Bit, 80 MSPS ADC SC
AD9236BCP-80EB 12-Bit, 80 MSPS ADC SC
AD9238-20PCB Dual 12-Bit, 20 MSPS ADC DC
AD9238-40PCB Dual 12-Bit, 40 MSPS ADC DC
AD9238-65PCB Dual 12-Bit, 65 MSPS ADC DC
AD9240-EB 14-Bit, 40 MSPS ADC SC Requires AD922xFFA
AD9241-EB 14-Bit, 1.25 MSPS ADC SC Requires AD922xFFA
AD9243-EB 14-Bit, 3 MSPS ADC SC Requires AD922xFFA
AD9244-40PCB 14-Bit, 40 MSPS ADC SC
AD9244-65PCB 14-Bit, 65 MSPS ADC SC
AD9245BCP-80EB 14-Bit, 80 MSPS ADC SC
AD9260-EB 16-Bit, 2.5 MSPS ADC SC Requires AD922xFFA
AD9280-EB 8-Bit, 32 MSPS ADC SC Requires AD922xFFA
AD9281-EB Dual 8-Bit, 28 MSPS ADC4 SC Requires AD922xFFA
AD9283/PCB 8-Bit, 100 MSPS ADC SC Requires AD9283FFA
AD9289BBC-65EB Quad 8-Bit, 65 MSPS ADC
AD9410/PCB 10-Bit, 210 MSPS ADC DC
AD9430-CMOS/PCB 12-Bit, 210 MSPS ADC DC
AD9432/PCB 12-Bit, 105 MSPS ADC SC Rev. 0 Requires AD9432FFA
AD9433/PCB 12-Bit, 125 MSPS ADC SC
AD9480BSU-250EB 8-Bit, 250 MSPS ADC DC
AD10200/PCB Dual 12-Bit, 105 MSPS ADC DC Requires LG-0204A
AD10201/PCB Dual 12-Bit, 105 MSPS ADC DC Requires LG-0204A
AD10226/PCB Dual 12-Bit, 125 MSPS ADC DC Requires LG-0204A
AD10235/PCB Dual 12-Bit, 215 MSPS ADC DC Requires LG-0204A
AD10265/PCB Dual 12-Bit, 65 MSPS ADC DC Requires LG-0204A
AD10401/PCB Dual 14-Bit, 105 MSPS ADC DC Requires LG-0204A
AD10465/PCB Dual 14-Bit, 65 MSPS ADC DC Requires LG-0204A
1
Send an email to highspeed.converters@analog.com for information on evaluating the AD9288 with the High Speed ADC FIFO Evaluation Kit.
2
Connector pin numbers and/or labeling on some evaluation boards (AD9214, AD9410, AD9430, AD9433, AD9235, and AD9244) may not match the FIFO connector
numbering; however, the physical connections are correct.
3
The AD6640 evaluation board has a 40-pin output connector that should be left (MSB) justified when connected to the 50-pin AD664x FIFO adapter.
4
The AD9281 and AD9201 have a single output bus
5
The High Speed ADC FIFO Evaluation Kit can be used to evaluate two channels of the AD9289 at a time.
5
DC
Rev. 0 | Page 7 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
TERMINOLOGY
SINGLE TONE FFT
Signal-to-Noise Ratio (SNR)
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components, excluding the first five
harmonics and dc. It is reported in dBc.
Harmonic Distortion, Image
The ratio of the rms signal amplitude to the rms value of the
nonharmonic component generated from the clocking phase
difference of two ADCs, reported in dBc. Note: This measurement
result is valid only when analyzing demultiplexed ADCs.
Signal-to-Noise Ratio Full Scale (SNRFS)
The ratio of the rms signal amplitude related to full scale (0 dB)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc. It is reported in dBFS.
User Defined Signal-to-Noise Ratio (UDSNR)
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components within a specified band
set by the user, excluding harmonics and dc. It is reported in dB.
Noise Figure (NF)
The noise figure is the ratio of the noise power at the output of
a device to the noise power at the input to the device, where the
input noise temperature is equal to the reference temperature
(273 K). The noise figure is expressed in dB.
1
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude to the rms value of the
sum of all other spectral components, including harmonics but
excluding dc. It is reported in dB.
Harmonic Distortion, Second (2nd)–Sixth (6th)
The ratio of the rms signal amplitude to the rms value of the
fundamental related harmonic component, reported in dBc.
Worst Other Spur (WoSpur)
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding all harmonically related
components) reported in dBc.
Total Harmonic Distortion (THD)
The rms value of the sum of all spectral harmonics specified by
the user. It is reported in dBc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It is reported in dBc.
Noise Floor
The rms value of the sum of all other spectral components,
excluding the fundamental, its harmonics, and dc referenced to
full-scale and reported in dBFS.
1
For Noise Figure for an ADC, the equation is
2
log10FigureNoise
×=
k= Boltzman’s Constant = 1.38 x 10
T = Temperature in Kelvin = 273 K
B = Bandwidth = 1 Hz
Encode Frequency = ADC Clock Rate
V
= RMS Fullscale Input Voltage
rms
= Input Impedance
Z
IN
SNRFS= FullScale ADC SNR
⎛
⎜
⎜
⎝
-23
/ZV
rms
0.001
in
⎞
⎟
⎟
⎠
⎛
log10SNRFS
×−−
⎜
⎝
Rev. 0 | Page 8 of 44
FrequencyEncode
2
⎞
⎟
⎠
⎛
×−
log10
⎜
⎝
××
0.001
BTk
⎞
⎟
⎠
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
TWO-TONE FFT
Two-Tone, Second Order Intermodulation
Distortion Products (F1 + F2)
The resulting rms second order distortion value reported by the
mixing of two analog input signals. The peak spurious
component is considered an IMD product. It is reported in dBc.
Two-Tone, Second Order Intermodulation
Distortion Products (F2–F1)
The resulting rms second order distortion value reported by the
mixing of two analog input signals. The peak spurious
component is considered an IMD product. It is reported in dBc.
Two-Tone, Third Order Intermodulation
Distortion Products (2F1
The resulting rms third order distortion value reported by the
mixing of two analog input signals. The peak spurious
component is considered an IMD product. It is reported in dBc.
+ F2)
Two-Tone, Third Order Intermodulation
Distortion Products (2F2
+ F1)
Two-Tone, Worst Other Spur (WoSpur)
The resulting rms distortion value, reported by the mixing of
two analog input signals that is not related to the second or
third order distortion products. The peak spurious component
is not considered an IMD product. It is reported in dBc.
Two-Tone, Second Order Input Intercept Point
(IIP2)
The measure of full-scale input signal power of the converter
minus half the IMD second order products. It is reported in dBm.
Two-Tone, Third Order Input Intercept Point (IIP3)
The measure of full-scale input signal power of the converter
minus half the IMD third order products. It is reported in dBm
Two-Tone, SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
is not an IMD product. It is reported in dBc.
.
The resulting rms third order distortion value reported by the
mixing of two analog input signals. The peak spurious
component is considered an IMD product. It is reported in dBc.
Rev. 0 | Page 9 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
THEORY OF OPERATION
The FIFO evaluation board can be divided into several circuits,
each of which plays an important part in acquiring digital data
from the ADC and allows the PC to upload and process that
data. The evaluation kit is based around the IDT72V283 FIFO
chip from IDT. The system can acquire digital data at speeds up
to 133 MSPS and data record lengths up to 32 kB using the
HSC-ADC-EVALA-SC FIFO evaluation kit. The HSC-ADCEVALA-DC, which has two FIFO chips, is available to evaluate
dual ADCs or demultiplexed data from ADCs sampling faster
than 133 MSPS. A USB 2.0 microcontroller communicating
with ADC Analyzer allows for easy interfacing to newer
computers using the USB 2.0 (USB 1.1 compatible) interface.
The process of filling the FIFO chip(s) and reading the data
back requires several steps. First, ADC Analyzer initiates the
FIFO chip(s) fill process. The FIFO chip(s) are reset using a
master reset signal (MRS). The USB Microcontroller then is
suspended, which turns off the USB oscillator, ensuring that it
does not add noise to the ADC input. After the FIFO chip(s)
completely fill, the full flags from the FIFO chip(s) send a signal
to the USB microcontroller to wake up the microcontroller
from suspend. ADC Analyzer waits for approximately 30 ms
and begins the readback process.
During the readback process, the acquisition of data from
FIFO 1 (U201) or FIFO 2 (U101) is controlled via the signals
OEA and OEB. Because the data outputs of both FIFO chips
drive the same 16-bit data bus, the USB microcontroller
controls the OEA and OEB signals to read data from the correct
FIFO chip. From an application standpoint, ADC Analyzer
sends commands to the USB microcontroller to initiate a read
from the correct FIFO chip, or both FIFO chips in dual or
interleaved mode.
CLOCKING DESCRIPTION
Each channel of the buffer memory requires a clock signal to
capture data. These clock signals are normally provided by the
ADC evaluation board and are passed along with the data
through Connector J104/204 (Pin 37 for both Channel 1 and
Channel 2). If only a single clock is passed for both channels,
they can be connected together by Jumper J303.
Jumpers J304 and J305 at the output of the LVDS receiver allow
the output clock to be inverted by the LVDS receiver. By default,
the clock outputs are inverted by the LVDS receiver.
The single-ended clock signal from each data channel is
buffered and converted to a differential CMOS signal by two
gates of a low voltage differential signal (LVDS) receiver, U301.
This allows the clock source for each channel to be CMOS, TTL,
or ECL. The clock signals are ac-coupled by 0.1 µF capacitors.
Potentiometers R312 and R315 allow for fine tuning the
threshold of the LVDS gates. In applications where fine-tuning
the threshold is critical, these potentiometers may be replaced
with a higher resistance value to increase the adjustment range.
Resistors R303, R304, R307, R308, R311, R313, R314, and R316
set the static input to each of the differential gates to a dc
voltage of approximately 1.5 V.
At assembly, solder Jumpers J310–J313 are set to bypass the
potentiometer. For fine adjustment using the pot, the solder
jumpers must be removed.
U302, an XOR gate array, is included in the design to let users
add gate delays to the FIFO memory chips clock paths. They are
not required under normal conditions and are bypassed at
assembly by Jumpers J314 and J315. Jumpers J306 and J307
allow the clock signals to be inverted through an XOR gate. In
the default setting, the clocks are not inverted by the XOR gate.
The clock paths described above determine the WRT_CLK1
and WRT_CLK2 signals at each FIFO memory chip (U101 and
U201, Pin 80). The timing options above should let you choose
a clock signal that meets the setup and hold time requirements
to capture valid data.
A clock generator can be applied directly to S1 and/or S3. This
clock generator should be the same unit that provides the clock
for the ADC. These clock paths are ac-coupled, so that a sine
wave generator can be used. DC bias can be adjusted by
R301/R302 and R305/R306. Note that J301 and J302 (SMA
connectors) and R301, R302, R305, and R306 are not installed at
the factory and must be installed by the user.
The DS90LV048A differential line receiver is used to square the
clock signal levels applied externally to the FIFO evaluation
board. The output of this clock receiver can either directly drive
the write clock of the IDT72V283 FIFO(s), or first pass through
the XOR gate timing circuitry described above.
CLOCKING WITH INTERLEAVED DATA
ADCs with very high data rates may exceed the capability of a
single buffer memory channel (~133 MSPS). These converters
often demultiplex the data into two channels to reduce the rate
required to capture the data. In these applications, ADC
Analyzer must interleave the data from both channels to
process it as a single channel. The user can configure the
software to process the first sample from Channel 1, the second
from Channel 2, and so on, or vice versa, (see the
Troubleshooting section for more information). The
synchronization circuit included in the buffer memory forces a
small delay between the write enable signals (WENA and
WENB) to the FIFO memory chips (Pin 1, U101 and U201),
ensuring that the data is captured in one FIFO before the other.
Jumpers J401 and J402 determine which FIFO receives WENA
and which FIFO receives WENB
Rev. 0 | Page 10 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
INSTALLING ADC ANALYZER
ADC Analyzer is designed to evaluate the performance of an
Analog Devices analog-to-digital converter quickly and easily.
INSTALLATION
A copy of ADC Analyzer is included on the CD that comes with
the FIFO Evaluation Kit. Check the Analog Devices website for
updates to the software at
1. Copy the AnalyzerSetup.exe file to the hard drive.
2. Run the setup file and follow the instructions given in the
installation wizard. Note that administrator privileges are
required to install the software on Windows
2000/Windows Me/Windows XP machines.
www.analog.com/hsc-FIFO.
Step 1
3. Once the software is installed, run the executable file (the
default location is in c:\program files\
ADC_Analyzer\ADC_Analyzer.exe).
CONFIGURATION FILE
A configuration file can be created for each high speed ADC
evaluation board used with ADC Analyzer. A configuration file
provides the software with important information about the
data sent from the ADC evaluation board to the FIFO
evaluation board, such as the number of bits, speed of the clock,
and format of the data bits (binary or twos complement).
Configuration files for some of the evaluation boards are
included with the ADC Analyzer files. Each time ADC Analyzer
is launched, a window opens where a configuration file can be
specified. Click Ye s to specify a configuration file and choose
the file corresponding to the ADC being used.
The default configuration files can be modified or a new
configuration file can be created using the instructions in the
Configuring An Evaluation Board section.
CONFIGURING AN EVALUATION BOARD
Follow Steps 1 through 5 to configure the software with the
ADC evaluation board:
04750-0-003
2. Choose Config > FFT from the pull-down menus or right-
click any of the analysis buttons to open the FFT
Configuration screen. Use this menu to configure the Fast
Fourier Transform plot. If needed, modify the options
under Channel A to select the appropriate channel.
Step 2
1. From the pull-down menus in the upper left hand corner,
choose Config > DUT. The screen, DUT Configuration
opens. Enter the name of the ADC being evaluated in the
Device dialog box and the number of bits (resolution of
the ADC) in the Number of Bits dialog box. (Note: This
information is used for display purposes only.) To specify a
directory different than the default to store the
configuration file, enter a new location in the Default Data
Directory dialog box, and click OK.
Rev. 0 | Page 11 of 44
04750-0-004
Note that Channel A in the software corresponds to Channel 1
on the FIFO schematics and the bottom FIFO on the evaluation
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
board. Channel B corresponds to Channel 2 on the FIFO
schematics and the top FIFO on the evaluation board (closest to
the Analog Devices logo). See the Jumpers section for more
information.
Configuring FFT— Defining Available Options
in the Max # of Harmonics’ box. Typically, this can be left at the
default value of 3.
DC Leakage: The number of bins (at dc) that are not used in
calculating SNR and SINAD. Typically, this can be left at the
default value of 6.
Samples: Choose the number of samples taken to calculate an
FFT. The default is 16 kB samples. Users can choose more or
fewer samples, depending on the application. The maximum
number of samples that can be selected in the software is 64 kB.
However, the FIFO evaluation boards are configured with 32 kB
FIFOs. For single ADCs evaluated with the HSC-ADC-EVALASC model, the maximum number of samples selected should
match the FIFO memory on the evaluation board. For dual
ADCs evaluated with the HSC-ADC-EVALA-DC model, the
maximum number of samples should match the FIFO memory
of each channel (a different number of samples can be selected
for each channel). ADCs with demultiplexed outputs (such as
the AD9430) can be used with a sample value of twice the FIFO
memory. See the Upgrading FIFO Memory section.
Ave rage s: Specify the number of averages taken for the average
FFT functions. See the ADC Analyzer Functions section for
more information.
Encode Frequency (MHz): Enter the speed of the sampling
clock to the ADC. If evaluating a dual ADC, two different clock
rates can be entered. Note: If the value is wrong, the analog
fundamental frequency displayed will be wrong.
FullScale Input Power (dBm): This feature lets the user enter
the amount of power (in dBm) needed on the input to
determine the output fullscale. It applies only in noise figure
and IIP2/IIP3 calculations.
Maximum Number of Harmonics: The number of harmonics
displayed by ADC Analyzer. The default value is 6 and the
maximum number of harmonics that can be displayed is 12.
Two s C ompl e ment: Check this box if the data from the ADC
evaluation board is in twos complement format. Refer to the
ADC data sheet to determine if the ADC outputs are configured
for twos complement or offset binary. If the Twos Comp l ement
option is not checked, ADC Analyzer will expect the data
outputs from the ADC to be in offset binary format.
User Defined SNR Left (MHz): This is the amount of
frequency specified to the left of the fundamental by the user to
analyze SNR. The resulting value is called UDSNR and will
show up after an FFT plot is captured.
User Defined SNR Right (MHz): This is the amount of
frequency specified to the right of the fundamental by the user
to analyze SNR. The resulting value is called UDSNR and will
show up after an FFT plot is captured.
After configuring the options for the Fast Fourier Transform
plot in this window, click OK.
3. Choose Config > Buffer. HSC-ADC-EVAL(A), opening the
Buffer Memory screen.
Step 3
Enable Fundamental Override: ADC Analyzer automatically
defaults the highest spur as the fundamental frequency of
interest. However, in some applications, the user may have a
very small analog input signal that could be equal to or below
another spurious harmonic. This option lets the user specify the
small analog input signal needed for evaluation. If Enable
Fundamental Override is checked, the Fundamental
Frequency (MHz) box is enabled for the user to specify.
Fundamental Leakage: The number of bins that are neglected
on either side of the fundamental signal when calculating the
SNR and SINAD results. For example, if an encode rate is
defined at 80 MSPS with 16384 samples, then
80M/21/(16384/21) = 4883 Hz/Bin is specified. The type of
windowing selected determines the default value of the
fundamental leakage. See the Windowing section for more
information. The default values are 25, 10, and 1 for Hanning,
Blackman Harris, and no windowing, respectively.
Harmonic Leakage: The number of bins that are neglected on
either side of each harmonic of the fundamental signal defined
Rev. 0 | Page 12 of 44
04750-0-005
Click OK, and the Buffer Configuration window opens. ADC
Analyzer automatically seeks a USB connection. If a USB
connection is not found, it will assume that you want to use an
older version FIFO board which has a parallel connection. If so,
choose the appropriate parallel connection made to the
computer and click OK.
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
Step 3a
04750-0-006
4. Choose Config > Bits > Data Bits to open the Bit Mask
screen. Configure the number and location of the data bits
used to calculate the FFTs.
Make sure that the number of bits matches the resolution of the
converter. All of the supported evaluation boards are MSB
justified, so check the number of bits for the converter starting
with Bit 15 (MSB). Exceptions to this are the AD9280, AD9281,
AD9200, and AD9201. For these four ADCs, check the number
of bits starting with Bit 13.
If a single ADC is being evaluated, check only Channel A and
the appropriate bits under Channel A. If a dual ADC is being
evaluated, check Channel A and Channel B on the Channel
Select screen. (Config > Channel Select).
Step 4
04750-0-007
If evaluating a demultiplexed ADC, go to Config > Channel
Select, opening the Channel Select pop-up menu, and check the
Interleaved Data box. This automatically selects both Channel
A and Channel B. When using a dual ADC, select only the
appropriate channel that corresponds to the ADC that is being
evaluated. Channel A is the default selected channel at startup.
Step 4a
04750-0-008
Note that Channel A in the software corresponds to Channel 1
on the FIFO schematics and the bottom FIFO (U201) on the
Rev. 0 | Page 13 of 44
HSC-ADC-EVALA-SC/HSC-ADC-EVALA-DC
evaluation board. Channel B corresponds to Channel 2 on the
FIFO schematics and the top FIFO (U101) on the evaluation
board (closest to the Analog Devices logo). See the Jumpers
section for more information. Click OK. (For more information
about the channel selection process, see the Troubleshooting
section.)
5. As a last step, choose File > Configuration File > Save
Configuration from the pull-down menu to save the
configuration for future use. Choose a file name and a
location to save the file.
ADDITIONAL CONFIGURATION OPTIONS
Other options under the configuration pull-down menu include
Windowing, Power Supply, and Y-Axis.
Windowing
Choose either the Hanning or Blackman Harris (default)
windowing functions or turn windowing off. See the
Windowing Functions section for a description of Hanning and
Blackman Harris windowing. Click OK.
For the calculator to work properly, the correct sampling
frequency must be entered under Config > FFT. Select either the
desired approximate Analog Input Frequency or the # of Sine
Wave Cyc l es . Enter the value in the dialog box (not labeled) and
click Calculate to view the Coherent Frequency. The Coherent
Frequency and Number of Integer Cycles will display in the
gray boxes. Click OK to exit the Coherent Sampling Calculator.
Power Supply
This option opens under Config > Power Supply, and users can
enter the value of the ADC analog and digital voltage supplies
(see Figure 5). Note this for user documentation only. No
external control is provided. ADC Analyzer displays this
information when data is captured. See the ADC Analyzer
Functions section for more information.
04750-0-009
Figure 3. Select Windowing Function
If you choose None, the Coherent Sampling Calculator window
opens (see Figure 4).
04750-0-011
Figure 5. Power Supply Configuration
Y-Axis
Use the Y Axis screen to configure the display of the FFT
Y-Axis. Go to Config > YAxis to change the default value of –
130, which is a typical setting for the noise floor of a 14-bit
ADC with 16,384 samples in the FFT calculation.
04750-0-012
Figure 6. Y Axis Configuration
04750-0-010
Figure 4. Coherent Sampling Calculator
Rev. 0 | Page 14 of 44
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