FEATURES
14-Bit/16-Bit Multiplying DAC
Guaranteed Monotonicity
Output Control on Power-Up and Power-Down
Internal or External Control
Versatile Serial Interface
DAC Clears to 0 V in Both Unipolar and Bipolar Output
Ranges
APPLICATIONS
Industrial Process Control
PC Analog I/O Boards
Instrumentation
GENERAL DESCRIPTION
The AD7849 is a 14-bit/16-bit serial input multiplying DAC.
The DAC architecture ensures excellent differential linearity
performance, and monotonicity is guaranteed to 14 bits for the
A grade and to 16 bits for all other grades over the specified
temperature ranges.
During power-up and power-down sequences (when the supply
voltages are changing), the V
impedance path. To prevent the output of A3 being shorted to
0 V during this time, transmission gate G1 is also opened.
These conditions are maintained until the power supplies
stabilize and a valid word is written to the DAC register. At this
time, G2 opens and G1 closes. Both transmission gates are also
externally controllable via the Reset In (RST IN) control input.
For instance, if the RST IN input is driven from a battery supervisor chip, then on power-off or during a brown out, the RSTIN input will be driven low to open G1 and close G2. The DAC
must be reloaded, with RST IN high, to re-enable the output.
Conversely, the on-chip voltage detector output (RST OUT) is
also available to the user to control other parts of the system.
pin is clamped to 0 V via a low
OUT
14-Bit/16-Bit DAC
AD7849*
FUNCTIONAL BLOCK DIAGRAM
V
DDVCC
V
REF+
R
A1
16-
SEG-
V
REF–
R
R
DGND
MENT
SWITCH
MATRIX
4
AD7849
SDIN SCLK
10-BIT/
12-BIT
DAC
10/
A2
12
DAC
LATCH
10/
12
INPUT
LATCH
INPUT SHIFT REGISTER/
CONTROL LOGIC
SYNC CLR BIN/
COMP
The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multichannel system. The DCEN (Daisy Chain Enable) input controls this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP
set to 0, the coding is straight binary; and with it set to 1, the
coding is 2s complement. This allows the user to reset the DAC
to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead DIP and 20-lead SOIC package.
R
R
A3
LOGIC
CIRCUITRY
VOLTAGE
MONITOR
DCEN SDOUT
G1
G2
LDAC
R
OFS
RST IN
V
OUT
AGND
RST OUT
V
SS
*Protected by U.S. Patent No. 5,319,371.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Differential Nonlinearity±0.25±0.9±0.5LSBs maxAll Grades Guaranteed Monotonic Over Temperature
MAX
±5±16±8LSBs max
Gain Error @ +25°C±1± 4± 4LSBs typV
T
MIN
to T
MAX
±4±16±16LSBs max
Offset Error @ +25°C±1±4±4LSBs typ
T
to T
MIN
Gain TC
Offset TC
MAX
3
3
±6±24±16LSBs max
±2±2±2ppm FSR/°C typ
±2±2±2ppm FSR/°C typ
BIPOLAR OUTPUTV
Relative Accuracy @ +25°C±2±3±2LSBs typ
to T
T
MIN
Differential Nonlinearity±0.25±0.9±0.5LSBs maxAll Grades Guaranteed Monotonic Over Temperature
MAX
±3±8±4LSBs max
Gain Error @ +25°C±1± 4± 4LSBs typV
T
MIN
to T
MAX
±4±16±16LSBs max
Offset Error @ +25°C±0.5±2±2LSBs typ
T
MIN
to T
MAX
±3±12±8LSBs max
Bipolar Zero Error @ +25°C±0.5±2±2LSBs typ
T
to T
MIN
MAX
3
Gain TC
Offset TC
3
Bipolar Zero TC
3
±4±12±8LSBs max
±2±2±2ppm FSR/°Ctyp
±2±2±2ppm FSR/°Ctyp
±2±2±2ppm FSR/°Ctyp
REFERENCE INPUT
Input Resistance252525kΩ minResistance from V
434343kΩ maxTypically 34 kΩ
V
RangeVSS + 6 toVSS + 6 toVSS + 6 toVolts
REF+
V
RangeVSS + 6 toVSS + 6 toVSS + 6 toVolts
REF–
VDD – 6VDD – 6VDD – 6
VDD – 6VDD – 6VDD – 6
OUTPUT CHARACTERISTICS
Output Voltage SwingVSS + 4 toVSS + 4 toVSS + 4 toV max
VDD – 4VDD – 4VDD – 4
Resistive Load222kΩ minTo 0 V
Capacitive Load200200200pF maxTo 0 V
Output Resistance0.30.30.3Ω typ
Short Circuit Current± 25± 25± 25mA typVoltage Range: –10 V to +10 V
DIGITAL INPUTS
V
, Input High Voltage2.42.42.4V min
INH
V
, Input Low Voltage0.80.80.8V max
INL
I
, Input Current±10±10±10µA max
INH
CIN, Input Capacitance101010pF max
DIGITAL OUTPUTS
VOL (Output Low Voltage)0.40.40.4Volts maxI
VOH (Output High Voltage)4.04.04.0Volts minI
Floating State Leakage Current±10±10±10µA max
Floating State Output
Capacitance101010pF max
POWER REQUIREMENTS
V
DD
V
SS
V
CC
I
DD
I
SS
I
CC
Power Supply Sensitivity
4
+14.25/+15.75 +14.25/+15.75 +14.25/+15.75 V min/V max
–14.25/–15.75 –14.25/–15.75 –14.25/–15.75V min/V max
+4.75/+5.25+4.75/+5.25+4.75/+5.25V min/V max
555mA maxV
555mA maxV
5
2.52.52.5mA maxV
0.41.51.5LSB/V max
Power Dissipation100100100mW typV
NOTES
1
Temperature ranges: A, B, C Versions: –40°C to +85°C; T Version: –55°C to +125°C.
2
Minimum load for T Version is 3 kΩ.
3
Guaranteed by design and characterization, not production tested.
4
The AD7849 is functional with power supplies of ± 12 V. See Typical Performance Curves.
5
Sensitivity of Gain Error, Offset Error and Bipolar Zero Error to VDD, VSS variations.
Specifications subject to change without notice.
loaded with 2 kΩ,2 200 pF to 0 V; V
OUT
B, C, T Versions: 1 LSB = 2 (V
= 0 V, V
REF–
Load = 10 MΩ
OUT
= –5 V, V
REF–
Load = 10 MΩ
OUT
= 1.6 mA
SINK
= 400 µA
SOURCE
Unloaded, V
OUT
Unloaded, V
OUT
= VDD – 0.1 V, V
INH
Unloaded
OUT
= 0 V to +10 V
OUT
= –10 V to +10 V
OUT
to V
REF+
= VDD – 0.1 V, V
INH
= VDD – 0.1 V, V
INH
INL
REF+
REF+–VREF–
REF+–VREF–
REF–
= 0.1 V
= +5 V;
14
)/2
)/2
= 0.1 V
INL
= 0.1 V
INL
16
–2–
REV. B
AD7849
RESET SPECIFICATIONS
power-down sequence.) V
unloaded.
OUT
(These specifications apply when the device goes into the Reset mode during a power-up or
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
3
SCLK mark/space ratio range is 40/60 to 60/40.
4
SDO load capacitance is 50 pF.
Specification subject to change without notice.
REV. B
200200ns minSCLK Cycle Time
5050ns minSYNC to SCLK Setup Time
7070ns minSYNC to SCLK Hold Time
1010ns minData Setup Time
4040ns minData Hold Time
8080ns maxSCLK Falling Edge to SDO Valid
8080ns minLDAC, CLR Pulsewidth
3030µs maxDigital Input Rise Time
3030µs maxDigital Input Fall Time
–3–
AD7849
SD103C
1N5711
1N5712
1N4148
V
DD
V
CC
V
DD
V
CC
AD7849
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to +17 V
to DGND2 . . . . . . . . . . . . . . . . . . –0.4 V, VDD + 0.4 V or
V
CC
+7 V (Whichever Is Lower)
V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.4 V to –17 V
Lead Temperature, Soldering (Soldering 10 secs) . . . 260°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
VCC must not exceed VDD by more than 0.4 V. If it is possible for this to happen
during power-up or power-down (for example, if V
VDD is still 0 V), the following diode protection scheme will ensure protection.
3
V
may be shorted to DGND, +10 V, –10 V, provided that the power dissipation
OUT
of the package is not exceeded.
4
Transient currents of up to 100 mA will not cause SCR latch-up.
is greater than +0.4 V while
CC
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7849 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
TemperatureResolutionBipolarPackage
ModelRange(Bits)INL (LSBs)Option
*
AD7849AN–40°C to +85°C14± 3N-20
AD7849BN–40°C to +85°C16± 8N-20
AD7849CN–40°C to +85°C16±4N-20
AD7849AR–40°C to +85°C14± 3R-20
AD7849BR–40°C to +85°C16±8R-20
AD7849CR–40°C to +85°C16± 4R-20
AD7849TQ–55°C to +125°C16± 8Q-20
This is the analog weighting of 1 bit of the digital word in a DAC.
For the AD7849, B, C and T versions, 1 LSB = (V
16
2
. For the AD7849, A version, 1 LSB = (V
REF+–VREF–
– V
REF+
REF–
)/
)/214.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for both endpoints (i.e., offset and gain errors are adjusted out) and is normally expressed in least significant bits or
as a percentage of full-scale range.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal change between any two adjacent codes. A
specified differential nonlinearity of less than ±1 LSB over the
operating temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output with all 1s loaded after offset
error has been adjusted out. Gain error is adjustable to zero
with an external potentiometer.
PIN FUNCTION DESCRIPTION
PinMnemonicDescription
Offset Error
This is the error present at the device output with all 0s loaded
in the DAC. It is due to op amp input offset voltage and bias
current and the DAC leakage current.
Bipolar Zero Error
When the AD7849 is connected for bipolar output and
(100 . . . 000) is loaded to the DAC, the deviation of the analog
output from the ideal midscale of 0 V, is called the bipolar zero
error.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected from the digital inputs to
the analog output when the inputs change state. This is normally specified as the area of the glitch in nV-secs.
Multiplying Feedthrough Error
This is an ac error due to capacitive feedthrough from either of
the V
terminals to V
REF
when the DAC is loaded with all 0s.
OUT
Digital Feedthrough
When the DAC is not selected (SYNC is held high), high frequency logic activity on the digital inputs is capacitively coupled
through the device to show up as noise on the V
pin. This
OUT
noise is digital feedthrough.
1V
REF+
2V
REF–
3V
SS
V
Input. The DAC is specified for V
REF+
V
Input. The DAC is specified for V
REF–
of +5 V. The DAC is fully multiplying so that the V
REF+
of –5 V. Since the DAC is fully multiplying the V
REF–
Negative supply for the analog circuitry. This is nominally –15 V.
range is +5 V to –5 V.
REF+
range is –5 V to +5 V.
REF–
4SYNCData Synchronization Logic Input. When it goes low, the internal logic is initialized in readiness for a new data word.
5SCLKSerial Clock Logic Input. Data is clocked into the input register on each SCLK falling edge.
6V
CC
Positive supply for the digital circuitry. This is nominally +5 V.
7SDOUTSerial Data Output. With DCEN at Logic “1,” this output is enabled and the serial data in the input shift register is
clocked out on each rising edge of SCLK.
8DCENDaisy-Chain Enable Logic Input. Connect this pin high if a daisy-chain interface is being used, otherwise this pin must be
connect low.
9BIN/COMPLogic Input. This input selects the data format to be either binary or 2s complement. In the unipolar output range,
natural binary format is selected by connecting the input to a Logic “0.” In the bipolar output range, offset binary is
selected by connecting this input to a Logic “0” and 2s complement is selected by connecting it to a Logic “1.”
10DGNDDigital Ground. Ground reference point for the on-chip digital circuitry.
11LDACLoad DAC Logic Input. This input updates the DAC output. The DAC output is updated on the falling edge of this
signal or alternatively, if this input is permanently low, an automatic update mode is selected whereby the DAC is updated
on the 16th falling SCLK edge.
12SDINSerial Data Input. The 16-bit serial data word is applied to this input.
13CLRClear Logic Input. Taking this input low sets V
ment output range. It sets V
OUT
to V
in the offset binary bipolar output range.
REF–
to 0 V in both the unipolar output range and the bipolar 2s comple-
OUT
14RSTINReset Logic Input. This input allows external access to the internal reset logic. Applying a Logic “0” to this input, resets
the DAC output to 0 V. In normal operation it should be tied to Logic “1.”
15RSTOUTReset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. It may used to control
other system components if desired.
16AGNDThis is the analog ground for the device. It is the point to which the output gets shorted in the reset mode.
17V
DD
Positive supply for the analog circuitry. This is +15 V nominal.
18NCNo Connect. Leave unconnected.
19V
20R
OUT
OFS
DAC Output Voltage Pin.
Input to summing resistor of DAC output amplifier. This is used to select output voltage ranges. See Figures 16 to 19
in “APPLYING THE AD7849.”
REV. B
–5–
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