Analog Devices AD7827BR Datasheet

3 V/5 V, 1 MSPS, 8-Bit, Serial Interface

BUF

T/H

2.5V
REF

8-BIT

HALF-FLASH

ADC

SERIAL

PORT

CONTROL

LOGIC

V

DD

DETECT

RFS

D

OUT

SCLK

CONVST

GND

V

DD

V

REFIN/VREFOUT

V

IN

COMP

AD7827

a

FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time

200 ns Acquisition Time
8-Lead Package
On-Chip Track-and-Hold
On-Chip 2.5 V Reference with 2% Tolerance
Operating Supply Range: 3 V 6 10% and 5 V 6 10%
Specifications @ 3 V and 5 V
DSP/Microcontroller Compatible Serial Interface
Automatic Power-Down at End of Conversion
Input Ranges

0 V to 2 V, V

0 V to 2.5 V, V

GENERAL DESCRIPTION

The AD7827 is a high speed, single channel, low power, analog­to-digital converter with a maximum throughput of 1 MSPS that
operates from a single 3 V or 5 V supply. The AD7827 contains
a track/hold amplifier, an on-chip 2.5 V reference (2% toler­ance), a 420 ns 8-bit half-flash ADC and a serial interface. The
serial interface is compatible with the serial interfaces of most
DSPs (Digital Signal Processors). The throughput rate of the
AD7827 is dependent on the clock speed of the DSP serial
interface.

The AD7827 combines the Convert Start and Power Down
signals at one pin, i.e., the CONVST pin. This allows a unique
automatic power-down at the end of a conversion to be imple­mented. The logic level on the CONVST pin is sampled at the
end of a conversion and, depending on its state, the AD7827
powers down.

The AD7827 has one single-ended analog input with an input
span determined by the supply voltage. With a V
input range of the AD7827 is 0 V to 2 V and with V
5 V, the input range is 0 V to 2.5 V.

The parts are available in a small, 8-lead, 0.3" wide, plastic
dual-in-line package (DIP) and an 8-lead, small outline IC
(SOIC).

= 3 V

DD

DD

= 5 V

of 3 V, the

DD

equal to

DD

Sampling ADC

AD7827

FUNCTIONAL BLOCK DIAGRAM

PRODUCT HIGHLIGHTS

1. Fast Conversion Time
The AD7827 has a conversion time of 420 ns. Faster conver­sion times maximize the DSP processing time in a real time
system.

2. Built-In Track-and-Hold
The analog input signal is held and a new conversion is initi­ated on the falling edge of the CONVST signal. The CONVST
signal allows the sampling instant to be exactly controlled.
This feature is a requirement in many DSP applications.

3. Automatic Power-Down
The CONVST signal is sampled approximately 100 ns after
the end of conversion and depending on its state the AD7827
is powered down.

4. An easy to use, fast serial interface allows direct interfacing to
most popular DSPs with no external circuitry.

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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD7827–SPECIFICA TIONS

(VDD = +3 V 6 10%, VDD = +5 V 6 10%, GND = 0 V, V

REFIN/REFOUT

specifications –408C to +1058C unless otherwise noted.)

= 2.5 V. All

Parameter Version B Units Test Conditions/Comments

DYNAMIC PERFORMANCE f

Signal-to-(Noise + Distortion) Ratio
Total Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion

1

1

1

1

48 dB min
–55 dB max
–55 dB max

= 30 kHz; f

IN

fa = 29.1 kHz; fb = 29.9 kHz

SAMPLE

= 1 MHz

2nd Order Terms –65 dB typ
3rd Order Terms –65 dB typ

DC ACCURACY

Resolution 8 Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
Gain Error

1

1

1

1

±0.5 LSB max
±0.5 LSB max
±1.5 LSB max
±2 LSB max

Minimum Resolution for Which

No Missing Codes are Guaranteed 8 Bits

ANALOG INPUT

2

Input Voltage Range 0 V min VDD = 5 V

2.5 V max
0 V min V

DD

= 3 V

2 V max
Input Leakage Current ±1 µA max
Input Capacitance 10 pF max

REFERENCE INPUT

V

REFIN/REFOUT

Input Voltage Range 2.55 V max

2.45 V min

Input Current ±1 µA typ

±50 µA max

LOGIC INPUTS

CONVST, SCLK

V

Input High Voltage 2.4 V min VDD = 5 V ± 10%

INH,

V

Input Low Voltage 0.8 V max VDD = 5 V ± 10%

INL,

V

Input High Voltage 2.0 V min VDD = 3 V ± 10%

INH,

V

Input Low Voltage 0.4 V max VDD = 3 V ± 10%

INL,

Input Current, I

INH

±1 µA max Typically 10 nA, VIN = 0 V or V

Input Capacitance 10 pF max

LOGIC OUTPUTS

D

, RFS

OUT

V

Output High Voltage I

OH,

4 V max V

2.4 V min V

V

Output Low Voltage I

OL,

0.4 V max V

0.2 V min V
High Impedance Leakage Current ±1 µA max
High Impedance Capacitance 15 pF max

CONVERSION RATE

Conversion Time 420 ns max
Track/Hold Acquisition Time 200 ns max

= 200 µA

SOURCE

= 5 V ± 10%

DD

= 3 V ± 10%

DD

= 200 µA

SINK

= 5 V ± 10%

DD

= 3 V ± 10%

DD

DD

–2–

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AD7827

Parameter Version B Units Test Conditions/Comments

POWER SUPPLY

V

DD

I

DD

Normal Operation 10 mA max 8 mA Typically
Power-Down 1 µA max Logic Inputs = 0 V or V

Power Dissipation VDD = 3 V

Normal Operation 30 mW max Typically 24 mW
Power-Down

200 kSPS 9.58 mW max
1 MSPS 47.88 mW max

NOTES

1

See Terminology section of this data sheet.

2

Refer to the Analog Input section for an explanation of the Analog Input(s).

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Parameter 5 V 6 10% 3 V 6 10% Units Conditions/Comments

t

CONVERT

t

1

t

2

3

t

3

t

4

3

t

5

3

t

6

t

7

t

8

4

t

9

t

10

t

11

t

POWER-UP

t

POWER-UP

NOTES

1

Sample tested to ensure compliance.

2

See Figures 13, 14 and 15.

3

Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10% and time required for an

output to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t9, quoted in the timing characteristics is the true bus relinquish time of
the part and as such is independent of external bus loading capacitances.

Specifications subject to change without notice.

420 420 ns max Conversion Time.
20 20 ns min Minimum CONVST Pulsewidth.
t

CONVERT+t3

t

CONVERT+t3+t7+t8tCONVERT+t3+t7+t8

t

CONVERT+t3

14 18 ns max Rising edge of SCLK to falling edge of RFS.
14 18 ns max Rising edge of SCLK to rising edge of RFS.
20 20 ns max Rising edge of SCLK to high impedance disabled.
14 18 ns max Rising edge of SCLK to D
25 25 ns min Minimum high SCLK pulse duration.
25 25 ns min Minimum low SCLK pulse duration.
20 20 ns min Bus relinquish time after SCLK falling edge.
35 35 ns max
20 20 ns max Maximum delay from falling edge CONVST to rising edge RFS if

30 30 ns min Minimum time between end of serial read and next falling edge of

11µs max Power-up time from rising edge of CONVST using external 2.5 V

25 25 µs max Power-up time from rising edge of CONVST using on-chip reference.

4.5 V min 5 V ± 10% For Specified Performance

5.5 V max

2.7 V min 3 V ± 10% For Specified Performance

3.3 V max

1, 2

(V

REFIN/REFOUT

= 2.5 V, all specifications –408C to +1058C, unless otherwise noted)

ns min Falling edge of CONVST to falling edge of RFS.
ns max

valid delay.

OUT

RFS reset by CONVST.

CONVST.

reference.

200mA

I

OL

DD

TO

OUTPUT

PIN

50pF

C

L

200mA

+2.1V

I

OH

Figure 1. Load Circuit for Digital Output Timing Specifications

–3–REV. 0

AD7827

WARNING!

ESD SENSITIVE DEVICE

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

CONVST

V

IN

RFS

V

DD

SCLK
D

OUT

V

REF

GND

AD7827

ABSOLUTE MAXIMUM RATINGS*

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DD

Digital Input Voltage to GND

(CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, V

+ 0.3 V

DD

Digital Output Voltage to GND

(D

, RFS) . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

OUT

V

to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V

REF

Analog Input Voltage to AGND . . . . . . –0.3 V, V

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C

Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W

JA

Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C

SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW

θ

Thermal Impedance . . . . . . . . . . . . . . . . . . . . +75°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

Linearity
Error Package Package

Model (LSB) Description Option

AD7827BN ±0.5 LSB Plastic DIP N-8
AD7827BR ±0.5 LSB Small Outline IC SO-8

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 CONVST Convert Start. Puts the track-and-

hold into hold mode and initiates a
conversion.
The state of this pin at the end of
conversion also determines whether
or not the part is powered down.

2V

IN

Analog Input is applied here.

3 RFS Receive Frame Sync. This is an

output. When this signal goes logic
high at the end of a conversion, the
DSP starts latching in data on the
next cycle of SCLK.

4 GND Ground reference for analog and

digital circuitry.
5V
6D

REF

OUT

Reference Input.

Serial Data is shifted out on this pin.

Data is clocked out by the rising

edges of SCLK.
7 SCLK Serial Clock. An external serial clock

is applied here. The clock must be

continuous so the RFS (frame SYNC)

can be synchronized to the clock for

high speed data transfers. (See

Microprocessor Interfacing section.)
8VDDPositive Supply Voltage 3 V/5 V ± 10%.

PIN CONFIGURATION

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7827 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–4–

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