ANALOG DEVICES AD7825 Service Manual

V

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3 V/5 V, 2 MSPS, 8-Bit, 1-/4-/8-Channel

FEATURES

8-bit half-flash ADC with 420 ns conversion time One, four, and eight single-ended analog input channels

Available with input offset adjust On-chip track-and-hold SNR performance given for input frequencies up to 10 MHz On-chip reference (2.5 V) Automatic power-down at the end of conversion Wide operating supply range

3 V ± 10% and 5 V ± 10% Input ranges

0 V to 2 V p-p, V

0 V to 2.5 V p-p, V

Flexible parallel interface with

standalone operation

APPLICATIONS

Data acquisition systems, DSP front ends Disk drives Mobile communication systems, subsampling

applications

= 3 V ± 10%

DD

= 5 V ± 10%

DD

EOC

pulse to allow

AD7822/AD7825/AD7829

FUNCTIONAL BLOCK DIAGRAM

CONVST

EOC

A01A11A2

CONTROL

LOGIC

V

IN1

4

V

IN2

4

V

IN3

4

V V V V V

INPUT

IN4

5

IN5

5

IN6

5

IN7

5

IN8

1

A0, A1 AD7825/AD7829

2

A2 AD7829

3

PD AD7822/AD7825

4

V

TO V

IN2

5

V

TO V

IN5

MUX

AD7825/AD7829

IN4

AD7829

IN8

T/H

V

MID

AGND

Sampling ADCs

2

8-BIT

HALF

FLASH

ADC

Figure 1.

PD

DGND

3

COMP

BUF

PARALLEL

PORT

RD

CS

DD

2.5V REF

V

REF IN/OUT

DB7

DB0

01321-001

GENERAL DESCRIPTION

The AD7822/AD7825/AD7829 are high speed, 1-, 4-, and 8-channel, microprocessor-compatible, 8-bit analog-to-digital converters with a maximum throughput of 2 MSPS. The AD7822/ AD7825/AD7829 contain an on-chip reference of 2.5 V (2% tolerance); a track-and-hold amplifier; a 420 ns, 8-bit halfflash ADC; and a high speed parallel interface. The converters can operate from a single 3 V ± 10% and 5 V ± 10% supply.

The AD7822/AD7825/AD7829 combine the convert start and

ower-down functions at one pin, that is, the

p

CONVST This allows a unique automatic power-down at the end of a conversion to be implemented. The logic level on the pin is sampled after the end of a conversion when an of conversion) signal goes high. If it is logic low at that point,

the ADC is powered down. The AD7822 and AD7825 also have a separate power-down pin (see the

Operating Modes section).

The parallel interface is designed to allow easy interfacing to

oprocessors and DSPs. Using only address decoding logic,

micr the parts are easily mapped into the microprocessor address space. The

EOC

pulse allows the ADCs to be used in a stand-

alone manner (see the Parallel Interface section.)

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

pin.

CONVST

EOC

(end

The AD7822 and AD7825 are available in 20-lead and 24-lead,

0.3" wide

, plastic dual in-line packages (PDIP); 20-lead and 24-lead standard small outline packages (SOIC); and 20-lead and 24-lead thin shrink small outline packages (TSSOP). The AD7829 is available in a 28-lead, 0.6" wide PDIP; a 28-lead SOIC; and a 28-lead TSSOP.

PRODUCT HIGHLIGHTS

1. Fast Conversion Time. The AD7822/AD7825/AD7829

have a conversion time of 420 ns. Faster conversion times maximize the DSP processing time in a real-time system.

2. Ana

log Input Span Adjustment. The V

user to offset the input span. This feature can reduce the requirements of single-supply op amps and take into account any system offsets.

3. FPB

W (Full Power Bandwidth) of Track-and-Hold. The track-and-hold amplifier has an excellent high frequency performance. The AD7822/AD7825/AD7829 are capable of converting full-scale input signals up to a frequency of 10 MHz. This makes the parts ideally suited to subsampling applications.

4. C

hannel Selection. Channel selection is made without the

necessity of writing to the part.

pin allows the

MID

AD7822/AD7825/AD7829

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REVISION HISTORY

8/06—Rev. B to Rev. C

Changes to General Description .................................................... 1

Changes to Table 1............................................................................ 3

Changes to Typical Connection Diagram Section..................... 10

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 25

10/01—Rev. A to Rev. B

C

hanges to Power Requirements.................................................... 3

Changes to Pin Function Description ........................................... 5

Changes to Circuit Description...................................................... 7

Changes to Typical Connection Diagram Section........................7

Changes to Analog Input Section....................................................8

Changes to Analog Input Selection Section...................................9

Changes to Power-Up Times Section .......................................... 10

Changes to Power vs. Throughput Section................................. 11

Added AD7822 Stand-Alone Operation section ....................... 15

12/99—Rev. 0 to Rev. A

Rev. C | Page 2 of 28

AD7822/AD7825/AD7829

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SPECIFICATIONS

VDD = 3 V ± 10%, VDD = 5 V ± 10%, GND = 0 V, V

REF IN/OUT

Table 1.

Parameter Version B Unit Test Condition/Comment

DYNAMIC PERFORMANCE fIN = 30 kHz, f

Signal to (Noise + Distortion) Ratio Total Harmonic Distortion

1

Peak Harmonic or Spurious Noise Intermodulation Distortion

1

Second-Order Terms −65 dB typ Third-Order Terms −65 dB typ

Channel-to-Channel Isolation

1

DC ACCURACY

Resolution 8 Bits Minimum Resolution for Which

No Missing Codes Are Guaranteed 8 Bits Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Gain Error Gain Error Match

1

Offset Error1 ±1 LSB max Offset Error Match

ANALOG INPUTS

1

2

VDD = 5 V ± 10% Input voltage span = 2.5 V

V

to V

IN1

Input Voltage VDD V max

IN8

0 V min

V

Input Voltage VDD − 1.25 V max Default V

MID

1.25 V min

VDD = 3 V ± 10% Input voltage span = 2 V

V

to V

IN1

Input Voltage VDD V max

IN8

0 V min

V

Input Voltage VDD − 1 V max Default V

MID

1 V min VIN Input Leakage Current ±1 µA max VIN Input Capacitance 15 pF max V

Input Impedance 6 kΩ typ

MID

REFERENCE INPUT

V

Input Voltage Range 2.55 V max 2.5 V + 2%

REF IN/OUT

2.45 V min 2.5 V − 2% Input Current 1 A typ 100 A max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ±50 mV max Temperature Coefficient 50 ppm/°C typ

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input High Voltage, V Input Low Voltage, V

2.4 V min VDD = 5 V ± 10%

INH

0.8 V max VDD = 5 V ± 10%

INL

2 V min VDD = 3 V ± 10%

INH

0.4 V max VDD = 3 V ± 10%

INL

Input Current, IIN ±1 A max 10 nA typical, VIN = 0 V to VDD Input Capacitance, CIN 10 pF max

= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.

= 2 MHz

SAMPLE

48 dB min

−55 dB max

−55 dB max fa = 27.3 kHz, fb = 28.3 kHz

−70 dB typ fIN = 20 kHz

±0.75 LSB max ±0.75 LSB max ±2 LSB max ±0.1 LSB typ

±0.1 LSB typ See Analog Input section

= 1.25 V

MID

= 1 V

MID

Rev. C | Page 3 of 28

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Parameter Version B Unit Test Condition/Comment

LOGIC OUTPUTS

Output High Voltage, VOH I 4 V min VDD = 5 V ± 10%

2.4 V min VDD = 3 V ± 10% Output Low Voltage, VOL I

0.4 V max VDD = 5 V ± 10%

0.2 V max VDD = 3 V ± 10% High Impedance Leakage Current ±1 A max High Impedance Capacitance 10 pF max

CONVERSION RATE

Track-and-Hold Acquisition Time 200 ns max See Circuit Description section Conversion Time 420 ns max

POWER SUPPLY REJECTION

VDD ± 10% ±1 LSB max

POWER REQUIREMENTS

VDD 4.5 V min 5 V ± 10%; for specified performance

5.5 V max VDD 2.7 V min 3 V ± 10%; for specified performance

3.3 V max IDD

Normal Operation 12 mA max 8 mA typical Power-Down 5 A max Logic inputs = 0 V or VDD

0.2 A typ Power Dissipation VDD = 3 V

Normal Operation 36 mW max 24 mW typical Power-Down

200 kSPS 9.58 mW typ 500 kSPS 23.94 mW typ

1

See the Terminology section of this data sheet.

2

Refer to the Analog Input section for an explanation of the analog input(s).

= 200 A

SOURCE

= 200 A

SINK

Rev. C | Page 4 of 28

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TIMING CHARACTERISTICS

V

Table 2.

Parameter

2

t1 420 420 ns max Conversion time t2 20 20 ns min

t3 30 30 ns min t4 110 110 ns max 70 70 ns min t5 10 10 ns max t6 0 0 ns min t7 0 0 ns min t8 30 30 ns min

3

t

9

t

10

20 20 ns max t11 10 10 ns min t12 15 15 ns min

t13 200 200 ns min Minimum time between new channel selection and convert start t

POWER UP

t

POWER UP

1

Sample tested to ensure compliance.

2

See Figure 24, Figure 25, and Figure 26.

3

Measured with the load circuit of Figure 2 and defined as the time required for an output to cross 0.8 V or 2.4 V with VDD = 5 V ± 10%, and time required for an output

to cross 0.4 V or 2.0 V with VDD = 3 V ± 10%.

4

Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back

to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish time of the part and, as such, is independent of external bus loading capacitances.

REF IN/OUT

= 2.5 V. All specifications −40°C to +85°C, unless otherwise noted.

1,

5 V ± 10% 3 V ± 10% Unit Conditions/Comments

10 20 ns max

4

5 5 ns min

25 25 s typ 1 1 s max

Minimum CONVST

pulse width

Minimum time between the rising edge of RD

pulse width

EOC

rising edge to EOC pulse high

RD

to RD setup time

CS

to RD hold time

CS Minimum RD Data access time after RD Bus relinquish time after RD

pulse width

low

high

Address setup time before falling edge of RD Address hold time after falling edge of RD

Power-up time from rising edge of CONVST Power-up time from rising edge of CONVST

and the next falling edge of convert star

using on-chip reference using external 2.5 V reference

TIMING DIAGRAM

200µA I

TO OUTPUT

C

L

50pF

200µA I

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

Rev. C | Page 5 of 28

OL

2.1V

OH

01321-002

AD7822/AD7825/AD7829

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

V

to AGND −0.3 V to +7 V

DD

V

to DGND −0.3 V to +7 V

DD

Analog Input Voltage to AGND

V

to V

IN1

Reference Input Voltage to AGND −0.3 V to V V

Input Voltage to AGND −0.3 V to VDD + 0.3 V

MID

Digital Input Voltage to DGND −0.3 V to V Digital Output Voltage to DGND −0.3 V to V Operating Temperature Range

Industrial (B Version) −40°C to +85°C Storage Temperature Range −65°C to +150°C Junction Temperature 150°C PDIP Package, Power Dissipation 450 mW

θ

JA

Lead Temperature, (Soldering, 10 sec) 260°C SOIC Package, Power Dissipation 450 mW

θ

JA

Lead Temperature, Soldering

TSSOP Package, Power Dissipation 450 mW

θ

JA

Lead Temperature, Soldering

ESD 1 kV

−0.3 V to V

IN8

Thermal Impedance 105°C/W

Thermal Impedance 75°C/W

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

Thermal Impedance 128°C/W

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 6 of 28

AD7822/AD7825/AD7829

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

28 27 26 25 24 23 22 21 20 19 18 17 16 15

DB3 DB4 DB5 DB6 DB7 AGND V

DD

V

REF IN/OUT

V

MID

V

IN1

V

IN2

V

IN3

V

IN4

V

IN5

01321-005

DB2 1 DB1 DB0

CONVST 4

CS 5 RD 6

DGND 7

EOC

PD NC 10

2 3

AD7822

TOP VIEW

(Not to Scale)

8 9

NC = NO CONNECT

17 16

14 13 12 11

DB320 DB419 DB518 DB6 DB7 AGND15 V

DD

V

REF IN/OUT

V

MID

V

IN1

1

DB2

2

DB2

1

DB1

2 3

DB0

CONVST

01321-003

CS RD

DGND

EOC

PD

V

A1 A0

IN4

4

AD7825

5

TOP VIEW

6

(Not to Scale)

7 8

9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

DB3 DB4 DB5 DB6 DB7 AGND V

DD

V

REF IN/OUT

V

MID

V

IN1

V

IN2

V

IN3

1321-004

DB1 DB0

CONVST

DGND

EOC

V V V

CS RD

A2 A1

A0

IN8 IN7 IN6

3 4 5 6 7 8

(Not to S cale)

9 10 11 12 13 14

AD7829

TOP VIEW

Figure 3. Pin Configuration Figure 4. Pin Configuration Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Mnemonic Description

V

to V

IN1

Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight analog input

IN8

channels, respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (V be centered anywhere in the range AGND to V 2 V (V

= 3 V ± 10%) or AGND to 2.5 V (V

DD

using the V

DD

= 5 V ± 10%). See the Analog Input section of the data sheet for more information.

DD

pin. The default input range (V

MID

unconnected) is AGND to

MID

DD

). This span can

VDD Positive Supply Voltage, 3 V ± 10% and 5 V ± 10%. AGND Analog Ground. Ground reference for track-and-hold, comparators, reference circuit, and multiplexer. DGND Digital Ground. Ground reference for digital circuitry. CONVST Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of this signal. The

falling edge of this signal places the track-and-hold in hold mode. The track-and-hold goes into track mode again 120 ns after the start of a conversion. The state of the CONVST

signal is checked at the end of a conversion. If it is logic low, the AD7822/

AD7825/AD7829 powers down (see the Operating Modes section of the data sheet).

EOC Logic Output. The end-of-conversion signal indicates when a conversion has finished. The signal can be used to interrupt

a microcontroller when a conversion has finished or latch data into a gate array (see the Parallel Interface section).

CS Logic Input Signal. The chip select signal is used to enable the parallel port of the AD7822/AD7825/AD7829. This is necessary

if the ADC is sharing a common data bus with another device.

PD Logic Input. The power-down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low places the AD7822 and

AD7825 in power-down mode. The ADCs power up when PD

is brought logic high again.

RD Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and drive data onto

signal. Both RD and CS must be logic low to enable the data bus.

signal

A0 to A2

the data bus. The signal is internally gated with the CS Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the RD

goes low.

DB0 to DB7

Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when both RD

and CS

go active low.

V

REF IN/OUT

Analog Input and Output. An external reference can be connected to the AD7822/AD7825/AD7829 at this pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 μF capacitor.

V

MID

pin, if connected, is used to center the analog input span anywhere in the range of AGND to VDD (see the Analog

The V

MID

Input section).

Rev. C | Page 7 of 28

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TERMINOLOGY

Signal-to-(Noise + Distortion) Ratio

The measured ratio of signal-to-(noise + distortion) at the

utput of the analog-to-digital converter. The signal is the rms

o amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f

/2), excluding dc. The ratio is dependent upon the number of

S

quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by

Signal-to-(No

Thus, for an 8-bit converter, this is 50 dB.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

e AD7822/AD7825/AD7829, it is defined as

th

THD

where V V

sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the AD value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and fb products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, … . Intermodulation terms are those for which neither m nor n is equal to zero. For example, the second-order terms include (fa + fb) and (fa − fb), and the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).

is the rms amplitude of the fundamental and V2, V3,

1

, V5, and V6 are the rms amplitudes of the second through the

4

C output spectrum (up to f

, any active device with nonlinearities creates distortion

ise + Distortion) = (6.02 N + 1.76) dB

22

log20(dB)

=

/2 and excluding dc) to the rms

S

4

V

1

222

++++

VVVVV

6532

The AD7822/AD7825/AD7829 are tested using the CCIF

andard, where two input frequencies near the top end of the

st input bandwidth are used. In this case, the second- and thirdorder terms are of different significance. The second-order terms are usually distanced in frequency from the original sine waves, and the third-order terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in decibels (dB).

Channel-to-Channel Isolation

A measure of the level of crosstalk between channels. It is m

easured by applying a full-scale 20 kHz sine wave signal to one input channel and determining how much that signal is attenuated in each of the other channels. The figure given is the worst case across all four or eight channels of the AD7825 and AD7829, respectively.

Relative Accuracy or Endpoint Nonlinearity

The maximum deviation from a straight line passing through

he endpoints of the ADC transfer function.

t

Differential Nonlinearity

The difference between the measured and the ideal one LSB

ange between any two adjacent codes in the ADC.

ch

Offset Error

The deviation of the 128th code transition (01111111) to (10000000) f

Offset Error Match

The difference in offset error between any two channels.

Zero-Scale Error

The deviation of the first code transition (00000000) to (00000001) f 5 V ± 10%), or V

Full-Scale Error

The deviation of the last code transition (11111110) to (11111111)

om the ideal; that is, V

fr or V

MID

rom the ideal, that is, V

rom the ideal; that is, V

− 1.0 V + 1 LSB (VDD = 3 V ± 10%).

MID

+ 1.25 V − 1 LSB (VDD = 5 V ± 10%),

MID

+ 1.0 V − 1 LSB (VDD = 3 V ± 10%).

.

MID

− 1.25 V + 1 LSB (VDD =

MID

Rev. C | Page 8 of 28

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Gain Error

The deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) f offset error has been adjusted out.

Gain Error Match

The difference in gain error between any two channels.

rom the ideal, that is, V

− 1 LSB, after the

REF

It also applies to situations where a change in the selected input

nnel takes place or where there is a step input change on the

cha input voltage applied to the selected V AD7825/AD7829. It means that the user must wait for the duration of the track-and-hold acquisition time after a channel change/step input change to V conversion, to ensure that the part operates to specification.

IN

input of the AD7822/

IN

before starting another

Track-and-Hold Acquisition Time

The time required for the output of the track-and-hold amplifier to r

each its final value, within ±1/2 LSB, after the point at which the track-and-hold returns to track mode. This happens approximately 120 ns after the falling edge of

CONVST

.

PSR (Power Supply Rejection)

Variations in power supply affect the full-scale transition but

ot the converter linearity. Power supply rejection is the

n maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value.

Rev. C | Page 9 of 28

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CIRCUIT INFORMATION

CIRCUIT DESCRIPTION

The AD7822/AD7825/AD7829 consist of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. These devices use a half-flash conversion technique where one 4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash ADC contains a sampling capacitor followed by 15 comparators that compare the unknown input to a reference ladder to achieve a 4-bit result. This first flash (that is, coarse conversion) provides the four MSBs. For a full 8-bit reading to be realized, a second flash (that is, fine conversion) must be performed to provide the four LSBs. The 8-bit word is then placed on the data output bus.

Figure 6 and Figure 7 show simplified schematics of the ADC.

hen the ADC starts a conversion, the track-and-hold goes

W into hold mode and holds the analog input for 120 ns. This is the acquisition phase, as shown in Figure 6, when Switch 2 is in P

osition A. At the point when the track-and-hold returns to its track mode, this signal is sampled by the sampling capacitor, as Switch 2 moves into Position B. The first flash occurs at this instant and is then followed by the second flash. Typically, the first flash is complete after 100 ns, that is, at 220 ns; and the end of the second flash and, hence, the 8-bit conversion result is available at 330 ns (minimum). The maximum conversion time is 420 ns. As shown in trac

k mode after 120 ns and starts the next acquisition before the end of the current conversion. Figure 10 shows the ADC tra

nsfer function.

REFERENCE

SW2

A

T/H 1

V

IN

HOLD

B

TIMING AND

CONTROL

LOGIC

Figure 8, the track-and-hold returns to

R16

15

R15

SAMPLING

CAPACITOR

R14

R13

Figure 6. ADC Acquisition Phase

14

LOGIC

DECODE

13

1

R1

OUTPUT

REGISTE R

DB7

DB6

DB5

DB4

DB3

OUTPUT

DRIVERS

DB2

DB1

DB0

01321-006

REFERENCE

R16

SW2

A

T/H 1

V

IN

HOLD

SAMPLING

B

CAPACITOR

TIMING AND

CONTROL

LOGIC

R14

R13

R15

15

14

LOGIC

DECODE

13

1

R1

OUTPUT

REGISTER

DB7

DB6

DB5

DB4

DB3

OUTPUT

DRIVERS

DB2

DB1

DB0

Figure 7. ADC Conversion Phase

CONVST

EOC

DB0 TO DB7

120ns

TRACK

CS

RD

HOLD HOLD

t

2

t

1

TRACK

VALID DATA

t

3

Figure 8. Track-and-Hold Timing

TYPICAL CONNECTION DIAGRAM

Figure 9 shows a typical connection diagram for the AD7822/ AD7825/AD7829. The AGND and DGND are connected together at the device for good noise suppression. The parallel interface is implemented using an 8-bit data bus. The end of conversion signal (

EOC

) idles high, the falling edge of

initiates a conversion, and at the end of conversion the falling

EOC

edge of

is used to initiate an interrupt service routine (ISR) on a microprocessor (see the Parallel Interface section for more

details.) V

REF

and V

such as the AD780, and V

are connected to a voltage source

MID

is connected to a voltage source

DD

that can vary from 4.5 V to 5.5 V (see Tabl e 5 in the Analog Input secti

on). When V

is first connected, the AD7822/AD7825/

DD

AD7829 power up in a low current mode, that is, power-down mode, with the default logic level on the

EOC

AD7822 and AD7825 equal to a low. Ensure the not floating when V

is applied, because this can put the

DD

AD7822/AD7825/AD7829 into an unknown state.

CONVST

pin on the

CONVST

line is

01321-007

01321-008

Rev. C | Page 10 of 28

AD7822/AD7825/AD7829

4

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A suggestion is to tie or pull-down resistor. A rising edge on the the AD7829 to fully power up, while a rising edge on the

CONVST

to VDD or DGND through a pull-up

CONVST

pin causes

PD

pin causes the AD7822 and AD7825 to fully power up. For applications where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance (see the

SUPPLY

.5V TO 5.5

1

A0, A1 AD7825/AD7829

2

A2 AD7829

3

PD AD7822/AD7825

4

V

IN2

5

V

IN5

1.25V TO

3.75V INPUT

TO V

IN4

TO V

IN8

10µF 0.1µF

AD7825/AD7829 AD7829

Figure 9. Typical Connection Diagram

Power vs. Throughput section).

2.5V

AD780

V

REF

DB0 TO DB7

CONVST

V

MID

EOC

RD

CS

1

A0

1

A1

2

A2

3

PD

V

IN1

V

IN2

V

IN4(VIN8

AGND

DGND

4

DD

AD7822/ AD7825/

AD7829

5

)

PARALLEL INTERFACE

µC/µP

ADC TRANSFER FUNCTION

The output coding of the AD7822/AD7825/AD7829 is straight binary. The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSBs, and so on). The LSB size = V

/256 (VDD = 5 V) or the LSB size = (0.8 V

REF

3 V). The ideal transfer characteristic for the AD7822/AD7825/ AD7829 is shown in

11111111

10000000

ADC CODE

00000000

(VDD = 5V) V (V

Figure 10.

= 5V)

(V

DD

/256

REF

V

MID

ANALOG INPUT VOLTAG E

= 3V) V

1LSB = V

1LSB

MID

– 1.25V

– 1V

111...110

111...000

000...111

000...010

000...001

DD

Figure 10. Transfer Characteristic

(V

DD

1LSB = 0.8V

V

+ 1.25V – 1LS B

MID

+ 1V – 1LSB

V

MID

= 3V)

REF

/256

)/256 (VDD =

1321-010

01321-009

ANALOG INPUT

The AD7822 has a single input channel, and the AD7825 and AD7829 have four and eight input channels, respectively. Each input channel has an input span of 2.5 V or 2.0 V, depending on the supply voltage (V by an on-chip V is detected when V detected when V a degree of glitch rejection; for example, a glitch from 5.5 V to

2.7 V up to 60 ns wide does not trip the V

The V

pin is used to center this input span anywhere in the

MID

range of AGND to V the default input range is AGND to 2.0 V (V that is, centered about 1.0 V; or AGND to 2.5 V (V 10%), that is, centered about 1.25 V. When using the default input range, the V cases, it can be decoupled to AGND with a 0.1 μF capacitor.

If, however, an external V is from V from V

− 1.0 V to V

MID

− 1.25 V to V

MID

The range of values of V value of V be applied to V V

− 1.25 V when VDD = 5 V ± 10%. Tabl e 5 shows the relevant

DD

ranges of V

. For VDD = 3 V ± 10%, the range of values that can

DD

MID

and the input span for various values of VDD.

MID

Figure 11 illustrates the input signal range available with various val

ues of V

MID

.

Table 5.

V

MID

V

Internal

DD

5.5 1.25 4.25 3.0 to 5.5 1.25 0 to 2.5 V

5.0 1.25 3.75 2.5 to 5.0 1.25 0 to 2.5 V

4.5 1.25 3.25 2.0 to 4.5 1.25 0 to 2.5 V

3.3 1.00 2.3 1.3 to 3.3 1.00 0 to 2.0 V

3.0 1.00 2.0 1.0 to 3.0 1.00 0 to 2.0 V

2.7 1.00 1.7 0.7 to 2.7 1.00 0 to 2.0 V

). This input span is automatically set up

DD

detector circuit. A 5 V operation of the ADCs

DD

exceeds 4.1 V, and a 3 V operation is

DD

falls below 3.8 V. This circuit also possesses

DD

detector.

DD

. If no input voltage is applied to V

DD

= 3 V ± 10%),

DD

pin can be left unconnected, or in some

MID

is applied, the analog input range

MID

+ 1.0 V (VDD = 3 V ± 10%), or

MID

+ 1.25 V (VDD = 5 V ± 10%).

MID

that can be applied depends on the

MID

D = 5 V ±

D

is from 1.0 V to VDD − 1.0 V and from 1.25 V to

V

Ext

MID

Max V

Span

IN

V

Ext

MID

Min V

Span Unit

IN

,

Rev. C | Page 11 of 28

AD7822/AD7825/AD7829

3V

V

www.BDTIC.com/ADI

V

= 5V

DD

5V

4V

3V

V

= 2.5V

MID

2V

V

= N/C (1.25V)

MID

1V

V

= 3V

DD

2V

V

= 1.5V

MID

V

1V

= N/C (1V)

MID

Figure 11. Analog Input Span Variation with V

V

can be used to remove offsets in a system by applying the

MID

offset to the V

pin as shown in Figure 12, or it can be used to

MID

accommodate bipolar signals by applying V circuit before V

, as shown in Figure 13. When V

IN

V

= 3.75V

MID

INPUT SIG NAL RANGE

FOR VARIOUS V

V

= 2V

MID

INPUT SIG NAL RANGE

FOR VARIOUS V

MID

to a level-shifting

is being

MID

1321-011

driven by an external source, the source can be directly tied to the level-shifting circuitry (see Figure 13). However, if the in

ternal V

, that is, the default value, is being used as an

MID

output, it must be buffered before applying it to the levelshifting circuitry because the V

pin has an impedance of

MID

approximately 6 kΩ (see Figure 14).

IN

V

MID

Figure 12. Removing Offsets Using V

V

IN

AD7822/ AD7825/ AD7829

V

MID

V

MID

01321-012

V

0V

V

0

NOTE: Although there is a V reference of 2.5 V can be sourced, or to which an external reference can be applied, this does not provide an option of varying the value of the voltage reference. As stated in the specifications for the AD7822/AD7825/AD7829, the input voltage range at this pin is 2.5 V ± 2%.

Analog Input Structure

Figure 15 shows an equivalent circuit of the analog input structure of the AD7822/AD7825/AD7829. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. Doing so causes these diodes to become forward biased and start conducting current into the substrate. A maximum current of 20 mA can be conducted by these diodes without causing irreversible damage to the part. However, it is worth noting that a small amount of current (1 mA) being conducted into the substrate, due to an overvoltage on an unselected channel, can cause inaccurate conversions on a selected channel.

2.5V

V

REF

V

MID

R4

R3

R2

V

R1

V

IN

2.5V

0V

AD7822/ AD7825/ AD7829

V

IN

Figure 13. Accommodating Bipolar Signals Using External V

EXTERNAL

2.5V

V

REF

V

R4

R3

R2

V

R1

V

MID

0V

MID

AD7822/ AD7825/ AD7829

V

IN

Figure 14. Accommodating Bipolar Signals Using Internal V

pin from which a voltage

REF

MID

01321-013

01321-014

Rev. C | Page 12 of 28

AD7822/AD7825/AD7829

V

www.BDTIC.com/ADI

Capacitor C2 in Figure 15 is typically about 4 pF and can be primarily attributed to pin capacitance. The resistor, R1, is a lumped component made up of the on resistance of several components, including that of the multiplexer and the trackand-hold. This resistor is typically about 310 Ω. Capacitor C1 is the track-and-hold capacitor and has a capacitance of 0.5 pF. Switch 1 is the track-and-hold switch, and Switch 2 is that of the sampling capacitor, as shown in

DD

D1

IN

C2

4pF

Figure 15. Equivalent Analog Input Circuit

310Ω

D2

Figure 6 and Figure 7.

R1

0.5pF

SW1

C1

SW2

A

B

01321-015

When in track phase, Switch 1 is closed and Switch 2 is in Position A. When in hold mode, Switch 1 opens and Switch 2 remains in Position A. The track-and-hold remains in hold mode for 120 ns (see the

hich it returns to track mode and the ADC enters its conversion

w

Circuit Description section), after

phase. At this point, Switch 1 opens and Switch 2 moves to Position B. At the end of the conversion, Switch 2 moves back to Position A.

120ns

TRACK CHx

CONVST

EOC

DB0 TO DB7

A0 TO A2

HOLD CHx

t

2

CS

RD

TRACK CHx

t

1

TRACK CHy

VALID

DATA

ADDRESS CHANNEL y

t

HOLD CHy

t

3

13

Figure 16. Channel Hopping Timing

There is a minimum time delay between the falling edge of RD and the next falling edge of the

CONVST

signal, t13. This is the minimum acquisition time required of the track-and-hold to maintain 8-bit performance.

nce of the AD7825 when channel hopping for various acquisition

a

Figure 17 shows the typical perform-

times. These results are obtained using an external reference and internal V

while channel hopping between V

MID

IN1

and V

IN4

with 0 V on Channel 4 and 0.5 V on Channel 1.

8.5

01321-016

Analog Input Selection

On power-up, the default VIN selection is V to normal operation from power-down, the V

. When returning

IN1

selected is the

IN

same one that was selected prior to initiation of power-down. Tabl e 6 shows the multiplexer address corresponding to each an

alog input from V

IN1

to V

for the AD7825 or AD7829.

IN4(8)

Table 6.

A2 A1 A0 Analog Input Selected

0 0 0 V 0 0 1 V 0 1 0 V 0 1 1 V 1 0 0 V 1 0 1 V 1 1 0 V 1 1 1 V

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

Channel selection on the AD7825 and AD7829 is made without the necessity of a write operation. The address of the next channel to be converted is latched at the start of the current read operation, that is, on the falling edge of

RD

while CS is low, as shown in

Figure 16. This allows for improved throughput rates in “channel

opping” applications.

h

8.0

7.5

7.0

ENOB

6.5

6.0

5.5

5.0 100 50 40 30 20 15

ACQUISITION TIME (ns)

Figure 17. Effective Number of Bits v

s. Acquisition Time for the AD7825

10500 200

01321-017

The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7822/AD7825/AD7829 ideal for subsampling applications. When the AD7825 is converting a 10 MHz input signal at a sampling rate of 2 MSPS, the effective number of bits typically remains above seven, corresponding to a signal-to-noise ratio of 42 dBs, as shown in

Figure 18.

Rev. C | Page 13 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

50

f

= 2MHz

48

46

44

SNR (dB)

42

40

SAMPLE

V

CONVST

V

CONVST

DD

EXTERNAL REFERENCE

t

POWER-UP

1µs

CONVERSI ON

INITIATED HERE

ON-CHIP REFERENCE

t

POWER- UP

25µs

38

Figure 18. SNR vs. Input Frequency on the AD7825

34568

INPUT FREQ UENCY (MHz)

012.01

01321-018

POWER-UP TIMES

The AD7822/AD7825/AD7829 have a 1 μs power-up time when using an external reference and a 25 μs power-up time when using the on-chip reference. When V the AD7822/AD7825/AD7829 are in a low current mode of operation. Ensure that the V

is applied. If there is a glitch on

DD

CONVST

line is not floating when

CONVST

rising, the part attempts to power up before V and can enter an unknown state. To carry out a conversion, the AD7822/AD7825/AD7829 must first be powered up. The AD7829 is powered up by a rising edge on the and a conversion is initiated on the falling edge of Figure 19 shows how to power up the AD7829 when V connected or after the AD7829 has been powered down using

CONVST

the

pin when using either the on-chip reference or an external reference. When using an external reference, the falling edge of

CONVST

may occur before the required power-up time has elapsed; however, the conversion is not initiated on the falling edge of

CONVST

but rather at the moment when the

part has completely powered up, that is, after 1 μs. If the falling

CONVST

edge of

occurs after the required power-up time has elapsed, then it is upon this falling edge that a conversion is initiated. When using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 μs before initiating a conversion; that is, a falling edge on not occur before the required power-up time has elapsed, when V

is first connected or after the AD7829 has been powered

DD

down using the

CONVST

pin, as shown in Figure 19.

is first connected,

DD

while VDD is

has fully settled

DD

CONVST

pin,

CONVST

is first

DD

CONVST

.

must

CONVERSI ON

INITIATED HERE

Figure 19. AD7829 Power-Up Time

Figure 20 shows how to power up the AD7822 or AD7825 when

is first connected or after the ADCs have been powered down,

V

DD

using the

PD

pin or the

CONVST

pin, with either the on-chip reference or an external reference. When the supplies are first connected or after the part has been powered down by the pin, only a rising edge on the

PD

pin causes the part to power up. When the part has been powered down using the pin, a rising edge on either the

PD

pin or the

CONVST

PD

CONVST

pin powers

the part up again.

As with the AD7829, when using an external reference with the AD7822 o

r AD7825, the falling edge of

CONVST

may occur before the required power-up time has elapsed. If this is the case, the conversion is not initiated on the falling edge of

CONVST but rather at the moment when the part has powered up completely, that is, after 1 μs. If the falling edge of

CONVST

occurs after the required power-up time has elapsed, it is upon this falling edge that a conversion is initiated. When using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 μs before initiating a conversion; that is, a falling edge on

CONVST

must not occur before the required power-up time has elapsed, when supplies are first connected to the AD7822 or AD7825, or when the ADCs have been powered down using the

PD

pin or the

CONVST

pin, as

shown in Figure 20.

01321-019

,

Rev. C | Page 14 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

V

CONVST

V

CONVST

DD

PD

DD

PD

t

POWER-UP

EXTERNAL REFERENCE

POWER-UP

1µs

CONVERSION

INITIATED HERE

ON-CHIP REFERENCE

25µs 25µs

CONVERSION

INITIATED HERE

t

POWER- UP

1µs

t

POWER-UP

CONVERSION

INITIATED HERE

CONVERSION

INITIAT ED HERE

Figure 20. AD7822/AD7825 Power-Up Time

POWER VS. THROUGHPUT

Superior power performance can be achieved by using the automatic power-down (Mode 2) at the end of a conversion (see the

Figure 21 shows how the automatic power-down is implemented usin performance for the AD7822/AD7825/AD7829. The duration of the time of the devices (see the Operating Modes section). As the t down state longer and the average power consumption over time drops accordingly.

CONVST

For example, if the AD7822 is operated in a continuous sampling mode, with a throughput rate of 100 kSPS and using an external reference, the power consumption is calculated as follows. The power dissipation during normal operation is 36 mW, V time is 330 ns (@ +25°C), the AD7822 can be said to dissipate 36 mW (maximum) for 1.33 μs during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs and the average power dissipated during each cycle is (1.33/10) × (36 mW) = 4.79 mW. This calculation uses the minimum conversion time, thus giving the best-case power dissipation at this throughput rate. However, the actual power dissipated during each conversion cycle could increase, depending on the actual conversion time (up to a maximum of 420 ns).

Operating Modes section).

CONVST

g the

CONVST

signal to achieve the optimum power

pulse is set to be equal to or less than the power-up

hroughput rate is reduced, the device remains in its power-

t

DD

t

POWER-UP

1µs

CONVERT

330ns

10µs @ 100kSPS

POWER-DOWN

t

CYCLE

Figure 21. Automatic Power-Down

= 3 V. If the power-up time is 1 μs and the conversion

Figure 22 shows the power vs. throughput rate for automatic

power-down.

full

100

10

1

POWER (mW)

0.1

0

50 150 250 350 450

1321-020

Figure 22. AD7822/AD7825/AD7829 Power vs. Throughput

0

–10

–20

–30

–40

(dB)

–50

–60

–70

–80

0

85

28

57

113

142

200 300 400

THROUG HPUT ( kSPS)

227

283

170

198

425

312

368

255

340

396

FREQUENCY (kHz)

453

481

2048 POINT FFT SAMPLING 2MSPS

f

= 200kHz

IN

623

680

510

566

708

765

651

538

595

736

793

0050100

01321-023

821

878

906

963

850

935

991

01321-024

Figure 23. AD7822/AD7825/AD7829 SNR

OPERATING MODES

The AD7822/AD7825/AD7829 have two possible modes of

1321-022

operation, depending on the state of the approximately 100 ns after the end of a conversion, that is, upon the rising edge of the

EOC

pulse.

CONVST

Mode 1 Operation (High Speed Sampling)

When the AD7822/AD7825/AD7829 are operated in Mode 1, they are not powered down between conversions. This mode of operation allows high throughput rates to be achieved.

Figure 24 shows how this optimum throughput rate is achieved

bringing

by is, before the

CONVST

EOC

high before the end of a conversion, that

pulses low. When operating in this mode, a new conversion should not be initiated until 30 ns after the end of a read operation. This allows the track-and-hold to acquire the analog signal to 0.5 LSB accuracy.

pulse

Rev. C | Page 15 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

Mode 2 Operation (Automatic Power-Down)

When the AD7822/AD7825/AD7829 are operated in Mode 2 (see Figure 25), they automatically power down at the end of a co

nversion. The

a conversion and is left logic low until after the

CONVST

signal is brought low to initiate

EOC

goes high, that is, approximately 100 ns after the end of the conversion. The state of the

CONVST

530 ns maximum after AD7825/AD7829 power down as long as

CONVST

EOC

CS

signal is sampled at this point (that is,

CONVST

falling edge), and the AD7822/

CONVST

120ns

TRACK

HOLD

t

2

t

1

is low.

The ADC is powered up again on the rising edge of the CONVST

signal. Superior power performance can be achieved in this mode of operation by powering up the AD7822/AD7825/ AD7829 only to carry out a conversion. The parallel interface of the AD7822/AD7825/AD7829 remains fully operational while the ADCs are powered down. A read may occur while the part is powered down, and, therefore, it does not necessarily need to be placed within the

TRACK

EOC

pulse, as shown in Figure 25.

HOLD

DB0 TO DB7

CONVST

EOC

CS

RD

DB0 TO DB7

RD

t

POWER-UP

Figure 24. Mode 1 Operation

t

1

Figure 25. Mode 2 Operation

VALID

DATA

VALID

DATA

POWER

DOWN

HERE

t

3

01321-025

01321-026

Rev. C | Page 16 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

PARALLEL INTERFACE

The parallel interface of the AD7822/AD7825/AD7829 is eight bits wide. Figure 26 shows a timing diagram illustrating the

perational sequence of the AD7822/AD7825/AD7829 parallel

o interface. The multiplexer address is latched into the AD7822/ AD7825/AD7829 on the falling edge of the chip track-and-hold goes into hold mode on the falling edge of CONVST

, and a conversion is also initiated at this point. When the conversion is complete, the end of conversion line ( pulses low to indicate that new data is available in the output register of the AD7822/AD7825/AD7829. The logic low for a maximum time of 110 ns.

t

CONVST

EOC

CS

RD

DB0 TO DB7

A0 TO A2

2

RD

input. The on-

EOC

)

EOC

pulse stays

t

1

Figure 26. AD7822/AD7825/AD7829 Parallel Port Timing

However, the

RD

of interrupt of a microprocessor. the 8-bit conversion result. It is possible to tie low and use only part is interfaced to a gate array or ASIC, this applied to the AD7825/AD7829 and into the gate array or ASIC. This means

that the gate array or ASIC does not need any conversion status recognition logic, and it also eliminates the logic required in the gate array or ASIC to generate the read signal for the AD7822/ AD7825/AD7829.

t

4

t

6

t

t11t

NEXT CHANNEL ADDRESS

. This

9

12

EOC

pulse can be reset high by a rising edge

EOC

line can be used to drive an edge-triggered

CS

and RD going low accesses

CS

permanently

RD

to access the data. In systems where the

EOC

CS

and RD inputs to latch data out of the AD7822/

t

5

t

7

t

8

VALID DATA

t

3

t

10

t

13

pulse can be

01321-027

Rev. C | Page 17 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

MICROPROCESSOR INTERFACING

The parallel port on the AD7822/AD7825/AD7829 allows the ADCs to be interfaced to a range of many different microcontrollers. This section explains how to interface the AD7822/ AD7825/AD7829 with some of the more common microcontroller parallel interface protocols.

AD7822/AD7825/AD7829 TO 8051

Figure 27 shows a parallel interface between the AD7822/AD7825/

EOC

AD7829 and the 8051 microcontroller. The

signal on the AD7822/AD7825/AD7829 provides an interrupt request to the 8051 when a conversion ends and data is ready. Port 0 of the 8051 can serve as an input or output port; or, as in this case when used together with the address latch enable (ALE) of the 8051, can be used as a bidirectional low order address and data bus. The ALE output of the 8051 is used to latch the low byte of the address during accesses to the device, while the high order address byte is supplied from Port 2. Port 2 latches remain stable when the AD7822/AD7825/ AD7829 are addressed because they do not have to be turned around (set to 1) for data input, as is the case for Port 0.

1

8051

AD0 TO AD7

LATCH

ALE

A8 TO A15

RD

INT

1

ADDITIONAL PINS O MITTED F OR CLARITY.

Figure 27. Interfacing to the 8051

DECODER

DB0 TO DB7

AD7822/ AD7825/ AD7829

CS

RD

EOC

1

AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x

Figure 28 shows a parallel interface between the AD7822/ AD7825/AD7829 and the PIC16C64/PIC16C65/PIC16C74.

EOC

The interrupt request to the microcontroller when a conversion begins. Of the PIC16C6x/PIC16C7x range of microcontrollers, only the PIC16C64/PIC16C65/PIC16C74 can provide the option of a parallel slave port. Port D of the microcontroller operates as an 8-bit wide parallel slave port when Control Bit PSPMODE in the TRISE register is set. Setting PSPMODE enables Port Pin RE0 to be the (chip select) output. For this functionality, the corresponding data direction bits of the TRISE register must be configured as outputs (reset to 0). See the PIC16C6x/PIC16C7x microcontroller user manual.

signal on the AD7822/AD7825/AD7829 provides an

RD

output and RE2 to be the CS

PIC16C6x/7x

PSP0 TO PSP7

1

ADDITIO NAL PINS O MITT ED FOR CL ARITY.

AD7822/AD7825/AD7829 TO ADSP-21xx

Figure 29 shows a parallel interface between the AD7822/ AD7825/AD7829 and the ADSP-21xx series of DSPs. As before,

EOC

the interrupt request to the DSP when a conversion ends.

ADSP-21xx

1

ADDITIO NAL PINS O MITT ED FOR CL ARITY.

01321-028

INTERFACING MULTIPLEXER ADDRESS INPUTS

Figure 30 shows a simplified interfacing scheme between the AD7825/AD7829 and any microprocessor or microcontroller, which facilitates easy channel selection on the ADCs. The multiplexer address is latched on the falling edge of the as outlined in the Parallel Interface section, allowing the use of the three LSBs of the address bus to select the channel address. As shown in a

re address decoded, allowing A0 to A2 to be changed according to

desired channel selection without affecting chip selection.

1

CS

RD

INT

Figure 28. Interfacing to the PIC16C6x/ PIC16C7x

AD7822/ AD7825/ AD7829

DB0 TO DB7

CS

RD

EOC

signal on the AD7822/AD7825/AD7829 provides an

1

D7 TO D0

A13 TO A0

DMS

RD

IRQ

ADDRESS

DECODE

LOGIC

EN

Figure 29. Interfacing to the ADSP-21xx

DB0 TO DB7

AD7822/ AD7825/ AD7829

CS

RD

EOC

RD

signal,

Figure 30, only Address Bit A3 to Address Bit A15

1

01321-029

01321-030

Rev. C | Page 18 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

AD7822 STANDALONE OPERATION

The AD7822, being the single channel device, does not have any multiplexer addressing associated with it and can be controlled with just one signal, that is, the Figure 31, the

RD

and CS pins are both tied to the

A15 TO A3

SYSTEM BUS

CONVST

ADDRESS

DECODE

signal. As shown in

EOC

pin.

A0 A1

A2

AD7825/ AD7829

CS

RD

DB7 TO DB0

Figure 30. AD7825/AD7829 Simplified Microinterfacing Scheme

DB0 TO DB7

A15 TO A3

A2 TO A0

The resulting signal can be used as an interrupt request signal

WR

(IRQ) o

n a DSP, as a

signal to memory, or as a CLK to a latch or ASIC. The timing for this interface, as shown in Figure 31, d

emonstrates how, with the

CONVST

signal alone, a conversion can be initiated, data is latched out, and the operating mode of the AD7822 can be selected.

MICROPROCESSOR READ CYCLE

CS

RD

ADC I/O ADDRESS

MUX ADDRESS

A/D RESULT

MUX ADDRESS

(CHANNEL SELE CTION A0 TO A2)

LATCHED

01321-031

t

1

CONVST

AD7822

DB7 TO DB0

RD

CS

EOC

DSP/

LATCH/ASIC

Figure 31. AD7822 Standalone Operation

CONVST

EOC

CS

RD

DB0 TO DB7 A/D RES ULT

t

4

01321-032

Rev. C | Page 19 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

1.060 (26.92)

1.030 (26.16)

0.980 (24.89)

0.210

(5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

PIN 1

MAX

20

1

0.100 (2.54) BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

11

10

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001-AD

Figure 32. 20-Lead Plastic Dual In-Line Package [PDIP]

Nar

row Body

(N-20)

Dimensions shown in inches and (millimeters)

13.00 (0.5 118)

12.60 (0.4961)

11

10

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

Wide Body

(R

W-20)

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

5

(

0

5

(

0

5

)

.

0

2

9

.

0

9

8

)

1.27 (0.0500)

0.40 (0.0157)

45°

060706-A

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

20

1

0.51 (0.0201)

1.27

(0.0500)

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

0.31 (0.0122)

BSC

COMPLIANT TO JEDEC STANDARDS MS-013-AC

Figure 33. 20-Lead Standard Small Outline Package [SOIC_W]

Dimensions shown in millimeters and (inches)

Rev. C | Page 20 of 28

AD7822/AD7825/AD7829

Y

www.BDTIC.com/ADI

6.60

6.50

6.40

20

1

PIN 1

0.65

BSC

0.15

0.05

COPLANARIT

0.30

0.19

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 34. 20-Lead Thin Shrink S

1.20 MAX

11

4.50

4.40

4.30

10

SEATING PLANE

6.40 BSC

0.20

0.09

mall Outline Package [TSSOP]

8° 0°

0.75

0.60

0.45

(RU-20)

Dimensions shown in millimeters

1.280 (32.51)

1.250 (31.75)

1.230 (31.24)

0.210

(5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

PIN 1

MAX

24

1

0.100 (2.54) BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

13

12

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001-AF

Figure 35. 24-Lead Plastic Dual In-Line Package [PDIP]

Nar

row Body

(N-24-1)

Dimensions shown in inches and (millimeters)

Rev. C | Page 21 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

0.30 (0.0 118)

0.10 (0.0039)

COPLANARIT Y

0.10

CONTROLL ING DIMENS IONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

24

1

1.27 (0.0500) BSC

15.60 (0.6142)

15.20 (0.5984)

13

7.60 (0.2992)

7.40 (0.2913)

12

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

0.33 (0.0130)

0.20 (0.0079)

(

0

.

0

2

9

5

7

5

2

5

0

(

0

.

0

)

45°

9

8

)

1.27 (0.0500)

0.40 (0.0157)

060706-A

0

.

0

.

8° 0°

Figure 36. 24-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(R

W-24)

Dimensions shown in millimeters and (inches)

7.90

7.80

7.70

24

PIN 1

0.65

0.15

0.05

0.10 COPLANARITY

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AD

Figure 37. 24-Lead Thin Shrink S

Dimensions shown in millimeters

13

4.50

4.40

4.30

121

1.20

MAX

SEATING PLANE

6.40 BSC

0.20

0.09

8° 0°

mall Outline Package [TSSOP]

(RU-24)

0.75

0.60

0.45

Rev. C | Page 22 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

28

114

PIN 1

0.250

(6.35)

MAX

0.200 (5.08)

0.115 (2.92)

0.022 (0.56)

0.014 (0.36)

1.565 (39.75)

1.380 (35.05)

15

0.580 (14.73)

0.485 (12.31)

0.625 (15.88)

0.100 (2.54) BSC

0.070 (1.78)

0.030 (0.76)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-011-AB

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.015 (0.38) GAUGE

PLANE

0.600 (15.24)

0.700 (17.78) MAX

0.195 (4.95)

0.125 (3.17)

0.015 (0.38)

0.008 (0.20)

Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]

Wide Body

(N-28-

2)

Dimensions shown in inches and (millimeters)

18.10 (0.7126)

17.70 (0.6969)

0.30 (0.0118)

0.10 (0.0039)

COPLANARIT Y

0.10

28

1

1.27 (0.0500) BSC

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-O FF MIL LIMET ER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

15

7.60 (0.2992)

7.40 (0.2913)

14

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

Figure 39. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(R

W-28)

Dimensions shown in millimeters and (inches)

0 0

.

7

.

2

5

(

0

.

5

(

0

.

9

5

)

0

2

45°

0

9

8

)

1.27 (0.0500)

0.40 (0.0157)

060706-A

Rev. C | Page 23 of 28

AD7822/AD7825/AD7829

C

Y

www.BDTIC.com/ADI

28

PIN 1

0.15

0.05

OPLANARIT

0.10

Figure 40. 28-Lead Thin Shrink S

9.80

9.70

9.60

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

8° 0°

141

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

mall Outline Package [TSSOP]

0.75

0.60

0.45

(RU-28)

Dimensions shown in millimeters

Rev. C | Page 24 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option Linearity Error

AD7822BN −40°C to +85°C 20-Lead PDIP N-20 ±0.75 LSB AD7822BNZ AD7822BR −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB AD7822BR-REEL −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB AD7822BR-REEL7 −40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB AD7822BRZ AD7822BRZ-REEL AD7822BRZ-REEL7 AD7822BRU −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB AD7822BRU-REEL −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB AD7822BRU-REEL7 −40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB AD7822BRUZ AD7822BRUZ-REEL AD7822BRUZ-REEL7 AD7825BN −40°C to +85°C 24-Lead PDIP N-24-1 ±0.75 LSB AD7825BNZ AD7825BR −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB AD7825BR-REEL −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB AD7825BR-REEL7 −40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB AD7825BRZ AD7825BRZ-REEL AD7825BRZ-REEL7 AD7825BRU −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB AD7825BRU-REEL −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB AD7825BRU-REEL7 −40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB AD7825BRUZ AD7825BRUZ-REEL AD7825BRUZ-REEL7 AD7829BN −40°C to +85°C 28-Lead PDIP N-28-2 ±0.75 LSB AD7829BNZ AD7829BR −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB AD7829BR-REEL −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB AD7829BR-REEL7 −40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB AD7829BRZ AD7829BRZ-REEL AD7829BRZ-REEL7 AD7829BRU −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB AD7829BRU-REEL −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB AD7829BRU-REEL7 −40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB AD7829BRUZ AD7829BRUZ-REEL AD7829BRUZ-REEL7

1

Z = Pb-free part.

1

−40°C to +85°C 20-Lead PDIP N-20 ±0.75 LSB

−40°C to +85°C 20-Lead SOIC_W RW-20 ±0.75 LSB

−40°C to +85°C 20-Lead TSSOP RU-20 ±0.75 LSB

−40°C to +85°C 24-Lead PDIP N-24-1 ±0.75 LSB

−40°C to +85°C 24-Lead SOIC_W RW-24 ±0.75 LSB

−40°C to +85°C 24-Lead TSSOP RU-24 ±0.75 LSB

−40°C to +85°C 28-Lead PDIP N-28-2 ±0.75 LSB

−40°C to +85°C 28-Lead SOIC_W RW-28 ±0.75 LSB

−40°C to +85°C 28-Lead TSSOP RU-28 ±0.75 LSB

Rev. C | Page 25 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

NOTES

Rev. C | Page 26 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

NOTES

Rev. C | Page 27 of 28

AD7822/AD7825/AD7829

www.BDTIC.com/ADI

NOTES

Rev. C | Page 28 of 28

ANALOG DEVICES AD7825 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

TIMING DIAGRAM

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TERMINOLOGY

CIRCUIT INFORMATION

CIRCUIT DESCRIPTION

TYPICAL CONNECTION DIAGRAM

ADC TRANSFER FUNCTION

ANALOG INPUT

POWER-UP TIMES

POWER VS. THROUGHPUT

OPERATING MODES

PARALLEL INTERFACE

MICROPROCESSOR INTERFACING

AD7822/AD7825/AD7829 TO 8051

AD7822/AD7825/AD7829 TO PIC16C6x/PIC16C7x

AD7822/AD7825/AD7829 TO ADSP-21xx

INTERFACING MULTIPLEXER ADDRESS INPUTS

AD7822 STANDALONE OPERATION

OUTLINE DIMENSIONS

ORDERING GUIDE