ANALOG DEVICES AD7324 Service Manual

4-Channel, Software-Selectable, True

V

V

V

V

V

V

Bipolar Input, 12-Bit Plus Sign ADC

AD7324

FEATURES FUNCTIONAL BLOCK DIAGRAM

2.5V

VREF

Figure 1.

REFIN/OUT

SUCCESSIVE

APPROXIMATION

CONTROL LO GIC
AND REG ISTER S

DGND

CC

13-BIT

ADC

12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges

±10 V, ±5 V, ±2.5 V, 0 V to +10 V
1 MSPS throughput rate
Four analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential

analog input capability
High analog input impedance
Low power: 21 mW
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
16-lead TSSOP package

™

iCMOS

process technology

IN

IN

IN

IN

AD7324

0

1

2

3

SEQUENCER

I/P

MUX

CHANNEL

AGND V

DD

T/H

SS

DOUT

SCLK

CS

DIN

V

DRIVE

4864-001

GENERAL DESCRIPTION PRODUCT HIGHLIGHTS

The AD73241 is a 4-channel, 12-bit plus sign, successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power
consumption, and reduced package size.

The AD7324 can accept true bipolar analog input signals. The
AD7324 has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7324 can be programmed
to be single-ended, true differential, or pseudo differential.

The ADC contains a 2.5 V internal reference. The AD7324 also
allows for external reference operation. If a 3 V reference is
applied to the REFIN/OUT pin, the AD7324 can accept a true
bipolar ±12 V analog input. Minimum ±12 V V

and VSS

DD

supplies are required for the ±12 V input range. The ADC has a
high speed serial interface that can operate at throughput rates
up to 1 MSPS.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

1. The AD7324 can accept true bipolar analog input signals,

±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.

2. The four analog inputs can be configured as four single-

ended inputs, two true differential input pairs, two pseudo
differential inputs, or three pseudo differential inputs.

3. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™-

compatible interface.

4. Low power, 30 mW maximum, at 1 MSPS throughput rate.

5. Channel sequencer.

Table 1. Similar Products Selection Table

Device
Number

Throughput
Rate

Number of bits

AD7329 250 kSPS 12-bit plus sign 8
AD7328 1000 kSPS 12-bit plus sign 8
AD7327 500 kSPS 12-bit plus sign 8
AD7323 500 kSPS 12-bit plus sign 4
AD7322 1000 kSPS 12-bit plus sign 2
AD7321 500 kSPS 12-bit plus sign 2

1

Protected by U.S. Patent No. 6,731,232.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

Number of
Channels

AD7324

TABLE OF CONTENTS

Features.............................................................................................. 1

Control Register ......................................................................... 23

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 10

Terminology .................................................................................... 14

Theory of Operation ...................................................................... 16

Circuit Information.................................................................... 16

Converter Operation.................................................................. 16

Analog Input Structure.............................................................. 17

Sequence Register....................................................................... 25

Range Register ............................................................................ 25

Sequencer Operation ..................................................................... 26

Reference ..................................................................................... 28

V

............................................................................................ 28

DRIVE

Modes of Operation ....................................................................... 29

Normal Mode.............................................................................. 29

Full Shutdown Mode.................................................................. 29

Autoshutdown Mode ................................................................. 30

Autostandby Mode ..................................................................... 30

Power vs. Throughput Rate....................................................... 31

Serial Interface ................................................................................ 32

Microprocessor Interfacing........................................................... 33

AD7324 to ADSP-218x.............................................................. 33

AD7324 to ADSP-BF53x........................................................... 33

Typical Connection Diagram ................................................... 19

Analog Input............................................................................... 19

Driver Amplifier Choice............................................................ 21

Registers........................................................................................... 22

Addressing Registers.................................................................. 22

REVISION HISTORY

12/05—Revision 0: Initial Version

Application Hints ........................................................................... 34

Layout and Grounding .............................................................. 34

Outline Dimensions....................................................................... 35

Ordering Guide .......................................................................... 35

Rev. 0 | Page 2 of 36

AD7324

SPECIFICATIONS

Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, V
internal/external, f

= 20 MHz, fS = 1 MSPS, TA = T

SCLK

MAX

to T

with VCC < 4.75 V, all specifications are typical.

MIN

Table 2.

B Version
Parameter

DYNAMIC PERFORMANCE F

Signal-to-Noise Ratio (SNR)

1

Min Typ Max Unit Test Conditions/Comments

= 50 kHz sine wave

2

76 dB Differential mode

IN

72.5 dB Single-ended/pseudo differential mode
Signal-to-Noise + Distortion

(SINAD)

2

75 dB Differential mode; ±2.5 V and ±5 V ranges

76 dB Differential mode; 0 V to 10 V and ±10 V ranges
72 dB

Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges

72.5 dB

Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges

Total Harmonic Distortion (THD)2 −80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−77 dB

Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges

−80 dB

Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges

Peak Harmonic or Spurious Noise

2

(SFDR)

−80 dB Differential mode; ±2.5 V and ±5 V ranges

−82 dB Differential mode; 0 V to +10 V and ±10 V ranges

−78 dB

Single-ended/pseudo differential mode; ±2.5 V and ±5 V
ranges

−79 dB

Single-ended/pseudo differential mode; 0 V to +10 V

and ±10 V ranges
Intermodulation Distortion (IMD)2 fa = 50 kHz, fb = 30 kHz
Second-Order Terms −88 dB
Third-Order Terms
Aperture Delay
Aperture Jitter
Common-Mode Rejection Ratio

(CMRR)

2

Channel-to-Channel Isolation
Full Power Bandwidth

3

3

−90 dB
7 ns
50 ps

−79 dB Up to 100 kHz ripple frequency; see Figure 17

2

−72 dB FIN on unselected channels up to 100 kHz; see Figure 14
22 MHz At 3 dB

5 MHz At 0.1 dB

= 2.7 V to 5.25 V, V

DRIVE

= 2.5 V to 3.0 V

REF

Rev. 0 | Page 3 of 36

AD7324

B Version
Parameter

DC ACCURACY

Resolution 13 Bits
No Missing Codes

Integral Nonlinearity

−0.7/+1.2 LSB

Differential Nonlinearity

±0.9 LSB

−0.7/+1 LSB

Offset Error

−7/+10 LSB Differential mode
Offset Error Match
±0.5 LSB Differential mode
Gain Error
±14 LSB Differential mode
Gain Error Match
±0.5 LSB Differential mode
Positive Full-Scale Error
±7 LSB Differential mode
Positive Full-Scale Error Match
±0.5 LSB Differential mode
Bipolar Zero Error
±7.5 LSB Differential mode
Bipolar Zero Error Match
±0.5 LSB Differential mode
Negative Full-Scale Error
±6 LSB Differential mode
Negative Full-Scale Error Match

±0.5 LSB Differential mode

1

4

Min Typ Max Unit Test Conditions/Comments

All dc accuracy specifications are typical for 0 V to
10 V mode.

12-bit

Bits Differential mode

plus sign
11-bit

Bits Single-ended/pseudo differential mode

plus sign

2

±1.1 LSB Differential mode
±1 LSB Single-ended/pseudo differential mode

Single-ended/pseudo differential mode
(LSB = FSR/8192)

2

−0.9/+1.5 LSB

Differential mode; guaranteed no missing codes to
13 bits

Single-ended mode; guaranteed no missing codes to
12 bits

Single-ended/psuedo differential mode
(LSB = FSR/8192)

2, 5

2, 5

2, 5

2, 5

2, 6

2, 6

2, 6

2, 6

−4/+9 LSB Single-ended/pseudo differential mode

±0.6 LSB Single-ended/pseudo differential mode

±8 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

±8.5 LSB Single-ended/pseudo differential mode

±0.5 LSB Single-ended/pseudo differential mode

±4 LSB Single-ended/pseudo differential mode

2, 6

±0.5 LSB Single-ended/pseudo differential mode

Rev. 0 | Page 4 of 36

AD7324

B Version
Parameter

ANALOG INPUT

Input Voltage Ranges Reference = 2.5 V; see Table 6

±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
±2.5 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V
0 to 10 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V

±3.5 V Reference = 2.5 V; range = ±10 V
±6 V Reference = 2.5 V; range = ±5 V
±5 V Reference = 2.5 V; range = ±2.5 V
+3/−5 V Reference = 2.5 V; range = 0 V to +10 V
DC Leakage Current ±80 nA VIN = VDD or VSS
3 nA Per channel, VIN = VDD or VSS
Input Capacitance

16.5 pF When in track, ±5 V and 0 V to +10 V ranges

21.5 pF When in track, ±2.5 V range
3 pF When in hold, all ranges
REFERENCE INPUT/OUTPUT

Input Voltage Range 2.5 3 V
Input DC Leakage Current ±1 μA
Input Capacitance 10 pF
Reference Output Voltage 2.5 V
Reference Output Voltage Error

Reference Output Voltage

Reference Temperature

3 ppm/°C
Reference Output Impedance 7 Ω

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V

0.4 V VCC = 2.7 to 3.6 V
Input Current, IIN ±1 μA V
Input Capacitance, C

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL 0.4 V I
Floating-State Leakage Current ±1 μA
Floating-State Output

Output Coding Straight natural binary Coding bit set to 1 in control register

Twos complement Coding bit set to 0 in control register
CONVERSION RATE

Conversion Time 800 ns 16 SCLK cycles with SCLK = 20 MHz
Track-and-Hold Acquisition

Throughput Rate 1 MSPS See the Serial Interface section; VCC = 4.75 V to 5.25 V

770 kSPS VCC < 4.75 V

1

(Programmed via Range

Register)

Pseudo Differential VIN(−)

Input Range

3

@ 25°C

to T

MAX

T

MIN

Coefficient

INH

0.8 V VCC = 4.75 V to 5.25 V

INL

3

IN

Capacitance

Time

3

2, 3

Min Typ Max Unit Test Conditions/Comments

±10 V V

= 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V

DD

= 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and

V

DD

Figure 41

13.5 pF When in track, ±10 V range

±5 mV

±10 mV

25 ppm/°C

2.4 V

= 0 V or V

IN

10 pF

V

DRIVE

V I

−

SOURCE

= 200 μA

0.2 V
= 200 μA

SINK

5 pF

305 ns Full-scale step input; see the Terminology section

DRIVE

Rev. 0 | Page 5 of 36

AD7324

B Version
Parameter

POWER REQUIREMENTS Digital inputs = 0 V or V

V
VSS −12 −16.5 V See Ta ble 6
VCC 2.7 5.25 V See Table 6; typical specifications for VCC < 4.75 V
V
Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V
Normal Mode (Operational) f

Autostandby Mode (Dynamic) F

Autoshutdown Mode (Static) SCLK on or off

Full Shutdown Mode SCLK on or off

POWER DISSIPATION

Normal Mode (Operational) 30 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
21 mW VDD = 12 V, VSS = −12 V, VCC = 5 V
Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V

1

Temperature range is −40°C to +85°C.

2

See the Terminology section.

3

Sample tested during initial release to ensure compliance.

4

For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless

otherwise noted.

5

Unipolar 0 V to 10 V range with straight binary output coding.

6

Bipolar range with twos complement output coding.

1

12 16.5 V See Table 6

DD

2.7 5.25 V

DRIVE

Min Typ Max Unit Test Conditions/Comments

= 1 MSPS

SAMPLE

IDD 360 μA VDD = 16.5 V
ISS 410 μA VSS = −16.5 V
ICC and I

3.2 mA VCC/V

DRIVE

DRIVE

SAMPLE

= 5.25 V

= 250 kSPS
IDD 200 μA VDD = 16.5 V
ISS 210 μA VSS = −16.5 V
ICC and I

1.3 mA VCC/V

DRIVE

DRIVE

= 5.25 V

IDD 1 μA VDD = 16.5 V
ISS 1 μA VSS = −16.5 V
ICC and I

1 μA VCC/V

DRIVE

DRIVE

= 5.25 V

IDD 1 μA VDD = 16.5 V
ISS 1 μA VSS = −16.5 V
ICC and I

1 μA VCC/V

DRIVE

DRIVE

= 5.25 V

DRIVE

DRIVE

= 5.25 V

Rev. 0 | Page 6 of 36

AD7324

TIMING SPECIFICATIONS

VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V
T

= T

to T

A

MAX

. Timing specifications apply with a 32 pF load, unless otherwise noted.

MIN

Table 3.

Limit at T

MIN

, T

MAX

Description

Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V

f

SCLK

50 50 kHz min
14 20 MHz max
t

CONVER T

t

75 60 ns min

QUIET

t

1

2

t

2

16 × t

16 × t

SCLK

ns max t

SCLK

12 5 ns min

25 20 ns min
45 35 ns min Unipolar input range (0 V to 10 V)

t

3

t

4

t5 0.4 × t
t6 0.4 × t
t

7

t

8

26 14 ns max

57 43 ns max Data access time after SCLK falling edge

SCLK

0.4 × t

SCLK

0.4 × t

SCLK

ns min SCLK high pulse width

SCLK

ns min SCLK low pulse width

13 8 ns min SCLK to data valid hold time

40 22 ns max SCLK falling edge to DOUT high impedance
10 9 ns min SCLK falling edge to DOUT high impedance
t

9

t

10

t

POWER-UP

1

Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

2

When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to

50:50.

4 4 ns min DIN setup time prior to SCLK falling edge

2 2 ns min DIN hold time after SCLK falling edge

750 750 ns max Power up from autostandby

μs max 500 500 Power up from full shutdown/autoshutdown mode, internal reference

25 25 μs typ Power up from full shutdown/autoshutdown mode, external reference

CS

t

CONVERT

t

6

t

7

t

4

t

10

Figure 2. Serial Interface Timing Diagram

SCLK

DOUT

DIN

THREE-

STAT E

t

2

12345 13141516

2 IDENTIFICATION BITS

t

3

ADD1

ZERO

WRITE

ADD0 SIGN DB11 DB10 DB2 DB1 DB0

t

9

REG

REG

SEL1

SEL2

= 2.7 V to 5.25, V

DRIVE

≤ VCC

DRIVE

SCLK

= 1/f

SCLK

= 2.5 V to 3.0 V Internal/External,

REF

1

Minimum time between end of serial read and next falling edge of
Minimum CS pulse width
CS

to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)

Delay from

CS

until DOUT three-state disabled

) and timed from a voltage level of 1.6 V.

DRIVE

t

5

LSBMSB

DON’T

CARE

t

8

THREE-STATE

t

QUIET

t

1

04864-002

CS

Rev. 0 | Page 7 of 36

AD7324

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted

Table 4.

Parameter Rating

VDD to AGND, DGND −0.3 V to +16.5 V
VSS to AGND, DGND +0.3 V to −16.5 V
VDD to VCC V

− 0.3 V to 16.5 V

CC

VCC to AGND, DGND −0.3 V to +7 V
V

to AGND, DGND −0.3 V to + 7 V

DRIVE

AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND VSS −0.3 V to VDD + 0.3 V

1

Digital Input Voltage to DGND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to V

DRIVE

+ 0.3 V
REFIN to AGND −0.3 V to VCC + 0.3 V
Input Current to Any Pin

Except Supplies

2

±10 mA

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package

θJA Thermal Impedance 150.4°C/W
θJC Thermal Impedance 27.6°C/W

Pb-Free Temperature, Soldering

Reflow 260(0)°C

ESD 2.5 kV

1

If the analog inputs are being driven from alternative VDD and VSS supply

circuitry, Schottky diodes should be placed in series with the AD7324’s VDD
and VSS supplies.

2

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 8 of 36

AD7324

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

CS

DIN

DGND

AGND

REFIN/O UT

V

V

IN

V

IN

SS

0

1

1

2

3

TOP VIEW

4

(Not to Scale)

5

6

7

8

AD7324

16

SCLK

15

DGND

14

DOUT

13

V

DRIVE

12

V

CC

11

V

DD

10

VIN2

9

3

V

IN

04864-003

Figure 3. TSSOP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7324 and frames the serial data transfer.

2 DIN

3, 15 DGND

Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the

Reference section).

Digital Ground. Ground reference point for all digital circuitry on the AD7324. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.

4 AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7324. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.

5 REFIN/OUT

Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7324. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin. Alternatively, the internal reference can be disabled and an
external reference applied to this input. On power-up, the external reference mode is the default
condition (see the

Reference section).
6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8, 10, 9 VIN0 to VIN3

Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD1
and ADD0 in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. The config­uration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in
the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a +2.5 V reference voltage is used (see the

Reference section).
11 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
12 VCC

13 V

DRIVE

Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7324.
This supply should be decoupled to AGND.

Specifications apply from VCC = 4.75 V to 5.25 V.

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V
but it should not exceed V

14 DOUT

Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits

by more than 0.3 V.

CC

are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of a leading ZERO bit, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the

16 SCLK

Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the

Serial Interface section).

AD7324. This clock is also used as the clock source for the conversion process.

,

CC

Rev. 0 | Page 9 of 36

AD7324

TYPICAL PERFORMANCE CHARACTERISTICS

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

Figure 4. FFT True Differential Mode

4096 POINT FF T
V

CC=VDRIVE

V

DD,VSS

T

A

INT/EXT 2.5V REFERENCE
±10V RANGE
F

IN

SNR = 77. 30dB
SINAD = 76.85dB
THD = –86 .96dB
SFDR = –88.22dB

= 25°C

= 50kHz

=5V

=±15V

500

04864-004

1.0
VCC=V

0.8

T

= 25°C

A

V

DD,VSS

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

512 1536 2560 3584 4608 5632 6656 7680

=5V

DRIVE

= ±15V

1024 2048 3072 4096 5120 6144 7168

INT/EXT 2.5V REFERENCE
±10V RANGE
+INL = + 0.55LSB
–INL = –0.68LSB

CODE

Figure 7. Typical INL True Differential Mode

04864-007

SNR (dB)

–20

–40

–60

–80

–100

–120

–140

0

0

50 100 150 200 250 300 350 400 450

FREQUENCY (kHz)

4096 POINT FFT
V

CC=VDRIVE

V

DD,VSS

T

A

INT/EXT 2.5V REFERENCE
±10V RANGE
F

IN

SNR = 74. 67dB
SINAD = 74. 03dB
THD = –82. 68dB
SFDR = –85 .40dB

=25°C

= 50kHz

= ±15V

=5V

Figure 5. FFT Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0 8192

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

VCC=V

DRIVE

T

=25°C

A

V

=±15V

DD,VSS

INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0. 22LSB

CODE

=5V

Figure 6. Typical DNL True Differential Mode

500

1.0

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

VCC=V

–0.6

T

A

V

–0.8

DD,VSS

INT/EXT 2.5V REFERENCE

–1.0

08

512 1536 2560 3584 4608 5632 6656 7680

04864-005

=5V

DRIVE

= 25°C

= ±15V

1024 2048 3072 4096 5120 6144 7168

±10V RANGE
+DNL = +0.79LSB
–DNL = –0. 38LSB

CODE

192

04864-043

Figure 8. Typical DNL Single-Ended Mode

1.0

0.8

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

08

1024 2048 3072 4096 5120 6144 7168

512 1536 2560 3584 4608 5632 6656 7680

04864-006

VCC=V

DRIVE

T

= 25°C

A

V

=±15V

DD,VSS

INT/EXT 2.5V REFERENCE
±10V RANGE
+INL = +0.87LSB
–INL = –0.49LSB

CODE

=5V

192

04864-044

Figure 9. Typical INL Single-Ended Mode

Rev. 0 | Page 10 of 36

AD7324

–

–

–

50

VCC=5V
V

DD/VSS

T

=25°C

A

f

=1MSPS

S

= ±12V

±10V SE

0V TO +10V SE

±10V DIFF

100

ANALOG INPUT FREQUENCY (kHz)

0V TO +10V DIFF

±5V SE

±5V DIFF

±2.5V DIFF

±2.5V SE

1000

04864-008

THD (dB)

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

10

Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 5 V V

CC

80

±10V DIFF

75

70

65

SINAD (dB)

60

55

50

10

0V TO + 10V SE

±10V SE

100

ANALOG INPUT FREQUENCY (kHz)

±5V DIFF

0V TO + 10V DIFF

VCC=3V
V
T
f

±2.5V DIFF

±5V SE

DD/VSS

= 25°C

A

=1MSPS

S

±2.5V SE

= ±12V

1000

Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and

Differential Mode (Diff) at 3 V V

CC

04864-011

50

VCC=3V

= ±12V

V

–55

DD/VSS

=25°C

T

A

=1MSPS

f

–60

S

–65

–70

–75

THD (dB)

–80

–85

–90

–95

–100

±10V DIFF

10 1000

0V TO +10V SE

ANALOG INPUT FREQUENCY (kHz)

100

±10V SE

±2.5V DIFF

0V TO +10V DIFF

±5V SE

±2.5V SE

±5V DIFF

04864-009

Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True

Differential Mode (Diff) at 3 V V

80

75

70

65

SINAD (dB)

60

55

50

10 1000

0V TO +10V SE

ANALOG INPUT FREQUENCY (kHz)

±10V DIFF

±10V SE

100

CC

±5V DIFF

±2.5V DIFF

±5V SE

0V TO +10V DIFF

VCC=5V
V

DD/VSS

= 25°C

T

A

=1MSPS

f

S

±2.5V SE

= ±12V

04864-010

Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and

Differential Mode (Diff) at 5 V V

CC

50

–55

–60

–65

–70

–75

–80

–85

–90

CHANNEL-TO-CHANNEL ISOLATION (dB)

–95

100 200 300 400 500

06

FREQUENCY O F INPUT NOISE (kHz)

VCC=3V

VDD/VSS= ±12V
SINGLE- ENDED MODE

= 1MSPS

f

S

T

A

50kHz ON SELECTED CHANNE L

VCC=5V

=25°C

00

04864-012

Figure 14. Channel-to-Channel Isolation

10k

9k

8k

7k

6k

5k

4k

3k

NUMBER OF OCCURRENCES

2k

1k

0

0

–2

228

–1 0 1 2

9469

CODE

VCC=5V

= ±12V

V

DD/VSS

RANGE = ±10V
10k SAMPLES

= 25°C

T

A

303

0

04864-013

Figure 15. Histogram of Codes, True Differential Mode

Rev. 0 | Page 11 of 36