ANALOG DEVICES AD7321 Service Manual
500 kSPS, 2-Channel, Software-Selectable,
V
V
True Bipolar Input, 12-Bit Plus Sign ADC
FEATURES
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
500 kSPS throughput rate
2 analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 18 mW
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
14-lead TSSOP package
iCMOS™ process technology
GENERAL DESCRIPTION
The AD73211 is a 2-channel, 12-bit plus sign successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power consumption,
and reduced package size.
The AD7321 can accept true bipolar analog input signals. The
AD7321 has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel is independently programmed to one of the four input ranges. The analog
input channels on the AD7321 are programmed to be single-ended,
true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7321 also
allows for external reference operation. If a 3 V reference is applied
to the REFIN/OUT pin, the AD7321 can accept a true bipolar
±12 V analog input. A minimum of ±12 V V
are required for the ±12 V input range. The ADC has a high speed
serial interface that can operate at throughput rates up to 500 kSPS.
1
Protected by U.S. Patent No. 6,731,232.
and VSS supplies
DD
AD7321
FUNCTIONAL BLOCK DIAGRAM
2.5V
VREF
Figure 1.
REFIN/OUT
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
AND REGISTERS
DGND
13-BIT
ADC
CC
Number of
Channels
DOUT
SCLK
CS
DIN
V
DRIVE
DD
AD7321
VIN0
VIN1
I/P
MUX
CHANNEL
SEQUENCER
AGND V
T/H
SS
PRODUCT HIGHLIGHTS
1. The AD7321 can accept true bipolar analog input signals,
±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
2. The two analog inputs are configured as two single-ended
inputs, one true differential input pair, or one pseudo
differential input.
3. A 500 kSPS serial interface. SPI®-/QSPI™-/DSP-/
MICROWIRE™-compatible interface.
4. Low power, 18 mW, at a maximum throughput rate of
500 kSPS.
5. Channel sequencer.
Table 1. Similar Devices
Device
Number
AD7329 1000 kSPS 12-bit plus sign 8
AD7328 1000 kSPS 12-bit plus sign 8
AD7327 500 kSPS 12-bit plus sign 8
AD7324 1000 kSPS 12-bit plus sign 4
AD7323 500 kSPS 12-bit plus sign 4
AD7322 1000 kSPS 12-bit plus sign 2
Throughput
Rate Number of bits
5399-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
AD7321
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 7
Absolute Maximum Ratings ............................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information .................................................................... 16
Converter Operation .................................................................. 16
Analog Input Structure .............................................................. 17
Typical Connection Diagram ................................................... 19
Analog Input ............................................................................... 19
Driver Amplifier Choice ............................................................ 21
Registers ........................................................................................... 22
Addressing Registers .................................................................. 22
Control Register ......................................................................... 23
Range Register ............................................................................ 25
Sequencer Operation ..................................................................... 26
Reference ..................................................................................... 27
V
............................................................................................ 27
DRIVE
Modes of Operation ....................................................................... 28
Normal Mode .............................................................................. 28
Full Shutdown Mode .................................................................. 28
Autoshutdown Mode ................................................................. 29
Autostandby Mode ..................................................................... 29
Power vs. Throughput Rate ....................................................... 30
Serial Interface ................................................................................ 31
Microprocessor Interfacing ........................................................... 32
AD7321 to ADSP-21xx .............................................................. 32
AD7321 to ADSP-BF53x ........................................................... 32
Application Hints ........................................................................... 33
Layout and Grounding .............................................................. 33
Power Supply Configuration .................................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
10/09—Rev. 0 to Rev. A
Changes to Table 2 ............................................................................ 4
Changes to Figure 53 ...................................................................... 33
Changes to Power Supply Configuration Section ...................... 33
Changes to Table 16 ........................................................................ 33
Changes to Outline Dimensions ................................................... 34
Changes to Ordering Guide .......................................................... 34
1/06—Revision 0: Initial Version
Rev. A | Page 2 of 36
AD7321
SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V
f
= 10 MHz, fS = 500 kSPS, TA = T
SCLK
MAX
to T
, unless otherwise noted.
MIN
Table 2.
B Version
Parameter
1
Min Typ Max Unit Test Conditions/Comments
DYNAMIC PERFORMANCE F
2
Signal-to-Noise Ratio (SNR)
76 dB Differential mode, VCC = 4.75 V to 5.25 V
75.5 dB Differential mode, VCC < 4.75 V
72.5 dB
72 dB
Signal-to-Noise + Distortion
(SINAD)
2
75 dB Differential mode: ±2.5 V and ±5 V ranges
74 Differential mode: 0 V to 10 V
76 dB Differential mode: ±10 V range
72 dB
72.5 dB
Total Harmonic Distortion
2
(THD)
−80 dB Differential mode: ±2.5 V and ±5 V ranges
−79 dB Differential mode: 0 V to 10 V ranges
−82 dB Differential mode: ±10 V range
−77 dB
−79 dB
−80 dB
Peak Harmonic or Spurious
Noise (SFDR)
2
−81 dB Differential mode: ±2.5 V and ±5 V ranges
−80 dB Differential mode: 0 V to 10 V ranges
−82 dB Differential mode: ±10 V ranges
−78 dB
−80
−79 dB
Intermodulation Distortion
2
(IMD)
fa = 50 kHz, fb = 30 kHz
Second-Order Terms −88 dB
Third-Order Terms
Aperture Delay
Aperture Jitter
Common-Mode Rejection
Channel-to-Channel
(CMRR)
Isolation
2
2
Full Power Bandwidth
3
3
−90 dB
7 ns
50 ps
−79 dB Up to 100 kHz ripple frequency: see Figure 17
−72 dB
22 MHz At 3 dB
5 MHz At 0.1 dB
= 2.7 V to 5.25 V, V
DRIVE
= 2.5 V to 3.0 V internal/external,
REF
= 50 kHz sine wave
IN
Single-ended/pseudo differential mode: ±10 V,
±2.5 V and ±5 V ranges, V
= 4.75 V to 5.25 V
CC
Single-ended/pseudo differential mode: 0 V to
10 V VCC = 4.75 V to 5.25 V and all ranges at VCC <
4.75 V
Single-ended/pseudo differential mode: ±2.5 V
and ±5 V ranges
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
Single-ended/pseudo differential mode:
±5 V range
Single-ended/pseudo differential mode:
±2.5 V range
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
Single-ended/pseudo differential mode:
±5 V range
Single-ended/pseudo differential mode:
±2.5 V range
Single-ended/pseudo differential mode: 0 V to
+10 V and ±10 V ranges
on unselected channels up to 100 kHz: see
F
IN
Figure 14
Rev. A | Page 3 of 36
AD7321
B Version
Parameter
DC ACCURACY
Resolution 13 Bits
No Missing Codes
Integral Nonlinearity
−0.7/+1.2 LSB
Differential Nonlinearity
±0.9 LSB
−0.7/+1 LSB
Differential mode LSB = FSR/8192
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Positive Full-Scale Error
Positive Full-Scale Error
Bipolar Zero Error
Bipolar Zero Error Match
Negative Full-Scale Error
Negative Full-Scale Error
Offset Error
Offset Error Match
Gain Error
Gain Error Match
Positive Full-Scale Error
Positive Full-Scale Error
Bipolar Zero Error
Bipolar Zero Error Match
Negative Full-Scale Error
Negative Full-Scale Error
Match
Match
Match
Match
1
4
Min Typ Max Unit Test Conditions/Comments
Differential mode LSB = FSR/8192
Single-ended/pseudo differential mode
LSB = FSR/4096, unless otherwise noted
12-bit plus
Bits Differential mode
sign (13 bits)
11-bit plus
Bits Single-ended/pseudo differential mode
sign (12 bits)
2
±1.1 LSB
±1 LSB
Differential mode; V
= 2.7 V
V
CC
Single-ended/pseudo differential mode, V
3 V to 5.25 V, typ for V
Single ended/pseudo differential mode
LSB = FSR/8192
2
−0.9/+1.2 LSB
Differential mode; guaranteed no missing
codes to 13 bits
Single-ended mode; guaranteed no missing
codes to 12 bits
Single ended/pseudo differential mode,
LSB = FSR/8192
2, 5
−0.085/+0.122 %FSR Equates to −7/+10 LSBs
2, 5
2, 5
2, 6
2, 6
±0.006 %FSR Equates to ±0.5 LSBs
±0.171 %FSR Equates to ±14 LSBs
2, 5
±0.006 %FSR Equates to ±0.5 LSBs
2, 6
±0.085 %FSR Equates to ±7 LSBs
±0.006 %FSR Equates to ±0.5 LSBs
2, 6
±0.092 %FSR Equates to ±7.5 LSBs
2, 6
±0.006 %FSR Equates to ±0.5 LSBs
2, 6
±0.073 %FSR Equates to ±6 LSBs
±0.006 %FSR Equates to ±0.5 LSBs
Single-ended/pseudo differential mode
LSB = FSR/4096
2, 5
2, 5
2, 5
2, 6
2, 6
2, 5
±0.012 %FSR Equates to ±0.5 LSBs
2, 6
2, 6
±0.208 %FSR Equates to ±8.5LSBs
−0.098/+0.22 %FSR Equates to −4/+9 LSBs
±0.015 %FSR Equates to ±0.6 LSBs
±0.195 %FSR Equates to ±8 LSBs
±0.098 %FSR Equates to ±4 LSBs
±0.012 %FSR Equates to ±0.5 LSBs
2, 6
±0.012 %FSR Equates to ±0.5 LSBs
2, 6
±0.098 %FSR Equates to ±4 LSBs
±0.012 %FSR Equates to ±0.5 LSBs
= 3 V to 5.25 V, typ for
CC
= 2.7 V
CC
=
CC
Rev. A | Page 4 of 36
AD7321
B Version
Parameter
ANALOG INPUT
Input Voltage Ranges Reference = 2.5 V; see Tabl e 6
±5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
±2.5 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
0 to 10 V
±3.5 V Reference = 2.5 V; range = ±10 V
±6 V Reference = 2.5 V; range = ±5 V
±5 V Reference = 2.5 V; range = ±2.5 V
+3/−5 V Reference = 2.5 V; range = 0 V to +10 V
DC Leakage Current ±80 nA VIN = VDD or VSS
3 nA Per input channel, VIN = VDD or VSS
Input Capacitance
16.5 pF When in track, ±5 V and 0 V to +10 V ranges
21.5 pF When in track, ±2.5 V range
3 pF When in hold, all ranges
REFERENCE INPUT/OUTPUT
Input Voltage Range 2.5 3 V
Input DC Leakage Current ±1 μA
Input Capacitance 10 pF
Reference Output Voltage 2.5 V
Reference Output Voltage
Reference Output Voltage
Reference Temperature
3 ppm/°C
Reference Output
LOGIC INPUTS
Input High Voltage, V
Input Low Voltage, V
0.4 V VCC = 2.7 to 3.6 V
Input Current, IIN ±1 μA VIN = 0 V or V
Input Capacitance, C
LOGIC OUTPUTS
Output High Voltage, VOH V
Output Low Voltage, VOL 0.4 V I
Floating-State Leakage
Floating-State Output
Output Coding Straight natural binary Coding bit set to 1 in control register
Twos complement Coding bit set to 0 in control register
1
(Programmed via Range
Register)
Pseudo Differential VIN(−)
Input Range
3
13.5 pF When in track, ±10 V range
Error @ 25°C
to T
MAX
T
MIN
Coefficient
Impedance
2.4 V
INH
0.8 V VCC = 4.75 V to 5.25 V
INL
3
IN
Current
3
Capacitance
Min Typ Max Unit Test Conditions/Comments
±10 V
VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to
5.25 V
= 10 V min, VSS = AGND min, VCC = 2.7 V to
V
DD
5.25 V
VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40
and Figure 41
±5 mV
±10 mV
25 ppm/°C
7 Ω
DRIVE
10 pF
− 0.2 V V I
DRIVE
= 200 μA
SOURCE
= 200 μA
SINK
±1 μA
5 pF
Rev. A | Page 5 of 36
AD7321
B Version
Parameter
CONVERSION RATE
Conversion Time 1.6 μs 16 SCLK cycles with SCLK = 10 MHz
Track-and-Hold Acquisition
Throughput Rate 500 kSPS See the Serial Interface section
POWER REQUIREMENTS Digital inputs = 0 V or V
V
VSS −12 −16.5 V See Table 6
VCC 2.7 5.25 V See Table 6
V
Normal Mode (Static) 0.9 mA VDD/VSS = ±16.5 V, VCC/V
Normal Mode (Operational) f
Autostandby Mode
Autoshutdown Mode (Static) SCLK on or off
Full Shutdown Mode SCLK on or off
POWER DISSIPATION
Normal Mode (Operational) 18 mW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
Full Shutdown Mode 38.25 μW VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
1
Temperature range is −40°C to +85°C.
2
See the Terminology section.
3
Sample tested during initial release to ensure compliance.
4
For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted. FSR is the theoretical difference between the max and min input values.
5
Unipolar 0 V to 10 V range with straight binary output coding.
6
Bipolar range with twos complement output coding.
1
2, 3
Time
12 16.5 V See Table 6
DD
2.7 5.25 V
DRIVE
Min Typ Max Unit Test Conditions/Comments
305 ns Full-scale step input; see the Terminology section
= 500 kSPS
SAMPLE
IDD 180 μA VDD = 16.5 V
ISS 205 μA VSS = −16.5 V
ICC and I
2.2 mA VCC/V
DRIVE
f
DRIVE
= 250 kSPS
SAMPLE
= 5.25 V
(Dynamic)
IDD 100 μA VDD = 16.5 V
ISS 110 μA VSS = −16.5 V
ICC and I
0.75 mA VCC/V
DRIVE
DRIVE
= 5.25 V
IDD 1 μA VDD = 16.5 V
ISS 1 μA VSS = −16.5 V
ICC and I
1 μA VCC/V
DRIVE
DRIVE
= 5.25 V
IDD 1 μA VDD = 16.5 V
ISS 1 μA VSS = −16.5 V
ICC and I
1 μA VCC/V
DRIVE
DRIVE
= 5.25 V
DRIVE
DRIVE
= 5.25 V
Rev. A | Page 6 of 36
AD7321
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, V
T
= T
to T
A
MAX
. Timing specifications apply with a 32 pF load, unless otherwise noted.1
MIN
Table 3.
Limit at T
MIN
, T
MAX
Description
Parameter VCC < 4.75 V VCC = 4.75 V to 5.25 V Unit V
f
SCLK
50 50 kHz min
10 10 MHz max
t
CONVER T
t
75 60 ns min
QUIET
t
1
2
t
2
16 × t
16 × t
SCLK
ns max t
SCLK
12 5 ns min
25 20 ns min
45 35 ns min Unipolar input range (0 V to 10 V)
t
3
t
4
t5 0.4 × t
t6 0.4 × t
t
7
t
8
26 14 ns max
57 43 ns max Data access time after SCLK falling edge
SCLK
0.4 × t
SCLK
0.4 × t
SCLK
ns min SCLK high pulse width
SCLK
ns min SCLK low pulse width
13 8 ns min SCLK to data valid hold time
40 22 ns max SCLK falling edge to DOUT high impedance
10 9 ns min SCLK falling edge to DOUT high impedance
t
9
t
10
t
POWER-UP
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
2
When using the 0 V to 10 V unipolar range, running at 500 kSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50.
4 4 ns min DIN set-up time prior to SCLK falling edge
2 2 ns min DIN hold time after SCLK falling edge
750 750 ns max Power-up from autostandby
500 500 μs max
25 25 μs typ
CS
t
t
6
t
4
CONVERT
t
7
t
10
SCLK
DOUT
DIN
THREE-
STATE
t
2
1 2 3 4 5 13 14 15 16
IDENTIFICATIONBIT
t
3
ZERO
ZERO
WRITE ZERO
ADD0 SIGN DB11 DB10 DB2 DB1 DB0
t
9
REG
SEL
Figure 2. Serial Interface Timing Diagram
= 2.7 V to 5.25 V, V
DRIVE
≤ VCC
DRIVE
SCLK
= 1/f
SCLK
= 2.5 V to 3.0 V internal/external,
REF
Minimum time between end of serial read and next falling edge of
Minimum CS pulse width
CS
to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Delay from CS until DOUT three-state disabled
Power-up from full shutdown/autoshutdown mode, internal
reference
Power-up from full shutdown/autoshutdown mode, external
reference
) and timed from a voltage level of 1.6 V.
DRIVE
t
1
t
5
LSBMSB
DON’T
CARE
t
8
THREE-STATE
t
QUIET
05399-002
CS
Rev. A | Page 7 of 36
AD7321
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to AGND, DGND −0.3 V to +16.5 V
VSS to AGND, DGND +0.3 V to −16.5 V
VDD to VCC V
− 0.3 V to 16.5 V
CC
VCC to AGND, DGND −0.3 V to +7 V
V
to AGND, DGND −0.3 V to +7 V
DRIVE
AGND to DGND −0.3 V to +0.3 V
Analog Input Voltage to AGND
1
VSS − 0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to +7 V
Digital Output Voltage to GND −0.3 V to V
DRIVE
+ 0.3 V
REFIN to AGND −0.3 V to VCC + 0.3 V
Input Current to Any Pin
Except Supplies
2
±10 mA
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP Package
θJA Thermal Impedance 113.5°C/W
θJC Thermal Impedance 30°C/W
Pb-Free Temperature, Soldering
Reflow 260(0)°C
ESD 2.5 kV
1
If the analog inputs are driven from alternative VDD and VSS supply circuitry,
Schottky diodes should be placed in series with the VDD and VSS supplies of
the AD7321. See the Application Hints section.
2
Transient currents of up to 100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 8 of 36
AD7321
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS
DIN
DGND
AGND
REFIN/OUT
V
V
IN
SS
0
1
2
3
AD7321
TOP VIEW
4
(Not to Scale)
5
6
7
14
SCLK
13
DGND
12
DOUT
11
V
DRIVE
V
10
CC
9
V
DD
8
VIN1
05399-003
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7321 and frames the serial data transfer.
2 DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Registers section).
3, 13 DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7321. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
4 AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7321. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
5 REFIN/OUT
Reference Input/Reference Output. The on-chip reference is available on this pin for external use to the
AD7321. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor
should be placed on the reference pin (see the Reference section). Alternatively, the internal reference
is disabled, and an external reference is applied to this input. On power-up, the external reference
mode is the default condition.
6 VSS Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7, 8 VIN0 to VIN1
Analog Input 0 to Analog Input 1. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD0 in
the control register. The inputs are configured as two single-ended inputs, one true differential input
pair, or one pseudo differential input. The configuration of the analog inputs is selected by programming the
mode bits, Bit Mode 1 and Bit Mode 0, in the control register. The input range on each input channel is
controlled by programming the range register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V are
selected on each analog input channel when a +2.5 V reference voltage is used (see the Registers section).
9 VDD Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
10 VCC
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7321.
This supply should be decoupled to AGND.
11 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at V
but it should not exceed V
12 DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
by more than 0.3 V.
CC
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of two ZERO bits, a channel identification bit, the sign bit, and 12 bits of conversion
data. The data is provided MSB first (see the Serial Interface section).
14 SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7321. This clock is also used as the clock source for the conversion process.
,
CC
Rev. A | Page 9 of 36
AD7321
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
VCC=V
DRIVE
T
= 25°C
0.8
A
V
= ±15V
DD,VSS
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 8192
1024 2048 3072 4096 5120 6144 7168
512 1536 2560 3584 4608 5632 6656 7680
INT/EXT 2.5V REFERENCE
=5V
±10V RANGE
+INL = +0.55LSB
–INL = –0.68LSB
CODE
Figure 7. Typical INL True Differential Mode
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
VCC=V
–0.6
T
= 25°C
A
V
–0.8
DD,VSS
INT/EXT 2.5V REFERENCE
–1.0
0 8192
512 1536 2560 3584 4608 5632 6656 7680
=5V
DRIVE
= ±15V
1024 2048 3072 4096 5120 6144 7168
±10V RANGE
+DNL = +0.79LSB
–DNL = –0.38LSB
CODE
Figure 8. Typical DNL Single-Ended Mode
05399-007
05399-043
SNR (dB)
–100
–120
–140
SNR (dB)
–100
–120
–140
–20
–40
–60
–80
–20
–40
–60
–80
0
0
50 100 150 200 250
FREQUENCY (kHz)
4096 POINT FFT
V
CC=VDRIVE
V
DD,VSS
T
A
INT/EXT 2.5V REFERENCE
±10V RANGE
F
IN
SNR = 77.30dB
SINAD = 76.85dB
THD = –86.96dB
SFDR = –88.22dB
= 25°C
= 50kHz
= ±15V
=5V
5399-004
Figure 4. FFT True Differential Mode
0
0
50 100 150 200 250
FREQUENCY (kHz)
4096 POINT FFT
V
CC=VDRIVE
V
DD,VSS
= 25°C
T
A
INT/EXT 2.5VREFERENCE
±10V RANGE
F
IN
SNR = 74.67dB
SINAD = 74.03dB
THD = –82.68dB
SFDR = –85.40dB
= 50kHz
= ±15V
=5V
5399-005
Figure 5. FFT Single-Ended Mode
1.0
0.8
0.6
0.4
0.2
0
–0.2
DNL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 8192
1024 2048 3072 4096 5120 6144 7168
512 1536 2560 3584 4608 5632 6656 7680
VCC=V
DRIVE
T
=25°C
A
V
= ±15V
DD,VSS
INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0.22LSB
CODE
=5V
Figure 6. Typical DNL True Differential Mode
05399-006
Rev. A | Page 10 of 36
1.0
0.8
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
0 8192
1024 2048 3072 4096 5120 6144 7168
512 1536 2560 3584 4608 5632 6656 7680
VCC=V
DRIVE
T
= 25°C
A
V
=±15V
DD,VSS
INT/EXT 2.5V REFERENCE
±10V RANGE
+INL = +0.87LSB
–INL = –0.49LSB
CODE
=5V
Figure 9. Typical INL Single-Ended Mode
05399-044
AD7321
–
–
–
50
VCC=V
V
–55
DD/VSS
T
A
f
= 500kSPS
–60
S
INTERNAL REFERENCE
–65
–70
–75
THD (dB)
–80
–85
–90
–95
–100
10
=3V
DRIVE
=±12V
= 25°C
ANALOG INPUT FREQUENCY (kHz)
0V TO +10V SE
±5V SE
100
±10V SE
±10V DIFF
0V TO +10V DIFF
±5V DIFF
±2.5V DIFF
±2.5V SE
1000
05399-060
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V V
CC
80
75
70
65
SINAD (dB)
60
55
50
10
ANALOG INPUT F RE Q UENCY (kHz)
±5V DIFF
±2.5V DIFF
±10V SE
0V TO +10V SE
VCC=V
V
DD/VSS
T
A
f
= 500kSPS
S
INTERNAL REFERENCE
100
0V TO +10V DIFF
DRIVE
= ±12V
=25°C
±5V SE
±2.5V SE
±10V DIFF
=5V
1000
05399-063
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V V
CC
50
VCC=V
–55
V
DD/VSS
T
A
= 500kSPS
f
–60
S
INTERNAL REFERENCE
–65
–70
–75
THD (dB)
–80
–85
–90
–95
–100
10
=5V
DRIVE
= ±12V
=25°C
ANALOG INPUT F RE Q UENCY (kHz)
100
0V TO +10V SE
±10V SE
±10V DIFF
0V TO +10V DIFF
±5V SE
±5V DIFF
±2.5V SE
±2.5V DIFF
1000
05399-061
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True
±2.5V DIFF
±10V SE
DD/VSS
=25°C
A
= 500kSPS
CC
±5V SE
±2.5V SE
0V TO +10V DIFF
±10V DIFF
=3V
DRIVE
= ±12V
1000
05399-062
Differential Mode (Diff) at 5 V V
80
75
70
65
SINAD (dB)
60
55
50
10
ANALOG INPUT F RE Q UENCY (kHz)
±5V DIFF
0V TO +10V SE
VCC=V
V
T
f
S
INTERNAL REFERENCE
100
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V V
CC
50
–55
–60
–65
–70
–75
–80
–85
–90
CHANNEL-TO- CHANNEL ISOLATION (dB)
–95
0
100 200 300 400 500
VCC=3V
VDD/VSS=±12V
SINGLE-ENDED MODE
= 500kSPS
f
S
T
A
50kHz ON SELECT ED CHANNEL
FREQUENCY OF INPUT NOISE (kHz)
VCC=5V
= 25°C
Figure 14. Channel-to-Channel Isolation
10k
9k
8k
7k
6k
5k
4k
3k
NUMBER OF OCCURRENCES
2k
1k
0
0
–2
228
–1 0 1 2
9469
CODE
VCC=5V
V
RANGE = ±10V
10k SAMPLES
T
303
Figure 15. Histogram of Codes, True Differential Mode
DD/VSS
= 25°C
A
600
05399-012
= ±12V
0
05399-013
Rev. A | Page 11 of 36
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