Analog Devices AD711TQ-883B, AD711SQ-883B, AD711KR-REEL7, AD711KR-REEL, AD711KR Datasheet

Precision, LowCost,

a

FEATURES
Enhanced Replacement for LF411 and TL081
AC PERFORMANCE

Settles to 0.01% in 1.0 s
16 V/s min Slew Rate (AD711J)
3 MHz min Unity Gain Bandwidth (AD711J)

DC PERFORMANCE

0.25 mV max Offset Voltage: (AD711C)
3 V/C max Drift: (AD711C)
200 V/mV min Open-Loop Gain (AD711K)
4 V p-p max Noise, 0.1 Hz to 10 Hz (AD711C)
Available in Plastic Mini-DIP, Plastic SO, Hermetic
Cerdip, and Hermetic Metal Can Packages

MIL-STD-883B Parts Available

Available in Tape and Reel in Accordance with
EIA-481A Standard
Surface Mount (SOIC)
Dual Version: AD712

PRODUCT DESCRIPTION

The AD711 is a high speed, precision monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that use
older precision BiFETs and, in many cases, bipolar op amps.

The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/µs
and a settling time of 1 µs to ±0.01%, the AD711 is ideal as a
buffer for 12-bit D/A and A/D Converters and as a high-speed
integrator. The settling time is unmatched by any similar IC
amplifier.

The combination of excellent noise performance and low input
current also make the AD711 useful for photo diode preamps.
Common-mode rejection of 88 dB and open loop gain of
400 V/mV ensure 12-bit performance even in high-speed unity
gain buffer circuits.

The AD711 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD711J and
AD711K are rated over the commercial temperature range of
0°C to 70°C. The AD711A, AD711B and AD711C are rated
over the industrial temperature range of –40°C to +85°C. The
AD711S and AD711T are rated over the military temperature
range of –40°C to +125°C and are available processed to MIL­STD-883B, Rev. C.

High Speed, BiFET Op Amp

AD711

CONNECTION DIAGRAMS

OFFSET

NULL

INVERTING

INPUT

NON

INVERTING

INPUT

NOTE
PIN 4 CONNECTED TO CASE

NONINVERTING

Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS
screening includes 168 hour burn-in, as well as other environ­mental and physical tests.

The AD711 is available in an 8-pin plastic mini-DIP, small
outline, cerdip, TO-99 metal can, or in chip form.

PRODUCT HIGHLIGHTS

1. The AD711 offers excellent overall performance at very
competitive prices.

2. Analog Devices’ advanced processing technology and 100%
testing guarantee a low input offset voltage (0.25 mV max,
C grade, 2 mV max, J grade). Input offset voltage is specified
in the warmed-up condition. Analog Devices’ laser wafer
drift trimming process reduces input offset voltage drifts to
3 µV/°C

max on the AD711C.

3. Along with precision dc performance, the AD711 offers
excellent dynamic response. It settles to ±0.01% in 1 µs and
has a 100% tested minimum slew rate of 16 V/µs. Thus this
device is ideal for applications such as DAC and ADC
buffers which require a combination of superior ac and dc
performance.

4. The AD711 has a guaranteed and tested maximum voltage
noise of 4 µV p-p, 0.1 to 10 Hz (AD711C).

5. Analog Devices’ well-matched, ion-implanted JFETs ensure
a guaranteed input bias current (at either input) of 25 pA
max (AD711C) and an input offset current of 10 pA max
(AD711C). Both input bias current and input offset current
are guaranteed in the warmed-up condition.

NC

AD711

–V

S

NC = NO CONNECT

OFFSET

1

NULL

INVERTING

2

INPUT

3

INPUT

–V

4

S

NC = NO CONNECT

+V

S

OUTPUT

OFFSET
NULL

AD711

10k

VOS TRIM

8

NC

+V

7

S

6

OUTPUT
OFFSET

5

NULL

–15V

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

AD711–SPECIFICATIONS

(VS = 15 V @ TA = 25C, unless otherwise noted.)

J/A/S K/B/T C

Parameter Min Typ Max Min Typ Max Min Typ Max Unit

INPUT OFFSET VOLTAGE

1

Initial Offset 0.3 2/1/1 0.2 0.5 0.10 0.25 mV

T

MIN

to T

MAX

3/2/2 1.0 0.45 mV

vs. Temp 7 20/20/20 5 10 2 5 µV/°C
vs. Supply 76 95 80 100 86 110 dB

T

MIN

to T

MAX

76/76/76 80 86 dB

Long-Term Stability 15 15 15 µV/Month

INPUT BIAS CURRENT

2

VCM = 0 V 15 50 15 50 15 25 pA
V

= 0 V @ T

CM

MAX

1.1/3.2/51 1.1/3.2/51 1.6 nA

VCM = ±10 V 20 100 20 100 20 50 pA

INPUT OFFSET CURRENT

V

= 0 V 10 25 5 25 5 10 pA

CM

VCM = 0 V @ T

MAX

0.6/1.6/26 0.6/1.6/26 0.65 nA

FREQUENCY RESPONSE

Small Signal Bandwidth 3.0 4.0 3.4 4.0 3.4 4.0 MHz
Full Power Response 200 200 200 kHz
Slew Rate 16 20 18 20 18 20 V/µs
Settling Time to 0.01% 1.0 1.2 1.0 1.2 1.0 1.2 µs
Total Harmonic Distortion 0.0003 0.0003 0.0003 %

INPUT IMPEDANCE

Differential 3 × 10

12

储5.5 3 × 1012储5.5 3 × 1012储5.5 Ω储pF

Common Mode 3 × 1012储5.5 3 × 1012储5.5 3 × 1012储5.5 Ω储pF

INPUT VOLTAGE RANGE

Differential
Common-Mode Voltage

3

T

to T

MIN

MAX

4

–VS + 4 +VS – 2 –VS + 4 +VS – 2 –VS + 4 +V – 2 V

±20 ±20 ±20 V
+14.5, –11.5 +14.5, –11.5 +14.5, –11.5

Common-Mode
Rejection Ratio

V

= ±10 V 76 88 8088 8694 dB

CM

T

to T

MIN

V

CM

T

MAX

= ±11 V 70 84 7684 7690 dB

to T

MIN

MAX

76/76/76 84 80 84 86 90 dB

70/70/70 80 74 80 74 84 dB

INPUT VOLTAGE NOISE 2 2 2 4 µV p-p

45 45 45 nV/√Hz
22 22 22 nV/√Hz
18 18 18 nV/√Hz
16 16 16 nV/√Hz

INPUT CURRENT NOISE 0.01 0.01 0.01 pA/√Hz

OPEN-LOOP GAIN 150 400 200 400 200 400 V/mV

100/100/100 100 100 V/mV

OUTPUT
CHARACTERISTICS

Voltage +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 +13, –12.5 +13.9, –13.3 V

±12/±12/±12 +13.8, –13.1 ± 12 +13.8, –13.1 ±12 +13.8, –13.1 V

Current 25 25 25 mA

POWER SUPPLY

Rated Performance ±15 ±15 ±15 V
Operating Range ± 4.5 ±18 ±4.5 ± 18 ± 4.5 ±18 V
Quiescent Current 2.5 3.4 2.5 3.0 2.5 2.8 mA

NOTES

1

Input Offset Voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.

2

Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.

3

Defined as voltage between inputs, such that neither exceeds ± 10 V from ground.

4

Typically exceeding –14.1 V negative common-mode voltage on either input results in an output phase reversal.

Specifications subject to change without notice.

–2–

REV. B

AD711

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

Internal Power Dissipation
Input Voltage

3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V

2

. . . . . . . . . . . . . . . . . . . . . 500 mW

1

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +V

and –V

S

S

Storage Temperature Range (Q, H) . . . . . . . –65°C to +150°C

Storage Temperature Range (N) . . . . . . . . . . –65°C to +125°C

Operating Temperature Range

AD711J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD711A/B/C . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C

AD711S/T . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

NOTES

1

Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

2

Thermal Characteristics:

8-Pin Plastic Package: θJC = 33°C/Watt; θJA = 100°C/Watt
8-Pin Cerdip Package: θJC = 22°C/Watt; θJA = 110°C/Watt
8-Pin Metal Can Package: θJC = 65°C/Watt; θJA = 150°C/Watt

3

For supply voltages less than ± 18 V, the absolute maximum input voltage is equal

to the supply voltage.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option*

*AD711AH –40°C to +85°C 8-Pin Metal Can H-08A
AD711AQ –40°C to +85°C 8-Pin Ceramic DIP Q-8

*AD711BQ –40°C to +85°C 8-Pin Ceramic DIP Q-8
*AD711CH –40°C to +85°C 8-Pin Metal Can H-08A

AD711JN 0°C to 70°C 8-Pin Plastic DIP N-8
AD711JR 0°C to 70°C 8-Pin Plastic SOIC R-8
AD711JR-REEL 0°C to 70°C 8-Pin Plastic SOIC R-8
AD711JR-REEL7 0°C to 70°C 8-Pin Plastic SOIC R-8
AD711KN 0°C to 70°C 8-Pin Plastic DIP N-8
AD711KR 0°C to 70°C 8-Pin Plastic SOIC R-8
AD711KR-REEL 0°C to 70°C 8-Pin Plastic SOIC R-8
AD711KR-REEL7 0°C to 70°C 8-Pin Plastic SOIC R-8

*AD711SQ/883B –55°C to +125°C 8-Pin Ceramic DIP Q-8
*AD711TQ/883B –55°C to +125°C 8-Pin Ceramic DIP Q-8

*Not for new design, obsolete April 2002

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD711 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. B

–3–

AD711–Typical Performance Characteristics

20

15

10

= 2k

R

L

25C

5

INPUT VOLTAGE SWING – Volts

0

05

SUPPLY VOLTAGE – Volts

10

15 20

TPC 1. Input Voltage Swing vs.
Supply Voltage

2.75

2.50

2.25

20

15

10

5

OUTPUT VOLTAGE SWING – Volts

0

05

SUPPLY VOLTAGE – Volts

+V

OUT

= 2k

R

L

25C

–V

OUT

10

15 20

TPC 2. Output Voltage Swing vs.
Supply Voltage

–6

10

–7

10

= 0) – Amps

–8

10

CM

–9

10

30

25

20

15V SUPPLIES

15

10

5

OUTPUT VOLTAGE SWING – Volts p-p

0

10

100 1k 10k

LOAD RESISTANCE – 

TPC 3. Output Voltage Swing vs.
Load Resistance

100

A

= 1

VCL

10

1

2.00

QUIESCENT CURRENT – mA

1.75
05

SUPPLY VOLTAGE – Volts

10 15 20

TPC 4. Quiescent Current vs. Sup­ply Voltage

100

VS = 15V
25C

75

50

MAX J GRADE LIMIT

25

INPUT BIAS CURRENT – pA

0

–10

–50 510

COMMON MODE VOLTAGE – Volts

–10

10

–11

10

INPUT BIAS CURRENT (V

–12

10

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE – C

TPC 5. Input Bias Current vs. Tem­perature

26

24

22

20

18

–OUTPUT CURRENT

16

14

12

SHORT CIRCUIT CURRENT LIMIT – mA

10

–60

–40 –20 0 20 40 60 80 100 120 140

AMBIENT TEMPERATURE – C

+OUTPUT CURRENT

0.01

OUTPUT IMPEDANCE – 

0.01
1k

10k 100k 1M 10M

FREQUENCY – Hz

TPC 6. Output Impedance vs. Fre­quency

5.0

4.5

4.0

3.5

UNITY GAIN BANDWIDTHT – MHz

3.0

–60

–40 –20 0 20 40 60 80 100 120 140

TEMPERATURE – C

TPC 7. Input Bias Current vs. Com­mon Mode Voltage

TPC 8. Short Circuit Current Limit
vs. Temperature

–4–

TPC 9. Unity Gain Bandwidth vs.
Temperature

REV. B

AD711

100

PHASE

OPEN LOOP GAIN – dB

80

60

GAIN

100 1k 10k 100k 1M

FREQUENCY – Hz

–20

40

20

0

10

RL = 2k

C = 100pF

TPC 10. Open-Loop Gain and
Phase Margin vs. Frequency

100

80

60

CMR – dB

40

0

1020100

1k 10k 100k 1M

FREQUENCY – Hz

VS = 15V

= 1V p-p

V

CM

C

25

10M

100

80

60

40

20

0

–20

PHASE MARGIN – Degrees

125

R

= 2k

L

25C

120

115

110

105

OPEN-LOOP GAIN – dB

100

95

0

5101520

SUPPLY VOLTAGE – Volts

TPC 11. Open-Loop Gain vs.
Supply Voltage

30

25

20

15

10

OUTPUT VOLTAGE – Volts p-p

5

0

INPUT FREQUENCY – Hz

1M

RL = 2k

C

25

= 15V

V

S

110

100

80

–SUPPLY

60

40

VS = 15 SUPPLIES

20

WITH 1V p-p SINE

POWER SUPPLY REJECTION – dB

0

C

WAVE 25

10

SUPPLY MODULATION FREQUENCY – Hz

+SUPPLY

100 1k 10k 10k1

TPC 12. Power Supply Rejection
vs. Frequency

2

8

6

4

2

0

–2

–4

–6

OUTPUT SWING FRIM 0V TO Volts

–8

10M100k

–10

0.5

1% 0.1% 0.01%

ERROR 1% 0.1% 0.01%

0.6

0.7

SETTLING TIME – s

0.8

0.9

1.0

TPC 13. Common Mode Rejection
vs. Frequency

–70

3V RMS
R

100

= 2k

L

C

= 100pF

L

1k 10k 100k

FREQUENCY – Hz

–80

–90

–100

THD – dB

–110

–120

–130

TPC 16. Total Harmonic Distor­tion vs. Frequency

TPC 14. Large Signal Frequency
Response

1k

100

INPUT NOISE VOLTAGE – nV/ Hz

1

11010

100 1k 10k 100k

FREQUENCY – Hz

TPC 17. Input Noise Voltage
Spectral Density

TPC 15. Output Swing and Error
vs. Settling Time

25

20

15

10

SLEW RATE – Vs

5

0

0

100 200 300 400

INPUT ERROR SIGNAL – mV

(AT SUMMING JUNCTION)

500 600 700 800 900

TPC 18. Slew Rate vs. Input
Error Signal

REV. B

–5–

AD711

+V

S

–V

S

0.1F

AD711

10k

0.1F

1.3Mk

+V

S

–V

S

0.1F

AD711

10k

0.1F

25

24

23

22

21

20

19

18

SLEW RATE – V/s

17

16

15

–60 –40 –20 0 20 40 60 80 100 120 140

TEMPERATURE – C

INPUT

+V

AD711

–V

S

S

0.1F

0.1F

2k

OUTPUT

100pF

TPC 19. Slew Rate vs. Temperature

+V

S

0.1F

V

IN

SQUARE WAVE

INPUT

AD711

–V

S

0.1F
2k

R

L

V

C

L

100pF

OUT

TPC 22a. Unity Gain Follower

5k

+V

S

0.1F

5k

V

IN

SQUARE WAVE

INPUT

AD711

–V

0.1F

S

2k

R

L

V

C

L

100pF

OUT

TPC 23a. Unity Gain Inverter

TPC 20. T.H.D. Test Circuit

TPC 22b. Unity Gain Follower
Pulse Response (Large Signal)

TPC 23b. Unity Gain Inverter
Pulse Response (Large Signal)

TPC 21. Offset Null Configurations

TPC 22c. Unity Gain Follower
Pulse Response (Small Signal)

TPC 23c. Unity Gain Inverter Pulse
Response (Small Signal)

–6–

REV. B

AD711

OPTIMIZING SETTLING TIME

Most bipolar high-speed D/A converters have current outputs;
therefore, for most applications, an external op amp is required
for current-to-voltage conversion. The settling time of the
converter/op amp combination depends on the settling time of
the DAC and output amplifier. A good approximation is:

tSTotal = (tSDAC )2+(tSAMP )

2

(1)

The settling time of an op amp DAC buffer will vary with the
noise gain of the circuit, the DAC output capacitance, and with
the amount of external compensation capacitance across the
DAC output scaling resistor.

Settling time for a bipolar DAC is typically 100 ns to 500 ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a
high-speed voltage-output D-to-A function. The introduction
of the AD711/712 family of op amps with their 1 µs (to ± 0.01%
of final value) settling time now permits the full high-speed
capabilities of most modern DACs to be realized.

GAIN

ADJUST

R2
100

REF

IN

REF

GND

0.1F

REF
OUT

10V

19.95k

20k

V

CC

0.5mA

AD565A

I

REF

BIPOLAR
OFFSET ADJUST

R1

100

DAC

I

OUT

I

REF

BIPOLAR

9.95k

= 4 

 CODE

OFF

In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD711 family assures 12-bit accuracy over the full
operating temperature range.

The excellent high-speed performance of the AD711 is shown
in the oscilloscope photos of Figure 2. Measurements were taken
using a low input capacitance amplifier connected directly to the
summing junction of the AD711 – both photos show the worst
case situation: a full-scale input transition. The DAC’s 4 kΩ
[10 kΩ储8 kΩ = 4.4 kΩ] output impedance together with a 10 kΩ
feedback resistor produce an op amp noise gain of 3.25. The
current output from the DAC produces a 10 V step at the op
amp output (0 to –10 V Figure 2a, –10 V to 0 V Figure 2b.)

Therefore, with an ideal op amp, settling to ±1/2 LSB (±0.01%)
requires that 375 µV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD711 summing junction) must
be less than 375 µV. As shown in Figure 2, the total settling time
for the AD711/AD565 combination is 1.2 microseconds.

20V
SPAN

10V
SPAN

DAC
OUT

10pF

+15V

AD711K

0.1F

0.1F

OUTPUT

–10V TO +10V

5k

5k

I

5k

O

–V

POWER

EE

0.1F

GND

Figure 1.±10 V Voltage Output Bipolar DAC

a. (Full-Scale Negative Transition)

Figure 2. Settling Characteristics for AD711 with AD565A

MSB

LSB

–15V

b. (Full-Scale Positive Transition)

REV. B

–7–

AD711

OP AMP SETTLING TIME—A MATHEMATICAL MODEL

The design of the AD711 gives careful attention to optimizing
individual circuit components; in addition, a careful tradeoff was

op amp is being simulated or it is the combined capacitance of
the DAC output and the op amp input if the DAC buffer is
being modeled.

made: the gain bandwidth product (4 MHz) and slew rate
(20 V/µs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction in
phase margin (and therefore stability). Thus designed, the AD711
settles to ±0.01%, with a 10 V output step, in under 1 µs, while
retaining the ability to drive a 100 pF load capacitance when
operating as a unity gain follower.

If an op amp is modeled as an ideal integrator with a unity gain
crossover frequency of ωο/2π, Equation 1 will accurately describe
the small signal behavior of the circuit of Figure 3a, consisting of
an op amp connected as an I-to-V converter at the output of a
bipolar or CMOS DAC. This equation would completely describe
the output of the system if not for the op amp’s finite slew rate
and other nonlinear effects.

In either case, the capacitance CX causes the system to go from
a one-pole to a two-pole response; this additional pole increases

V

O

=

R(C

I

IN

where:

ω

ο

=op amp’s unity gain frequency

2

π

G

= “noise” gain of circuit

N

= CX)

f

ω

ο

–R

s2+

+ RC

R

R

O



s +1



f










G

N



ω



ο



1 +




settling time by introducing peaking or ringing in the op amp
output. Since the value of C

(3)

accuracy, Equation 2 can be used to choose a small capacitor,
C
Figure 4 is a graphical solution of Equation 2 for the AD711
with R = 4 kΩ.

This equation may then be solved for Cf:

Cf=

2 − G

Rω

2 RC

N

+

ο

In these equations, capacitor C

+(1 −GN)

Xωο

Rω

ο

is the total capacitor appearing

X

(3)

the inverting terminal of the op amp. When modeling a DAC
buffer application, the Norton equivalent circuit of Figure 3a
can be used directly; capacitance C

is the total capacitance of

X

the output of the DAC plus the input capacitance of the op amp
(since the two are in parallel).

AD711

C

F

R

IN

V

IN

C

X

R

R

L

V

OUT

C

L

Figure 3b. Simplified Model of the AD711
Used as an Inverter

can be estimated with reasonable

X

, to cancel the input pole and optimize amplifier response.

F

60

GN = 4.0

50

40

X

30

C

20

10

0

0

GN = 3.0

GN = 2.0

GN = 1.0

20 30 40 50 60

10

C

F

GN = 1.5

AD711

C

F

R

I

O

C

R

X

O

R

L

V

OUT

C

L

Figure 3a. Simplified Model of the AD711 Used as a
Current-Out DAC Buffer

When RO and IO are replaced with their Thevenin VIN and R

IN

equivalents, the general purpose inverting amplifier of Figure 26b
is created. Note that when using this general model, capacitance
CX is either the input capacitance of the op amp if a simple inverting

–8–

Figure 4. Value of Capacitor CF vs. Value of C

X

The photos of Figures 5a and 5b show the dynamic response of
the AD711 in the settling test circuit of Figure 6.

The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.

REV. B

Figure 5a. Settling Characteristics 0 to +10 V Step

1

8

7

6

5

4

3

2

6

5

7

8

2

3

1

4

Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)

Figure 5b. Settling Characteristics 0 to –10 V Step
Upper Trace: Output of AD711 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)

GUARDING

The low input bias current (15 pA) and low noise characteristics
of the AD711 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere

AD711

current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 7, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the printed
circuit board.

Figure 7. Board Layout for Guarding Inputs

D/A CONVERTER APPLICATIONS

The AD711 is an excellent output amplifier for CMOS DACs.
It can be used to perform both 2-quadrant and 4-quadrant
operation. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, 3R
for codes containing a single 1, and for codes containing all
zero, the output impedance is infinite.

For example, the output resistance of the AD7545 will modu­late between 11 kΩ and 33 kΩ. Therefore, with the DAC’s
internal feedback resistance of 11 kΩ, the noise gain will vary
from 2 to 4/3. This changing noise gain modulates the effect of
the input offset voltage of the amplifier, resulting in nonlinear
DAC amplifier performance.

The AD711K with guaranteed 500 µV offset voltage minimizes
this effect to achieve 12-bit performance.

5pF

V

205

0.47F

1.1k

10pF

–9–

–15V

AD3554

V

OUT

0.47F

+15V

10k

0.2-0.0pF

HP2835

4.99k 4.99k

DATA

DYNAMICS

5109

(OR
EQUIVALENT
FLAT TOP
PULSE
GENERATOR)

REV. B

V

IN

200k

5-18pF

10k

10k

0.1F

–15V

AD711

0.1F

+15V

5k

Figure 6. Settling Time Test Circuit

ERROR

HP2835

 5

INPUT SELECTION

TEXTRONIX 7A26

OSCILLOSCOPE

PREAMP

1M

20pF

AD711

Figures 8 and 9 show the AD711 and AD7545 (12-bit CMOS
DAC) configured for unipolar binary (2-quadrant multiplication)
or bipolar (4-quadrant multiplication) operation. Capacitor C1
provides phase compensation to reduce overshoot and ringing.

*

R2

+15

AD711K

–15

0.1F

0.1F

V

OUT

C

F

GAIN

ADJUST

V

IN

*

FOR VALUES R1 AND R2,
REFER TO TABLE 1

R1

*

DB11-DB0

V

V

DD

V

DD

REF

DGND AGND

R

OUT1

FB

AD7545

C1

33pF

ANALOG

COMMON

Figure 8. Unipolar Binary Operation

R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are shown below.

Table I. Recommended Trim Resistor Values vs. Grades
of the AD7545 for V

DD

= 5 V

TRIM
RESISTOR JN/AQ/SD KN/BQ/TD LN/CQ/UD GLN/GCQ/GUD

R1 500 Ω 200 Ω 100 Ω 20 Ω
R2 150 Ω 68 Ω 33 Ω 6.8 Ω

compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred millivolts
resulting in high frequency modulation of A/D input current.

Figures 10a and 10b show the settling time characteristics of the
AD711 when used as a DAC output buffer for the AD7545.

a. Full-Scale Positive b. Full-Scale Negative
Transition Transition

Figure 10. Settling Characteristics for AD711 with AD7545

compared to a series of switched trial currents. The comparison
point is diode clamped but may deviate several hundred milli­volts resulting in high frequency modulation of A/D input
current. The output impedance of a feedback amplifier is made
artificially low by the loop gain. At high frequencies, where the
loop gain is low, the amplifier output impedance can approach
its open loop value. Most IC amplifiers exhibit a minimum open
loop output impedance of 25 Ω due to current limiting resistors.
A few hundred microamps reflected from the change in con­verter loading can introduce errors in instantaneous input

NOISE CHARACTERISTICS

The random nature of noise, particularly in the 1/f region, makes
it difficult to specify in practical terms. At the same time,
designers of precision instrumentation require certain guaranteed
maximum noise levels to realize the full accuracy of their equipment.

The AD711C grade is specified at a maximum level of 4.0 µV p-p,
in a 0.1 Hz to 10 Hz bandwidth. Each AD711C receives a 100%
noise test for two 10-second intervals; devices with any excursion
in excess of 4.0 µV are rejected. The screened lot is then submitted
to Quality Control for verification on an AQL basis.

All other grades of the AD711 are sample-tested on an AQL
basis to a limit of 6 µV p-p, 0.1 to 10 Hz.

ANALOG

DRIVING THE ANALOG INPUT OF AN A/D CONVERTER

An op amp driving the analog input of an A/D converter, such
as that shown in Figure 11, must be capable of maintaining a
constant output voltage under dynamically changing load conditions.
In successive-approximation converters, the input current is

*

GAIN

ADJUST

V

IN

*

FOR VALUES R1 AND R2,
REFER TO TABLE 1

*

R1

V

V

V

REF

DGND

DD

DD

AD7545

R

FB

OUT1

AGND

DB11-DB0

12

DATA INPUT

R2

+15V

C1
33pF

ANALOG
COMMON

0.1F

AD711K

0.1F

–15V

Figure 9. Bipolar Operation

–10–

12/8

CS

A

O

AD574

R/C

CE

REF IN

R2

REF OUT

R1

BIP OFF

10V

IN

20V

IN

ANA COM

10V

INPUT

+15V

AD711

–15V

0.1F

0.1F

GAIN

ADJUST

100

100

OFFSET
ADJUST

ANALOG COM

Figure 11. AD711 as ADC Unity Gain Buffer

20k

1%

R3

10k

1%

R4

R5

20k

1%

+15V

AD711K

–15V

0.1F

0.1F

V

OUT

STS

HIGH

BITS

MIDDLE

BITS

LOW
BITS

+5V

+15V

–15V

DIG COM

REV. B

AD711

voltage. If the A/D conversion speed is not excessive and the
bandwidth of the amplifier is sufficient, the amplifier’s output
will return to the nominal value before the converter makes its
comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD711 is ideally suited to drive high speed A/D converters since
it offers both wide bandwidth and high open-loop gain.

a. Source Current = 2 mA b. Sink Current = 1 mA

Figure 12. ADC Input Unity Gain Buffer Recovery Times

DRIVING A LARGE CAPACITIVE LOAD

The circuit in Figure 13 employs a 100 Ω isolation resistor which
enables the amplifier to drive capacitive loads exceeding 1500 pF;
the resistor effectively isolates the high frequency feedback from
the load and stabilizes the circuit. Low frequency feedback is
returned to the amplifier summing junction via the low pass
filter formed by the 100 Ω series resistor and the load capaci­tance, C

. Figure 14 shows a typical transient response for

L

this connection.

4.99k

30pF

+V

S

0.1F

INPUT

4.99k

TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS

R

L

2k 1500pF
10k 1500pF
20k 1000pF

CL UP TO

AD711

–V

S

0.1F

100

C

OUTPUT

R

L

L

Figure 13. Circuit for Driving a Large Capacitive Load

large value input resistors, bias currents flowing through these
resistors will also generate an offset voltage.

In addition, at higher frequencies, an op amp’s dynamics must
be carefully considered. Here, slew rate, bandwidth, and open-loop
gain play a major role in op amp selection. The slew rate must
be fast as well as symmetrical to minimize distortion. The amplifier’s
bandwidth in conjunction with the filter’s gain will dictate the
frequency response of the filter.

The use of a high performance amplifier such a s the AD711
will minimize both dc and ac errors in all active filter applica­tions.

SECOND ORDER LOW PASS FILTER

Figure 15 depicts the AD711 configured as a second order
Butterworth low pass filter. With the values as shown, the corner
frequency will be 20 kHz; however, the wide bandwidth of the
AD711 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are shown below.

R1 = R2 = user selected (typical values: 10 kΩ – 100 kΩ) (4)

C1=

(2 π)( f

1.414

cutoff

)(R1)

, C 2 =

(2 π)( f

0.707

cutoff

)(R1)

(5)

Where:

C1 and C2 are in farads.

C1

560pF

+15V

V

20k

IN

R2

R1

20k

C2

280pF

AD711

–15V

0.1F

0.1F

V

OUT

Figure 15. Second Order Low Pass Filter

An important property of filters is their out-of-band rejection.
The simple 20 kHz low pass filter shown in Figure 15, might be
used to condition a signal contaminated with clock pulses or
sampling glitches which have considerable energy content at
high frequencies.

The low output impedance and high bandwidth of the AD711
minimize high frequency feedthrough as shown in Figure 16.

The upper trace is that of another low-cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.

Figure 14. Transient Response RL = 2 kΩ, CL = 500 pF

ACTIVE FILTER APPLICATIONS

In active filter applications using op amps, the dc accuracy of the
amplifier is critical to optimal filter performance. The amplifier’s
offset voltage and bias current contribute to output error. Offset
voltage will be passed by the filter and may be amplified to produce
excessive output offset. For low frequency applications requiring

REV. B

–11–

Figure 16.

AD711

9-POLE CHEBYCHEV FILTER

Figure 17 shows the AD711 and its dual counterpart, the AD712,
as a 9-pole Chebychev filter using active frequency dependent
negative resistors (FDNR). With a cutoff frequency of 50 kHz
and better than 90 dB rejection, it may be used as an anti-aliasing
filter for a 12-bit data acquisition system with 100 kHz throughput.

As shown in Figure 17, the filter is comprised of four FDNRs (A,
B, C, D) having values of 4.9395 ⫻ 10

–15

10

farad-seconds. Each FDNR active network provides a

+15V

0.1F

V

IN

A1

AD711

–15V

*

SEE TEXT

0.1F

–15

and 5.9276 ⫻

0.001F
2800 6190 6490 6190

100k

4.9395E

–15

A

*

5.9276E

–15

B

*

5.9276E

–15

C

*

Figure 17. 9-Pole Chebychev Filter

+15V

0.1F

2-pole response; for a total of 8 poles. The 9th pole consists of a

0.001 µF capacitor and a 124 kΩ resistor at Pin 3 of amplifier A2.
Figure 18 depicts the circuits for each FDNR with the proper
selection of R. To achieve optimal performance, the 0.001 µF
capacitors must be selected for 1% or better matching and all
resistors should have 1% or better tolerance.

+15V

0.1F

2800

4.9395E

–15

D

*

0.001
F

124k

A2

AD711

–15V

0.1F

4.99k

4.99k

V

OUT

0.001F

1/2

AD712

R

1/2

AD712

R: 24.9k FOR 4.9395E

29.4k FOR 5.9276E

–15

–15

0.001F

1k

4.99k

0.1F

–15V

Figure 18. FDNR for 9-Pole Chebychev Filter

Figure 19. High Frequency Response for 9-Pole
Chebychev Filter

–12–

REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

AD711

PIN 1

0.175(4.44)

0.165(4.19)

0.155(3.94)

0.125 (3.18)
MIN

0.023(0.54)

0.018(0.46)

0.015(0.38)

Mini-DIP Package (N-8)

8

5

0.033 (0.84)
NOM

0.25 (6.35)

0.045(1.14)

0.035(0.89)

0.025(0.64)

14

0.39 (9.91)
MAX

0.100
(2.54)

TYP

0.21(5.33)

0.18(4.57)

0.15(3.81)

SEATING
PLANE

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

0.300 (7.62)
REF

0.15

PIN 1

0.012 (0.278)

0.008 (0.203)

0.004 (0.128)

0.014(0.36)

0.011(0.28)

0.008(0.20)

Small Outline Package (R-8)

0.201 (5.00)

0.193 (4.90)

0.175 (4.80)

85

0.0500 (1.27)

SEATING

PLANE

41

BSC

0.020 (0.49)

0.017 (0.42)

0.014 (0.35)

0.248 (6.20)

0.236 (6.00)

0.224 (5.80)

0.104 (2.72)

0.098 (2.49)

0.092 (2.26)

0.013 (0.300)

0.011 (0.269)

0.009 (0.238)

PIN 1

0.200 (5.08)
MAX

0.200 (5.08)

0.125 (3.18)

Cerdip Package (Q-8)

0.005 (0.13)

0.023 (0.58)

0.014 (0.36)

0.050 (1.26)

0.033 (0.83)

0.016 (0.40)

0.055 (1.35)

1

MAX

4

0.070 (1.78)

0.030 (0.76)

MIN

85

0.100 (2.54) BSC

0.405 (10.29) MAX

0.310 (7.87)

0.220 (5.59)

0.060 (1.52)

0.015 (0.38)

0.150
(3.81)
MIN

SEATING
PLANE

0.320 (8.13)

0.290 (7.37)

15°

0°

0.015 (0.38)

0.008 (0.20)

REV. B

SEATING

PLANE

INSULATION

0.05 (1.27)
MAX

8 LEADS

0.019 (0.48)

0.016 (0.41)

0.040
(1.00)

MAX

DIA

0.370 (9.40)

0.335 (8.51)

0.335 (8.51)

0.305 (7.75)

TO-99 Package (H-8)

0.185 (4.70)

0.165 (4.19)

REFERENCE
PLANE

0.500 (12.70)
MIN

–13–

0.200
(5.1)
TYP

5

4

3

2

6

8

1

0.034 (0.86)

0.028 (0.71)

0.045 (1.14)

0.020 (0.51)

7

BOTTOM

45° EQUALLY

SPACED

VIEW

AD711

Revision History

Location Page

Data Sheet changed from REV. A to REV. B.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

–14–

REV. B

–15–

C00832–0–1/02(B)

–16–

PRINTED IN U.S.A.