+
–
+
–
+
–
+
–
+
–
50
50
10k
10k
10k
10k
V
B
–INPUT
–GAIN
SENSE
+INPUT
–GAIN
DRIVE
+GAIN
SENSE
+GAIN
DRIVE
SENSE
OUTPUT
REFERENCE
AD625
Programmable Gain
a
FEATURES
User Programmed Gains of 1 to 10,000
Low Gain Error: 0.02% Max
Low Gain TC: 5 ppm/C Max
Low Nonlinearity: 0.001% Max
Low Offset Voltage: 25 V
Low Noise 4 nV/√Hz (at 1 kHz) RTI
Gain Bandwidth Product: 25 MHz
16-Lead Ceramic or Plastic DIP Package,
20-Terminal LCC Package
Standard Military Drawing Available
MlL-Standard Parts Available
Low Cost
PRODUCT DESCRIPTION
The AD625 is a precision instrumentation amplifier specifically
designed to fulfill two major areas of application: 1) Circuits requiring nonstandard gains (i.e., gains not easily achievable with
devices such as the AD524 and AD624). 2) Circuits requiring a
low cost, precision software programmable gain amplifier.
For low noise, high CMRR, and low drift the AD625JN is the
most cost effective instrumentation amplifier solution available.
An additional three resistors allow the user to set any gain from
1 to 10,000. The error contribution of the AD625JN is less than
0.05% gain error and under 5 ppm/°C gain TC; performance
limitations are primarily determined by the external resistors.
Common-mode rejection is independent of the feedback resistor
matching.
A software programmable gain amplifier (SPGA) can be configured with the addition of a CMOS multiplexer (or other switch
network), and a suitable resistor network. Because the ON
resistance of the switches is removed from the signal path, an
AD625 based SPGA will deliver 12-bit precision, and can be
programmed for any set of gains between 1 and 10,000, with
completely user selected gain steps.
For the highest precision the AD625C offers an input offset
voltage drift of less than 0.25 µV/°C, output offset drift below
15 µV/°C, and a maximum nonlinearity of 0.001% at G = 1. All
grades exhibit excellent ac performance; a 25 MHz gain bandwidth product, 5 V/µs slew rate and 15 µs settling time.
The AD625 is available in three accuracy grades (A, B, C) for
industrial (–40°C to +85°C) temperature range, two grades (J,
K) for commercial (0°C to +70°C) temperature range, and one
(S) grade rated over the extended (–55°C to +125°C) temperature range.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Instrumentation Amplifier
AD625
FUNCTIONAL BLOCK DIAGRAM
PRODUCT HIGHLIGHTS
1. The AD625 affords up to 16-bit precision for user selected
fixed gains from 1 to 10,000. Any gain in this range can be
programmed by 3 external resistors.
2. A 12-bit software programmable gain amplifier can be configured using the AD625, a CMOS multiplexer and a resistor
network. Unlike previous instrumentation amplifier designs,
the ON resistance of a CMOS switch does not affect the gain
accuracy.
3. The gain accuracy and gain temperature coefficient of the
amplifier circuit are primarily dependent on the user selected
external resistors.
4. The AD625 provides totally independent input and output
offset nulling terminals for high precision applications. This
minimizes the effects of offset voltage in gain-ranging
applications.
5. The proprietary design of the AD625 provides input voltage
noise of 4 nV/√Hz at 1 kHz.
6. External resistor matching is not required to maintain high
common-mode rejection.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
AD625–SPECIFICATIONS
AD625A/J/S AD625B/K AD625C
Model Min Typ Max Min Typ Max Min Typ Max Unit
GAIN
Gain Equation
Gain Range 1 10,000 1 10,000 1 110,000
Gain Error
Nonlinearity, Gain = 1-256 ±0.005 ± 0.002 ±0.001 %
Gain vs. Temp. Gain<1000
GAIN SENSE INPUT
Gain Sense Current 300 500 150 250 50 100 nA
vs. Temperature 5 20 2 15 2 10 nA/°C
Gain Sense Offset Current 150 500 75 250 50 100 nA
vs. Temperature 2 15 1 10 2 10 nA/°C
VOLTAGE OFFSET (May be Nulled)
Input Offset Voltage 50 200 25 50 10 25 µV
vs. Temperature 1 2/2 0.25 0.50/1 0.1 0.25 µV/°C
Output Offset Voltage 4 5 2 3 1 2 mV
vs. Temperature 20 50/50 10 25/40 10 15 µV/°C
Offset Referred to the
Input vs. Supply
INPUT CURRENT
Input Bias Current ±30
vs. Temperature ±50 ±50 ± 50 pA/°C
Input Offset Current ±2
vs. Temperature ±20 ±20 ± 20 pA/°C
INPUT
Input Impedance
Differential Resistance 1 1 1 GΩ
Differential Capacitance 4 4 4 pF
Common-Mode Resistance 1 1 1 GΩ
Common-Mode Capacitance 4 4 4 pF
Input Voltage Range
Differ. Input Linear (V
Common-Mode Linear (V
Common-Mode Rejection Ratio dc to
60 Hz with 1 kΩ Source Imbalance
OUTPUT RATING ± 10 V ±10 V ±10 V
DYNAMIC RESPONSE
Small Signal –3 dB
G = 1 (RF = 20 kΩ) 650 650 650 kHz
G = 10 400 400 400 kHz
G = 100 150 150 150 kHz
G = 1000 25 25 25 kHz
Slew Rate 5.0 5.0 5.0 V/µs
Settling Time to 0.01%, 20 V Step
G = 1 to 200 15 15 15 µs
G = 500 35 35 35 µs
G = 1000 75 75 75 µs
1
Gain>256 ±0.01 ±0.008 ±0.005 %
G = 1 70 75 75 85 80 90 dB
G = 10 85 95 90 100 95 105 dB
G = 100 95 100 105 110 110 120 dB
G = 1000 100 110 110 120 115 140 dB
G = 1 70 75 75 85 80 90 dB
G = 10 90 95 90 105 100 115 dB
G = 100 100 105 105 115 110 125 dB
G = 1000 110 115 110 125 120 140 dB
1
2
)
DL
)
CM
12 V –
(typical @ VS = 15 V, RL = 2 k and TA = + 25C, unless otherwise noted)
2 R
F
+ 1
R
G
±.0350.05 ±0.02
5 5 5 ppm/°C
50 ±20
35 ±1
±10 ±10 ± 10 V
G
×V
D
(
2
@ 5 mA @ 5 mA @ 5 mA
)
12 V –
2 R
F
+ 1
R
G
0.03 ±0.01
25 ±10
15 ±1
G
×V
D
(
)
2
12 V –
2 R
F
+ 1
R
G
G
×V
D
(
2
0.02 %
15 nA
5 nA
)
–2–
REV. D
AD625
AD625A/J/S AD625B/K AD625C
Model Min Typ Max Min Typ Max Min Typ Max Unit
NOISE
Voltage Noise, 1 kHz
R.T.I. 4 4 4 nV/√Hz
R.T.O. 75 75 75 nV/√Hz
R.T.I., 0.1 Hz to 10 Hz
G = 1 10 10 10 µV p-p
G = 10 1.0 1.0 1.0 µV p-p
G = 100 0.3 0.3 0.3 µV p-p
G = 1000 0.2 0.2 0.2 µV p-p
Current Noise
0.1 Hz to 10 Hz 60 60 60 pA p-p
SENSE INPUT
R
IN
I
IN
Voltage Range ± 10 ±10 ± 10 V
Gain to Output 1 ± 0.01 1 ± 0.01 1 ± 0.01 %
REFERENCE INPUT
R
IN
I
IN
Voltage Range ± 10 ±10 ± 10 V
Gain to Output 1 ± 0.01 1 ± 0.01 1 ± 0.01 %
TEMPERATURE RANGE
Specified Performance
J/K Grades 0 +70 0 +70 °C
A/B/C Grades –40 +85 –40 +85 –40 +85 °C
S Grade –55 +125 °C
Storage –65 +150 –65 +150 –65 +150 °C
POWER SUPPLY
Power Supply Range ±6 to ± 18 ±6 to ±18 ± 6 to ± 18 V
Quiescent Current 3.5 5 3.5 5 3.5 5 mA
NOTES
1
Gain Error and Gain TC are for the AD625 only. Resistor Network errors will add to the specified errors.
2
VDL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at other gains = 10 V/G. VD = actual differential input voltage.
Example: G = 10, VD = 0.50; VCM = 12 V – (10/2 × 0.50 V) = 9.5 V.
Specifications subject to change without notice.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are
used to calculate outgoing quality levels.
10 10 10 kΩ
30 30 30 µA
20 20 20 kΩ
30 30 30 µA
REV. D
–3–
AD625
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 450 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range (D, E) . . . . . . . . –65°C to +150°C
Storage Temperature Range (N) . . . . . . . . . . –65°C to +125°C
Operating Temperature Range
AD625J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD625A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
S
S
AD625S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD625AD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD625BD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD625BD/+ –40°C to +85°C 16-Lead Ceramic DIP D-16
AD625CD –40°C to +85°C 16-Lead Ceramic DIP D-16
AD625SD –55°C to +125°C 16-Lead Ceramic DIP D-16
AD625SD/883B –55°C to +125°C 16-Lead Ceramic DIP D-16
AD625SE/883B –55°C to +125°C 20-Terminal Leadless Chip Carrier E-20A
AD625JN 0°C to +70°C 16-Lead Plastic DIP N-16
AD625KN 0°C to +70°C 16-Lead Plastic DIP N-16
AD625ACHIPS –40°C to +85°CDie
AD625SCHIPS –55°C to +125°CDie
5962-87719012A* –55°C to +125°C 20-Terminal Leadless Chip Carrier E-20A
5962-8771901EA* –55°C to +125°C 16-Lead Ceramic DIP D-16
*Standard Military Drawing Available
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD625 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONNECTIONS
Ceramic DIP (D) and Plastic DIP (N) Packages
1
+INPUT –INPUT
+GAIN SENSE –GAIN SENSE
RTI NULL RTO NULL
S
RTI NULL RTO NULL
+GAIN DRIVE
REFERENCE V
2
3
10k 10k+V
–V
AD625
4
TOP VIEW
5
(Not to Scale)
NC SENSE
6
7
8
S
NC = NO CONNECT
16
15
14
13
–GAIN DRIVE
12
11
10
OUT
+V
9
S
–V
S
Leadless Chip Carrier (E) Package
+INPUT
+GAIN SENSE
4
RTI NULL
5
RTI NULL
NC
+GAIN DRIVE
NC
6
(Not to Scale)
7
8
910111213
AD625
TOP VIEW
–V
S
NC
NC
20 19123
–INPUT
–GAIN SENSE
S
OUT
+V
V
18
RTO NULL
17
RTO NULL
16
NC
15
–GAIN NULL
14
SENSE
REFERENCE
NC = NO CONNECT
REV. D–4–
Typical Performance Characteristics–A
D625
20
15
10
25C
5
INPUT VOLTAGE RANGE – V
0
0
5101520
SUPPLY VOLTAGE – V
Figure 1. Input Voltage Range vs.
Supply Voltage, G = 1
–160
–140
G = 1000
G = 100
–120
G = 10
–100
G = 1
–80
CMRR – dM
–60
–40
–20
0
0
10 100 1k 10k 100k 10M
FREQUENCY – Hz
Figure 4. CMRR vs. Frequency
RTI, Zero to 1 k
Ω
Source Imbal-
ance
20
15
10
5
OUTPUT VOLTAGE SWING – V
0
0
5101520
SUPPLY VOLTAGE – V
Figure 2. Output Voltage Swing
vs. Supply Voltage
30
G = 1, 100
20
BANDWIDTH
LIMITED
G = 100
10
FULL POWER RESPONSE – V p-p
0
G = 500
G = 1000
1k
10k 100k 1M
FREQUENCY – Hz
Figure 5. Large Signal Frequency
Response
30
20
10
OUTPUT VOLTAGE SWING – V p-p
0
10
100 1k 10k
LOAD RESISTANCE –
Figure 3. Output Voltage Swing
vs. Load Resistance
1000
100
GAIN
10
1
1k 10k 100k 1M 10M
100
FREQUENCY – Hz
Figure 6. Gain vs. Frequency
–1
0
1
2
3
4
FROM FINAL VALUE – V
5
OS
V
6
7
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
WARM-UP TIME – Minutes
Figure 7. Offset Voltage, RTI, Turn
On Drift
REV. D
160
–VS = –15V dc+
1V p-p SINEWAVE
FREQUENCY – Hz
POWER SUPPLY REJECTION – dB
140
120
100
80
60
40
20
0
10
G = 500
G = 100
G = 1
100 1k 10k 100k
Figure 8. Negative PSRR vs.
Frequency
–5–
160
140
G = 500
120
G = 100
100
G = 1
80
60
40
20
POWER SUPPLY REJECTION – dB
0
10
100 1k 10k 100k
1V p-p SINEWAVE
FREQUENCY – Hz
Figure 9. Positive PSRR vs.
Frequency
+VS = +15V dc+
AD625
40
30
20
10
0
–10
INPUT CURRENT – nA
–20
–30
–40
–125
–75 –25 25 75 125
TEMPERATURE – C
Figure 10. Input Bias Current vs.
Temperature
+V
S
V
10V
AD625
–V
S
Figure 11. Overrange and Gain
Switching Test Circuit (G = 8, G = 1)
OUT
Figure 12. Gain Overrange Recovery
8.0
6.0
4.0
2.0
AMPLIFIER QUIESCENT CURRENT – A
0
0
5101520
SUPPLY VOLTAGE – V
Figure 13. Quiescent Current vs.
Supply Voltage
1000
100
10
VOLT NSD – nV/ Hz
1
0.1
10 100 1k 10k 100k
1
G = 1
G = 10
G = 100, 1000
FREQUENCY – Hz
Figure 14. RTI Noise Spectral
Density vs. Gain
+V
S
–V
S
AD625
DUT
1F
G = 1, 10, 100
100
+V
S
1/2
AD712
9.09k
G = 1000
1k
16.2k
1F
1/2
–V
1.62M
G = 1000
AD712
1F
S
1.82k
16.2k
100k
10k
1k
100
10
1
CURRENT NOISE SPECTRAL DENSITY – fA/ Hz
10 100 1k 10k 100k
FREQUENCY – Hz
Figure 15. Input Current Noise
Figure 16. Low Frequency Voltage
Noise, G = 1 (System Gain = 1000)
Figure 17. Noise Test Circuit
Figure 18. Low Frequency Voltage
Noise, G = 1000 (System
Gain = 100,000)
REV. D–6–
–12 TO 12
–8 TO 8
–4 TO 4
OUTPUT
STEP – V
G = 1
AD625
G = 1000
G = 100
Figure 19. Large Signal Pulse
Response and Settling Time, G = 1
Figure 22. Large Signal Pulse
Response and Settling Time, G = 10
4 TO –4
8 TO –8
12 TO –12
G = 1
0
G = 100
G = 1000
10 20 30 40 50 60 70
SETTLING TIME – S
Figure 20. Settling Time to 0.01%
INPUT
20V p-p
1k
0.1%
100k
500
0.1%
0.1%
200
0.1%
10k1%1k
+V
AD625
–V
10k
10T
1%
S
S
V
Figure 23. Settling Time Test Circuit
Figure 21. Large Signal Pulse
Response and Settling Time, G = 100
OUT
Figure 24. Large Signal Pulse
Response and Settling Time,
G = 1000
REV. D
–7–
AD625
S
THEORY OF OPERATION
The AD625 is a monolithic instrumentation amplifier based on
a modification of the classic three-op-amp approach. Monolithic
construction and laser-wafer-trimming allow the tight matching
and tracking of circuit components. This insures the high level
of performance inherent in this circuit architecture.
A preamp section (Q1–Q4) provides additional gain to A1 and
A2. Feedback from the outputs of A1 and A2 forces the collector currents of Q1–Q4 to be constant, thereby, impressing the
input voltage across R
outputs of A1 and A2 which is given by the gain (2R
. This creates a differential voltage at the
G
F/RG
+ 1)
times the differential portion of the input voltage. The unity
gain subtracter, A3, removes any common-mode signal from the
output voltage yielding a single ended output, V
, referred to
OUT
the potential at the reference pin.
The value of R
tance of the input preamp stage. As R
is the determining factor of the transconduc-
G
is reduced for larger
G
gains the transconductance increases. This has three important
advantages. First, this approach allows the circuit to achieve a
very high open-loop gain of (3 × 10
8
at programmed gains ≥ 500)
thus reducing gain related errors. Second, the gain-bandwidth
product, which is determined by C3, C4, and the input transconductance, increases with gain, thereby, optimizing frequency
response. Third, the input voltage noise is reduced to a value
determined by the collector current of the input transistors
(4 nV/√Hz).
The diodes to the supplies are only necessary if input voltages
outside of the range of the supplies are encountered. In higher
gain applications where differential voltages are small, back-toback Zener diodes and smaller resistors, as shown in Figure
26b, provides adequate protection. Figure 26c shows low cost
FETs with a maximum ON resistance of 300 Ω configured to offer
input protection with minimal degradation to noise, (5.2 nV/√Hz
compared to normal noise performance of 4 nV/√Hz).
During differential overload conditions, excess current will flow
through the gain sense lines (Pins 2 and 15). This will have no
effect in fixed gain applications. However, if the AD625 is being
used in an SPGA application with a CMOS multiplexer, this
current should be taken into consideration. The current capabilities of the multiplexer may be the limiting factor in allowable
overflow current. The ON resistance of the switch should be
included as part of R
when calculating the necessary input
G
protection resistance.
+V
S
FD333
FD333
1.4k
+IN
R
F
R
AD625
G
R
1.4k
–IN
FD333
F
FD333
V
OUT
INPUT PROTECTION
Differential input amplifiers frequently encounter input voltages
outside of their linear range of operation. There are two considerations when applying input protection for the AD625; 1) that
continuous input current must be limited to less than 10 mA
and 2) that input voltages must not exceed either supply by
more than one diode drop (approximately 0.6 V @ 25°C).
Under differential overload conditions there is (R
+ 100) Ω in
G
series with two diode drops (approximately 1.2 V) between the
plus and minus inputs, in either direction. With no external protection and R
very small (i.e., 40 Ω), the maximum overload
G
voltage the AD625 can withstand, continuously, is approximately
±2.5 V. Figure 26a shows the external components necessary to
protect the AD625 under all overload conditions at any gain.
+V
S
+
C3
GAIN
GAIN
SENSE
V
B
–
A1 A2
R
FRF
R
G
GAIN
SENSE
–V
C4
GAIN
DRIVE
10k
10k
50
10k
10k
+IN
SENSE
V
O
REF
50A50A
DRIVE
50
–IN
Q1, Q3 Q2, Q4
50A50A
Figure 25. Simplified Circuit of the AD625
–V
S
Figure 26a. Input Protection Circuit
+V
S
FD333
500
+IN
1N5837A
1N5837A
500
–IN
FD333
FD333
R
F
R
G
R
F
FD333
AD625
–V
S
V
OUT
Figure 26b. Input Protection Circuit for G > 5
+V
FD333
+IN
2N5952
–IN
2N5952
2k
2k
FD333
R
F
R
G
R
F
FD333
FD333
S
AD625
–V
S
V
OUT
Figure 26c. Input Protection Circuit
REV. D–8–
Any resistors in series with the inputs of the AD625 will degrade
RTO OFFSET VOLTAGE DRIFT
6
5
4
3
2
1
60k50k40k30k20k10k
MULTIPLYING FACTOR
BANDWIDTH
1M
100k
10k
1 10 100 1k
FREQUENCY – Hz
10k
20k
50k
FEEDBACK RESISTANCE – FEEDBACK RESISTANCE –
RTO NOISE RTO OFFSET VOLTAGE
300
200
100
3
2
10k 20k 30k 40k 50k 60k 10k 20k 30k 40k 50k 60k
VOLTAGE NOISE – nV Hz
MULTIPLYING FACTOR
FEEDBACK RESISTANCE – FEEDBACK RESISTANCE –
the noise performance. For this reason the circuit in Figure 26b
should be used if the gains are all greater than 5. For gains less
than 5, either the circuit in Figure 26a or in Figure 26c can be
used. The two 1.4 kΩ resistors in Figure 26a will degrade the
noise performance to:
AD625
4 kTR
+(4 nV/ Hz )2= 7.9 nV / Hz
ext
RESISTOR PROGRAMMABLE GAIN AMPLIFIER
In the resistor-programmed mode (Figure 27), only three external resistors are needed to select any gain from 1 to 10,000.
Depending on the application, discrete components or a
pretrimmed network can be used. The gain accuracy and gain
TC are primarily determined by the external resistors since the
AD625C contributes less than 0.02% to gain error and under
5 ppm/°C gain TC. The gain sense current is insensitive to
common-mode voltage, making the CMRR of the resistor programmed AD625 independent of the match of the two feedback
resistors, R
.
F
Selecting Resistor Values
As previously stated each RF provides feedback to the input
stage and sets the unity gain transconductance. These feedback
resistors are provided by the user. The AD625 is tested and
specified with a value of 20 kΩ for R
. Since the magnitude of
F
RTO errors increases with increasing feedback resistance, values
much above 20 kΩ are not recommended (values below 10 kΩ
may lead to instability). Refer to the graph of RTO noise,
for R
F
offset, drift, and bandwidth (Figure 28) when selecting the
feedback resistors. The gain resistor (R
formula R
A list of standard resistors which can be used to set some common gains is shown in Table I.
For single gain applications, only one offset null adjust is necessary; in these cases the RTI null should be used.
REV. D
= 2 RF/(G – l).
G
2R
F
G = +1
R
R
F
+GAIN
SENSE
RTI NULL
+V
S
RTI NULL
+GAIN DRIVE –GAIN DRIVE
Figure 27. AD625 in Fixed Gain Configuration
G
R
A1 A2
10k 10k
10k
G
A3
+INPUT –INPUT
1
2
3
4
5
6
NC
REF
7
8
–V
S
AD625
10k
) is determined by the
G
R
F
16
–GAIN
SENSE
15
RTO
14
NULL
RTO
13
NULL
12
11
V
10
OUT
+V
9
S
Figure 28. RTO Noise, Offset, Drift and Bandwidth vs.
Feedback Resistance Normalized to 20 k
Ω
Table I. Common Gains Nominally Within 0.5% Error
Using Standard 1% Resistors
GAIN R
F
R
G
1 20 kΩ∞
2 19.6 kΩ 39.2 kΩ
5 20 kΩ 10 kΩ
10 20 kΩ 4.42 kΩ
20 20 kΩ 2.1 kΩ
50 19.6 kΩ 806 Ω
100 20 kΩ 402 Ω
200 20.5 kΩ 205 Ω
500 19.6 kΩ 78.7 Ω
1000 19.6 kΩ 39.2 Ω
4 20 kΩ 13.3 kΩ
8 19.6 kΩ 5.62 kΩ
16 20 kΩ 2.67 kΩ
32 19.6 kΩ 1.27 kΩ
64 20 kΩ 634 Ω
128 20 kΩ 316 Ω
256 19.6 kΩ 154 Ω
512 19.6 kΩ 76.8 Ω
1024 19.6 kΩ 38.3 Ω
SENSE TERMINAL
The sense terminal is the feedback point for the AD625 output
amplifier. Normally it is connected directly to the output. If
heavy load currents are to be drawn through long leads, voltage
drops through lead resistance can cause errors. In these instances the sense terminal can be wired to the load thus putting
–9–
AD625
S
the I × R drops “inside the loop” and virtually eliminating this
error source.
Typically, IC instrumentation amplifiers are rated for a full ±10
volt output swing into 2 kΩ. In some applications, however, the
need exists to drive more current into heavier loads. Figure 29
shows how a high-current booster may be connected “inside the
loop” of an instrumentation amplifier. By using an external
power boosting circuit, the power dissipated by the AD625 will
remain low, thereby, minimizing the errors induced by selfheating. The effects of nonlinearities, offset and gain inaccuracies of the buffer are reduced by the loop gain of the AD625’s
output amplifier.
+V
VIN+
R
F
R
G
R
F
V
–
IN
Figure 29. AD625 /Instrumentation Amplifier with Output
Current Booster
REFERENCE TERMINAL
The reference terminal may be used to offset the output by up
to ±10 V. This is useful when the load is “floating” or does not
share a ground with the rest of the system. It also provides a
direct means of injecting a precise offset. However, it must be
remembered that the total output swing is ±10 volts, from
ground, to be shared between signal and reference offset.
The AD625 reference terminal must be presented with nearly
zero impedance. Any significant resistance, including those
caused by PC layouts or other connection techniques, will increase the gain of the noninverting signal path, thereby, upsetting the common-mode rejection of the in-amp. Inadvertent
thermocouple connections created in the sense and reference
lines should also be avoided as they will directly affect the output offset voltage and output offset voltage drift.
In the AD625 a reference source resistance will unbalance the
CMR trim by the ratio of 10 kΩ/R
ence source impedance is 1 Ω, CMR will be reduced to 80 dB
(10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to
provide the low impedance reference point as shown in Figure
30. The input offset voltage characteristics of that amplifier will
add directly to the output offset voltage performance of the
instrumentation amplifier.
The circuit of Figure 30 also shows a CMOS DAC operating in
the bipolar mode and connected to the reference terminal to
provide software controllable offset adjustments. The total offset
range is equal to ±(V
cal about 0 V R3 = 2 × R4.
The offset per bit is equal to the total offset range divided by 2
where N = number of bits of the DAC. The range of offset for
Figure 30 is ±120 mV, and the offset is incremented in steps of
0.9375 mV/LSB.
S
SENSE
AD625
–V
REF
/2 × R5/R4), however, to be symmetri-
REF
X1
R
I
REFERENCE
. For example, if the refer-
N
,
GND VDDV
SS
+IN
+V
S
SENSE
20k
R4
10k
REFERENCE
R3
5k
V
OUT
0.01F
R5
2k
1/2
AD712
–V
S
AD625
–V
V
C
REF
1
OUT 1
OUT 2
S
+V
S
1/2
AD712
–IN
R
FB
DATA
INPUTS
V
A
0
A
1
E
N
39k
S
AD589 1.2V
MSB
LSB
CS
WR
AD7502
+V
AD7524
8-BIT DAC
S
Figure 30. Software Controllable Offset
An instrumentation amplifier can be turned into a voltage-tocurrent converter by taking advantage of the sense and reference
terminals as shown in Figure 31.
VIN+
V
R
F
R
AD625
G
R
F
–
IN
SENSE
AD711
+VX–
R1
LOAD
I
L
Figure 31. Voltage-to-Current Converter
By establishing a reference at the “low” side of a current setting
resistor, an output current may be defined as a function of input
voltage, gain and the value of that resistor. Since only a small
current is demanded at the input of the buffer amplifier A1, the
forced current I
will largely flow through the load. Offset and
L
drift specifications of A2 must be added to the output offset and
drift specifications of the In-Amp.
INPUT AND OUTPUT OFFSET VOLTAGE
Offset voltage specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but this requires extra
circuitry.
REV. D–10–
AD625
AD625
+V
S
–V
S
R
F
R
G
R
F
SENSE
REFERENCE
AD711
V
OUT
+INPUT
–INPUT
100
AD625
+V
S
–V
S
R
F
R
G
R
F
AD712
100
100
V
OUT
SENSE
REFERENCE
–INPUT
+INPUT
–V
S
Offset voltage and offset voltage drift each have two components: input and output. Input offset is that component of offset
that is generated at the input stage. Measured at the output it is
directly proportional to gain, i.e., input offset as measured at the
output at G = 100 is 100 times greater than that measured at
G = 1. Output offset is generated at the output and is constant
for all gains.
The input offset and drift are multiplied by the gain, while the
output terms are independent of gain, therefore, input errors
dominate at high gains and output errors dominate at low gains.
The output offset voltage (and drift) is normally specified at
G = 1 (where input effects are insignificant), while input offset
(and drift) is given at a high gain (where output effects are negligible). All input-related parameters are specified referred to the
input (RTI) which is to say that the effect on the output is “G”
times larger. Offset voltage vs. power supply is also specified as
an RTI error.
By separating these errors, one can evaluate the total error independent of the gain. For a given gain, both errors can be combined to give a total error referred to the input (RTI) or output
(RTO) by the following formula:
Total Error RTI = input error + (output error/gain)
Total Error RTO = (Gain × input error) + output error
The AD625 provides for both input and output offset voltage
adjustment. This simplifies nulling in very high precision applications and minimizes offset voltage effects in switched gain
applications. In such applications the input offset is adjusted
first at the highest programmed gain, then the output offset is
adjusted at G = 1. If only a single null is desired, the input offset
null should be used. The most additional drift when using only
the input offset null is 0.9 µV/°C, RTO.
COMMON-MODE REJECTION
Common-mode rejection is a measure of the change in output
voltage when both inputs are changed by equal amounts. These
specifications are usually given for a full-range input voltage
change and a specified source imbalance.
In an instrumentation amplifier, degradation of common-mode
rejection is caused by a differential phase shift due to differences
in distributed stray capacitances. In many applications shielded
cables are used to minimize noise. This technique can create
Figure 32. Common-Mode Shield Driver
common-mode rejection errors unless the shield is properly
driven. Figures 32 and 33 show active data guards which are
configured to improve ac common-mode rejection by “bootstrapping” the capacitances of the input cabling, thus minimizing differential phase shift.
Figure 33. Differential Shield Driver
GROUNDING
In order to isolate low level analog signals from a noisy digital
environment, many data-acquisition components have two or
more ground pins. These grounds must eventually be tied together at one point. It would be convenient to use a single
ground line, however, current through ground wires and pc runs
of the circuit card can cause hundreds of millivolts of error.
Therefore, separate ground returns should be provided to minimize the current flow from the sensitive points to the system
ground (see Figure 34). Since the AD625 output voltage is
developed with respect to the potential on the reference terminal, it can solve many grounding problems.
REV. D
STATUS
AD7502
INPUT
SIGNAL
–VS+V
S
Figure 34. Basic Grounding Practice for a Data Acquisition System
AD625
+V
S
HOLD
CAP
–V
S
–11–
AD583
SAMPLE
AND
HOLD
–VS+V
ANALOG
OUT
+V
S
–V
S
S
AD574A
A/D
CONVERTER
ANALOG POWER
DIGITAL
COMMON
GROUND
V
LOGIC
AD625
GROUND RETURNS FOR BIAS CURRENTS
Input bias currents are those currents necessary to bias the input
transistors of a dc amplifier. There must be a direct return path
for these currents, otherwise they will charge external capacitances, causing the output to drift uncontrollably or saturate.
Therefore, when amplifying “floating” input sources such as
transformers, or ac-coupled sources, there must be a dc path
from each input to ground as shown in Figure 35.
+V
S
R
F
R
AD625
G
R
F
–V
S
SENSE
REFERENCE
V
LOAD
TO POWER
OUT
SUPPLY
GROUND
Figure 35a. Ground Returns for Bias Currents with
Transformer Coupled Inputs
+V
S
R
F
R
AD625
G
R
F
–V
S
SENSE
REFERENCE
V
LOAD
TO POWER
OUT
SUPPLY
GROUND
Figure 35b. Ground Returns for Bias Currents with
Thermocouple Input
+V
S
R
F
R
G
R
F
100k 100k
AD625
–V
S
SENSE
REFERENCE
V
LOAD
TO POWER
OUT
SUPPLY
GROUND
Figure 35c. Ground Returns for Bias Currents with AC
Coupled Inputs
AUTOZERO CIRCUITS
In many applications it is necessary to maintain high accuracy.
At room temperature, offset effects can be nulled by the use of
offset trimpots. Over the operating temperature range, however,
offset nulling becomes a problem. For these applications the
autozero circuit of Figure 36 provides a hardware solution.
OTHER CONSIDERATIONS
One of the more overlooked problems in designing ultralowdrift dc amplifiers is thermocouple induced offset. In a circuit
comprised of two dissimilar conductors (i.e., copper, kovar), a
current flows when the two junctions are at different temperatures. When this circuit is broken, a voltage known as the
“Seebeck” or thermocouple emf can be measured. Standard IC
lead material (kovar) and copper form a thermocouple with a
high thermoelectric potential (about 35 µV°C). This means that
care must be taken to insure that all connections (especially
those in the input circuit of the AD625) remain isothermal. This
includes the input leads (1, 16) and the gain sense lines (2, 15).
These pins were chosen for symmetry, helping to desensitize the
input circuit to thermal gradients. In addition, the user should
also avoid air currents over the circuitry since slowly fluctuating
GND VDDV
SS
+V
S
15 16
14
+
13
V
IN
–
V
DD
V
SS
GND
ZERO PULSE
AD7502
200s
A1 A2 A3 A4
AD625
–V
S
0.1F LOW
LEAKAGE
AD711
1k
12
AD7510DIKD
V
OUT
10
9
11
Figure 36. Auto-Zero Circuit
thermocouple voltages will appear as “flicker” noise. In SPGA
applications relay contacts and CMOS mux leads are both
potential sources of additional thermocouple errors.
The base emitter junction of an input transistor can rectify out
of band signals (i.e., RF interference). When amplifying small
signals, these rectified voltages act as small dc offset errors. The
AD625 allows direct access to the input transistors’ bases and
emitters enabling the user to apply some first order filtering to
these unwanted signals. In Figure 37, the RC time constant
should be chosen for desired attenuation of the interfering signals.
In the case of a resistive transducer, the capacitance alone working against the internal resistance of the transducer may suffice.
+IN
A1 A2
10k 10k
10k
AD625
R
G
16
–IN
–GAIN SENSE
15
RTO
14
NULL
RTO
13
NULL
12
–GAIN DRIVE
SENSE
11
10
V
OUT
+V
9
S
FILTER
–IN
10k
A3
CAP
R
F
CC
V
OUT
R
F
FILTER
CAP
+IN
+GAIN SENSE
RTI NULL
+V
RTI NULL
+GAIN DRIVE
REF
–V
R R
1
2
3
4
5
6
NC
7
8
S
Figure 37. Circuit to Attenuate RF Interference
REV. D–12–
AD625
These capacitances may also be incorporated as part of the
external input protection circuit (see section on Input Protection). As a general practice every effort should be made to
match the extraneous capacitance at Pins 15 and 2, and Pins 1
and 16, to preserve high ac CMR.
SOFTWARE PROGRAMMABLE GAIN AMPLIFIER
An SPGA provides the ability to externally program precision
gains from digital inputs. Historically, the problem in systems
requiring electronic switching of gains has been the ON resistance (R
gain setting resistor R
) of the multiplexer, which appears in series with the
ON
. This can result in substantial gain errors
G
and gain drifts. The AD625 eliminates this problem by making
the gain drive and gain sense pins available (Pins 2, 15, 5, 12;
see Figure 39). Consequently the multiplexer’s ON resistance is
removed from the signal current path. This transforms the ON
resistance error into a small nullable offset error. To clarify this
point, an error budget analysis has been performed in Table II
based on the SPGA configuration shown in Figure 39.
V
V
GND
AD7502
SS
DD
TTL/DTL TO CMOS LEVEL TRANSLATOR
DECODER/DRIVER
3.9k 975 650 975 3.9k
15.6k 15.6k20k 20k
+INPUT
1
+GAIN
SENSE
2
RTI NULL
S
RTI NULL
REF
–V
3
4
A1 A2
5
6
NC
S
7
8
10k 10k
10k
AD625
+V
+GAIN DRIVE –GAIN DRIVE
–INPUT
16
–GAIN
SENSE
15
RTO NULL
14
–V
13
RTO NULL
12
11
V
10
10k
A3
OUT
+V
9
S
A0
A1
E
N
S
Figure 38. SPGA in a Gain of 16
Figure 38 shows an AD625 based SPGA with possible gains of
1, 4, 16, 64. R
lines (Pins 2 and 15) of the AD625. In Figure 38, R
equals the resistance between the gain sense
G
equals
G
the sum of the two 975 Ω resistors and the 650 Ω resistor, or
2600 Ω. R
gain drive pins (Pins 12 and 15, or Pins 2 and 5), that is R
equals the resistance between the gain sense and the
F
F
equals the 15.6 kΩ resistor plus the 3.9 kΩ resistor, or 19.5 kΩ.
The gain, therefore equals:
2R
R
G
F
+1 =
2(19.5kΩ)
(2.6 kΩ)
+1 =16
As the switches of the differential multiplexer proceed synchronously, R
and RF change, resulting in the various programmed
G
gain settings.
–INPUT
–GAIN
SENSE
20k
–GAIN
C
S-OUT
R
OUT
OUT
ON
I
OUT
C
S-OUT
R
ON
I
OUT
C
S
I
S
C
S
I
S
C
–
V
IN
+
C
15.6k
3.9k
975k
650k
975k
3.9k
15.6k
20k
DRIVE
+GAIN
DRIVE
+GAIN
SENSE
+INPUT
AD625
10k
10k
V
S
10k
10k
12-BIT
DAS
Figure 39. SPGA with Multiplexer Error Sources
Figure 39 shows a complete SPGA feeding a 12-bit DAS with a
0 V–10 V input range. This configuration was used in the error
budget analysis shown in Table II. The gain used for the RTI
calculations is set at 16. As the gain is changed, the ON resistance of the multiplexer and the feedback resistance will change,
which will slightly alter the values in the table.
Table II. Errors Induced by Multiplexer to an SPGA
Induced Specifications Voltage Offset
Error AD625C AD7520KN Calculation Induced RTI
RTI Offset Gain Sense Switch 40 nA × 170 Ω = 6.8 µV
Voltage Offset Resistance 6.8 µV
RTI Offset Gain Sense Differential 60 nA × 6.8 Ω = 0.41 µV
Voltage Current Switch 0.41 µV
RTO Offset Feedback Differential 2 (0.2 nA × 20 kΩ) 0.5 µV
Voltage Resistance Leakage = 8 µV/16
RTO Offset Feedback Differential 2 (1 nA × 20 kΩ) 2.5 µV
Voltage Resistance Leakage = 40 µV/16
Total error induced by a typical CMOS multiplexer
to an SPGA at +25°C 10.21 A
NOTES
1
The resistor for this calculation is the user-provided feedback resistance (RF).
20 kΩ is recommended value (see Resistor Programmable Gain Amplifier section).
2
The leakage currents (IS and I
will be determined by the difference between the leakages of each “half’’ of the
differential multiplexer. The differential leakage current is multiplied by the
feedback resistance (see Note 1), to determine offset voltage. Because differential
leakage current is not a parameter specified on multiplexer data sheets, the most
extreme difference (one most positive and one most negative) was used for the
calculations in Table II. Typical performance will be much better.
**The frequency response and settling will be affected by the ON resistance and
internal capacitance of the multiplexer. Figure 40 shows the settling time vs.
ON resistance at different gain settings for an AD625 based SPGA.
**Switch resistance and leakage current errors can be reduced by using relays.
Current 170 Ω
40 nA
60 nA Resistance
6.8 Ω
1
20 kΩ
Current (IS)
+0.2 nA
–0.2 nA
1
20 kΩ
Current
(I
)
OUT
+1 nA
2
–1 nA
) will induce an offset voltage, however, the offset
OUT
2
REV. D
–13–
AD625
1000
800
400
200
100
80
40
20
10
SETTLING TIME – s
8
4
2
1
1
4 16 64 256 1024 4096
R
ON
GAIN
= 500
R
ON
RON = 0
= 1k
R
= 200
ON
Figure 40. Time to 0.01% of a 20 V Step Input for
SPGA with AD625
DETERMINING SPGA RESISTOR NETWORK VALUES
The individual resistors in the gain network can be calculated
sequentially using the formula given below. The equation determines the resistors as labeled in Figure 41. The feedback resistors and the gain setting resistors are interactive, therefore; the
formula must be a series where the present term is dependent on
the preceding term(s). The formula
j
∑
1
F
j
0
=
RkR
=
20 1
( – )( – )Ω
F
1
i
+
G
i
G
1
i
=
=
1
G
0
=
0
R
F
0
can be used to calculate the necessary feedback resistors for any
set of gains. This formula yields a network with a total resistance
of 40 kΩ. A dummy variable (j) serves as a counter to keep a
running total of the preceding feedback resistors. To illustrate
how the formula can be applied, an example similar to the
calculation used for the resistor network in Figure 38 is examined below.
1) Unity gain is treated as a separate case. It is implemented
with separate 20 kΩ feedback resistors as shown in Figure 41.
It is then ignored in further calculations.
2) Before making any calculations it is advised to draw a resistor
network similar to the network in Figure 41. The network
will have (2 × M) + 1 resistors, where M = number of gains.
For Figure 38 M = 3 (4, 16, 64), therefore, the resistor string
will have seven resistors (plus the two 20 kΩ “side” resistors
for unity gain).
3) Begin all calculations with G
R
= (20 kΩ – R
F
1
R
= [20 kΩ – (R
F
2
R
F
0
R
= [20 kΩ – (R
F
3
R
F
0
+ R
+ R
) (1–1/4): R
F
0
+ R
F
0
= 15 kΩ ∴ R
F
1
+ R
F
0
+ R
F
F
1
4) The center resistor (R
= 1 and R
0
= 0 ∴ R
F
0
)] (1–4/16):
F
1
= 3.75 kΩ
F
2
+ R
1
)] (1–16/64):
F
2
F
= 18.75 kΩ ∴ R
2
of the highest gain setting), is deter-
G
= 0.
F
0
= 15 kΩ
F
1
= 937.5 Ω
F
3
mined last. Its value is the remaining resistance of the 40 kΩ
string, and can be calculated with the equation:
Rk R
=
( – )40 2
GF
RG = 40 kΩ – 2 (R
Ω
– 39.375 kΩ = 625
40 k
Ω
F
+ R
0
M
∑
j
F
=
0
+ R
1
j
R
F
)
F
+
2
3
Ω
5) If different resistor values are desired, all the resistors in the
network can be scaled by some convenient factor. However,
raising the impedance will increase the RTO errors, lowering
the total network resistance below 20 kΩ can result in amplifier instability. More information on this phenomenon is
given in the RPGA section of the data sheet. The scale factor
will not affect the unity gain feedback resistors. The resistor
network in Figure 38 has a scaling factor of 650/625 = 1.04,
if this factor is used on R
tor values will match exactly.
, R
, R
F
1
, and RG, then the resis-
F
F
2
3
6) Round off errors can be cumulative, therefore, it is advised to
carry as many significant digits as possible until all the values
have been calculated.
AD75xx
TO GAIN SENSE
(PIN 2)
CONNECT IF UNITY
GAIN IS DESIRED
20k RF
TO GAIN DRIVE
(PIN 5)
RF
2
1
RFNRFGRF
N
RF
2
TO GAIN DRIVE
(PIN 12)
TO GAIN SENSE
(PIN 15)
20k
CONNECT IF UNITY
GAIN IS DESIRED
Figure 41. Resistors for a Gain Setting Network
REV. D–14–
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
AD625
PIN 1
0.17 (4.32)
MAX
0.175 (4.45)
0.12 (3.05)
0.02 (0.508)
0.015 (0.381)
16-Lead Plastic DIP (N-16)
0.755 (19.18)
0.745 (18.93)
16
18
0.015 (2.67)
0.095 (2.42)
9
0.26 (6.61)
0.24 (6.1)
0.065 (1.66)
0.045 (1.15)
SEATING
PLANE
16-Lead Ceramic DIP (D-16)
0.430
(10.922)
16
0.040R
0.310 0.01
0.306 (7.78)
0.294 (7.47)
0.012 (0.305)
0.008 (0.203)
0.14 (3.56)
0.12 (3.05)
.874 0.254)
0.095 (2.41)
0.125 (3.175)
0.047 0.007
(1.19 0.18)
MIN
1
PIN 1
0.800 0.010
20.32 0.254
+0.003
0.017
–0.002
+0.076
0.43
–0.05
0.700 (17.78) BSC
20-Terminal Leadless Chip Carrier (E-20A)
0.050
(1.27)
0.350 0.008
(8.89 0.20)
19
20
18
1
BOTTOM
VIEW
14
13
SQ
4
8
3
9
0.20 45°
(0.51 45°)
REF
0.025 0.003
(0.635 0.075)
0.040 45°
(1.02 45°)
REF 3 PLCS
0.082 0.018
(2.085 0.455)
9
0.265
(6.73)
8
0.035 0.01
(0.889 0.254)
0.180 0.03
(4.57 0.762)
SEATING
PLANE
0.100 (254)
BSC
0.290 0.010
(7.37 0.254)
0.300
(7.62)
REF
0.010 0.002
(0.254 0.05)
0.085 (2.159)
C00780c–0–6/00 (rev. D)
REV. D
–15–
–15–
PRINTED IN U.S.A.
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