ANALOG DEVICES AD5516 Service Manual

16-Channel, 12-Bit Voltage-Output DAC

www.BDTIC.com/ADI

with 14-Bit Increment Mode

FEATURES
High Integration:

16-Channel DAC in 12 mm ⴛ 12 mm

CSPBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic

®

Low Power, SPI

, QSPI™, MICROWIRE™, and
DSP Compatible
3-Wire Serial Interface

Output Impedance 0.5 ⍀
Output Voltage Range

ⴞ2.5 V (AD5516-1)
ⴞ5 V (AD5516-2)
ⴞ10 V (AD5516-3)

Asynchronous Reset Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O

FUNCTIONAL BLOCK DIAGRAM

AD5516

*

GENERAL DESCRIPTION

The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial inter­face. DAC selection is accomplished via address bits A3–A0.
14-bit resolution can be achieved by fine adjustment in Incre­ment/Decrement Mode (Mode 2). The serial interface operates
at clock rates up to 20 MHz and is compatible with standard
SPI, MICROWIRE, and DSP interface standards. The output
voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),
and ± 10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via the R

The device is operated with AV
to 5.25 V, V

= –4.75 V to –12 V, and V

SS

0 to RFB15 pins.

FB

= 5 V ± 5%, DVCC = 2.7 V

CC

= +4.75 V to +12 V,

DD

and requires a stable 3 V reference on REF_IN.

PRODUCT HIGHLIGHTS

1. Sixteen 12-bit DACs in one package, guaranteed monotonic.

2. Available in a 74-lead CSPBGA package with a body size of
12 mm ⫻ 12 mm.

DV

AV

CC

CC

AD5516

RESET

BUSY

DACGND

AGND

DGND

DCEN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

ANALOG

CALIBRATION

LOOP

MODE1

INTERFACE

CONTROL

LOGIC

SCLK DIND

12-BIT BUS

SYNC

OUT

MODE2

7-BIT BUS

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

LOGIC

PD

V

DDVSS

R

OFFS

R

OFFS

R

OFFS

R

OFFS

R

FB

RFB0

V

0

OUT

R

FB

R

1

FB

V

1

OUT

R

FB

R

FB

14

R

FB

V

14

OUT

R

15

FB

15

V

OUT

REF_IN

V

BIAS

DAC

DAC

DAC

DAC

POWER-DOWN

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC =

www.BDTIC.com/ADI

AD5516–SPECIFICATIONS

Parameter

DAC DC PERFORMANCE

Resolution 12 Bits
Integral Nonlinearity (INL) ± 2 LSB max Mode 1
Differential Nonlinearity (DNL) –1/+1.3 LSB max ± 0.5 LSB typ, Monotonic; Mode 1
Increment/Decrement Step-Size ± 0.25 LSB typ Monotonic; Mode 2 Only
Bipolar Zero Error ± 7 LSB max
Positive Full-Scale Error ± 10 LSB max
Negative Full-Scale Error ± 10 LSB max

VOLTAGE REFERENCE

REF_IN

ANALOG OUTPUTS (V

Output Temperature Coefficient
DC Output Impedance
Output Range

Resistive Load
Capacitive Load
Short Circuit Current
DC Power Supply Rejection Ratio
DC Crosstalk

DIGITAL INPUTS

Input Current ± 10 mA max ± 5 mA typ
Input Low Voltage 0.8 V max DV

Input High Voltage 2.4 V min DV

Input Hysteresis (SCLK and SYNC) 150 mV typ
Input Capacitance 10 pF max 5 pF typ

DIGITAL OUTPUTS (BUSY, D

Output Low Voltage, DVCC = 5 V 0.4 V max Sinking 200 mA
Output High Voltage, DV
Output Low Voltage, DV
Output High Voltage, DV
High Impedance Leakage Current (D
High Impedance Output Capacitance (D

POWER REQUIREMENTS

Power Supply Voltages

Power Supply Currents

Power-Down Currents

Power Dissipation

NOTES

1

See Terminology section.

2

A Version: Industrial temperature range –40∞C to +85∞C; typical at +25∞C.

3

Guaranteed by design and characterization; not production tested.

4

AD780 as reference for the AD5516.

5

Output range is restricted from V

6

Ensure that you do not exceed T

7

With 5 kW resistive load, footroom required is as follows: AD5516–1, 2 V; AD5516–2, 2.5 V; AD5516–3, 3 V.

8

Outputs unloaded.

Specifications subject to change without notice.

1

Nominal Input Voltage 3 V
Input Voltage Range

3

Input Current ± 1 mA max < 1 nA typ

0–15)

OUT

3

5

3, 4

AD5516-1 ± 2.5 V typ 100 mA Output Load
AD5516-2 ± 5V typ 100 mA Output Load
AD5516-3 ± 10 V typ 100 mA Output Load

V

DD

V

SS

AV
DV

I

DD

I

SS

AI

CC

DI

CC

I

DD

I

SS

AI

CC

DI

CC

CC

CC

3, 6, 7

3

3, 6

3

3

8

8

8

3

3

)

OUT

= 5 V 4 V min Sourcing 200 mA

CC

= 3 V 0.4 V max Sinking 200 mA

CC

= 3 V 2.4 V min Sourcing 200 mA

CC

SS

J (MAX)

+ 2 V to V

only) ± 1 mA max DCEN = 0

OUT

only) 5 pF typ DCEN = 0

OUT

– 2 V. Output span varies with reference voltage and is functional down to 2 V.

DD

. See Absolute Maximum Ratings section.

2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.
All specifications T

A Version

2.875/3.125 V min/max

10 ppm/∞C typ of FSR

0.5 W typ

5kW min
200 pF
7 mA typ
–85 dB typ VDD = +12 V ± 5%, VSS = –12 V ± 5%

0.1 LSB max

0.4 V max DV

2V min DV

4.75/15.75 V min/max
–4.75/–15.75 V min/max

4.75/5.25 V min/max

2.7/5.25 V min/max

5 mA max 3.5 mA typ. All Channels Full-Scale.
5 mA max 3.5 mA typ. All Channels Full-Scale.
17 mA max 13 mA typ

1.5 mA max 1 mA typ

1 mA typ
1 mA typ
2 mA max 200 nA typ
2 mA max 200 nA typ

105 mW typ VDD= +5 V, VSS= –5 V

2

MIN

to T

, unless otherwise noted.)

MAX

Unit Conditions/Comments

= 5 V ± 5%

CC

= 3 V ± 10%

CC

= 5 V ± 5%

CC

= 3 V ± 10%

CC

REV. B–2–

(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

www.BDTIC.com/ADI

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time (Mode 1)

1, 2

AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.
All specifications T

4

to T

MIN

MAX

A Version

, unless otherwise noted.)

3

Unit Conditions/Comments

100 pF, 5 kW Load Full-Scale Change
AD5516–1 32 ␮s max
AD5516–2 32 ␮s max
AD5516–3 36 ␮s max

Output Voltage Settling Time (Mode 2)

4

100 pF, 5 kW Load, 127 Code Increment
AD5516–1 2.5 ␮s max
AD5516–2 3.35 ␮s max
AD5516–3 7 ␮s max

Slew Rate 0.85 V/␮s typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk

AD5516–1 1 nV-s typ
AD5516–2 5 nV-s typ
AD5516–3 20 nV-s typ

Digital Feedthrough 1 nV-s typ
Output Noise Spectral Density @ 10 kHz

AD5516–1 150 nV/(Hz)
AD5516–2 350 nV/(Hz)
AD5516–3 700 nV/(Hz)

NOTES

1

See Terminology section.

2

Guaranteed by design and characterization; not production tested.

3

A version: Industrial temperature range –40∞C to +85∞C.

4

Timed from the end of a write sequence and includes BUSY low time.

Specifications subject to change without notice.

1/2

1/2

1/2

typ
typ
typ

AD5516

(VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

TIMING CHARACTERISTICS

Parameter

f

UPDATE1

f

UPDATE2

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

7MODE2

t

8MODE1

t

9MODE2

t

10

4

t

11

t

12

NOTES

1

See Timing Diagrams in Figures 1 and 2.

2

Guaranteed by design and characterization; not production tested.

3

All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

4

This is measured with the load circuit of Figure 3.

Specifications subject to change without notice.

1, 2, 3

Limit at T
(A Version) Unit Conditions/Comments

32 kHz max DAC Update Rate (Mode 1)
750 kHz max DAC Update Rate (Mode 2)
20 MHz max SCLK Frequency
20 ns min SCLK High Pulsewidth
20 ns min SCLK Low Pulsewidth
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
5 ns min DIN Setup Time
5 ns min DIN Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
10 ns min Minimum SYNC High Time (Standalone Mode)
400 ns min Minimum SYNC High Time (Daisy-Chain Mode)
10 ns min BUSY Rising Edge to SYNC Falling Edge
200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
20 ns max SCLK Rising Edge to D
20 ns min RESET Pulsewidth

MIN

, T

AGND = DGND = DACGND = 0 V. All specifications T

MAX

to T

MIN

Valid (Daisy-Chain Mode)

OUT

, unless otherwise noted.)

MAX

REV. B

–3–

AD5516

www.BDTIC.com/ADI

TIMING DIAGRAMS

SCLK

SYNC

DIN

BUSY

RESET

SCLK

SYNC

D

12 1718

t

MODE1

8

t

t

7

3

t

4

BIT 17 BIT 0

t

2

t

5

t

1

t

6

t

MODE2

LSBMSB

9

t

12

Figure 1. Serial Interface Timing Diagram

t

t

MODE2

7

IN

3

t

4

BIT 17 BIT 0 BIT 17 BIT 0

t

2

t

5

t

1

LSBMSB

t

10

t

6

D

OUT

BUSY

t

MODE1

8

INPUT WORD FOR DEVICE N

t

11

BIT 17 BIT 0

UNDEFINED INPUT WORD FOR DEVICE N

Figure 2. Daisy-Chaining Timing Diagram

200␮A

TO OUTPUT

PIN

C

L

50pF

200␮A

Figure 3. Load Circuit for D

I

OL

I

OH

Timing Specifications

OUT

INPUT WORD FOR DEVICE N+1

1.6V

REV. B–4–

AD5516

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V

SS

to AGND, DACGND . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

CC

to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

DV

CC

Digital Inputs to DGND . . . . . . . . . . .–0.3 V to DV

Digital Outputs to DGND . . . . . . . . . .–0.3 V to DV

REF_IN to AGND, DACGND . . . . . . –0.3 V to AV

V

0–15 to AGND . . . . . . . . . . . . V

OUT

– 0.3 V to V

SS

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

0–15 to AGND . . . . . . . . . . . . . V

R

FB

– 0.3 V to VDD+0.3 V

SS

Operating Temperature Range, Industrial . . . . . –40°C to +85°C

ORDERING GUIDE

Model Function Output Voltage Span Package Option

AD5516ABC-1 16 DACs ± 2.5 V 74-Lead CSPBGA
AD5516ABC-2 16 DACs ± 5 V 74-Lead CSPBGA
AD5516ABC-3 16 DACs ± 10 V 74-Lead CSPBGA
EVAL-AD5516-1EB Evaluation Board
EVAL-AD5516-2EB Evaluation Board
EVAL-AD5516-3EB Evaluation Board

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T
74-Lead CSPBGA Package, ␪

) . . . . . . . . . . . . . . . . . . . 150°C

J MAX

Thermal Impedance . . . 41°C/W

JA

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B

–5–