8-/10-/12-Bit, High Bandwidth
Multiplying DACs with Parallel Interface
Data Sheet
FEATURES
2.5 V to 5.5 V supply operation
Fast parallel interface (17 ns write cycle)
Update rate of 20.4 MSPS
INL of ±1 LSB for 12-bit DAC
10 MHz multiplying bandwidth
±10 V reference input
Extended temperature range: –40°C to +125°C
20-lead TSSOP and chip scale (4 mm × 4 mm) packages
8-, 10-, and 12-bit current output DACs
Upgrades to AD7524/AD7533/AD7545
Pin-compatible 8-, 10-, and 12-bit DACs in chip scale
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection
Readback function
0.4 μA typical power consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
AD5424/AD5433/AD5445
GENERAL DESCRIPTION
The AD5424/AD5433/AD54451 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suitable for battery-powered applications and
many other applications. These DACs utilize data readback,
allowing the user to read the contents of the DAC register via
the DB pins. On power-up, the internal register and latches are
filled with 0s and the DAC outputs are at zero scale.
As a result of manufacturing with a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The applied external reference input voltage (V
full-scale output current. An integrated feedback resistor (R
provides temperature tracking and full-scale voltage output
when combined with an external I-to-V precision amplifier.
While these devices are upgrades of the AD5424/AD5433/
AD5445 in multiplying bandwidth performance, they have a
latched interface and cannot be used in transparent mode.
The AD5424 is available in small, 20-lead LFCSP and 16-lead
TSSOP packages, while the AD5433/AD5445 DACs are available
in small, 20-lead LFCSP and TSSOP packages.
The EVAL-AD5445SDZ evaluation board is available for
evaluating DAC performance. For more information, see the
UG-333 evaluation board user guide.
1
U.S Patent No. 5,689,257.
) determines the
REF
)
FB
FUNCTIONAL BLOCK DIAGRAM
V
DD
AD5424/
AD5433/
AD5445
POWER-ON
RESET
CS
R/W
GND DB0
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
V
8-/10-/12-BIT
DAC REGISTER
INPUT LATCH
REF
R-2R DAC
DATA
INPUTS
Figure 1.
R
R
DB7/DB9/DB11
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2011 Analog Devices, Inc. All rights reserved.
I
I
OUT
OUT
FB
1
2
03160-001
AD5424/AD5433/AD5445 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Terminology................................................................................ 17
Theory of Operation ...................................................................... 18
REVISION HISTORY
12/12—Rev. B to Rev. C
Changes to General Description Section ...................................... 1
Added Note 2 to Table 1 .................................................................. 4
Added EPAD Note to Table 4 and EPAD Note to Figure 4......... 7
Added EPAD Note to Table 5 and EPAD Note to Figure 6......... 8
Added EPAD Note to Table 6 and EPAD Note to Figure 8......... 9
Deleted the Evaluation Board for AD5424/AD5433/AD5445
Section and Power Supplies for Evaluation Board Section ....... 23
Deleted Figure 59; Renumbered Sequentially ............................ 24
Deleted Figure 60 and Figure 61................................................... 25
Changes to Ordering Guide.......................................................... 26
Deleted Figure 62 and Table 12; Renumbered Sequentially ..... 26
8/09—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide.......................................................... 29
Circuit Operation....................................................................... 18
Bipolar Operation....................................................................... 19
Single-Supply Applications ....................................................... 20
Positive Output Voltage............................................................. 20
Adding Gain................................................................................ 21
DACs Used as a Divider or Programmable Gain Element... 21
Reference Selection .................................................................... 22
Amplifier Selection .................................................................... 22
Parallel Interface......................................................................... 23
Microprocessor Interfacing....................................................... 23
PCB Layout and Power Supply Decoupling................................ 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 26
3/05—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to Specifications.................................................................4
Changes to Figure 49...................................................................... 17
Changes to Figure 50...................................................................... 18
Changes to Figure 51, Figure 52, and Figure 54......................... 19
Added Microprocessor Interfacing Section ................................ 22
Added Figure 59 ............................................................................. 24
Added Figure 60 ............................................................................. 25
10/03—Initial Version: Revision 0
Rev. C | Page 2 of 28
Data Sheet AD5424/AD5433/AD5445
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, V
otherwise noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
STATIC PERFORMANCE
AD5424
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
AD5433
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5445
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±10 mV
Gain Error Temperature Coefficient1 ±5 ppm FSR/°C
Output Leakage Current1 ±10 nA Data = 0×0000, TA = 25°C, I
±20 nA Data = 0×0000, T = −40°C to +125°C, I
REFERENCE INPUT1
Reference Input Range ±10 V
V
Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C
REF
RFB Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C
Input Capacitance
Code Zero Scale 3 6 pF
Code Full Scale 5 8 pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH 1.7 V
Input Low Voltage, VIL 0.6 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I
0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL 1 μA
Input Capacitance 4 10 pF
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time
Measured to ±16 mV of full scale 30 60 ns
Measured to ±4 mV of full scale 35 70 ns
Measured to ±1 mV of full scale 80 120 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 15 30 ns Rise and fall time, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error DAC latch loaded with all 0s, V
70 dB Reference = 1 MHz
48 dB Reference = 10 MHz
= 10 V, I
REF
2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T
OUT
− 0.5 V VDD = 2.5 V to 3.6 V, I
DD
= ±3.5 V; DAC loaded all 1s
REF
= ±3.5 V, R
V
REF
LOAD
alternately loaded with 0s and 1s
to T
MIN
MAX
1
OUT
= 200 μA
SOURCE
= 200 μA
SOURCE
= 200 μA
SINK
= 200 μA
SINK
= 100 Ω, DAC latch
= 10 V, R
REF
= 100 Ω
LOAD
= ±3.5 V
REF
REF
, unless
1
OUT
= 0 V
Rev. C | Page 3 of 28
AD5424/AD5433/AD5445 Data Sheet
Parameter Min Typ Max Unit Test Conditions
Output Capacitance
I
1 12 17 pF All 0s loaded
OUT
25 30 pF All 1s loaded
I
2 22 25 pF All 0s loaded
OUT
10 12 pF All 1s loaded
Digital Feedthrough 1 nV-s
Feedthrough to DAC output with CS
alternate loading of all 0s and all 1s
Analog THD 81 dB V
Digital THD Clock = 10 MHz, V
50 kHz f
65 dB
OUT
= 3.5 V p-p, all 1s loaded, f = 100 kHz
REF
= 3.5 V
REF
Output Noise Spectral Density2 25 nV√Hz @ 1 kHz
SFDR Performance (Wide Band) AD5445, V
= 3.5 V
REF
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
55 dB
OUT
63 dB
OUT
65 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
SFDR Performance (Narrow Band) AD5445, V
50 dB
OUT
60 dB
OUT
62 dB
OUT
= 3.5 V
REF
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
73 dB
OUT
80 dB
OUT
82 dB
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
Intermodulation Distortion AD5445, V
70 dB
OUT
75 dB
OUT
80 dB
OUT
= 3.5 V
REF
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.6 μA TA = 25°C, logic inputs = 0 V or VDD
0.4 5 μA Logic inputs = 0 V or VDD, T= −40°C to +125°C
Power Supply Sensitivity 0.001 %/% ΔV
1
Guaranteed by design, not subject to production test.
2
Specification measured with OP27.
= ±5%
DD
high and
Rev. C | Page 4 of 28
Data Sheet AD5424/AD5433/AD5445
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
V
= 10 V, I
REF
Table 2.
Parameter1 V
t1 0 0 ns min
t2 0 0 ns min
t3 10 10 ns min
t4 6 6 ns min Data setup time
t5 0 0 ns min Data hold time
t6 5 5 ns min
t7 9 7 ns min
t8 20 10 ns typ Data access time
40 20 ns max
t9 5 5 ns typ Bus relinquish time
10 10 ns max
1
Guaranteed by design, not subject to production test.
2 = 0 V; temperature range for Y version: −40°C to +125°C; all specifications T
OUT
= 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Test Conditions/Comments
DD
R/W
t
t
1
2
t
6
MIN
to T
, unless otherwise noted.
MAX
R/W
to CS setup time
R/W
to CS hold time
CS
low time (write cycle)
R/W
high to CS low
CS
min high time
t
2
t
7
t
8
t
9
03160-002
CS
DATA
t
3
t
4
DATA VALID DATA VALID
t
5
Figure 2. Timing Diagram
Rev. C | Page 5 of 28
AD5424/AD5433/AD5445 Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND –0.3 V to +7 V
V
, RFB to GND –12 V to +12 V
REF
I
1, I
OUT
Logic Inputs and Output1 –0.3 V to VDD + 0.3 V
Operating Temperature Range
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP θJA Thermal Impedance 150°C/W
20-Lead TSSOP θJA Thermal Impedance 143°C/W
20-Lead LFCSP θJA Thermal Impedance 135°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
1
Overvoltages at DBx, CS, and R/W, are clamped by internal diodes.
2 to GND –0.3 V to +7 V
OUT
Extended Industrial (Y Version) –40°C to +125°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. C | Page 6 of 28
Data Sheet AD5424/AD5433/AD5445
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
1
FB
1
1
I
OUT
I
2
2
OUT
3
GND
4
DB7
DB6
DB5
DB4
DB3
(Not to Scale)
5
6
7
8
AD5424
Figure 3. AD5424 Pin Configuration (TSSOP)
R
16
FB
V
15
REF
14
V
DD
13
R/W
CS
12
11
DB0 (LSB)
10
DB1
9
DB2
03160-004
2019 18 17 16
GND
1
DB7
2
3
DB6
DB5
4
DB4
5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 4. AD5424 Pin Configuration (LFCSP)
Table 4. AD5424 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 I
2 20 I
3 1 GND
4 to 11 2 to 9 DB7 to DB0
10 to 13 NC
12 14
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
Ground.
Parallel Data Bits 7 to 0.
No Internal Connection.
CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
13 15
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS
R/W
to read back contents of DAC register.
14 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
15 17 V
16 18 R
DAC Reference Voltage Input Terminal.
REF
FB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
Not applicable
EPAD The exposed pad should be connected to ground.
Rev. C | Page 7 of 28
REFVDD
OUT
OUT
V
R
I
I
PIN 1
INDICATOR
AD5424
TOP VIEW
678910
DB3
DB2
DB1
DB0
NC
R/W
15
CS
14
13
NC
NC
12
11
NC
3160-005
AD5424/AD5433/AD5445 Data Sheet
2
1
I
1
OUT
I
2
2
OUT
3
GND
4
DB9
DB8
5
AD5433
(Not to Scale)
6
DB7
7
DB6
DB5
8
DB4 DB1
9
DB3 DB2
10
NC = NO CONNECT
R
20
FB
V
19
REF
18
V
DD
17
R/W
16
CS
15
NC
14
NC
13
DB0 (LSB)
12
11
Figure 5. AD5433 Pin Configuration (TSSOP)
03160-006
GND
1
DB9
2
3
DB8
DB7
4
DB6
5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 6. AD5433 Pin Configuration (LFCSP)
1
FB
OUT
OUT
I
I
V
R
2019 18 17 16
PIN 1
INDICATOR
AD5433
TOP VIEW
678910
DB5
DB4
DB3
DB2
REFVDD
DB1
R/W
15
CS
14
13
NC
NC
12
11
DB0
03160-007
Table 5. AD5433 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 I
2 20 I
3 1 GND
4 to 13 2 to
11
14, 15 12, 13 NC
16 14
17 15
18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19 17 V
20 18 R
Not applicable EPAD
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
Ground.
DB9 to
Parallel Data Bits 9 to 0.
DB0
Not Internally Connected.
CS Chip Select Input. Active low. Use in conjunction with R/W to load parallel data to the input latch or to
read data from the DAC register. Rising edge of
R/
W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with CS to read
CS loads data.
back contents of DAC register.
DAC Reference Voltage Input Terminal.
REF
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external amplifier output.
FB
The exposed pad should be connected to ground.
Rev. C | Page 8 of 28
Data Sheet AD5424/AD5433/AD5445
2
1
1
I
OUT
I
2
2
OUT
3
GND
4
DB11
DB10
5
AD5445
(Not to Scale)
6
DB9
7
DB8
DB7
8
DB6 DB3
9
DB5 DB4
10
R
20
FB
V
19
REF
18
V
DD
17
R/W
16
CS
15
DB0 (LSB)
14
DB1
13
DB2
12
11
Figure 7. AD5445 Pin Configuration (TSSOP)
03160-008
GND
1
DB11
2
3
DB10
DB9
4
DB8
5
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
Figure 8. AD5445 Pin Configuration (LFCSP)
1
FB
REFVDD
OUT
OUT
V
R
I
I
2019 18 1716
PIN 1
INDICATOR
AD5445
TOP VIEW
678910
DB7
DB6
DB5
DB4
DB3
R/W
15
CS
14
13
DB0
DB1
12
11
DB2
03160-009
Table 6. AD5445 Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 I
2 20 I
3 1 GND
4 to 15 2 to 13 DB11 to DB0
16 14
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
Ground Pin.
Parallel Data Bits 11 to 0.
CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
17 15
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with
R/W
CS to read back contents of DAC register.
18 16 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
19 17 V
20 18 R
DAC Reference Voltage Input Terminal.
REF
FB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
Not applicable EPAD The exposed pad should be connected to ground.
Rev. C | Page 9 of 28
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