ANALOG DEVICES AD5424, AD5433, AD5445 Service Manual

8-/10-/12-Bit, High Bandwidth,

Multiplying DACs with Parallel Interface

FEATURES

2.5 V to 5.5 V Supply Operation
Fast Parallel Interface (17 ns Write Cycle)
10 MHz Multiplying Bandwidth
10 V Reference Input
Extended Temperature Range –40C to +125C
20-Lead TSSOP and Chip Scale (4 mm  4 mm) Packages
8-, 10-, and 12-Bit Current Output DACs
Upgrades to AD7524/AD7533/AD7545
Pin Compatible 8-, 10-, and 12-Bit DACs in Chip Scale
Guaranteed Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function

0.4 A Typical Power Consumption

APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming

AD5424/AD5433/AD5445

FUNCTIONAL BLOCK DIAGRAM

V

REF

8-/10-/12-BIT

R-2R DAC

DAC REGISTER

INPUT LATCH

DB0

DATA

INPUTS

DB7/DB9/DB11

R

I

OUT

I

OUT

FB

R

CS

R/W

V

AD5424/
AD5433/
AD5445

POWER-ON

RESET

DD

GND

*

1

2

GENERAL DESCRIPTION

The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respectively.

These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.

These DACs utilize data readback allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s and the DAC
outputs are at zero scale.

As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of up to 10 MHz.

*U.S. Patent No. 5,689,257

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The applied external reference input voltage (V

) determines

REF

the full-scale output current. An integrated feedback resistor

) provides temperature tracking and full-scale voltage output

(R

FB

when combined with an external I-to-V precision amplifier.

While these devices are upgrades of AD7524/AD7533/AD7545
in multiplying bandwidth performance, they have a latched
interface and cannot be used in transparent mode.

The AD5424 is available in small 20-lead LFCSP and 16-lead
TSSOP packages, while the AD5433/AD5445 DACs are avail­able in small 20-lead LFCSP and TSSOP packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5424/AD5433/AD5445–SPECIFICATIONS

1

(VDD = 2.5 V to 5.5 V, V
AC performance with AD8038, unless otherwise noted.)

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

AD5424

Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic

AD5433

Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5445

Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic

Gain Error ±10 mV
Gain Error Temperature Coefficient
Output Leakage Current

REFERENCE INPUT

Reference Input Range ±10 V
V

Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/⬚C

REF

Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/⬚C

R

FB

Input Capacitance

Code 0 3 6 pF
Code 4095 5 8 pF

DIGITAL INPUTS/OUTPUT

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, I
Input Capacitance 4 10 pF

= 4.5 V to 5.5 V

V

DD

Output Low Voltage, V
Output High Voltage, V

= 2.5 V to 3.6 V

V

DD

Output Low Voltage, V
Output High Voltage, V

DYNAMIC PERFORMANCE

Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time V

AD5424 30 60 ns Measured to ±16 mV of full scale
AD5433 35 70 ns Measured to ±4 mV of full scale
AD5445 80 120 ns Measured to ± 1 mV of full scale

Digital Delay 20 40 ns Interface delay time

to 90% Settling Time 15 30 ns Rise and Fall time, V

10%
Digital to Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error DAC latch loaded with all 0s. V

= 10 V, I

REF

2

IH

IL

2 = O V. All specifications T

OUT

2

2

2

1.7 V

IL

OL

OH

OL

OH

2

VDD – 1 V I

VDD – 0.5 V I

to T

MIN

, unless otherwise noted. DC performance measured with OP1177,

MAX

±5 ppm FSR/⬚C

±10 nA Data = 0x0000, TA = 25⬚C, I
±20 nA Data = 0x0000, I

OUT

0.6 V
1 ␮A

0.4 V I

0.4 V I

= 200 µA

SINK

= 200 µA

SOURCE

= 200 µA

SINK

= 200 µA

SOURCE

= ± 3.5 V; DAC loaded all 1s

REF

= 10 V, R

REF

LOAD

= 100 Ω, C

70 dB Reference = 1 MHz
48 dB Reference = 10 MHz

1

= 10 V, R

REF

OUT

LOAD

REF

1

= 15 pF

LOAD

REF

= ±3.5 V

= 100 Ω

= 0 V

REV. 0–2–

AD5424/AD5433/AD5445

Parameter Min Typ Max Unit Conditions

Output Capacitance

I

22225pFAll 0s loaded

OUT

11217pFAll 0s loaded

I

OUT

Digital Feedthrough 1 nV-s Feedthrough to DAC output with CS high and

Total Harmonic Distortion –81 dB V
Digital THD

Clock = 10 MHz

50 kHz f

OUT

Output Noise Spectral Density 25 nV√Hz @ 1 kHz
SFDR Performance (Wide Band) AD5445, 65k codes, V
Clock = 10 MHz

500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

Clock = 25 MHz

500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

SFDR Performance (Narrow Band) AD5445, 65k codes, V

Clock = 10 MHz

500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

Clock = 25 MHz

500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

Intermodulation Distortion AD5445, 65k codes, V

Clock = 10 MHz

= 400 kHz, f2 = 500 kHz 65 dB

f

1

f

= 40 kHz, f2 = 50 kHz 72 dB

1

Clock = 25 MHz

= 400 kHz, f2 = 500 kHz 51 dB

f

1

f1 = 40 kHz, f2 = 50 kHz 65 dB

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
I

DD

NOTES

1

Temperature range is as follows: Y version: –40⬚C to +125⬚C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

10 12 pF All 1s loaded

25 30 pF All 1s loaded

alternate loading of all 0s and all 1s

= 3.5 V pk-pk; all 1s loaded, f = 100 kHz

REF

65 dB

REF

55 dB
63 dB
65 dB

50 dB
60 dB
62 dB

REF

73 dB
80 dB
87 dB

70 dB
75 dB
80 dB

REF

0.6 ␮AT

= 25⬚C, logic inputs = 0 V or V

A

0.4 5 ␮ALogic inputs = 0 V or V

= 3.5 V

= 3.5 V

= 3.5 V

DD

DD

REV. 0

–3–

AD5424/AD5433/AD5445

1, 2

(V

TIMING CHARACTERISTICS

= 5 V, I

REF

Parameter VDD = 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

00 ns min R/W to CS setup time
00 ns min R/W to CS hold time
10 10 ns min CS low time (write cycle)
66 ns min Data setup time
00 ns min Data hold time
55 ns min R/W high to CS low
97 ns min CS min high time
20 10 ns typ Data access time
40 20 ns max

t

9

55 ns typ Bus relinquish time
10 10 ns max

NOTES

1

See Figure 1. Temperature range is as follows: Y version: –40⬚C to +125⬚C. Guaranteed by design and characterization, not subject to production test.

2

All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured with load
circuit in Figure 2.

Specifications subject to change without notice.

2 = O V. All specifications T

OUT

MIN

to T

, unless otherwise noted.)

MAX

R/W

CS

DATA

t

t

1

t

3

t

4

DATA VALID

2

t

5

t

6

t

7

t

8

DATA VALID

t

2

t

9

Figure 1. Timing Diagram

REV. 0–4–

AD5424/AD5433/AD5445

ABSOLUTE MAXIMUM RATINGS

(TA = 25⬚C, unless otherwise noted.)

1

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

REF, RFB

I

OUT

Logic Inputs and Output

to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V

1, I

2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

OUT

2

. . . . . . . . . . . –0.3 V to VDD +0.3 V

Operating Temperature Range

Extended Industrial (Y Version) . . . . . . . . –40⬚C to +125⬚C

Storage Temperature Range . . . . . . . . . . . . . –65⬚C to +150⬚C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150⬚C

16-Lead TSSOP ␪
20-Lead TSSOP ␪
20-Lead LFCSP ␪

Thermal Impedance . . . . . . . . . 150⬚C/W

JA

Thermal Impedance . . . . . . . . . 143⬚C/W

JA

Thermal Impedance . . . . . . . . . 135⬚C/W

JA

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300⬚C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235⬚C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Overvoltages at DBx, CS, and R/W, will be clamped by internal diodes.

ORDERING GUIDE

I

OL

V

+ V

OH (MIN)

I

OH

OL (MAX)

2

OUTPUT

PIN

200A

TO

C

L

50pF

200A

Figure 2. Load Circuit for Data Output Timing Specifications

Resolution INL Temperature Package

Model (Bits) (LSB) Range Package Description Option

AD5424YRU 8 ±0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-16
AD5424YRU-REEL 8 ± 0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5424YRU-REEL7 8 ±0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5424YCP 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5424YCP-REEL 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5424YCP-REEL7 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YRU 10 ±0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YRU-REEL 10 ± 0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YRU-REEL7 10 ±0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YCP 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YCP-REEL 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YCP-REEL7 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YRU 12 ±1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YRU-REEL 12 ± 1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YRU-REEL7 12 ±1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YCP 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YCP-REEL 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YCP-REEL7 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
EVAL-AD5424EB Evaluation Kit
EVAL-AD5433EB Evaluation Kit
EVAL-AD5445EB Evaluation Kit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD5424/AD5433/AD5445

PIN 1
INDICATOR

TOP VIEW

AD5424

1

GND

2

DB7

3

DB6

4

DB5

5

DB4

DB3 6

DB2 7

DB1 8

DB0 9

NC 10

15 R/W
14 CS
13 NC
12 NC
11 NC

20 I

OUT

2

19 I

OUT

1

18 R

FB

17 V

REF

16 V

DD

NC = NO CONNECT

PIN CONFIGURATIONS

I

OUT

I

OUT

GND

DB7

DB6

DB5

DB4

DB3

1

1

2

2

3

4

5

6

7

8

TSSOP

AD5424

(Not to Scale)

16

R

FB

15

V

REF

14

V

DD

13

R/W

12

CS

11

DB0 (LSB)

10

DB1

DB2

9

LFCSP

AD5424 PIN FUNCTION DESCRIPTIONS

Pin No.

TSSOP LFCSP Mnemonic Function

119I

220I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

31GND Ground

4–11 2–9 DB7–DB0 Parallel Data Bits 7 to 0.

10–13 NC No Internal Connection.

12 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input

latch or to read data from the DAC register. Rising edge of CS loads data.

13 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use

with CS to readback contents of DAC register.

14 16 V

15 17 V

16 18 R

DD

REF

FB

Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.

DAC Reference Voltage Input Terminal.

DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.

REV. 0–6–

PIN 1
INDICATOR

TOP VIEW

AD5433

1

GND

2

DB9

3

DB8

4

DB7

5

DB6

DB5 6

DB4 7

DB3 8

DB2 9

DB1 10

15 R/W
14 CS
13 NC
12 NC
11 DB0

20 I

OUT

2

19 I

OUT

1

18 R

FB

17 V

REF

16 V

DD

NC = NO CONNECT

PIN CONFIGURATIONS

AD5424/AD5433/AD5445

TSSOP

I

1

1

OUT

2

I

2

OUT

GND

DB9

DB8

DB7

DB6

DB5

DB4

DB3

AD5433

(Not to Scale)

3

4

5

6

7

8

9

10

NC = NO CONNECT

20

R

19

V

18

V

17

R/W

16

CS

NC

15

14

NC

DB0 (LSB)

13

12

DB1

11

DB2

FB

REF

DD

LFCSP

AD5433 PIN FUNCTION DESCRIPTIONS

Pin No.
TSSOP LFCSP Mnemonic Function

119I

220I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

31GND Ground

4–13 2–11 DB9–DB0 Parallel Data Bits 9 to 0.

14, 15 12, 13 NC Not Internally Connected.
16 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input

latch or to read data from the DAC register. Rising edge of CS loads data.

17 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use

with CS to readback contents of DAC register.

18 16 V

19 17 V

20 18 R

DD

REF

FB

Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.

DAC Reference Voltage Input Terminal.

DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.

REV. 0

–7–

AD5424/AD5433/AD5445

PIN 1
INDICATOR

TOP VIEW

AD5445

1

GND

2

DB11

3

DB10

4

DB9

5

DB8

DB7 6

DB6 7

DB5 8

DB4 9

DB3 10

15 R/W
14 CS
13 DB0
12 DB1
11 DB2

20 I

OUT

2

19 I

OUT

1

18 R

FB

17 V

REF

16 V

DD

PIN CONFIGURATIONS

I

OUT

I

OUT

GND

DB11

DB10

DB9

DB8

DB7

DB6

DB5

1

1

2

2

3

4

5

6

7

8

9

10

TSSOP

AD5445

(Not to Scale)

20

R

19

V

REF

18

V

DD

17

R/W

16

CS

15

DB0 (LSB)

14

DB1

13

DB2

DB3

12

DB4

11

FB

LFCSP

AD5445 PIN FUNCTION DESCRIPTIONS

Pin No.
TSSOP LFCSP Mnemonic Function

119I

220I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

31GND Ground Pin.

4–15 2–13 DB11–DB0 Parallel Data Bits 11 to 0.
16 14 CS Chip Select Input. Active low. Rising edge of CS loads data. Used in conjunction with R/W to

load parallel data to the input latch or to read data from the DAC register.

17 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with

CS to readback contents of DAC register.

18 16 V

19 17 V

20 18 R

DD

REF

FB

Positive Power Supply Input. These parts can be operated from a supply of +2.5 V to +5.5 V.

DAC Reference Voltage Input Terminal.

DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.

REV. 0–8–