8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Parallel Interface
FEATURES
2.5 V to 5.5 V Supply Operation
Fast Parallel Interface (17 ns Write Cycle)
10 MHz Multiplying Bandwidth
10 V Reference Input
Extended Temperature Range –40C to +125C
20-Lead TSSOP and Chip Scale (4 mm 4 mm) Packages
8-, 10-, and 12-Bit Current Output DACs
Upgrades to AD7524/AD7533/AD7545
Pin Compatible 8-, 10-, and 12-Bit DACs in Chip Scale
Guaranteed Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function
0.4 A Typical Power Consumption
APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming
AD5424/AD5433/AD5445
FUNCTIONAL BLOCK DIAGRAM
V
REF
8-/10-/12-BIT
R-2R DAC
DAC REGISTER
INPUT LATCH
DB0
DATA
INPUTS
DB7/DB9/DB11
R
I
OUT
I
OUT
FB
R
CS
R/W
V
AD5424/
AD5433/
AD5445
POWER-ON
RESET
DD
GND
*
1
2
GENERAL DESCRIPTION
The AD5424/AD5433/AD5445 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters (DACs), respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.
These DACs utilize data readback allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s and the DAC
outputs are at zero scale.
As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of up to 10 MHz.
*U.S. Patent No. 5,689,257
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The applied external reference input voltage (V
) determines
REF
the full-scale output current. An integrated feedback resistor
) provides temperature tracking and full-scale voltage output
(R
FB
when combined with an external I-to-V precision amplifier.
While these devices are upgrades of AD7524/AD7533/AD7545
in multiplying bandwidth performance, they have a latched
interface and cannot be used in transparent mode.
The AD5424 is available in small 20-lead LFCSP and 16-lead
TSSOP packages, while the AD5433/AD5445 DACs are available in small 20-lead LFCSP and TSSOP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD5424/AD5433/AD5445–SPECIFICATIONS
1
(VDD = 2.5 V to 5.5 V, V
AC performance with AD8038, unless otherwise noted.)
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
AD5424
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
AD5433
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5445
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±10 mV
Gain Error Temperature Coefficient
Output Leakage Current
REFERENCE INPUT
Reference Input Range ±10 V
V
Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/⬚C
REF
Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/⬚C
R
FB
Input Capacitance
Code 0 3 6 pF
Code 4095 5 8 pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, I
Input Capacitance 4 10 pF
= 4.5 V to 5.5 V
V
DD
Output Low Voltage, V
Output High Voltage, V
= 2.5 V to 3.6 V
V
DD
Output Low Voltage, V
Output High Voltage, V
DYNAMIC PERFORMANCE
Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time V
AD5424 30 60 ns Measured to ±16 mV of full scale
AD5433 35 70 ns Measured to ±4 mV of full scale
AD5445 80 120 ns Measured to ± 1 mV of full scale
Digital Delay 20 40 ns Interface delay time
to 90% Settling Time 15 30 ns Rise and Fall time, V
10%
Digital to Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error DAC latch loaded with all 0s. V
= 10 V, I
REF
2
IH
IL
2 = O V. All specifications T
OUT
2
2
2
1.7 V
IL
OL
OH
OL
OH
2
VDD – 1 V I
VDD – 0.5 V I
to T
MIN
, unless otherwise noted. DC performance measured with OP1177,
MAX
±5 ppm FSR/⬚C
±10 nA Data = 0x0000, TA = 25⬚C, I
±20 nA Data = 0x0000, I
OUT
0.6 V
1 A
0.4 V I
0.4 V I
= 200 µA
SINK
= 200 µA
SOURCE
= 200 µA
SINK
= 200 µA
SOURCE
= ± 3.5 V; DAC loaded all 1s
REF
= 10 V, R
REF
LOAD
= 100 Ω, C
70 dB Reference = 1 MHz
48 dB Reference = 10 MHz
1
= 10 V, R
REF
OUT
LOAD
REF
1
= 15 pF
LOAD
REF
= ±3.5 V
= 100 Ω
= 0 V
REV. 0–2–
AD5424/AD5433/AD5445
Parameter Min Typ Max Unit Conditions
Output Capacitance
I
22225pFAll 0s loaded
OUT
11217pFAll 0s loaded
I
OUT
Digital Feedthrough 1 nV-s Feedthrough to DAC output with CS high and
Total Harmonic Distortion –81 dB V
Digital THD
Clock = 10 MHz
50 kHz f
OUT
Output Noise Spectral Density 25 nV√Hz @ 1 kHz
SFDR Performance (Wide Band) AD5445, 65k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
SFDR Performance (Narrow Band) AD5445, 65k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Intermodulation Distortion AD5445, 65k codes, V
Clock = 10 MHz
= 400 kHz, f2 = 500 kHz 65 dB
f
1
f
= 40 kHz, f2 = 50 kHz 72 dB
1
Clock = 25 MHz
= 400 kHz, f2 = 500 kHz 51 dB
f
1
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
I
DD
NOTES
1
Temperature range is as follows: Y version: –40⬚C to +125⬚C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
10 12 pF All 1s loaded
25 30 pF All 1s loaded
alternate loading of all 0s and all 1s
= 3.5 V pk-pk; all 1s loaded, f = 100 kHz
REF
65 dB
REF
55 dB
63 dB
65 dB
50 dB
60 dB
62 dB
REF
73 dB
80 dB
87 dB
70 dB
75 dB
80 dB
REF
0.6 AT
= 25⬚C, logic inputs = 0 V or V
A
0.4 5 ALogic inputs = 0 V or V
= 3.5 V
= 3.5 V
= 3.5 V
DD
DD
REV. 0
–3–
AD5424/AD5433/AD5445
1, 2
(V
TIMING CHARACTERISTICS
= 5 V, I
REF
Parameter VDD = 2.5 V to 5.5 V VDD = 4.5 V to 5.5 V Unit Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
00 ns min R/W to CS setup time
00 ns min R/W to CS hold time
10 10 ns min CS low time (write cycle)
66 ns min Data setup time
00 ns min Data hold time
55 ns min R/W high to CS low
97 ns min CS min high time
20 10 ns typ Data access time
40 20 ns max
t
9
55 ns typ Bus relinquish time
10 10 ns max
NOTES
1
See Figure 1. Temperature range is as follows: Y version: –40⬚C to +125⬚C. Guaranteed by design and characterization, not subject to production test.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured with load
circuit in Figure 2.
Specifications subject to change without notice.
2 = O V. All specifications T
OUT
MIN
to T
, unless otherwise noted.)
MAX
R/W
CS
DATA
t
t
1
t
3
t
4
DATA VALID
2
t
5
t
6
t
7
t
8
DATA VALID
t
2
t
9
Figure 1. Timing Diagram
REV. 0–4–
AD5424/AD5433/AD5445
ABSOLUTE MAXIMUM RATINGS
(TA = 25⬚C, unless otherwise noted.)
1
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
REF, RFB
I
OUT
Logic Inputs and Output
to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V
1, I
2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
OUT
2
. . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating Temperature Range
Extended Industrial (Y Version) . . . . . . . . –40⬚C to +125⬚C
Storage Temperature Range . . . . . . . . . . . . . –65⬚C to +150⬚C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150⬚C
16-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP
Thermal Impedance . . . . . . . . . 150⬚C/W
JA
Thermal Impedance . . . . . . . . . 143⬚C/W
JA
Thermal Impedance . . . . . . . . . 135⬚C/W
JA
Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300⬚C
IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235⬚C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at DBx, CS, and R/W, will be clamped by internal diodes.
ORDERING GUIDE
I
OL
V
+ V
OH (MIN)
I
OH
OL (MAX)
2
OUTPUT
PIN
200A
TO
C
L
50pF
200A
Figure 2. Load Circuit for Data Output Timing Specifications
Resolution INL Temperature Package
Model (Bits) (LSB) Range Package Description Option
AD5424YRU 8 ±0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-16
AD5424YRU-REEL 8 ± 0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5424YRU-REEL7 8 ±0.25 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5424YCP 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5424YCP-REEL 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5424YCP-REEL7 8 ±0.25 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YRU 10 ±0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YRU-REEL 10 ± 0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YRU-REEL7 10 ±0.5 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5433YCP 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YCP-REEL 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5433YCP-REEL7 10 ±0.5 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YRU 12 ±1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YRU-REEL 12 ± 1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YRU-REEL7 12 ±1 –40⬚C to +125⬚CTSSOP (Thin Shrink Small Outline Package) RU-20
AD5445YCP 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YCP-REEL 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
AD5445YCP-REEL7 12 ±1 –40⬚C to +125⬚C LFCSP (Chip Scale Package) CP-20
EVAL-AD5424EB Evaluation Kit
EVAL-AD5433EB Evaluation Kit
EVAL-AD5445EB Evaluation Kit
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5424/AD5433/AD5445 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD5424/AD5433/AD5445
PIN 1
INDICATOR
TOP VIEW
AD5424
1
GND
2
DB7
3
DB6
4
DB5
5
DB4
DB3 6
DB2 7
DB1 8
DB0 9
NC 10
15 R/W
14 CS
13 NC
12 NC
11 NC
20 I
OUT
2
19 I
OUT
1
18 R
FB
17 V
REF
16 V
DD
NC = NO CONNECT
PIN CONFIGURATIONS
I
OUT
I
OUT
GND
DB7
DB6
DB5
DB4
DB3
1
1
2
2
3
4
5
6
7
8
TSSOP
AD5424
(Not to Scale)
16
R
FB
15
V
REF
14
V
DD
13
R/W
12
CS
11
DB0 (LSB)
10
DB1
DB2
9
LFCSP
AD5424 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP LFCSP Mnemonic Function
119I
220I
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
31GND Ground
4–11 2–9 DB7–DB0 Parallel Data Bits 7 to 0.
10–13 NC No Internal Connection.
12 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
13 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use
with CS to readback contents of DAC register.
14 16 V
15 17 V
16 18 R
DD
REF
FB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
REV. 0–6–
PIN 1
INDICATOR
TOP VIEW
AD5433
1
GND
2
DB9
3
DB8
4
DB7
5
DB6
DB5 6
DB4 7
DB3 8
DB2 9
DB1 10
15 R/W
14 CS
13 NC
12 NC
11 DB0
20 I
OUT
2
19 I
OUT
1
18 R
FB
17 V
REF
16 V
DD
NC = NO CONNECT
PIN CONFIGURATIONS
AD5424/AD5433/AD5445
TSSOP
I
1
1
OUT
2
I
2
OUT
GND
DB9
DB8
DB7
DB6
DB5
DB4
DB3
AD5433
(Not to Scale)
3
4
5
6
7
8
9
10
NC = NO CONNECT
20
R
19
V
18
V
17
R/W
16
CS
NC
15
14
NC
DB0 (LSB)
13
12
DB1
11
DB2
FB
REF
DD
LFCSP
AD5433 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP LFCSP Mnemonic Function
119I
220I
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
31GND Ground
4–13 2–11 DB9–DB0 Parallel Data Bits 9 to 0.
14, 15 12, 13 NC Not Internally Connected.
16 14 CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
17 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use
with CS to readback contents of DAC register.
18 16 V
19 17 V
20 18 R
DD
REF
FB
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
REV. 0
–7–
AD5424/AD5433/AD5445
PIN 1
INDICATOR
TOP VIEW
AD5445
1
GND
2
DB11
3
DB10
4
DB9
5
DB8
DB7 6
DB6 7
DB5 8
DB4 9
DB3 10
15 R/W
14 CS
13 DB0
12 DB1
11 DB2
20 I
OUT
2
19 I
OUT
1
18 R
FB
17 V
REF
16 V
DD
PIN CONFIGURATIONS
I
OUT
I
OUT
GND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
1
1
2
2
3
4
5
6
7
8
9
10
TSSOP
AD5445
(Not to Scale)
20
R
19
V
REF
18
V
DD
17
R/W
16
CS
15
DB0 (LSB)
14
DB1
13
DB2
DB3
12
DB4
11
FB
LFCSP
AD5445 PIN FUNCTION DESCRIPTIONS
Pin No.
TSSOP LFCSP Mnemonic Function
119I
220I
1 DAC Current Output.
OUT
2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
OUT
31GND Ground Pin.
4–15 2–13 DB11–DB0 Parallel Data Bits 11 to 0.
16 14 CS Chip Select Input. Active low. Rising edge of CS loads data. Used in conjunction with R/W to
load parallel data to the input latch or to read data from the DAC register.
17 15 R/W Read/Write. When low, used in conjunction with CS to load parallel data. When high, use with
CS to readback contents of DAC register.
18 16 V
19 17 V
20 18 R
DD
REF
FB
Positive Power Supply Input. These parts can be operated from a supply of +2.5 V to +5.5 V.
DAC Reference Voltage Input Terminal.
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
REV. 0–8–
Typical Performance Characteristics–AD5424/AD5433/AD5445
0.20
TA = 25C
= 10V
V
0.15
REF
= 5V
V
DD
0.10
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
050100 150 250200
CODE
TPC 1. INL vs. Code (8-Bit DAC)
0.20
TA = 25C
= 10V
V
0.15
REF
= 5V
V
DD
0.10
0.05
0
DNL (LSB)
–0.05
–0.10
–0.15
–0.20
0
50
100
CODE
150
200
TPC 4. DNL vs. Code (8-Bit DAC)
250
0.5
TA = 25C
0.4
= 10V
V
REF
= 5V
V
DD
0.3
0.2
0.1
0
INL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 200 400 800600 1000
CODE
TPC 2. INL vs. Code (10-Bit DAC)
0.5
TA = 25C
0.4
0.3
0.2
0.1
–0.1
DNL (LSB)
–0.2
–0.3
–0.4
–0.5
= 10V
V
REF
= 5V
V
DD
0
0 200 400 800600 1000
CODE
TPC 5. DNL vs. Code (10-Bit DAC)
1.0
TA = 25C
0.8
0.6
0.4
0.2
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
= 10V
V
REF
= 5V
V
DD
0
0 500 1000 1500 2000 2500 3000 3500 4000
CODE
TPC 3. INL vs. Code (12-Bit DAC)
1.0
TA = 25C
0.8
= 10V
V
REF
= 5V
V
DD
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
0 500 1000 2000 2500 3000 35001500 4000
CODE
TPC 6. DNL vs. Code (12-Bit DAC)
0.6
0.5
0.4
0.3
0.2
0.1
INL (LSB)
0
–0.1
–0.2
–0.3
2345678910
MAX INL
MIN INL
REFERENCE VOLTAGE
TA = 25C
= 10V
V
REF
= 5V
V
DD
TPC 7. INL vs. Reference Voltage,
AD5445
–0.40
TA = 25C
= 10V
V
REF
= 5V
V
–0.45
DD
–0.50
–0.55
DNL (LSB)
–0.60
MIN DNL
–0.65
–0.70
2345678910
REFERENCE VOLTAGE
TPC 8. DNL vs. Reference Voltage,
AD5445
5
4
3
2
1
0
–1
ERROR (mV)
–2
–3
–4
V
–5
–60 –40 –20 0 20 40 60 80 100 120 140
REF
= 10V
VDD = 5V
VDD = 2.5V
TEMPERATURE (C)
TPC 9. Gain Error vs. Temperature
REV. 0
–9–
AD5424/AD5433/AD5445
2.0
1.5
LSB
–0.5
–1.0
–1.5
–2.0
1.0
0.5
0
MAX INL
MAX DNL
MIN INL
MIN DNL
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
V
BIAS
TPC 10. Linearity vs. V
Applied to I
0.5
0.4
0.3
0.2
0.1
0
–0.1
VOLTAGE (mV)
–0.2
–0.3
–0.4
–0.5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
2, AD5445
OUT
OFFSET ERROR
V
BIAS
TA = 25C
V
V
(V)
Voltage
BIAS
GAIN ERROR
TA = 25C
= 2.5V
V
REF
= 3V AND 5V
V
DD
(V)
TPC 13. Gain and Offset Errors
vs. V
Voltage Applied to I
BIAS
REF
DD
= 0V
= 3V
OUT
4
TA = 25C
3
= 2.5V
V
REF
= 3V
V
DD
2
1
0
LSB
–1
–2
–3
–4
–5
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
V
TPC 11. Linearity vs. V
Applied to I
3
TA = 25C
V
REF
V
DD
2
1
0
LSB
–1
–2
–3
0.5 1.0
= 0V
= 5V
MAX DNL
2, AD5445
OUT
MIN INL
MIN DNL
V
TPC 14. Linearity vs. V
2
Applied to I
2, AD5445
OUT
MAX INL
(V)
BIAS
MAX INL
1.5
BIAS
BIAS
(V)
BIAS
MAX DNL
MIN DNL
MIN INL
Voltage
2.0
Voltage
2.5
0.5
TA = 25C
0.4
0.3
0.2
0.1
–0.1
VOLTAGE (mV)
–0.2
–0.3
–0.4
–0.5
= 0V
V
REF
= 3V AND 5V
V
DD
0
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
V
OFFSET ERROR
(V)
BIAS
GAIN ERROR
TPC 12. Gain and Offset Errors
vs. V
LSB
TPC 15. Linearity vs. V
Applied to I
Voltage Applied to I
BIAS
4
TA = 25C
= 2.5V
V
3
REF
= 5V
V
DD
2
1
0
–1
–2
–3
–4
–5
0.5 1.0 1.5 2.0
MAX DNL
V
BIAS
2, AD5445
OUT
(V)
MIN DNL
MIN INL
Voltage
BIAS
OUT
MAX INL
2
8
7
6
5
4
3
CURRENT (mA)
2
1
0
1.00.50
VDD = 5V
VDD = 3V
VDD = 2.5V
INPUT VOLTAGE (V)
TA = 25C
4.54.03.53.02.52.01.5
5.0
TPC 16. Supply Current vs. Logic
Input Voltage (Driving DB0–DB11,
All Other Digital Inputs @ Supplies)
1.6
1.4
1.2
1.0
0.8
LEAKAGE (nA)
0.6
OUT
I
0.4
0.2
0
–40 –20 0 20 40 60 80 100 120
TPC 17. I
TEMPERATURE (C)
OUT
I
OUT1 VDD
I
3V
OUT1 VDD
1 Leakage Cur-
rent vs. Temperature
5V
0.50
0.45
0.40
0.35
0.30
0.25
0.20
CURRENT (A)
0.15
ALL 1s
0.10
0.05
0
–40
–60 –20 0 20 40 60 80 100 140
VDD = 5V
VDD = 2.5V
ALL 0s
TEMPERATURE (C)
TA = 25C
ALL 0s
ALL 1s
TPC 18. Supply Current vs.
Temperature
120
REV. 0–10–
AD5424/AD5433/AD5445
14
TA = 25C
LOADING ZS TO FS
12
10
VDD = 5V
8
(mA)
DD
6
I
4
VDD = 3V
VDD = 2.5V
2
0
110100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
TPC 19. Supply Current vs.
Update Rate
3
TA = 25C
= 5V
V
DD
AD5445
0
–3
GAIN (dB)
–6
V
= 2V, AD8038 CC 1.47pF
REF
= 2V, AD8038 CC 1pF
V
REF
= 0.15V, AD8038 CC 1pF
V
REF
= 0.15V, AD8038 CC 1.47pF
V
REF
= 3.51V, AD8038 CC 1.8pF
V
REF
–9
10k 100k 1M 10M 100M
FREQUENCY (Hz)
TPC 22. Reference Multiplying
Bandwidth vs. Frequency and
Compensation Capacitor
6
TA = 25C
LOADING
ZS TO FS
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ALL OFF
FREQUENCY (Hz)
V
REF
C
COMP
AD8038 AMPLIFIER
AD5445 DAC
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
GAIN (dB)
–60
–66
–72
–78
–84
–90
–96
–102
110100 1k 10k 100k 1M 10M 100M
TPC 20. Reference Multiplying
Bandwidth vs. Frequency and
Code
0.045
7FF TO 800H
0.040
0.035
0.030
VDD = 5V
0.025
0.020
0.015
0.010
0.005
OUTPUT VOLTAGE (V)
0
–0.005
–0.010
0 200
20 40 60 80 100 120 140 160 180
VDD = 3V
800 TO 7FFH
VDD = 3V
VDD = 5V
TIME (ns)
TA = 25C
= 0V
V
REF
AD8038 AMPLIFIER
= 1.8pF
C
COMP
TPC 23. Midscale Transition,
V
= 0 V
REF
TA = 25C
V
= 5V
DD
= 3.5V
INPUT
= 1.8pF
0.2
0
–0.2
GAIN (dB)
–0.4
TA = 25C
= 5V
V
DD
V
= 3.5V
REF
–0.6
–0.8
= 1.8pF
C
COMP
AD8038 AMPLIFIER
AD5445 DAC
110100 1k 10k 100k 1M 100M
FREQUENCY (Hz)
TPC 21. Reference Multiplying
Bandwidth—All Ones Loaded
–1.68
7FF TO 800H
–1.69
–1.70
VDD = 5V
–1.71
–1.72
–1.73
–1.74
–1.75
OUTPUT VOLTAGE (V)
–1.76
–1.77
20 40 60 80 100 120 140 160 180
0 200
VDD = 3V
VDD = 5V
TIME (ns)
VDD = 3V
TA = 25C
V
= 3.5V
REF
AD8038 AMPLIFIER
= 1.8pF
C
COMP
800 TO 7FFH
TPC 24. Midscale Transition,
V
= 3.5 V
REF
10M
20
TA = 25C
= 3V
V
DD
0
AMP = AD8038
–20
–40
–60
–80
FULL SCALE
ZERO SCALE
PSRR (dB)
–100
–120
110100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
TPC 25. Power Supply
Rejection vs. Frequency
REV. 0
–60
TA = 25C
= 3V
V
DD
= 3.5 V p-p
V
REF
–65
–70
–75
THD + N (dB)
–80
–85
–90
110100 1k 10k 100k 1M
FREQUENCY (Hz)
TPC 26. THD and Noise vs.
Frequency
–11–
100
MCLK = 1MHz
80
60
40
SFDR (dB)
MCLK = 200kHz
TA = 25C
= 3.5V
V
REF
AD8038 AMPLIFIER
AD5445
MCLK = 0.5MHz
20
0
0 200
20 40 60 80 100 120 140 160 180
f
OUT
(kHz)
TPC 27. Wideband SFDR vs.
f
Frequency
OUT
AD5424/AD5433/AD5445
90
MCLK = 5MHz
80
MCLK = 10MHz
70
60
50
MCLK = 25MHz
40
SFDR (dB)
30
20
10
0
0 1000
100 200 300 400 500 600 700 800 900
TA = 25C
V
REF
AD8038 AMPLIFIER
AD5445
f
(kHz)
OUT
= 3.5V
TPC 28. Wideband SFDR vs.
f
Frequency
OUT
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
05.0
0.5 1.0 1.5 4.0 4.52.0 2.5 3.0 3.5
FREQUENCY (MHz)
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 31. Wideband SFDR,
= 50 kHz, Clock = 10 MHz
f
OUT
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
012
246810
TPC 29. Wideband SFDR,
= 100 kHz, Clock = 25 MHz
f
OUT
0
–10
–20
–30
–40
–50
–60
SFDR (dB)
–70
–80
–90
–100
250 750
300 350 400 650 700
TPC 32. Narrow-Band Spectral
Response, f
Clock = 25 MHz
FREQUENCY (MHz)
TA = 25C
V
AMP = AD8038
AD5445
65k CODES
450 500 550 600
FREQUENCY (kHz)
= 500 kHz,
OUT
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
= 3V
DD
0
–10
–20
–30
–40
–50
–60
SFDR (dB)
–70
–80
–90
–100
05.0
0.5 1.0 1.5 4.0 4.5
2.0 2.5 3.0 3.5
FREQUENCY (MHz)
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 30. Wideband SFDR,
f
= 500 kHz, Clock = 10 MHz
OUT
20
0
–20
–40
–60
SFDR (dB)
–80
–100
–120
50 150
60 70 80 130 140
90 100 110 120
FREQUENCY (MHz)
TA = 25C
= 3V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 33. Narrow-Band SFDR,
= 100 kHz, MCLK = 25 MHz
f
OUT
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
200 700
250 300 350 600 650
400 450 500 550
FREQUENCY (MHz)
TA = 25C
= 3V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 34. Narrow-Band IMD,
= 400 kHz, 500 kHz,
f
OUT
Clock = 10 MHz
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
70 120
75 80 85 110 115
90 95 100 105
FREQUENCY (MHz)
TA = 25C
= 3V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 35. Narrow-Band IMD,
= 90 kHz, 100 kHz,
f
OUT
Clock = 10 MHz
0
–10
–20
–30
–40
–50
(dB)
–60
MCLK 10MHz
–70
–80
–90
–100
20 70
5V
V
DD
25 30 35 60 65
40 45 50 55
FREQUENCY (MHz)
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
TPC 36. Narrow-Band IMD,
= 40 kHz, 50 kHz,
f
OUT
Clock = 10 MHz
REV. 0–12–
AD5424/AD5433/AD5445
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
0 400
50 300 350
100 150 200 250
FREQUENCY (kHz)
TPC 37. Wideband IMD, f
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
OUT
90 kHz, 100 kHz, Clock = 25 MHz
=
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
4020
0 200
60 160 180
80 100 120 140
FREQUENCY (kHz)
TPC 38. Wideband IMD, f
TA = 25C
= 5V
V
DD
AMP = AD8038
AD5445
65k CODES
OUT
60 kHz, 50 kHz, Clock = 10 MHz
=
REV. 0
–13–
AD5424/AD5433/AD5445
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for 0 and full scale and is normally expressed in LSBs
or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
– 1 LSB. Gain error of
REF
the DACs is adjustable to 0 with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I
1 terminal, it
OUT
can be measured by loading all 0s to the DAC and measuring
the I
1 current. Minimum current will flow in the I
OUT
OUT
2 line
when the DAC is loaded with all 1s.
Output Capacitance
Capacitance from I
Output Current Settling Time
OUT
1 or I
2 to AGND.
OUT
This is the amount of time it takes for the output to settle to a
specified level for a full scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.
The settling time specification includes the digital delay from
CS rising edge to the full-scale output change.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs may be capacitively coupled through the
device to show up as noise on the I
pins and subsequently
OUT
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal, when all 0s are
OUT
loaded to the DAC.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms
sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonics are
included, such as second to fifth.
VVVV
+++
2232425
THD
=
20
Digital Intermodulation Distortion
()
log
V
1
2
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa – fb and
2fb – fa.
Spurious-Free Dynamic Range (SFDR)
It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and
the largest harmonically or nonharmonically related spur from
dc to full Nyquist bandwidth (half the DAC sampling rate, or
/2). Narrow band SFDR is a measure of SFDR over an arbi-
f
S
trary window size, in this case 50% of the fundamental. Digital
SFDR is a measure of the usable dynamic range of the DAC
when the signal is digitally generated sine wave.
REV. 0–14–
AD5424/AD5433/AD5445
DAC SECTION
The AD5424, AD5433, and AD5445 are 8-, 10- and 12-bit
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit AD5424
is shown in Figure 3. The matching feedback resistor R
FB
has a
value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If I
OUT
1 and I
are kept at the same
OUT2
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
is always constant and nominally of resistance value R.
at V
REF
The DAC output (I
) is code-dependent, producing various
OUT
resistances and capacitances. External amplifier choice should
take into account the variation in impedance generated by the
DAC on the amplifiers inverting input node.
V
REF
DAC DATA LATCHES
2RS12RS22R
AND DRIVERS
RRR
2RS82R
S3
R
A
R
FB
I
1
OUT
I
2
OUT
Figure 3. Simplified Ladder
Access is provided to the V
REF
, RFB, I
OUT
1 and I
2 terminals
OUT
of the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for example,
to provide a unipolar output, 4-quadrant multiplication in bipolar mode or in single-supply modes of operation. Note that a
matching switch is used in series with the internal R
resistor. If users attempt to measure R
to achieve continuity.
to V
DD
, power must be applied
FB
feedback
FB
PARALLEL INTERFACE
Data is loaded to the AD5424/33/45 in the format of an 8-, 10-, or
12-bit parallel word. Control lines CS and R/W allow data to be
written to or read from the DAC register. A write event takes place
when CS and R/W are brought low, data available on the data
lines fills the shift register, and the rising edge of CS latches the
data and transfers the latched data-word to the DAC register.
The DAC latches are not transparent, thus a write sequence must
consist of a falling and rising edge on CS to ensure data is loaded
to the DAC register and its analog equivalent reflected on the
DAC output.
A read event takes place when R/W is held high and CS is brought
low. Now data is loaded from the DAC register back to the input
register and out onto the data line where it can be read back to
the controller for verification or diagnostic purposes.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing as shown in Figure 4.
V
DD
V
DD
V
REF
R1
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
AD5424/
V
REF
AD5433/AD5445
DATA
INPUTS
CSR/W
R
GND
R2
FB
I
OUT
I
OUT
C1
1
2
AGND
A1
V
=
OUT
0 TO –V
REF
Figure 4. Unipolar Operation
When an output amplifier is connected in unipolar mode, the
output voltage is given by
VV
=×–
OUT REF
D
n
2
where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
D= 0 to 255 (8-Bit AD5424)
= 0 to 1023 (10-Bit AD5433)
= 0 to 4095 (12-Bit AD5445)
Note that the output voltage polarity is opposite to the V
REF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The V
power pin is only used
DD
by the internal digital logic to drive the DAC switches’ on
and off states.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 4 will
give a unipolar 0 V to –10 V output voltage swing. When V
is
IN
an ac signal, the circuit performs 2-quadrant multiplication.
Table I shows the relationship between digital code and expected
output voltage for unipolar operation. (AD5424, 8-bit device).
Table I. Unipolar Code Table
Digital Input Analog Output (V)
1111 1111 –V
1000 0000 –V
0000 0001 –V
0000 0000 –V
(255/256)
REF
(128/256) = –V
REF
(1/256)
REF
(0/256) = 0
REF
REF
/2
REV. 0
–15–
AD5424/AD5433/AD5445
REF
R1
V
REF
V
10V
V
DD
V
DD
AD5424/
AD5433/AD5445
CSR/W
R
GND
R3
10k
FB
I
OUT
I
OUT
R2
C1
1
2
A1
R4
10k
R5
20k
A2
V
= –V
REF
TO +V
REF
OUT
DATA
INPUTS
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.
3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.
= 0 V WITH CODE 10000000 LOADED TO DAC.
OUT
AGND
Figure 5. Bipolar Operation (4-Quadrant Multiplication)
Bipolar Operation
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing. This
can be easily accomplished by using another external amplifier and
some external resistors as shown in Figure 5. In this circuit, the
second amplifier A2 provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages
are created as the input data (D) is incremented from code
zero (V
(V
OUT
OUT
= +V
= –V
REF
) to midscale (V
REF
= 0 V ) to full scale
OUT
).
−21
VVD V
=×
()
OUT REF
n
−
REF
where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
D= 0 to 255 (8-Bit AD5424)
= 0 to 1023 (10-Bit AD5433)
= 0 to 4095 (12-Bit AD5445)
When V
is an ac signal, the circuit performs 4-quadrant
IN
multiplication.
Table II shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5426, 8-bit
device).
Stability
In the I-to-V configuration, the I
of the DAC and the invert-
OUT
ing node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP and there is excessive
parasitic capacitance at the inverting node. This parasitic capacitance introduces a pole into the open-loop response, which can
cause ringing or instability in closed-loop applications.
An optional compensation capacitor, C1, can be added in parallel
with R
for stability as shown in Figures 4 and 5. Too small a
FB
value of C1 can produce ringing at the output, while too large
a value can adversely affect the settling time. C1 should be
found empirically but 1 pF to 2 pF is generally adequate
for compensation.
Table II. Bipolar Code Table
Digital Input Analog Output (V)
1111 1111 +V
(127/128)
REF
1000 0000 0
0000 0001 –V
0000 0000 –V
(127/128)
REF
(128/128)
REF
REV. 0–16–
AD5424/AD5433/AD5445
SINGLE-SUPPLY APPLICATIONS
Current Mode Operation
Figure 6 shows a typical circuit for operation with a single 2.5 V to
5 V supply. In the current mode circuit of Figure 6, I
hence I
1 is biased positive by the amount applied to V
OUT
OUT2
and
BIAS
. In
this configuration, the output voltage is given by
VDRRVVV
=×
()
{}
OUT FB DAC BIAS IN BIAS
×−
()
+
As D varies from 0 to 255 (AD5424), 1023 (AD5433), or
4095 (AD5445), the output voltage varies from V
to V
V
= 2 V
OUT
should be a low impedance source capable of sinking and
BIAS
BIAS
– VIN.
sourcing all possible variations in current at the I
V
DD
C1
1
2
A1
BIAS
R
FB
I
OUT
I
OUT
V
DD
V
IN
V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
REF
DAC
GND
V
= V
OUT
2 terminal.
OUT
BIAS
V
OUT
Figure 6. Single-Supply Current Mode Operation
Voltage Switching Mode of Operation
Figure 7 shows these DACs operating in the voltage-switching
mode. The reference voltage, V
2 is connected to AGND; and the output voltage is avail-
I
OUT
able at the V
terminal. In this configuration, a positive
REF
, is applied to the I
IN
OUT
1 pin;
reference voltage results in a positive output voltage making
single-supply operation possible. The output from the DAC is
voltage at a constant impedance (the DAC ladder resistance),
thus an op amp is necessary to buffer the output voltage. The
reference input no longer sees a constant input impedance, but
one that varies with code. So, the voltage input should be driven
from a low impedance source.
It is important to note that V
is limited to low voltages be-
IN
cause the switches in the DAC ladder no longer have the same
source-drain drive voltage. As a result, their on resistance differs, which degrades the linearity of the DAC. See TPCs 10–15.
Also, V
must not go negative by more than 0.3 V or an inter-
IN
nal diode will turn on, exceeding the max ratings of the device.
In this type of application, the full range of multiplying capability of the DAC is lost.
V
DD
R
V
FB
V
IN
1
I
OUT
I
2
OUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
DAC
GND
DD
V
REF
R2R1
A1
V
OUT
Figure 7. Single-Supply Voltage Switching Mode Operation
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the V
REF
polarity for dc reference voltages. In order to achieve a positive
voltage output, an applied negative reference to the input of the
DAC is preferred over the output inversion through an inverting
amplifier because of the resistor tolerance errors. To generate a
negative reference, the reference can be level shifted by an op
amp such that the V
and GND pins of the reference become
OUT
the virtual ground and –2.5 V respectively, as shown in Figure 8.
VDD = 5V
ADR03
V
V
IN
OUT
GND
+5V
–2.5V
1/2 AD8552
–5V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
V
V
8-/10-/12-BIT DAC
REF
GND
R
DD
FB
I
OUT
I
OUT
1
2
C1
1/2 AD8552
V
=
OUT
0 TO +2.5V
Figure 8. Positive Voltage Output with Minimum
of Components
REV. 0
–17–
AD5424/AD5433/AD5445
ADDING GAIN
In applications where the output voltage is required to be greater
than V
, gain can be added with an additional external amplifier or
IN
it can also be achieved in a single stage. It is important to consider
the effect of temperature coefficients of the thin film resistors of
the DAC. Simply placing a resistor in series with the RFB resistor
will cause mismatches in the temperature coefficients resulting in
larger gain temperature coefficient errors. Instead, the circuit of
Figure 9 is a recommended method of increasing the gain of the
circuit. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
great than 1 are required.
V
DD
V
R1
V
IN
V
REF
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY
2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.
DD
8-/10-/12-BIT DAC
GND
R
FB
I
OUT
I
OUT
C1
1
2
R3
R2
V
OUT
GAIN = R2 + R3
R2
R1 = R2R3
R2 + R3
Figure 9. Increasing Gain of Current Output DAC
resistor as shown in Figure 10, then the output voltage is inversely
proportional to the digital input fraction D. For D = 1 – 2
n
the
output voltage is
−
VVDV
=− =− −
OUT IN IN
n
12
()
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
10H (00010000), i.e., 16 decimal, in the circuit of Figure 10
should cause the output voltage to be 16⫻ V
. However, if the
IN
DAC has a linearity specification of ±0.5 LSB then D can in
fact have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage will be in the range 15.5 V
to
IN
16.5 VIN—an error of +3% even though the DAC itself has a
maximum error of 0.2%.
V
V
IN
I
OUT
I
OUT
DD
R
V
FB
DD
1
2
GND
V
REF
V
OUT
USING DACS AS A DIVIDER OR A PROGRAMMABLE GAIN ELEMENT
Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R
is used as the input
FB
Figure 10. Current Steering DAC Used as a Divider
or Programmable Gain Element
NOTE
ADDITIONAL PINS OMITTED FOR CLARITY
Table III. Suitable ADI Precision References Recommended for Use with AD5424/AD5433/AD5445 DACs
Part No. Output Voltage Initial Tolerance Temperature Drift 0.1 Hz to 10 Hz Noise Package
ADR01 10 V 0.1% 3 ppm/°C 20 V p-p SC70, TSOT, SOIC
ADR02 5 V 0.1% 3 ppm/°C 10 V p-p SC70, TSOT, SOIC
ADR03 2.5 V 0.2% 3 ppm/°C 10 V p-p SC70, TSOT, SOIC
ADR425 5 V 0.04% 3 ppm/°C 3.4 V p-p MSOP, SOIC
Table IV. Some Precision ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Part No. Max Supply Voltage (V) V
(max) (V) IB (max) (nA) GBP (MHz) Slew Rate (V/s)
OS
OP97 ±20 25 0.1 0.9 0.2
OP1177 ±18 60 2 1.3 0.7
AD8551 ±650.05 1.5 0.4
Table V. Some High Speed ADI Op Amps Suitable for Use with AD5424/AD5433/AD5445 DACs
Max Supply Voltage BW @ A
CL
Slew Rate V
(max) IB (max)
OS
Part No. (V) (MHz) (V/s) (V) (nA)
AD8065 ±12 145 180 1500 0.01
AD8021 ±12 200 100 1000 1000
AD8038 ±5 350 425 3000 0.75
AD9631 ±5 320 1300 10000 7000
REV. 0–18–
AD5424/AD5433/AD5445
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction D of the current into the V
routed to the I
1 terminal, the output voltage has to change
OUT
terminal is
REF
as follows:
Output Error Voltage Due to DAC Leakage = (Leakage ⫻ R)/D
where R is the DAC resistance at the V
terminal. For a DAC
REF
leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of 16
the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD5424 series of
current output DACs, pay attention to the references output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0⬚C to 50⬚C
dictates that the maximum system drift with temperature should
be less than 78 ppm/⬚C. A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a
maximum drift of 10 ppm/⬚C. By choosing a precision reference
with low output temperature coefficient this error source can be
minimized. Table III suggests some references available from
Analog Devices that are suitable for use with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable gain (due to the code dependent output resistance of the
DAC) of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity error,
which if large enough, could cause the DAC to be nonmonotonic.
In general, the input offset voltage should be <1/4 LSB to ensure
monotonic behavior when stepping through codes.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor RFB. Most op amps have input bias currents
low enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage
switching circuits since it produces a code dependent error at the
voltage output of the circuit. Most op amps have adequate common
mode rejection for use at 8-, 10-, and 12-bit resolution.
Provided the DAC switches are driven from true wideband
low impedance sources (V
and AGND), they settle quickly.
IN
Consequently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is important
to minimize capacitance at the V
node (voltage output node
REF
in this application) of the DAC. This is done by using low
inputs capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
REV. 0
–19–
rail-to-rail signals; there is a large range of single-supply amplifiers
available from Analog Devices.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5424/AD5433/AD5445 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10 F in
parallel with 0.1 F on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 F capacitor should have low effective series resistance (ESR) and effective
series inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching. Low
ESR 1 F to 10 F tantalum or electrolytic capacitors should
also be applied at the supplies to minimize transient disturbance
and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane, while signal traces are
placed on the solder side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
and RFB should also be
REF
matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE AD5424/AD5433/AD5445
The board consists of a 12-bit AD5445 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows
the user to write a code to the device.
OPERATING THE EVALUATION BOARD
Power Supplies
The board requires ±12 V, and +5 V supplies. The +12 V V
DD
and VSS are used to power the output amplifier, while the +5 V
is used to power the DAC (V
) and transceivers (VCC).
DD1
Both supplies are decoupled to their respective ground plane
with 10 F tantalum and 0.1 F ceramic capacitors.
Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
AD5424/AD5433/AD5445
V
DD
V
SS
I
OUT
2
V
DD
R
FB
V
REF
TP2
V
DD
+V
IN
V
OUT
TRIM
GND
I
OUT
1
AD5424/AD5433/
AD5445
U1
U3
LK1
C8
0.1F
C7
4.7pF
C9
10F
C10
0.1F
C3
10F
C4
0.1F
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
P2–3
P2–2
P2–1
P2–4
AGND
V
SS
V
DD
1
V
DD
C13
0.1F
C14
10F
C15
0.1F
C16
10F
C17
0.1F
C18
10F
+
P2–6
P2–5
C19
0.1F
C20
10F
+
+
+
U2
ADR01AR
4
5
2
6
J1
7
4
3
2
6
V–
V+
+
C11
10F
C12
0.1F
+
TP1
R1
V
DD
1
C5
10F
C6
0.1F
+
DB0
15
DB1
14
DB7
8
DB8
7
DB9
6
DB10
5
DB11
4
CS
16
RW
17
DB6
9
DB5
10
DB4
11
DB3
12
DB2
13
3
AB
17
18
13
14
22
21
20
19
23
23
15
16
5
6
12
11
10
9
8
7
2
1
3
4
B5
B4
OEAB
LEAB
B0
B1
B2
B3
CEBA
B7
B6
A2
A3
GND
CEAB
A7
A6
A5
A4
OEBA
LEBA
A0
A1
5
6
12
11
10
9
8
7
2
1
3
4
B5
B4
OEAB
LEAB
B0
B1
B2
B3
CEBA
B7
B6
A2
A3
GND
CEAB
A7
A6
A5
A4
OEBA
LEBA
A0
A1
R2
10k
V
CC
R3
10k
V
CC
R4
10k
V
CC
R5
10k
V
CC
V
CC
VCC
V
CC
VCC
P1–36
P1–31
P1–8
P1–1
P1–14
P1–7
P1–6
P1–5
P1–4
P1–3
P1–2
P1–9
A–B (MSB)
B–A (MSB)
A–B (LSB)
B–A (LSB)
J4
J3
J2
EXTERNAL
REFERENCE
OUTPUT
C2 0.1F
C1 0.1F
U5
U4
74ABT543
74ABT543
V
CC
17
18
13
14
22
21
20
19
23
24
15
16
GND
DB0
DB1
DB7
DB8
DB9
DB10
DB11
CS
R/W
DB6
DB5
DB4
DB3
DB2
18
20
1
2
19
Figure 11. Evaluation Board Schematic
REV. 0–20–
P1
C1
R2
R4
U5
R3
DB10
DB8
R5
DB6
DB4
C2
DB2
DB0
U4
J4
CS
C20
EVAL-AD5424/
AD5433/AD5445EB
Figure 12. Silkscreen—Component Side View
DB11
DB9
DB7
DB5
DB3
DB1
CS RW
J3
R/W
C19
VCC
U3
U1
C10
R1
C6
C5
TP2
J2
C18 C14 C16
C17
VDD
VDD1
DGND
C12
TP1
LK1
C7
C8
C13
AGND
EXT
VREF
U2
VSS
C15
P2
J1
OUTPUT
C4
C3
AD5424/AD5433/AD5445
REV. 0
–21–
AD5424/AD5433/AD5445
Table VI. Bill of Materials for AD5424/AD5433/AD5445 Evaluation Board
Name Part Description Value Tolerance PCB Decal Stock Code
C1, C2, C4,
C6, C8 X7R Ceramic Capacitor 0.1 F 10% 0603 FEC 499-675
C10, C12, C13,
C15 X7R Ceramic Capacitor 0.1 F 10% 0603 FEC 499-675
C3, C5, C9,
C11, C14 Tantalum Capacitor – Taj Series 10 F 20 V 10% CAP\TAJ_B FEC 197-427
C17, C19 X7R Ceramic Capacitor 0.1 F 10% 0603 FEC 499-675
C16, C18, C20 Tantalum Capacitor – Taj Series 10 F 10 V 10% CAP\TAJ_A FEC 197-130
C7 X7R Ceramic Capacitor 4.7 pF 10% 0603
CS TESTPOINT TESTPOINT FEC 240-345 (Pack)
DB0–DB11 Red Testpoint TESTPOINT FEC 240-345 (Pack)
J1–J4 SMB Socket SMB FEC 310-682
LK1 3-Pin Header (3 ⫻ 1) LINK-3P- FEC 511-717 and 150-411
P1 36-Pin Centronics Connector 36WAY FEC 147-753
P2 6-Pin Terminal Block CON\POWER6 FEC 151-792
R1 0.063 W Resistor 0603 Not Inserted
R2, R3, R4, R5 0.063 W Resistor 10 kΩ 1% 0603 FEC 911-355
RW, TP1, TP2 Red Testpoint TESTPOINT FEC 240-345 (Pack)
U1 AD5445 TSSOP20 AD5445BRU
U2* ADR425/ADR01/ADR02/ADR03 SO8NB ADR01AR
U3* AD8065 SO8NB AD8065AR
U4 74ABT543 TSSOP24 Fairchild 74ABT543CMTC
U5 74ABT543 TSSOP24 Fairchild 74ABT543CMTC
Each Corner Rubber Stick-on Feet FEC 148-922
*See section on Amplifier and Reference Selection
FEC - Farnell Electronic Components, Units 4 and 5 Gofton Court, Jamestown Road, Finglas, Dublin 11, Ireland. Tel. Int +353 (0)1 8309277
www.farnell.com
REV. 0–22–
AD5424/AD5433/AD5445
Overview of AD54xx Devices
Part No. Resolution No. DACs INL tS max Interface Package Features
AD5403* 82± 0.25 60 ns Parallel CP-40 10 MHz Bandwidth,
10 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5410* 81± 0.25 100 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5413* 82± 0.25 100 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5424 8 1 ± 0.25 60 ns Parallel RU-16, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5425 8 1 ± 0.25 100 ns Serial RM-10 Byte Load, 10 MHz Bandwidth,
50 MHz Serial
AD5426 8 1 ± 0.25 100 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5428 8 2 ± 0.25 60 ns Parallel RU-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5429 8 2 ± 0.25 100 ns Serial RU-10 10 MHz Bandwidth, 50 MHz Serial
AD5450 8 1 ± 0.25 100 ns Serial RJ-8 10 MHz Bandwidth, 50 MHz Serial
AD5404* 10 2 ±0.5 70 ns Parallel CP-40 10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5411* 10 1 ±0.5 110 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5414* 10 2 ±0.5 110 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5432 10 1 ±0.5 110 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5433 10 1 ±0.5 70 ns Parallel RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5439 10 2 ±0.5 110 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial
AD5440 10 2 ±0.5 70 ns Parallel RU-24 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5451 10 1 ±0.25 110 ns Serial RJ-8 10 MHz Bandwidth, 50 MHz Serial
AD5405 12 2 ±1 120 ns Parallel CP-40 10 MHz Bandwidth,
17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors
AD5412* 12 1 ±1 160 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5415 12 2 ±1 160 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,
4-Quadrant Multiplying Resistors
AD5443 12 1 ±1 160 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5445 12 1 ±1 120 ns Parallel RU-20, CP-20 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5447 12 2 ±1 120 ns Parallel RU-24 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5449 12 2 ±1 160 ns Serial RU-16 10 MHz Bandwidth,
17 ns CS Pulse Width
AD5452 12 1 ±0.5 160 ns Serial RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial
AD5453 14 1 ±2 180 ns Serial RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial
*Future parts, contact factory for availability
REV. 0
–23–
AD5424/AD5433/AD5445
OUTLINE DIMENSIONS
16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
5.10
5.00
4.90
0.15
0.05
4.50
4.40
4.30
PIN 1
16
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153AB
0.10
0.30
0.19
9
81
1.20
MAX
6.40
BSC
SEATING
PLANE
0.20
0.09
0.75
8
0
0.60
0.45
20-Lead Lead Frame Chip Scale Package [LFCSP]
Dimensions shown in millimeters
COPLANARITY
(CP-20)
20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
6.60
6.50
6.40
0.15
0.05
PIN 1
0.10
20
1
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AC
0.65
BSC
11
10
1.20
MAX
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8
0
0.75
0.60
0.45
C03160–0–10/03(0)
PIN 1
INDICATOR
1.00
0.90
0.80
SEATING
PLANE
4.0
BSC SQ
TOP
VIEW
12 MAX
0.80 MAX
0.65 NOM
0.50
BSC
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
0.20
REF
3.75
BSC SQ
0.05
0.02
0.00
0.60
MAX
0.75
0.55
0.35
COPLANARITY
0.08
0.60
MAX
16
15
11
10
BOTTOM
VIEW
0.30
0.23
0.18
20
1
2.25
2.10 SQ
1.95
5
6
0.25 MIN
–24–
REV. 0
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