Analog Devices AD5415 Datasheet
Dual 12-Bit, High Bandwidth, Multiplying DAC
with 4-Quadrant Resistors and Serial Interface
FEATURES
On-chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to +125°C
24-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
SYNC
SCLK
SDIN
SDO
LDAC
DD
AD5415
SHIFT
REGISTER
REGISTER
GENERAL DESCRIPTION
The AD54151 is a CMOS 12-bit, dual-channel, current output
digital-to-analog converter. This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered applications as well as many other applications.
The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor
) provides temperature tracking and full-scale voltage
(R
FB
output when combined with an external current-to-voltage
precision amplifier. In addition, this device contains all the
4-quadrant resistors necessary for bipolar operation and other
configuration modes.
This DAC utilizes a double-buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros, and the DAC outputs
are at zero scale. As a result of manufacture on a CMOS submicron process, this part offers excellent 4-quadrant multiplication
characteristics, with large-signal multiplying bandwidths of
10 MHz.
1
US Patent Number 5,689,257.
R3A R2_3A R2A V
R32RR2
2R
INPUT
DAC
REGISTER
A R1A
REF
12-BIT
R-2R DAC A
AD5415
) determines
REF
R
R1
FB
2R
2R
R
I
I
OUT
OUT
A
FB
1A
2A
INPUT
REGISTER
R3B R2_3B R2B V
CLR
GND
POWER-ON
RESET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
R3
2R
Figure 1.
I
1B
DAC
REGISTER
R2
2R
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
12-BIT
R-2R DAC B
R12RR
2R
B R1B
REF
www.analog.com
OUT
I
2B
OUT
R
B
FB
FB
04461-0-001
AD5415
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 17
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r m in o l o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
General Description ....................................................................... 15
DAC Section................................................................................ 15
Unipolar Mode............................................................................ 15
Bipolar Operation....................................................................... 16
Stability ........................................................................................ 16
Single-Supply Applications............................................................ 17
Voltage Switching Mode of Operation .................................... 17
Positive Output Voltage ............................................................. 17
Adding Gain................................................................................ 17
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Serial Interface ................................................................................ 20
Low Power Serial Interface ....................................................... 20
Control Register ......................................................................... 20
SYNC
Function........................................................................... 21
Daisy-Chain Mode..................................................................... 21
Standalone Mode........................................................................ 21
LDAC
Function .......................................................................... 21
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling................................ 24
Evaluation Board for the DAC ................................................. 24
Power Supplies for the Evaluation Board................................ 24
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
AD5415
SPECIFICATIONS
Temperature range for Y Version: −40°C to +125°C.
= 2.5 V to 5.5 V, V
V
DD
DC performance measured with OP1177, ac performance with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Gain Error ±25 mV
Gain Error Temperature Coefficient1 ±5 ppm FSR/°C
Bipolar Zero Code Error ±25 mV
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I
±10 nA Data = 0x0000, I
REFERENCE INPUT1 Typical Resistor TC = −50 ppm/°C
Reference Input Range ±10 V
V
A, V
REF
V
REF
B Input Resistance 8 10 12 kΩ DAC input resistance
REF
A to V
B Input Resistance
REF
Mismatch
R1, RFB Resistance 16 20 24 kΩ
R2, R3 Resistance 16 20 24 kΩ
R2 to R3 Resistance Mismatch 0.06 0.18 % Typ = 25°C, Max = 125°C
DIGITAL INPUTS/OUTPUT1
Input High Voltage, V
Input Low Voltage, V
0.7 V VDD = 2.5 V to 2.7 V
Input Leakage Current, IIL 1 µA
Input Capacitance 10 pF
VDD = 4.5 V to 5.5 V
Output Low Voltage, V
Output High Voltage, V
VDD = 2.5 V to 3.6 V
Output Low Voltage, V
Output High Voltage, VOH V
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time 90 160 ns
Digital Delay 20 40 ns
Digital-to-Analog Glitch Impulse 3 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error −75 dB DAC latch loaded with all 0s, reference = 10 kHz
Output Capacitance 2 pF DAC latches loaded with all 0s
4 pF DAC latches loaded with all 1s
Digital Feedthrough 5 nV-s
Total Harmonic Distortion −75 dB V
−75 dB V
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
= 10 V, I
REF
IH
IL
2A, I
OUT
2B = 0 V; all specifications T
OUT
MIN
to T
, unless otherwise noted.
MAX
OUT
1
OUT
1
1.6 2.5 % Typ = 25°C, Max = 125°C
1.7 V VDD = 2.5 V to 5.5 V
0.8 V VDD = 2.7 V to 5.5 V
OL
OH
OL
0.4 V I
V
− 1 V I
DD
0.4 V I
− 0.5 V I
DD
= 200 µA
SINK
= 200 µA
SOURCE
= 200 µA
SINK
= 200 µA
SOURCE
= 5 V p-p, DAC loaded all 1s
REF
Measured to ±4 mV of FS; R
= 100 Ω, C
LOAD
LOAD
=
0s, 15 pF, DAC latch alternately loaded with 0s
and 1s
= 0 V
REF
Feedthrough to DAC output with
CS high and
alternate loading of all 0s and all 1s
= 5 V p-p, all 1s loaded, f = 1 kHz
REF
= 5 V, sine wave generated from digital code
REF
Rev. 0 | Page 3 of 28
AD5415
Parameter Min Typ Max Unit Conditions
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
SFDR Performance (Narrow-Band)
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
I
DD
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%
55 dB
63 dB
65 dB
50 dB
60 dB
62 dB
73 dB
80 dB
87 dB
70 dB
75 dB
80 dB
10 µA Logic inputs = 0 V or VDD
1
Guaranteed by design and characterization, not subject to production test.
Rev. 0 | Page 4 of 28
AD5415
TIMING CHARACTERISTICS
Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
V
= 2.5 V to 5.5 V, V
DD
= 5 V, I
REF
2 = 0 V. All specifications T
OUT
Table 2.
Parameter Limit at T
f
50 MHz max Maximum clock frequency
SCLK
MIN
, T
Unit Conditions/Comments
MAX
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min
t5 5 ns min Data setup time
t6 4 ns min Data hold time
t7 5 ns min
t8 30 ns min
t9 0 ns min
t10 12 ns min
t11 10 ns min
2
t
12
25 ns min SCLK active edge to SDO valid, strong SDO driver
60 ns min SCLK active edge to SDO valid, weak SDO driver
) and timed from a voltage level of (VIL + VIH)/2.
DD
MIN
to T
, unless otherwise noted.
MAX
1
SYNC falling edge to SCLK falling edge setup time
SYNC rising edge to SCLK falling edge
Minimum
SCLK falling edge to
SYNC high time
LDAC falling edge
LDAC pulse width
SCLK falling edge to
LDAC rising edge
1
Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in . Figure 4
t
1
SCLK
SYNC
LDAC
LDAC
DIN
t
t
4
t
8
t
6
t
5
DB15
1
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
2
Figure 2. Standalone Mode Timing Diagram
t
3
t
7
DB0
t
10
t
9
t
11
04461-0-002
Rev. 0 | Page 5 of 28
AD5415
t
1
SCLK
t
t
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
4
DB15
(N)
t
6
t
5
2
t
3
DB15
DB0
(N+1)
(N)
t
12
DB15
(N)
DB0
(N+1)
DB0
(N)
t
7
t
8
04461-0-003
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200µAI
TO OUTPUT
PIN
C
L
50pF
200µAI
Figure 4. Load Circuit for SDO Timing Specifications
OL
VOH (MIN) + VOL (MAX)
OH
2
04461-0-004
Rev. 0 | Page 6 of 28
AD5415
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
= 25°C, unless otherwise noted.
T
A
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
, RFB to GND −12 V to +12 V
REF
I
1, I
OUT
2 to GND −0.3 V to +7 V
OUT
Input Current to Any Pin except Supplies ±10 mA
Logic Inputs and Output
Operating Temperature Range
Extended (Y Version)
1
−0.3 V to VDD + 0.3 V
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
24-Lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering
(10 seconds)
IR Reflow, Peak Temperature
(<20 seconds)
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Overvoltages at SCLK,
Current should be limited to the maximum ratings given.
, and DIN are clamped by internal diodes.
SYNC
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
AD5415
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
I
OUT
I
OUT
R
FB
R1A
R2A
R2_3A
R3A
V
REF
GND
LDAC
SCLK
SDIN
1A
2A
A
A
1
2
3
4
5
AD5415
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
24
1B
I
OUT
23
I
2B
OUT
22
R
B
FB
21
R1B
20
R2B
19
R2_3B
18
R3B
17
V
B
REF
16
V
DD
15
CLR
14
SYNC
13
SDO
04461-0-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1 I
2 I
1A DAC A Current Output.
OUT
OUT
2A
DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
3 RFBA
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
4–7 R1A–R3A
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
8 V
A DAC A Reference Voltage Input Pin.
REF
9 GND Ground Pin.
10
LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge
11 SCLK
when the device is in standalone mode or on the rising edge of
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
SYNC when in daisy-chain mode.
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
12 SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
13 SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
14
SYNC
Active Low Control Input. The frame synchronization signal for the input data. When
the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift
register on the 16th active clock edge.
15
CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware
CLR pin as a clear to zero scale or midscale, as required.
16 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
17 V
18–21 R1B–R3B
B DAC B Reference Voltage Input Pin.
REF
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum of external components.
22 RFBB
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
23 I
OUT
2B
DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
24 I
1B DAC B Current Output.
OUT
SYNC goes low, it powers on
Rev. 0 | Page 8 of 28
AD5415
(
(
)
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale, and is normally expressed
in LSB or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference in the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
− 1 LSB. Gain error of the
REF
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when they are turned off. For the I
1 terminal, it can
OUT
be measured by loading all 0s to the DAC and measuring the
1 current. Minimum current flows in the I
I
OUT
2 line when
OUT
the DAC is loaded with all 1s.
Digital Crosstalk
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed
in nV-s.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
LDAC
(all 0s to all 1s and vice versa), while keeping
LDAC
pulse
low and monitor the output of the DAC whose
high. Then
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel-to-Channel Isolation
The proportion of input signal from one DAC reference input
that appears at the output of the other DAC and is expressed
in dB.
Harmonic Distortion
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the total harmonic distortion (THD). Usually only the lowerorder harmonics are included, such as second to fifth.
Output Capacitance
Capacitance from I
OUT
1 or I
2 to AGND.
OUT
Output Current Settling Time
The amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is
specified with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs is capacitively coupled through the
device to show up as noise on the I
pins and subsequently
OUT
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal when all 0s are
OUT
loaded to the DAC.
THD
2
2
log20
=
4
3
V
1
)
VVVV
+++
5
2
2
2
Intermodulation Distortion
The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at sum
and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ...
Intermodulation terms are those for which m or n is not equal
to zero. The second-order terms include (fa + fb) and (fa − fb)
and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa +
2fb) and (fa − 2fb). IMD is defined as
IMD log20=
productsdistortiondiffandsumtheofsumrms
lfundamentatheofamplituderms
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. 0 | Page 9 of 28
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