Analog Devices AD5383 a Datasheet

32-Channel, 3 V/5 V, Single-Supply,

FEATURES

Guaranteed monotonic
INL error: ±1 LSB max
On-chip 1.25 V/2.5 V, 10 ppm/°C reference
Temperature range: –40°C to +85°C
Rail-to-rail output amplifier
Power-down mode
Package type: 100-lead LQFP (14 mm × 14 mm)
User Interfaces

Parallel
Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,

featuring data readback)

2

C®-compatible

I

FUNCTIONAL BLOCK DIAGRAM

PD

SER/PAR

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

DB11/(DIN/SDA)

DB10/(SCLK/SCL)

DB9/(SPI/I

REG 0

REG 1

RESET

MON_IN1
MON_IN2
MON_IN3
MON_IN4

2

DB8

DB0

BUSY

CLR

A4
A0

(×3)

DV

DD

DGND (×3)

AD5383

MACHINE

CONTROL

31

OUT

FIFO

+

STATE

+

LOGIC

C)

INTERFACE

CONTROL

LOGIC

POWER-ON

RESET

V

0………V

OUT

36-TO-1

MUX

AVDD (×4)

INPUT
REG 0

12
12

INPUT
REG 1

12
12

INPUT
REG 6

12
12

INPUT
REG 7

12
12

12-Bit, Voltage Output DAC

AD5383

INTEGRATED FUNCTIONS

Channel monitor
Simultaneous output update via

Clear function to user-programmable code
Amplifier boost mode to optimize slew rate
User programmable offset and gain adjust
Toggle mode enables square wave generation
Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA)
Level setting (ATE)
Optical microelectro-mechanical systems (MEMS)
Control systems
Instrumentation

AGND (×4) DAC GND (×4) REFGND REFOUT/REFIN SIGNAL GND (×4)

1.25V/2.5V

REFERENCE

1212 1212

m REG 0

c REG 0

m REG 1

c REG 1

m REG 6

c REG 6

m REG 7

c REG 7

×4

DAC

REG 0

DAC

REG 1

DAC

REG 6

DAC

REG 7

DAC 0

1212 1212

DAC 1

1212 1212

DAC 6

1212 1212

DAC 7

LDAC

R

R

R

R

R

R

R

R

V

0

OUT

V

1

OUT

V

2

OUT

V

3

OUT

V

4

OUT

V

5

OUT

V

6

OUT

V

7

OUT

V

8

OUT

V

31

OUT

MON_OUT LDAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

03734-001

AD5383

TABLE OF CONTENTS

General Description......................................................................... 3

Asynchronous Clear Function.................................................. 25

Specifications..................................................................................... 4

AD5383-5 Specifications............................................................. 4

AD5383-3 Specifications............................................................. 6

AC Characteristics........................................................................ 7

Timing Characteristics..................................................................... 8

Serial Interface Timing................................................................ 8

2

I

C Serial Interface Timing........................................................ 10

Parallel Interface Timing........................................................... 11

Absolute Maximum Ratings.......................................................... 13

ESD CAUTION ..........................................................................13

Pin Configuration and Function Descriptions........................... 14

Terminology ....................................................................................17

Typical Performance Characteristics ...........................................18

Functional Description.................................................................. 21

DAC Architecture—General..................................................... 21

BUSY

FIFO Operation in Parallel Mode............................................ 25

Power-On Reset.......................................................................... 25

Power-Down ............................................................................... 25

Interfaces.......................................................................................... 26

DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26

2

I

C Serial Interface ..................................................................... 28

Parallel Interface......................................................................... 30

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 33

Power Supply Decoupling......................................................... 33

Typical Configuration Circuit ..................................................33

Channel Monitor Function....................................................... 34

Toggle Mode Function............................................................... 34

Thermal Monitor Function....................................................... 34

and

LDAC

Functions...................................................... 25

Data Decoding............................................................................ 21

On-Chip Special Function Registers (SFR) ............................22

SFR Commands.......................................................................... 22

Hardware Functions....................................................................... 25

Reset Function ............................................................................25

REVISION HISTORY

3/05 — Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 3............................................................................ 6

Change to Table 5 .............................................................................7

Change to Table 18......................................................................... 24

5/04 — Revision 0: Initial Version

Optical Attenuators.................................................................... 35

Utilizing the FIFO...................................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Rev. A | Page 2 of 40

AD5383

GENERAL DESCRIPTION

The AD5383 is a complete, single-supply, 32-channel, 12-bit
DAC available in a 100-lead LQFP package. All 32 channels
have an on-chip output amplifier with rail-to-rail operation.
The AD5383 includes a programmable internal 1.25 V/2.5 V,
10 ppm/°C reference; an on-chip channel monitor function that
multiplexes the analog outputs to a common MON_OUT pin
for external monitoring; and an output amplifier boost mode
that allows optimization of the amplifier slew rate. The AD5383
features

• Double-buffered parallel interface with a 20 ns

width.

WR

pulse

• SPI-/QSPI-/MICROWIRE-/DSP-compatible serial

interface with interface speeds in excess of 30 MHz.

2

• I

C-compatible interface that supports a 400 kHz data

transfer rate.

An input register followed by a DAC register provides double
buffering, allowing the DAC outputs to be updated indepen­dently or simultaneously using the

Each channel has a programmable gain and offset adjust
register that allows the user to fully calibrate any DAC channel.
With boost off, power consumption is typically 0.25 mA/channel.

Table 1 and Table 2 show additional products featuring high
channel count, low voltage, single-supply operation, and bipolar
voltage output operation.

LDAC

input.

Table 1. Other H l n olt D liigh Channe

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100
AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100
AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100
AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100
AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100
AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100
AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100
AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100
AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52
AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64
AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52
AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64
AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64
AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52
AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64
AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52
AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64
AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52
AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64

Cou t, Low V age, Single-Supply AC Products in Portfo

ion

arity Error (LSB)

o

ption Model Resolut AVDD Range Output Channels Line Package Descri Package Option

Table 2. 40-Ch ar Aannel, Bipol

AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108

Voltage Output D C

ion

ls Model Resolut Analog Supplies Output Channe Linearity Error (LSB) Package Package Option

Rev. A | Page 3 of 40

AD5383

SPECIFICATIONS

AD5383-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T
otherwise noted.

Table 3.

Parameter AD5383-51 Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy2 (INL) ±1 LSB max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error ±4 mV max
Offset Error ±4 mV max Measured at Code 32 in the linear region
Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.06 % FSR max T

MIN

to T

MAX

Gain Temperature Coefficient3 2 ppm FSR/°C typ
DC Crosstalk3 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±10 µA max Typically ±30 nA
Reference Range 1 to VDD/2 V min/max

Reference Output4

Enabled via CR8 in the AD5383 control register,
CR10 selects the reference voltage

Output Voltage 2.495/2.505 V min/max At ambient; optimized for 2.5 V operation; CR10 = 1

1.22/1.28 V min/max 1.25 V reference selected; CR10 = 0
Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C
±15 ppm/°C max Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS3

Output Voltage Range2 0/AVDD V min/max
Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 5.5 V

VIH, Input High Voltage 2 V min
VIL, Input Low Voltage 0.8 V max
Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus compatible at DVDD < 3.6 V
VIL, Input Low Voltage 0.3 DVDD V max SMBus compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MAX

MIN

to T

MAX

, unless

Rev. A | Page 4 of 40

AD5383

Parameter AD5383-51 Unit Test Conditions/Comments

LOGIC OUTPUTS (

BUSY

, SDO)3
VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA
VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA
VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 4.5/5.5 V min/max
DVDD 2.7/5.5 V min/max
Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ
DIDD 1 mA max VIH = DVDD, VIL = DGND
AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 3 µA
Power Dissipation 65 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V

1

AD5383-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5383-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5383 control register; operating the AD5383-5 with a 1.25 V reference leads to degraded

accuracy specifications.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

Rev. A | Page 5 of 40

AD5383

AD5383-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T
otherwise noted.

Table 4.

Parameter AD5383-31 Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits
Relative Accuracy2 (INL) ±1 LSB max
Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error 4 mV max
Offset Error ±4 mV max Measured at Code 64 in the linear region
Offset Error TC ±5 µV/°C typ
Gain Error ±0.024 % FSR max At 25°C
±0.1 % FSR max T

MIN

to T

MAX

Gain Temperature Coefficient3 2 ppm FSR/°C typ
DC Crosstalk3 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 1.25 V ±1% for specified performance
DC Input Impedance 1 MΩ min Typically 100 MΩ
Input Current ±10 µA max Typically ±30 nA
Reference Range 1 to AVDD/2 V min/max

Reference Output4

Enabled via CR8 in the AD5383 control register,
CR10 selects the reference voltage

Output Voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0

2.47/2.53 V min/max 2.5 V reference enabled; CR10 = 1
Reference TC ±10 ppm/°C typ Temperature range: +25°C to +85°C
±15 ppm/°C typ

Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS3

Output Voltage Range2 0/AVDD V min/max
Short-Circuit Current 40 mA max
Load Current ±1 mA max
Capacitive Load Stability

RL = ∞ 200 pF max
RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ
Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 3.6 V

VIH, Input High Voltage 2 V min
V

Input Low Voltage 0.8 V max

IL,

Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

MAX

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V
VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V
IIN, Input Leakage Current ±1 µA max
V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ
Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MIN

to T

MAX

, unless

Rev. A | Page 6 of 40

AD5383

Parameter AD5383-31 Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max Sinking 200 µA
VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA
High Impedance Leakage Current ±1 µA max SDO only
High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I
Three-State Leakage Current ±1 µA max
Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 2.7/3.6 V min/max
DVDD 2.7/5.5 V min/max
Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ
DIDD 1 mA max VIH = DVDD, VIL = DGND.
AIDD (Power-Down) 2 µA max Typically 200 nA
DIDD (Power-Down) 20 µA max Typically 1 µA
Power Dissipation 39 mW max Outputs unloaded, boost off; AVDD = DVDD = 3 V

1

AD5383-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.

2

Accuracy guaranteed from V

3

Guaranteed by characterization, not production tested.

4

Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference leads to degraded

accuracy specifications and limited input code range.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

AC CHARACTERISTICS1

AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 5.

Parameter All Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time2 ¼ scale to ¾ scale change settling to ±1 LSB
6 µs typ
8 µs max
Slew Rate2 2 V/µs typ Boost mode off, CR9 = 0
3 V/µs typ Boost mode on, CR9 = 1
Digital-to-Analog Glitch Energy 12 nV-s typ
Glitch Impulse Peak Amplitude 15 mV typ
DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section
Digital Crosstalk 0.8 nV-s typ
Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test
Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC
40 µV p-p typ Internal reference, midscale loaded to DAC
Output Noise Spectral Density

@ 1 kHz 150 nV/√Hz typ
@ 10 kHz 100 nV/√Hz typ

1

Guaranteed by design and characterization, not production tested.

2

The slew rate can be programmed via the current boost control bit (CR9) in the AD5383 control register.

Rev. A | Page 7 of 40

AD5383

T

TIMING CHARACTERISTICS

SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
noted.

MIN

to T

, unless otherwise

MAX

Table 6.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK high time
t3 13 ns min SCLK low time
t4 13 ns min

4

t

13 ns min

5

4

t

33 ns min

6

t7 10 ns min
t7A 50 ns min

SYNC

falling edge to SCLK falling edge setup time

SYNC

24th SCLK falling edge to
Minimum

Minimum
Minimum

SYNC low time
SYNC high time
SYNC high time in readback mode

falling edge

t8 5 ns min Data setup time
t9 4.5 ns min Data hold time

4

t

30 ns max

10

t11 670 ns max

4

t

20 ns min

12

t13 20 ns min
t14 100 ns max
t15 0 ns min
t16 100 ns min

24th SCLK falling edge to
BUSY

pulse width low (single channel update)
24th SCLK falling edge to
LDAC

pulse width low
BUSY

rising edge to DAC output response time
BUSY

rising edge to
LDAC

falling edge to DAC output response time

BUSY

LDAC

LDAC

falling edge

falling edge

falling edge

t17 8 µs typ DAC output settling time, boost mode off
t18 20 ns min

t

35 µs max

19

5

t

20 ns max SCLK rising edge to SDO valid

20

5

t

5 ns min

21

5

t

8 ns min

22

t23 20 ns min

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with t

3

See , F , and . Figure 2 igure 3 Figure 4, Figure 5

4

Standalone mode only.

5

Daisy-chain mode only.

= t

= 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V.

r

f

CLR

pulse width low

CLR

pulse activation time

SCLK falling edge to
SYNC

rising edge to SCLK rising edge
SYNC

rising edge to

SYNC

LDAC

rising edge

falling edge

O OUTPUT PIN

C

L

50pF

200µA

200µA

I

OL

V

(MIN) OR

OH

V

(MAX)

OL

I

OH

03734-002

Figure 2. Load Circuit for SDO Timing Diagram

(Serial Interface, Daisy- Chain Mode)

Rev. A | Page 8 of 40

AD5383

t

1

SCLK

SYNC

BUSY

LDAC

V

OUT

LDAC

V

OUT

CLR

V

DIN

1
1

2

2

OUT

t

1

LDAC ACTIVE DURING BUSY

2

LDAC ACTIVE AFTER BUSY

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

t

3

t

4

t

6

t8t

7

DB23

9

t

18

t

2

t

5

DB0

t

10

t

11

t

t

19

t

12

13

t

15

2424

t

17

t

14

t

13

t

17

t

16

03734-003

SYNC

DIN

SDO

SCLK

SYNC

DIN

SDO

24 48SCLK

t

7A

DB23 DB0 DB23 DB0

INPUT WORD SPECIFIES

REGISTER TO BE READ

UNDEFINED

DB23 DB0

NOP CONDITION

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t

1

t

t

7

t

4

t8t

DB23 DB0 DB0DB23

INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1

t

9

2

3

t

20

DB23 DB0

t

21

03734-004

4824

t

22

UNDEFINED INPUT WORD FOR DAC N

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

t

13

t

23

03734-005

Rev. A | Page 9 of 40

AD5383

I2C SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
noted.

MIN

to T

, unless otherwise

MAX

Table 7.

Parameter

F

SCL

1, 2

Limit at T

, T

Unit Description

MIN

MAX

400 kHz max SCL clock frequency
t1 2.5 µs min SCL cycle time
t2 0.6 µs min t
t3 1.3 µs min t
t4 0.6 µs min t
t5 100 ns min t

3

t

0.9 µs max t

6

0 µs min t
t7 0.6 µs min t
t8 0.6 µs min t
t9 1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

, data setup time

SU,DAT

, data hold time

HD,DAT

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a STOP and a START condition

BUF

t10 300 ns max tR, rise time of SCL and SDA when receiving
0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t11 300 ns max tF, fall time of SDA when transmitting
0 ns min tF, fall time of SDA when receiving (CMOS-compatible)
300 ns max tF, fall time of SCL and SDA when receiving
20 + 0.1 C

4

ns min tF, fall time of SCL and SDA when transmitting

b

Cb 400 pF max Capacitive load for each bus line

1

Guaranteed by design and characterization, not production tested.

2

See . Figure 6

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

falling edge.

4

Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

min of the SCL signal) in order to bridge the undefined region of SCL’s

IH

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

Figure 6. I

t

2

C-Compatible Serial Interface Timing Diagram

t

11

2

t

5

REPEATED

CONDITION

t

7

START

t

4

t

1

t

8

STOP

CONDITION

03734-006

Rev. A | Page 10 of 40

AD5383

PARALLEL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
noted.

MIN

to T

, unless otherwise

MAX

Table 8.

Parameter

t0 4.5 ns min
t1 4.5 ns min
t2 20 ns min
t3 20 ns min
t4 0 ns min
t5 0 ns min
t6 4.5 ns min
t7 4.5 ns min
t8 20 ns min

4

t

700 ns min

9

4

t

30 ns max

10

4, 5

t

11

t12 30 ns min
t13 20 ns min
t14 100 ns max
t15 20 ns min
t16 0 ns min
t17 100 ns min

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

670 ns max

REG0, REG1, address to
REG0, REG1, address to
CS

pulse width low

WR

pulse width low

CS

to WR falling edge setup time

WR

to CS rising edge hold time

Data to WR rising edge setup time

WR

Data to
WR

Minimum
WR

BUSY
WR
LDAC
BUSY
LDAC
BUSY
LDAC

rising edge hold time

pulse width high

WR

cycle time (single-channel write)

rising edge to

BUSY

pulse width low (single-channel update)

rising edge to

LDAC

pulse width low

rising edge to DAC output response time

rising edge to WR rising edge

rising edge to

LDAC

falling edge to DAC output response time
t18 8 µs max DAC output settling time
t19 20 ns min

t20 35 µs max

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

3

See . Figure 7

4

See . Figure 29

5

Measured with the load circuit of . Figure 2

CLR

pulse width low

CLR

pulse activation time

WR

rising edge setup time

WR

rising edge hold time

falling edge

falling edge

falling edge

Rev. A | Page 11 of 40

AD5383

t

t

0

1

REG0, REG1, A4..A0

CS

WR

DB11..DB0

BUSY

LDAC

V

OUT

LDAC

V

OUT

CLR

V

OUT

1

1

2

2

t

4

t

5

t

2

t

9

t

3

t

6

t

t

t

8

t

t

7

10

t

11

t

12

19

t

13

t

20

15

t

18

t

14

t

16

t

13

t

18

t

17

1

LDAC ACTIVE DURING BUSY

2

LDAC ACTIVE AFTER BUSY

03734-007

Figure 7. Parallel Interface Timing Diagram

Rev. A | Page 12 of 40