ANALOG DEVICES AD5174 Service Manual

Single-Channel, 1024-Position, Digital Rheostat

V

FEATURES

Single-channel, 1024-position resolution
10 kΩ nominal resistance
50-times programmable (50-TP) wiper memory
Rheostat mode temperature coefficient: 35 ppm/°C

2.7 V to 5.5 V single-supply operation
±2.5 V to ±2.75 V dual-supply operation for ac or bipolar

operations
SPI-compatible interface
Wiper setting and memory readback
Power on refreshed from memory
Resistor tolerance stored in memory
Thin LFCSP 10-lead, 3 mm × 3 mm× 0.8 mm package
Compact MSOP, 10-lead, 3 mm × 4.9 mm × 1.1 mm package

APPLICATIONS

Mechanical rheostat replacements
Op-amp: variable gain control
Instrumentation: gain, offset adjustment
Programmable voltage-to-current conversions
Programmable filters, delays, time constants
Programmable power supply
Sensor calibration

with SPI Interface and 50-TP Memory

AD5174

FUNCTIONAL BLOCK DIAGRAM

DD

POWER-ON

SCLK

SYNC

DIN

SDO

RESET

SPI

SERIAL

INTERFACE

V

SS

REGISTER

10

50-TP

MEMORY

BLOCK

EXT_CAP GND

Figure 1.

AD5174

RDAC

A

W

08718-001

GENERAL DESCRIPTION

The AD5174 is a single-channel, 1024-position digital rheostat
that combines industry leading variable resistor performance
with nonvolatile memory (NVM) in a compact package.

This device supports both dual-supply operation at ±2.5 V to
±2.75 V and single-supply operation at 2.7 V to 5.5 V and offers
50-times programmable (50-TP) memory.

The AD5174 device wiper settings are controllable through the
SPI digital interface. Unlimited adjustments are allowed before
programming the resistance value into the 50-TP memory. The
AD5174 does not require any external voltage supply to facili­tate fuse blow and there are 50 opportunities for permanent
programming. During 50-TP activation, a permanent blow fuse
command freezes the resistance position (analogous to placing
epoxy on a mechanical rheostat).

The AD5174 is available in a 3 mm × 3mm 10-lead LFCSP
package and in a 10-lead MSOP package. The part is guaranteed
to operate over the extended industrial temperature range of

−40°C to +125°C.

Rev. B

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AD5174

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Interface Timing Specifications.................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Test Circuits..................................................................................... 11

Theory of Operation ...................................................................... 12

Serial Data Interface................................................................... 12

Shift Register............................................................................... 12

RDAC Register............................................................................ 12

50-TP Memory Block ................................................................ 12

Write Protection ......................................................................... 12

RDAC and 50-TP Read Operation .......................................... 13

Shutdown Mode ......................................................................... 14

Reset ............................................................................................. 14

SDO Pin and Daisy-Chain Operation..................................... 15

RDAC Architecture.................................................................... 16

Programming the Variable Resistor......................................... 16

EXT_CAP Capacitor.................................................................. 17

Terminal Voltage Operating Range ......................................... 17

Power-Up Sequence ................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

12/10—Rev. A to Rev. B

Changes to SDO Pin Description................................................... 7

Changes to SDO Pin and Daisy-Chain Operation Section....... 15

7/10—Rev. 0 to Rev. A

Changes to Daisy-Chain Operation Section including Changing

Title to SDO Pin and Daisy-Chain Operation Section ............. 15

Added Table 11 ...............................................................................15

Changes to Ordering Guide.......................................................... 18

3/10—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5174

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V; −40°C < TA < 125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resolution 10 Bits

Resistor Integral Nonlinearity

|VDD − VSS| = 3.3 V to 3.6 V −1 +1.5 LSB

|VDD − VSS| = 2.7 V to 3.3 V −2.5 +2.5 LSB
Resistor Differential Nonlinearity2 R-DNL
Nominal Resistor Tolerance ±15 %
Resistance Temperature Coefficient
Wiper Resistance Code = zero scale 35 70 Ω

RESISTOR TERMINALS

Terminal Voltage Range
Capacitance A4 f = 1 MHz, measured to GND, code = half scale 90 pF
Capacitance W4 f = 1 MHz, measured to GND, code = half scale 40 pF
Common-Mode Leakage Current4 V

DIGITAL INPUTS

Input Logic4

High V

Low V
Input Current IIN ±1 μA
Input Capacitance4 C

DIGITAL OUTPUT

Output Voltage4

High VOH R

Low VOL R
V
V
Tristate Leakage Current −1 +1 μA
Output Capacitance4 5 pF

POWER SUPPLIES

Single-Supply Power Range VSS = 0 V 2.7 5.5 V
Dual-Supply Power Range ±2.5 ±2.75 V
Supply Current

Positive IDD 1 μA

Negative ISS −1 μA
50-TP Store Current

Positive I

Negative I
50-TP Read Current

4, 8

Positive I

Negative I
Power Dissipation9 P
Power Supply Rejection Ratio4 PSRR ΔVDD/ΔVSS = ±5 V ± 10% −50 −55 dB

2, 3

R-INL |VDD − VSS| = 3.6 V to 5.5 V −1 +1 LSB

4, 5

Code = full scale 35 ppm/°C

4, 6

V

4, 7

V

TERM

= VW 50 nA

A

2.0 V

INH

0.8 V

INL

5 pF

IN

= 2.2 kΩ to VDD V

PULL_UP

= 2.2 kΩ to VDD

PULL_UP

= 2.7 V to 5.5 V, VSS = 0 V 0.4 V

DD

= 2.5 V to 2.75 V, VSS = −2.5 V to −2.75 V 0.6 V

DD

DD_OTP_STORE

SS_OTP_STORE

4 mA

−4 mA

−1 +1 LSB

V

SS

− 0.1 V

DD

V

DD

DD_OTP_READ

SS_OTP_READ

DISS

500 μA

−500 μA

VIH = VDD or VIL = GND 5.5 μW

Rev. B | Page 3 of 20

AD5174

Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB, RAW = 5 kΩ, Terminal W, see Figure 24 700 kHz
Total Harmonic Distortion VA = 1 V rms, f = 1 kHz, RAW = 5 kΩ −90 dB
Resistor Noise Density RWB = 5 kΩ, TA = 25°C, f = 10 kHz 13 nV/√Hz

1

Typical specifications represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions.

3

The maximum current in each code is defined by IAW = (VDD − 1)/RAW.

4

Guaranteed by design and not subject to production test.

5

See Figure 9 for more details.

6

Resistor Terminal A and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar

signal adjustment.

7

Different from operating current; the supply current for the fuse program lasts approximately 55 ms.

8

Different from operating current; the supply current for the fuse read lasts approximately 500 ns.

9

P

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

10

All dynamic characteristics use VDD = +2.5 V, VSS = −2.5 V.

INTERFACE TIMING SPECIFICATIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V; VDD = 2.5 V, VSS = −2.5 V; all specifications T

Table 2.

Parameter Limit1 Unit Test Conditions/Comments

2

t

20 ns min SCLK cycle time

1

t2 10 ns min SCLK high time
t3 10 ns min SCLK low time
t4 15 ns min

t5 5 ns min Data setup time
t6 5 ns min Data hold time
t7 1 ns min

3

t

400 ns min

8

t9 15 ns min

4

t

450 ns max SCLK rising edge to SDO valid

10

t

MEMORY_READ

t

MEMORY_PROGRAM

t

RESET

t

POWER-UP

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 50 MHz.

3

Refer to t

4

R

PULL_UP

5

Maximum time after VDD − VSS is equal to 2.5 V.

6 μs max Memory readback execute time

350 ms max Memory program time

600 μs max Reset OTP restore time

5

2 ms max Power-on 50-TP restore time

and

MEMORY_READ

= 2.2 kΩ to VDD with a capacitance load of 168 pF.

t

MEMORY_PROGRAM

4, 10

to SCLK falling edge setup time

SYNC

SCLK falling edge to SYNC
Minimum SYNC

rising edge to next SCLK fall ignored

SYNC

for memory commands operations.

MIN

high time

to T

rising edge

, unless otherwise noted.

MAX

Rev. B | Page 4 of 20

AD5174

Shift Register and Timing Diagrams

DB9 (MSB) DB0 (LSB)

C0C1

D9

D7 D6 D5 D4 D3

D8

DATA BITS

Figure 2. Shift Register Content

t

5

D2 D1

t

6

D0

08718-002

t

7

t

9

SCLK

SYNC

DIN

C3

00

t

4

t

8

t

2

t

3

0 0 C3 C2 D7 D6 D5 D2 D1 D0

C2

CONTROL BITS

t

1

SDO

SCLK

SYNC

DIN

SDO

Figure 3. Write Timing Diagram, CPOL=0, CPHA = 1

00 00C3 C3

X X C3 D1 D0

Figure 4. Read Timing Diagram, CPOL=0, CPHA = 1

08718-003

t

9

D1 D0D0 D0

t

10

08718-004

Rev. B | Page 5 of 20

AD5174

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW to GND VSS − 0.3 V, VDD + 0.3 V
Digital Input and Output Voltage to GND −0.3 V to VDD + 0.3 V
EXT_CAP to VSS 7 V
IA, IW

Pulsed1

Frequency > 10 kHz ±6 mA/d2
Frequency ≤ 10 kHz ±6 mA/√d2

Continuous ±6 mA
Operating Temperature Range3 −40°C to +125°C
Maximum Junction Temperature

(T

Maximum)

J

150°C

Storage Temperature Range −65°C to +150°C
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation (TJ max − TA)/θJA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A and W terminals at a given
resistance.

2

Pulse duty factor.

3

Includes programming of 50-TP memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is defined by JEDEC specification JESD-51 and the value is
dependent on the test board and test environment.

Table 4. Thermal Resistance

Package Type θ

10-Lead LFCSP 50 3 °C/W
10-Lead MSOP 135 N/A °C/W

1

JEDEC 2S2P test board, still air (0 m/sec airflow).

ESD CAUTION

1

θJC Unit

JA

Rev. B | Page 6 of 20