Analog Devices AD5061 prc Datasheet

16 Bit 4LSB Vout nanoDacTM,

Buffered, 3V/5V, Sot 23

Preliminary Technical Data

FEATURES

Single 16-Bit DAC, 4 Lsb inl.

1.8 Volt Digital Interface Capability
Power-On-Reset to Zero Volts/Mid Scale
Three Power-Down Functions
Low Power Serial Interface with Schmitt­Triggered Inputs
8-Lead Sot23
Low Power Operation
Fast Settling.
Low Glitch on Powerup.

APPLICATIONS

Process Control
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

GENERAL DESCRIPTION

The AD5061, a member of the nanoDAC

TM

family, is a single
16-bit buffered voltage out DAC, available in a 8 ld Sot23. The
AD5061 can be operated at 3V/5V.

The part utilizes a versatile three-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI™, MICROWIRE™ and DSP interface
standards.

The reference for the AD5061 is supplied from an external
REF pin. A reference buffer is also provided on chip. The parts
incorporate a power-on-reset circuit that ensures that the DAC
output powers up to zero volts/ mid scale and remains there
until a valid write takes place to the device. The parts also
contain a power-down feature that reduces the current
consumption of the device to 50nA at 5 V and provides
software selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
Total unadjusted error for the part is <1mV.

AD5061

Part Number Description

AD5062

AD5063

2.7 V to 5.5 V, 16 Bit
Unbuffered, Sot 23.

2.7 V to 5.5 V, 16 Bit
Unbuffered, 10 uSOIC, uncommitted bi-polar resistors.

AD5040/60

2.7 V to 5.5 V, 14/16 Bit
INL, Buffered, Sot23.

PRODUCT HIGHLIGHTS

1. Available in 8-lead SOT23.

2. 16 Bit Accurate, 4 LSB INL.

3. Low Glitch on Power-up.

4. High speed serial interface with clock speeds up to 30 MHz.

5. Three power down modes available to the user.

nano

nano

nano

AD5061

TM

DAC

TM

DAC

DAC

D/A, 1LSBs INL.,

D/A, 1 LSBs INL.,

TM

D/A, 1 LSBs

These parts also provide a very low glitch on power-up.

Rev. PrC

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

Rev. PrC | Page 1 of 17

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Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

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AD5061 Preliminary Technical Data

AD5061—SPECIFICATIONS1

AD5061, VDD = 5.5V, Vref =4.096V, RL=5k, 200pF . T

Parameter B Version1

Min Typ Max

STATIC PERFORMANCE

AD5061
Resolution 16 Bits
Relative Accuracy ±4 LSB
TUE 0.5 mV
Differential Nonlinearity ±1 LSB Guaranteed Monotonic by Design.

Offset Error +/-0.125 % of FSR
Zero Code Error +/-0.2 mv Code 160 loaded to dac reg
Full scale Error +/-0.01 LSB All 1’s loaded to dac reg

Gain Error +/-0.04 % of FSR
Offset Drift 6 µV/°C
Gain Temperature Coefficient 2.5 ppm of FSR/°C
OUTPUT CHARACTERISTICS

Output Voltage Range

0 V
Output Voltage Settling Time 10 µs 1/4 to 3/4 to +/-1lsb
Slew Rate 1 V/µs
Capacitive Load Stability 470 pF RL=
1000 pF RL = 5K
Output Noise Spectral Density

50

50
Digital-to-Analog Glitch

5 nV-s 1 LSB Change Around Major Carry.
Impulse

Digital Feedthrough 0.5 nV-s
DC Output Impedance 1

REFERENCE INPUT/OUPUT

Vref Input Range

2 V
Input Current 1
DC Input Impedance 1

LOGIC INPUTS

Input Current ±1 µA

V

, Input Low Voltage

INL

V

, Input High Voltage

INH

V

, Input Low Voltage

INL

V

, Input High Voltage

INH

0.8 V

1.8 V

0.6 V

1.4 V

Pin Capacitance 3 pF

POWER REQUIREMENTS

VDD
I

(Normal Mode)

DD

VDD = +2.7 V to +3.6 V
IDD (All Power-Down Modes)

2.7 3.6 V AD5060 (3 Volt Option)

DAC Active and Excluding Load Current

900 µA

VDD
I

(Normal Mode)

DD

5.0 5.5 V AD5060 (5 Volt Option)

DAC Active and Excluding Load Current

MIN

to T

; unless otherwise noted.

MAX

-150mV

ref

DD-100mV

Unit Test Conditions/Comments

V

DAC code=TBD , 1kHz

DAC code=TBD , 10kHz

nV/√Hz

nV/√Hz

Ω

V

uA
MΩ

VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V

VIH = VDD and VIL = GND

Rev. PrC | Page 2 of 17

Preliminary Technical Data AD5040/AD5060

Parameter B Version1

Min Typ Max

VDD = +5.0 V to +5.5 V
IDD (All Power-Down Modes)

1.3 mA

VDD
I

(Normal Mode)

DD

VDD = +2.7 V to +5.5 V
IDD (All Power-Down Modes)

2.7 5.5 V AD5040
DAC Active and Excluding Load Current

50 nA

PSSR 0.5 LSB VDD +/- 10%

NOTES
1

Temperature ranges are as follows: B Version: –40°C to +125°C, typical at 25°C.

2

Guaranteed by design and characterization, not production tested.
3 Linearity calculated using a reduced code range 480-64716.
Specifications subject to change without notice.

Unit Test Conditions/Comments

VIH = VDD and VIL = GND

VIH = VDD and VIL = GND

Rev. PrC | Page 3 of 17

AD5061 Preliminary Technical Data

TIMING CHARACTERISTICS

(VDD = 2.7-5.5 V; all specifications T

Parameter Limit1 Unit Test Conditions/Comments

3

t

1

t2
t3
t4
t5
t6
t7
t8
t9

NOTES
1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

See Figure 1.

3

Maximum SCLK frequency is 30 MHz.

Specifications subject to change without notice.

to T

MIN

unless otherwise noted)

MAX

33 ns min SCLK Cycle Time

13 ns min SCLK High Time
12 ns min SCLK Low Time
13 ns min

SYNC to SCLK Falling Edge Setup Time

5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min
33 ns min
13 ns min

SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Rising Edge to next SCLK Fall

Ignore

.

Figure 1. Timing DiagramAD506. AD5040 has same timing specs with 14 bit Word.

Rev. PrC | Page 4 of 17

Preliminary Technical Data AD5040/AD5060

ABSOLUTE MAXIMUM RATINGS

Table 1. Absolute Maximum Ratings (TA = 25°C unless otherwise noted)

Parameter Rating

VDD to GND –0.3 V to + 7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
V

to GND1 –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (B Version) –40°C to +125°C
Storage Temperature Range –65°C to +150°C
Maximum Junction Temperature 150°C
SOT23 Package
Power Dissipation (Tj Max-Ta)/ θJA
θJA Thermal Impedance 229.6°C/W
θJC Thermal Impedance 91.99°C/W

Lead Temperature, Soldering
Vapour Phase (60 Sec) 300°C
Infrared (15 Sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be
taken for handling and assembly.

Model Temperature

INL Description Package Options

Range

O

AD5061BRJ-1
AD5061BRJ-2

AD5061BRJ-3

C to 125 OC

-40

O

C to 125 OC

-40

O

C to 125 OC

-40

4 LSB 5V, Buffered DAC in SOT-23, Reset to Zero
4 LSB 5V, Buffered DAC in SOT-23, Reset to Mid

4 LSB 3V, Buffered DAC in SOT-23, Reset to Zero

RT8

RT8

RT8

Rev. PrC | Page 5 of 17

AD5061 Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION
DESCRIPTION

Table 2. Pin Function Descriptions

1

DIN

AD5061

VDD

2

TOP VIEW

(Not to Scale)

REF

3

V

OUT

4

Figure 2. AD5062 8 ld SOT23

Mnemonic Function

VDD Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and VDD should be decoupled to GND.
REF Reference Voltage Input.
DacGND Ground input to the DAC.
V

OUT

Analog output voltage from DAC.

Level triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes low,

SYNC

it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated

following the 16th clock cycle unless SYNC is taken high before this edge in which case the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the DAC.

SCLK

DIN

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates up to 30 MHz.

Serial Data Input. This device has a 24 bit shift register. Data is clocked into the register on the falling edge of the serial clock
input.

AGND Ground reference point for Analog circuitry on the part.

8

SYNC

7

DacGND

6

5

SCLK

AGND

Rev. PrC | Page 6 of 17