ANALOG DEVICES AD5061 Service Manual

16-Bit V

A

nanoDAC

OUT

™

SPI Interface 2.7 V to 5.5 V, in an SOT-23

FEATURES

Single 16-bit DAC, 4 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
Small 8-lead SOT-23 package, low power
Fast settling time of 4 μs typically

2.7 V to 5.5 V power supply
Low glitch on power-up

interrupt facility

SYNC

APPLICATIONS

Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators

GENERAL DESCRIPTION

The AD5061, a member of ADI’s nanoDAC family, is a low
power, single 16-bit buffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of ±4 LSB and operation is guaranteed
monotonic with a ±1 LSB DNL specification. The part uses a
versatile 3-wire serial interface that operates at clock rates
up to 30 MHz, and is compatible with standard SPI®, QSPI™,
MICROWIRE™, and DSP interface standards. The reference for
the AD5061 is supplied from an external V
buffer is also provided on-chip. The part incorporates a power­on reset circuit that ensures the DAC output powers up to mid­scale or zero scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
330 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <3 mV. This part exhibits very low glitch on power-up.

pin. A reference

REF

AD5061

FUNCTIONAL BLOCK DIAGRAM

V

REF

POWER-ON

RESET

DAC

REGISTER

INPUT

CONTROL

LOGIC

SCLK DIN

SYNC DACGND

BUF

REF(+)

DAC

POWER-DOWN

CONTROL LO GIC

Figure 1.

Table 1. Related Devices

Part No. Description

AD5062

2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23

AD5063

2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP

AD5040/AD5060

2.7 V to 5.5 V, 14-bit/16-bit nanoDAC D/A,
1 LSB INL, SOT-23

PRODUCT HIGHLIGHTS

1. Available in a small 8-lead SOT-23 package.

2. 16-bit resolution, 4 LSB INL.

3. Low glitch on power-up.

4. High speed serial interface with clock speeds up to 30 MHz.

5. Three power-down modes available to the user.

6. Reset to known output voltage (midscale or zero scale).

V

DD

OUTPUT
BUFFER

AD5061

RESISTOR
NETWORK

V

OUT

GND

04762-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005–2011 Analog Devices, Inc. All rights reserved.

AD5061

TABLE OF CONTENTS

Features.............................................................................................. 1

Reference Buffer ......................................................................... 15

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Product Highlights........................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Terminology .................................................................................... 14

Theory of Operation ......................................................................15

DAC Architecture....................................................................... 15

Serial Interface............................................................................ 15

Input Shift Register .................................................................... 15

SYNC

Interrupt ..........................................................................15

Power-On to Zero-Scale or Midscale ...................................... 16

Software Reset............................................................................. 16

Power-Down Modes .................................................................. 16

Microprocessor Interfacing....................................................... 16

Applications..................................................................................... 18

Choosing a Reference ................................................................18

Bipolar Operation....................................................................... 18

Using a Galvanically-Isolated Interface Chip......................... 19

Power Supply Bypassing and Grounding................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

5/11—Rev. A to Rev. B

Changes to Data Sheet Title and Product Highlights Section.... 1

Changes to Ordering Guide.......................................................... 20

1/06—Rev. 0 to Rev. A

Changes to General Description .................................................... 1

Changes to Table 2............................................................................ 3

Changes to Figure 19 Caption....................................................... 10

Added Figure 28 to Figure 36........................................................12

Changes to Serial Interface Section.............................................. 15

Changes to Power-Down Modes Section.................................... 16

Changes to Ordering Guide.......................................................... 20

7/05—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5061

SPECIFICATIONS

VDD = 5.5 V, V

Table 2.

B Grade1
Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 16 Bits
Relative Accuracy (INL)2 ±0.5 ±4 LSB −40°C to +85°C, B grade
±0.5 ±4 −40°C to +125°C, Y grade
Total Unadjusted Error (TUE) ±0.5 ±3.0 mV −40°C to +85°C, B grade
±0.5 ±3.0 −40°C to +125°C, Y grade
Differential Nonlinearity (DNL) ±0.5 ±1 LSB Guaranteed monotonic, −40°C to +85°C, B grade
±0.5 ±1

Gain Error ±0.01 ±0.05 % of FSR TA = −40°C to +85°C, B grade
±0.01 ±0.05 TA = −40°C to +125°C , Y grade
Gain Error Temperature Coefficient 1 ppm of FSR/°C
Offset Error ±0.02 ±3.0 mV TA = −40°C to + 85°C, B grade
±0.02 ±3.0 TA = −40°C to + 125°C, Y grade
Offset Error Temperature Coefficient 0.5 µV/°C
Full-Scale Error ±0.05 ±3.0 mV

±0.05 ±3.0

OUTPUT CHARACTERISTICS3

Output Voltage Range 0 V
Output Voltage Settling Time 4 µs

Output Noise Spectral Density 64
Output Voltage Noise 6 µV p-p DAC code = midscale , 0.1 Hz to 10 Hz bandwidth

Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, RL = 5 KΩ
Digital Feedthrough 0.003 nV-s DAC code = full-scale
DC Output Impedance (Normal) 0.015 Ω Output impedance tolerance ±10%
DC Output Impedance (Power-Down)

(Output Connected to 1 kΩ Network) 1 kΩ Output impedance tolerance ±400 Ω
(Output Connected to 100 kΩ Network) 100 kΩ Output impedance tolerance ±20 kΩ

Capacitive Load Stability 1 nF Loads used: RL = 5 kΩ, RL = 100 kΩ, RL = ∞
Output Slew Rate 1.2 V/s

Short-Circuit Current 60 mA

45 mA

DAC Power-Up Time

DC Power Supply Rejection Ratio −92 dB VDD ±10%, DAC code = full-scale
Wideband Spurious-Free Dynamic Range −67 dB Output frequency = 10 kHz

REFERENCE INPUT/OUTPUT

V

Input Range4 2 V

REF

Input Current (Power-Down) ±0.1 µA Zero-scale loaded
Input Current (Normal) ±0.5 µA
DC Input Impedance 1 MΩ

= 4.096 V, RL = unloaded, CL= unloaded, T

REF

MIN

to T

, unless otherwise specified.

MAX

V

REF

nV/√Hz

− 50 mV

DD

Guaranteed monotonic, −40°C to +125°C,
Y grade

All 1s loaded to DAC register,
TA = −40°C to +85°C, B grade

All 1s loaded to DAC register,

= −40°C to +125°C , Y grade

T

A

¼ scale to ¾ scale code transition to ±1LSB,

= 5 KΩ

R

L

DAC code = midscale, 1 kHz

¼ scale to ¾ scale code transition to ±1 LSB,
R

= 5 kΩ, CL = 200 pF

L

DAC code = full-scale, output shorted to GND,

= 25°C

T

A

DAC code = zero-scale, output shorted to V

= 25°C

T

A

Time to exit power-down mode to normal
mode of AD5061, 24

th

clock edge to 90% of

DD

DAC final value, output unloaded

,

Rev. B | Page 3 of 20

AD5061

B Grade1
Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

Input Current5 ±1 ±5 μA
Input Low Voltage (VIL) 0.8 V VDD = 4.5 V to 5.5 V

0.8 VDD = 2.7 V to 3.6 V
Input High Voltage (VIH) 2.0 V VDD = 2.7 V to 5.5 V

1.8 VDD = 2.7 V to 3.6 V
Pin Capacitance 4 pF

POWER REQUIREMENTS

VDD 2.7 5.5 V All digital inputs at 0 V or VDD
IDD (Normal Mode) DAC active and excluding load current
VDD = 2.7 V to 5.5 V 1.0 1.2 mA

0.89

IDD (All Power-Down Modes)

VDD = 2.5 V to 5.5 V 1 μA

0.265

1

Temperature range for B grade: −40°C to +85°C, typical at 25°C; temperature range for Y grade: −40°C to +125°C.

2

Linearity calculated using a reduced code range (160 to 65535).

3

Guaranteed by design and characterization, not production tested.

4

The typical output supply headroom performance for various reference voltages at −40°C can be seen in Figure 27.

5

Total current flowing into all pins.

= VDD and VIL = GND, VDD = 5.5 V,

V

IN

V

= 4.096 V, code = midscale

REF

= VDD and VIL = GND, VDD = 3.0 V,

V

IN

= 4.096 V, code = midscale

V

REF

= VDD and VIL = GND, VDD = 5.5 V,

V

IH

= 4.096 V, code = midscale

V

REF

= VDD and VIL = GND, VDD = 3.0 V,

V

IH

V

= 4.096 V, code = midscale

REF

Rev. B | Page 4 of 20

AD5061

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V, all specifications T

Table 3.

Parameter Limit1 Unit Test Conditions/Comments

2

t

33 ns min SCLK cycle time

1

t2
t

3

t

4

t5
t

6

t

7

t8
t9

1

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Maximum SCLK frequency is 30 MHz.

5 ns min
3 ns min
10 ns min
3 ns min
2 ns min
0 ns min
12 ns min
9 ns min

SCLK

SYNC

DIN

t

8

MIN

to T

unless otherwise specified.

MAX

,

SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK fall ignore

t

4

t

t

2

1

t

3

t

6

t

5

t

9

t

7

D0D1D2D22D23

D23 D22

04762-002

Figure 2. Timing Diagram

Rev. B | Page 5 of 20

AD5061

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Operating Temperature Range

Industrial (B Grade) −40°C to + 85°C
Extended Automotive Temperature

Range (Y Grade) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
SOT-23 Package

Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance 206°C/W
θJC Thermal Impedance 44°C/W

Reflow Soldering (Pb-Free)

Peak Temperature 260°C
Time-at-Peak Temperature 10 sec to 40 sec

ESD 1.5 kV

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance integrated circuit with an
ESD rating of <2 kV, and is ESD-sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 20