Programmable
FREQUENCY
SELECT
SINE WAVE
GENERATOR
PHASE
DETECT
LOGIC
SIN COS
FROM
TRANSDUCER
FBIAS
SEL1
SEL2
AD2S99
EXC
SYNREF
SYNCHRONOUS
REFERENCE
LOS
TO
TRANSDUCER
PUSH/
PULL
O/P STAGE
EXC
a
FEATURES
Programmable Sinusoidal Oscillator
Synthesized Synchronous Reference Output
Programmable Output Frequency Range: 2 kHz–20 kHz
“Loss-of-Signal” Indicator
20-Pin PLCC Package
Low Cost
APPLICATIONS
Excitation Source for:
Resolvers
Synchros
LVDTs
RVDTs
Pressure Transducers
Load Cells
AC Bridges
Oscillator
AD2S99
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD2S99 programmable sinusoidal oscillator provides sine
wave excitation for resolvers and a wide variety of ac transducers. The AD2S99 also provides a synchronous reference output
signal (3 V p-p square wave) that is phase locked to its SIN and
COS inputs. In an application, the SIN and COS inputs are
connected to the transducer’s secondary windings.
The synchronous reference output compensates for temperature
and cabling dependent phase shifts and eliminates the need for
external preset phase compensation circuits. The synchronous
reference output can be used as a zero crossing reference for
resolver-to-digital converters such as Analog Devices’ AD2S80A,
AD2S82A, AD2S83 and AD2S90.
The AD2S99 is packaged in a 20-pin PLCC and operates over
–40°C to +85°C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
Dynamic Phase Compensation
The AD2S99 dynamically compensates for any phase variation
in a transducer by phase locking its synchronous reference output to the transducer’s secondary windings.
Programmable Excitation Frequency
The excitation frequency is easily programmed to 2 kHz, 5 kHz,
10 kHz, or 20 kHz by using the frequency select pins. Intermediate frequencies are available by adding an external resistor.
Signal Loss Detection
The AD2S99 has the ability to detect if both the transducer secondary winding connections become disconnected from its SIN
and COS inputs. The “LOS” output pin pulls high when a signal loss is detected.
Integration
The AD2S99 integrates the transducer excitation, synchronous
reference, and loss of signal detection functions into a small,
cost effective package.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700 Fax: 617/326-8703
AD2S99–SPECIFICATIONS
(VS = 64.75 V to 65.25 V @ –408C to +858C unless otherwise noted)
Parameter Min Typ Max Units Test Conditions
FREQUENCY OUTPUT RANGE SEL1 SEL2
2 kHz 2000 Hz V
5 kHz 5000 Hz V
SS
SS
10 kHz 10000 Hz GND V
V
SS
GND
SS
20 kHz 20000 Hz GND GND
ACCURACY
Frequency ±10 % AP Grade @ +25°C
±20 % AP Grade –40°C to +85°C
±5 % BP Grade @ +25°C
±10 % BP Grade –40°C to +85°C
Amplitude ±3 ±10 % AP Grade @ +25°C
±20 % AP Grade –40°C to +85°C
±3 ±5 % BP Grade @ +25°C
±10 % BP Grade –40°C to +85°C
Power Supply Rejection Ratio 0.002 V p-p/V Output Variation as Function of
Change in Power Supply Voltage
ANALOG OUTPUTS
Amplitude
EXC 2 V rms EXC to GND, EXC to GND
EXC,
SYNREF ±3 V p-p Square Wave
SYNREF OFFSET ±200 mV
Current Drive Capability
EXC,
EXC V
= ±5 V 8 mA rms R
S
= 500 Ω EXC to EXC
LOAD
= 1000 pF
C
LOAD
Capacitive Drive 1000 pF
Total Harmonic Distortion
EXC, EXC –25 dB
ANALOG INPUTS SIN, COS
Amplitude 1.8 2.0 2.2 V rms
Phase Lock Range –45 +45 Degrees
Additional Phase Delay
±10 Degrees AP Grade
±10 Degrees BP Grade
FREQUENCY SELECT INPUTS
SEL1, SEL2
1
V
SS
AGND V dc
LOS OUTPUT
Output Low Voltage 0.7 V dc I
Output High Voltage V
DD
V dc 50 kΩ Pull Up to V
SIN, COS LOS Threshold 0.5 0.6 0.8 V rms
POWER SUPPLIES
V
DD
V
SS
Quiescent Current IDD, I
SS
+4.75 +5.25 V dc
–4.75 –5.25 V dc
±8 ±15 mA No Load
TEMPERATURE RANGE
Operating –40 +85 °C
Storage –65 +150 °C
NOTES
1
Frequency select pins SEL1 and SEL2 must be connected to appropriate voltage levels before power is applied.
Specifications subject to change without notice.
= 400 µA
OL
Drain Output)
(Open
DD
–2–
REV. B
AD2S99
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
V
SS
Operating Temperature . . . . . . . . . . . . . . . . . .–40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . .–65°C to +150°C
Analog Input Voltages (SIN and COS) . . . . . . . . . V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .to V
Frequency Select (SEL1, SEL2) . . . . . . . . . . . . . . V
– 0.3 V
SS
+ 0.3 V
DD
– 0.4 V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to AGND + 0.4 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Power Supply Voltage (VDD to V
) . . . . . . ±4.75 V to ±5.25 V
SS
Analog Input Voltage (SIN and COS) . . . . . . . . 2 V rms ±10%
Frequency Select (SEL1 and SEL2) . . . . . . . . . V
to AGND
SS
Operating Temperature Range . . . . . . . . . . . . .–40°C to +85°C
ORDERING GUIDE
Model Temperature Range Package Option*
AD2S99AP –40°C to +85°C P-20A
AD2S99BP –40°C to +85°C P-20A
*P = PLCC.
PIN DESIGNATIONS
Pin
No. Mnemonic Description
1 SEL2 Frequency Select 2
2 SEL1 Frequency Select 1
3 FBIAS External Frequency Adjust Pin
5 SIN Resolver Output SIN
1
6
DGND Digital Ground
7 COS Resolver Output COS
10 SYNREF Synthesized Reference Output
11 LOS Indicates When Both the SIN and
COS Are Below the Threshold.
12 V
1
16
DD
AGND Analog Ground
Positive Power Supply
17 EXC Resolver Reference One
18
2
19
2
20
NOTES
1
Pins 6 and 16 must be connected together.
2
Pins 19 and 20 must be connected together.
3
Resolver Reference two (EXC) is 180° phase advanced with respect to Resolver
Reference one (EXC).
EXC Resolver Reference Two
V
SS
V
SS
Negative Power Supply
Negative Power Supply
3
PIN CONFIGURATION
FBIAS
NC
4
SIN
5
DGND
COS
NC
AD2S99
6
TOP VIEW
(Not to Scale)
7
8
NC
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD2S99 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
SEL2
SEL1
LOS
SYNREF
SS
SS
V
V
19312 20
EXC
18
EXC
17
AGND
16
NC
15
NC
14
12 1391110
DD
NC
V
REV. B
–3–
20
0
6
2
4
4
0
12
8
10
14
16
18
28242016128
ADDITIONAL RESISTANCE – kΩ
RESISTOR PULLUP TO V
DD
FROM FBIAS
FREQUENCY – kHz
AD2S99
CONNECTING THE AD2S99 OSCILLATOR
Refer to Figure 1. Positive supply voltage VDD should be connected to Pin 12 and negative supply voltage V
nected to both Pins 19 and 20. Reversal of these power supplies will
destroy the device. The appropriate voltage level for the power
supplies is ±5 V dc ± 5%. Both V
Pins (19 and 20) must be
SS
connected together, and Digital Ground (Pin 6) must be connected to Analog Ground (Pin 16) locally at the AD2S99.
4.7µF
SS
SS
SEL1
AD2S99
NC
SYNREF
50kΩ
4.7µF
SEL2
LOS
V
V
19312 20
EXC
18
EXC
17
AGND
16
NC
15
NC
14
12 1391110
DD
NC
V
FBIAS
NC
4
SIN
5
DGND
6
COS
7
NC
8
.
.
R
*
.
X
0.1µF
V
DD
NC = NO CONNECT
*
R
IS ONLY REQUIRED FOR INTERMEDIATE FREQUENCIES.
X
FIXED FREQUENCIES ONLY REQUIRE A LINK.
Figure 1. Typical Configuration
It is recommended that decoupling capacitors are connected in
parallel between V
and Analog Ground and VSS and Analog
DD
Ground in close proximity to the AD2S99. The recommended
values for the decoupling capacitors are 100 nF (ceramic) and
4.7 µF (tantalum). When multiple AD2S99s are used, separate
decoupling capacitors should be used for each AD2S99.
FREQUENCY ADJUSTMENT
The output frequency of the AD2S99 is programmable to four
standard frequencies (2, 5, 10, or 20 kHz) using the SEL1 and
SEL2 pins. The output can also be adjusted to provide intermediate frequencies by connecting a resistor from the FBIAS pin to
the positive supply V
during normal operation. A graph showing the typical
V
DD
. The FBIAS pin is connected directly to
DD
added resistance values for various intermediate frequencies is
provided in Figure 2. The procedure for obtaining an intermediate frequency is:
1. Set the output frequency via the SEL1, SEL2 pins to the frequency immediately above the required intermediate frequency.
2. Connect the frequency adjust pin FBIAS to V
nal resistor.
For example: to obtain an output frequency of 8 kHz, set the
nominal output frequency to 10 kHz by connecting SEL1 to
GND and SEL2 to V
. Connect FBIAS to V
SS
resistor (refer to Figure 2).
should be con-
SS
V
SS
0.1µF
RESOLVER
REF
SIN
COS
100nF
SEL2 = GND ]
SEL1 = V
INCREASE RX TO LOWER
OUTPUT FREQUENCY
(SEE GRAPH)
TO AD2S80/
AD2S90 REF INPUT
100kΩ
–5kHz MODE
]
SS
via an exter-
DD
via a 6 kΩ
DD
Figure 2. Typical Added Resistance Value
AD2S99 OSCILLATOR OUTPUT STAGE
The output of the AD2S99 oscillator consists of two sinusoidal
signals, EXC, and
EXC. EXC is 180° phase advanced with re-
spect to EXC. The excitation winding of a transducer should be
connected across EXC (Pin 17) and
EXC (Pin 18).
With low impedance transducers, it may be necessary to increase the output current drive of the AD2S99. In such an instance, an external buffer amplifier can be used to provide gain
(as needed), and additional current drive for the excitation output (either EXC or
EXC) of the AD2S99, providing a single
ended drive to the transducer. Refer to Figures 6, 7 and 8 for
sample buffer configurations.
The amplitude modulated SIN and COS output signals from a resolver should be connected as feedback signals to the AD2S99.
The SYNREF output compensates for any primary to secondary
phase errors in the resolver. These errors can degrade the accuracy
of a Resolver-to-Digital Converter (R/D Converter).
SIN, from the resolver, should be connected to the AD2S99 SIN
input and COS should be connected to the AD2S99 COS input.
The SIN Lo, COS Lo (resolver signal returns) should be connected to AGND and the R/D Converter as applicable.
The synthesized reference (SYNREF) from the AD2S99 should
be connected to the reference input pin of the R/D Converter.
The SYNREF signal is a square wave at the oscillator frequency
of amplitude ±3 V p-p and is phase coherent with the SIN and
COS inputs. If this signal is used to drive the reference input of
the AD2S90 R/D Converter, a coupling capacitor and resistor to
GND must be connected between the SYNREF output of the
AD2S99 and the REF input of the R/D Converter (see Figure
3). Please read the appropriate R/D Converter data sheets for
further clarification.
LOSS OF SIGNAL
During normal operation when both the SIN and COS signals
on the resolver secondary windings are connected to the
AD2S99, the LOS output pin of the AD2S99 (Pin 11) is at a
Logic Lo (<0.7 V). If both the SIN and COS signals on the resolver secondary windings fall below the LOS threshold level of
the AD2S99, the LOS pin of the AD2S99 will pull up to a
Logic Hi (V
–4–
) level.
DD
REV. B
AD2S99
AD2S99/AD2S90 TYPICAL CONFIGURATION
Figure 3 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S90 Resolver-to-Digital Converter. The
maximum level of the SIN and COS input signals to the
AD2S90 should be 2 V rms ±10%. All the analog ground signals should be star connected to the AD2S90 AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
NC = NO CONNECT
NC
SIN
DGND
SEL2 = GND
SEL1 = V
SS
F
= 5kHz
OUT
COS
NC
shields should also be terminated at the AD2S90 AGND pin.
The SYNREF output of the AD2S99 should be connected to
the REF input pin of the AD2S90 via a 0.1 µF capacitor with a
100 kΩ resistor to GND. This is to block out any dc offset in
the SYNREF signal. For more detailed information please refer
to the AD2S90 data sheet.
4
5
6
7
8
V
DD
SEL1
FBIAS
AD2S99
TOP VIEW
(Not to Scale)
NC
SYNREF
SEL2
LOS
50kΩ
0.1µF
SS
SS
V
V
1931220
EXC
18
EXC
17
AGND
16
NC
15
NC
14
12 1391110
DD
NC
V
V
DD
0.1µF
4.7µF
4.7µF
V
SS
S2
R2
R4
RESOLVER
COS
0.1µF
S4
19
20
S2
S4
S3
SINREF
S1
S3
S1
1
2
3
POWER
RETURN
100kΩ
18 17 1416 15
REF
COS LO
COS
AGND
SIN
AD2S90
TOP VIEW
SIN LO
(Not to Scale)
586
4
V
DGND
7
Figure 3. AD2S99 and AD2S90 Example Configuration
V
DD
DD
13
V
DD
12
V
SS
11
10
9
0.1µF
0.1µF
4.7µF
4.7µF
V
SS
REV. B
–5–
AD2S99
AD2S99/AD2S82A TYPICAL CONFIGURATION
Figure 4 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S82A Resolver-to-Digital Converter.
The maximum level of the SIN and COS input signals to the
AD2S82A should be 2 V rms ±10%. All the analog ground signals should be star connected to the AD2S82A AGND pin. If
shielded twisted pair cables are used for the resolver signals, the
shields should also be terminated at the AD2S82A AGND pin.
SYNREF
COS
COS
AGND
SINREF
0.1µF
MSB DB1
DGND
SIN
I/P
+V
S
NC
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DIGITAL
OUTPUT
DATA
SIN
NC
4
SIN
DGND
COS
NC
NC = NO CONNECT
5
6
7
8
FBIAS
FBIAS
NC
SEL1 = GND
SEL2 = V
F
OUT
–5V
SEL1
SEL2
AD2S99
TOP VIEW
(Not to Scale)
LOS
SYNREFNCV
12 1391110
50k
SS
= 10kHz
V
SS
DD
4.7µF
193 12 20
V
0.1µF
0.1µF
SS
LOS
RESOLVER
10µF
EXC
18
EXC
17
AGND
16
15
NC
NC
14
4.7µF
+12V
+5V
Coupling capacitor C3, and resistor to GND R3, between the
SYNREF output of the AD2S99 and the REF input pin of the
AD2S82A are optional. For additional information on selecting
component values for the AD2S82A, please refer to the
AD2S82A data sheet or the application note “Passive Component Selection and Dynamic Modeling for the AD2S80 Series
Resolver-to-Digital Converters” (AN-266).
R3, C3 OPTIONAL VELOCITY
C3
R3
C1
R1
7
8
A GND
COS I/P
SIG GND
9
10
11
12
13
14
15
16
17
DB9
DB10
DB11
OUTPUT
R2
R4
3
DEMOD I/P
AC ERROR O/P
REFERENCE I/P
AD2S82A
TOP VIEW
(Not to Scale)
DB13
DB14
DB12
21 24232218 2019
C5
R5
C4
C2
4412645
43
DEMOD O/P
DB15
0.1µF 10µF
VCO O/P
INTEGRATOR I/P
INTEGRATOR O/P
L
ENABLE
LSB DB16
+V
25 282726
R6
404142
VCO I/P
BYTE
39
38
37
36
35
34
33
32
31
30
29
SELECT
+5V
AGND
0V
–V
S
–12V
RC
DIR
BUSY
DATA LOAD
COMP
SC2
SC1
DIGITAL GND
INHIBIT
NC
10µF0.1µF
Figure 4. AD2S99 and AD2S82A Example Configuration
–6–
REV. B
AD2S99
AD2S99/AD2S93 TYPICAL CONFIGURATION
Figure 5 shows a typical circuit configuration for the AD2S99
Oscillator and the AD2S93 LVDT-to-Digital Converter. The
maximum level of the A and B transducer input signals to the
AD2S93 should be 1 V rms ± 20%. All the analog ground signals should be star connected to the AD2S93 AGND pin. If
shielded twisted pair cables are used for the LVDT signals, the
V
DD
NC
SIN
NC
FBIAS
4
5
6
7
8
SEL2 = GND
SEL1 = V
SS
F
= 5kHz
OUT
NC = NO CONNECT
DGND
COS
shields should also be terminated at the AD2S93 AGND pin.
The SYNREF output of the AD2S99 cannot be used as the
REF input signal for the AD2S93. The zero crossing reference
for the AD2S93 should be taken from the primary winding of
the LVDT through a phase lead or lag network. The phase compensation network ensures that the REF input is phase coherent
with the A and B input signals to the AD2S93.
V
SS
SS
SEL1
V
SEL2
AD2S99
TOP VIEW
(Not to Scale)
12 1391110
DD
NC
V
LOS
SYNREF
50kΩ
LOS
SS
V
193 12 20
0.1µF
NC
0.1µF 4.7µF
EXC
18
EXC
17
AGND
16
NC
15
14
NC
V
DD
4.7µF
C1
INTIN
NC
VGAIN
UNR
R6
DMODIN
ACERROR
DGND
NULL
CLKOUT
PRI
LVDT
C2
R2
PHASE
COMP
25 24 21 20 1923 22
NC
VEL
26
B
SEC
A
27
28
1
2
3
4
REF
NC
B
A
AGND
DIFF
GAIN
LOS
56 9101178
SCLK
DATA
AD2S93
TOP VIEW
(Not to Scale)
CS
Figure 5. AD2S99 and AD2S93 Example Configuration
V
V
OVR
NC
C3
DIR
DD
SS
C4
R5
R7
18
DMODOUT
17
0.1µF
16
0.1µF
15
14
13
12
NC = NO CONNECT
4.7µF
4.7µF
V
DD
V
SS
REV. B
–7–
AD2S99
+V
S
SSM2142
4
6
7
8
5
2
1
3
–V
S
NC = NO CONNECT
NC
SIN
NC
DGND
COS
EXC
EXC
NC
AGND
NC
1931220
4
5
8
6
7
12 1391110
18
17
14
16
15
TOP VIEW
(Not to Scale)
AD2S99
FBIAS
SEL1
V
SS
SEL2
V
SS
NC
SYNREF
NC
LOS
V
DD
*
*
*
OPTIONAL; CONSULT APPROPRIATE
ANALOG DEVICES DATA SHEET.
RESOLVER
0.395 (10.02)
0.385 (9.78)
SQ
0.110 (2.79)
0.085 (2.16)
0.330 (8.38)
0.290 (7.37)
0.048 (1.21)
0.042 (1.07)
0.356 (9.04)
0.350 (8.89)
SQ
0.048 (1.21)
0.042 (1.07)
0.050
(1.27)
BSC
0.020
(0.50)
R
19 3
TOP VIEW
18
14
9
8
PIN 1
IDENTIFIER
4
13
0.032 (0.81)
0.026 (0.66)
0.021 (0.53)
0.013 (0.33)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.040 (1.01)
0.025 (0.64)
0.180 (4.57)
0.165 (4.19)
NC
4
SIN
5
DGND
6
COS
7
NC
8
FBIAS
AD2S99
TOP VIEW
(Not to Scale)
SEL2
V
V
193 12 20
V
= 2V
OUT
RMS
EXC
18
EXC
17
AGND
16
NC
15
NC
14
V
OUT
SS
SS
SEL1
12 139 1110
NC
DD
NC
V
LOS
NC = NO CONNECT
SYNREF
Figure 6. Sample Buffer Configuration
R2
R1
V
EXC
AGND
EXC
IN
V
= 2V
OUT
R1
V
IN
RMS
R2
OP279
R2
x (– –––
R1
V
OUT
RESOLVER
)
V
OUT
PIN 17
PIN 16
PIN 18
SINREF
COS
C1978b–10–6/95
Figure 8. The SSM2142 as a Single Ended to Differential
Driver
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PLCC (P-20A)
PIN 16
AGND
EXC
PIN 17
A SUITABLE AMPLIFIER FOR ABOVE IS THE OP279
R1
V
OUT
= 2V
OP279
R2
x 2 x (– –––
RMS
RESOLVER
R2
)
R1
Figure 7. Sample Buffer Configurations
–8–
PRINTED IN U.S.A.
REV. B
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