Analog Devices AD15700 a Datasheet

1 MSPS 16-/14-Bit

Analog I/O Port

AD15700

FEATURES
16-Bit A/D Converter

1 MSPS
S/(N + D): 90 dB Typ @ 250 kHz
No Pipeline Delay

14-Bit D/A Converter

Settling Time: 1 s
S/N: 92 dB Typ

2 80 MHz Amplifiers

30 V/s Slew Rate
Rail-to-Rail Input and Output
Output Current 15 mA

2 Gain Setting Center Tapped Resistors

Resistor Ratio Tracking: 2 ppm/C

Unipolar Operation

®

/QSPI™/MICROWIRE™/DSP Compatible

SPI
132 mW Typical Power Dissipation

APPLICATIONS
Optical MEMS Mirror Control
Industrial Process Control
Data Acquisition
Instrumentation
Communication

GENERAL DESCRIPTION

The AD15700 is a precision component to interface analog input
and output channels to a digital processor. It is ideal for area­limited applications that require maximum circuit density. The
AD15700 contains the functionality of a 16-bit,
redistribution SAR analog-to-digital converter that
a 5 V power supply. The high speed 16-bit sampling
porates a resistor input scaler that allows various input
internal conversion clock, error correction circuits,
and parallel system interface ports. The AD15700 also

1 MSPS charge

operates from

ADC incor-

ranges, an

and both serial

contains a
14-bit, serial input, voltage output DAC that operates from a 5 V
supply and has a
voltage feedback amplifiers with rail-to-rail input and
characteristics featuring 80 MHz of small signal bandwidth

settling time of 1 ms. Two single- or

split-supply

output

and

10 mV/∞C offset drift provide ADC and DAC buffering capability.
The center tapped 3 kW resistors are precision resistor

networks
with 2 ppm/∞C ratio tracking that provide low gain drift when
used for scaling.

The ADC, DAC, and amp functions are electrically isolated from
each other to provide maximum design flexibility. Input and
output signal conditioning circuits for the converters can be easily
configured with short interconnects under the device at the board
level. The AD15700 is available in a 10 mm CSPBGA package.

FUNCTIONAL BLOCK DIAGRAM

VDD_DAC DGND_DAC

VREF

CS_DAC

DIN

SCLK

COMMON

REF

REFGND

IND(4R)

INC(4R)

INB(2R)

INA(R)

INGND

VOU T2

+VS2

+IN2

–IN2

–VS2

RESET

RPAD2

CONTROL

LOGIC

4R

4R

2R

R

PD

1.5k

1.5k

RC2

RB2

RA2

14-BIT DAC

14-BIT DATA LATCH

SERIAL INPUT REGISTER

AD15700

SWITCHED

CAP DAC

SAR ADC
CONTROL LOGIC AND
CALIBRATION CIRCUITRY

CLOCK

CNVST

WARP IMPULSE

SERIAL

PORT

PARALLEL

INTERFACE

DVDD

1.5k

1.5k

DGND

ADC

VOU T_DAC

AGND_DAC

–IN1

+IN1

+VS1

VOU T1

–VS1

RA1

RB1

RC1

RPAD1

OVD D

OGND

SER/PAR

BUSY

16

D[15:0]

CS_ADC

RD

OB/2C

BYTESWAP

AVD D

AGND_ADC

PRODUCT HIGHLIGHTS

1. Fast Throughput ADC.
The AD15700 incorporates a high speed, 1 MSPS, 16-bit
SAR ADC.

2. Superior ADC INL.
The 16-bit ADC has a maximum integral nonlineariy of

2.5 LSB with no missing codes.

3. Two Precision Resistor Networks with 2 ppm/∞C Ratio
Tracking for Gain Setting.

4. Low Power Consumption.
Typically 132 mW at maximum performance levels.

5. Industrial Temperature Range: –40∞C to +85∞C.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD15700–SPECIFICATIONS

(–40C to +85C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless

16-BIT ADC ELECTRICAL CHARACTERISTICS

Parameter Condition Min Typ Max Unit

RESOLUTION 16 Bits

ANALOG INPUT

Voltage Range VIND – VINGND
Common-Mode Input Voltage VINGND –0.1 +0.5 V
Analog Input CMRR f
Input Impedance See Table I

THROUGHPUT SPEED

Complete Cycle In Warp Mode 1 ms
Throughput Rate In Warp Mode 1 1000 kSPS
Time between Conversions In Warp Mode 1 ms
Complete Cycle In Normal Mode 1.25 ms
Throughput Rate In Normal Mode 0 800 kSPS
Complete Cycle In Impulse Mode 1.5 ms
Throughput Rate In Impulse Mode 0 666 kSPS

DC ACCURACY

Integral Linearity Error –2.5 +2.5 LSB
No Missing Codes 16 Bits
Transition Noise 0.7 LSB
Bipolar Zero Error

Bipolar Full-Scale Error2, T
Unipolar Zero Error
Unipolar Full-Scale Error2, T

2

, T

to T

2

MIN

, T

MIN

MIN

to T

MIN

MAX

to T

MAX

to T

MAX

MAX

Power Supply Sensitivity AVDD = 5 V ± 5% ± 9.5 LSB

AC ACCURACY

Signal-to-Noise fIN = 20 kHz 89 90 dB

Spurious-Free Dynamic Range f
Total Harmonic Distortion f

Signal-to-(Noise + Distortion) f

–3 dB Input Bandwidth 9.6 MHz

SAMPLING DYNAMICS

Aperture Delay 2ns
Aperture Jitter 5 ps rms
Transient Response Full-Scale Step 250 ns

REFERENCE

External Reference Voltage Range 2.3 2.5 3.0 V
External Reference Current Drain 1 MSPS Throughput 200 mA

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

= 100 kHz 74 dB

IN

± 5 V Range, Normal or –45 +45 LSB
Impulse Modes
Other Range or Mode ± 0.1% % of FSR

fIN = 250 kHz 90 dB

= 250 kHz 100 dB

IN

= 20 kHz –100 –96 dB

IN

= 250 kHz –100 dB

f

IN

= 20 kHz 88.5 90 dB

IN

= 250 kHz, –60 dB Input 30 dB

f

IN

otherwise noted.)

± 4 REF, 0 V to 4 REF, ± 2 REF (See Table I)

–0.38 +0.38 % of FSR
–0.18 +0.18 % of FSR
–0.76 +0.76 % of FSR

–0.3 +0.8 V
+2.0
–1 +1 mA
–1 +1 mA

DVDD + 0.3

1

3

V

REV. A–2–

AD15700

Parameter Condition Min Typ Max Unit

DIGITAL OUTPUTS

Data Format Parallel or Serial 16-Bit
Pipeline Delay Conversion Results Available Immediately

after Completed Conversion

I

V

OL

V

OH

POWER SUPPLIES

Specified Performance

AVDD 4.75 5 5.25 V
DVDD 4.75 5 5.25 V
OVDD 2.7 5.25 V

Operating Current

AVDD 15 mA

5

DVDD

5

OVDD

Power Dissipation

In Power-Down Mode

4

5, 6

8

TEMPERATURE RANGE

Specified Performance T

NOTES

1

LSB means Least Significant Bit. With the ± 5 V input range, one LSB is 152.588 mV.

2

These specifications do not include the error contribution from the external reference.

3

All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

4

In Warp Mode.

5

Tested in Parallel Reading Mode.

6

Tested with the 0 V to 5 V range and VIN – VINGND = 0 V.

7

In Impulse Mode.

8

With OVDD below DVDD + 0.3 V and all digital inputs forced to OVDD or OGND, respectively.

Specifications subject to change without notice.

= 1.6 mA 0.4 V

SINK

I

= –570 mA OVDD – 0.6 V

SOURCE

7.2 mA
37 mA
84 95 mW
15 mW
112 125 mW

666 kSPS Throughput
100 SPS Throughput
1 MSPS Throughput

7

4

7

1mW

MIN

to T

MAX

–40 +85 ∞C

Table I. Analog Input Configuration

Input Voltage Range IND(4R) INC(4R) INB(2R) INA(R) Input Impedance

± 4 REF V
± 2 REF V
± REF V

0 V to 4 REF V
0 V to 2 REF V

0 V to REF V

NOTES

1

Typical analog input impedance.

2

For this range, the input is high impedance.

IN

IN

IN

IN

IN

IN

INGND INGND REF 1.63 kW
V

IN

V

IN

V

IN

V

IN

V

IN

INGND REF 948 W
V

IN

REF 711 W

INGND INGND 948 W
V

IN

V

IN

INGND 711 W
V

IN

Note 2

1

REV. A

–3–

AD15700

16-BIT ADC TIMING CHARACTERISTICS

(–40C to +85C, AVDD = DVDD = 5 V, 0VDD = 2.7 V to 5.25 V, unless otherwise noted.)

Parameter Symbol Min Typ Max Unit

Refer to Figures 14 and 15

Convert Pulsewidth t
Time between Conversions

1

t

2

5ns
1/1.25/1.5 Note 1 ms

(Warp Mode/Normal Mode/Impulse Mode)

CNVST LOW to BUSY HIGH Delay t
BUSY HIGH All Modes Except in Master Serial Read after t

3

4

30 ns

0.75/1/1.25

ms

Convert Mode (Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay t
End of Conversion to BUSY LOW Delay t
Conversion Time (Warp Mode/Normal Mode/Impulse Mode) t
Acquisition Time t
RESET Pulsewidth t

5

6

7

8

9

10 ns

1 ms
10 ns

2ns

0.75/1/1.25

ms

Refer to Figures 16, 17, and 18 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay t

10

0.75/1/1.25

ms

(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay t
Bus Access Request to DATA Valid t
Bus Relinquish Time t

Refer to Figures 20 and 21 (Master Serial Interface Modes)

2

CS_ADC LOW to SYNC Valid Delay t
CS_ADC LOW to Internal SCLK Valid Delay t
CS_ADC LOW to SDOUT Delay t
CNVST LOW to SYNC Delay (Read During Convert) t

(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH
Internal SCLK LOW
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay

3

3

3

3

3

3

3

CS_ADC HIGH to SYNC HI-Z t
CS_ADC HIGH to Internal SCLK HI-Z t
CS_ADC HIGH to SDOUT HI-Z t

BUSY HIGH in Master Serial Read after Convert

3

CNVST LOW to SYNC Asserted Delay t

11

12

13

14

15

16

17

t

18

t

19

t

20

t

21

t

22

t

23

t

24

25

26

27

t

28

29

20 ns

40 ns

515ns

10 ns
10 ns
10 ns

25/275/525 ns

4ns
25 40 ns
15 ns
9ns

4.5 ns
2ns
3ns

10 ns
10 ns
10 ns

See Table II ms

0.75/1/1.25 ms

Master Serial Read after Convert

SYNC Deasserted to BUSY LOW Delay t

30

25 ns

Refer to Figures 22 and 24 (Slave Serial Interface Modes)
External SCLK Setup Time t
External SCLK Active Edge to SDOUT Delay t
SDIN Setup Time t
SDIN Hold Time t
External SCLK Period t
External SCLK HIGH t
External SCLK LOW t

NOTES

1

In Warp Mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.

2

In Serial Interface Modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.

3

In serial master Read during Convert Mode. See Table II.

Specifications subject to change without notice.

31

32

33

34

35

36

37

5ns
316ns
5ns
5ns
25 ns
10 ns
10 ns

REV. A–4–

AD15700

Table II. Serial Clock Timings in Master Read after Convert

DIVSCLK[1] 0011
DIVSCLK[0]

SYNC to SCLK First Edge Delay Minimum t
Internal SCLK Period Minimum t
Internal SCLK Period Maximum t
Internal SCLK HIGH Minimum t
Internal SCLK LOW Minimum t
SDOUT Valid Setup Time Minimum t
SDOUT Valid Hold Time Minimum t
SCLK Last Edge to SYNC Delay Minimum t
BUSY HIGH Width Maximum (Warp) t
BUSY HIGH Width Maximum (Normal) t
BUSY HIGH Width Maximum (Impulse) t

Symbol

18

19

19

20

21

22

23

24

28

28

28

0101Unit

4202020ns
25 50 100 200 ns
40 70 140 280 ns
15 25 50 100 ns
9244999ns

4.5 22 22 22 ns
243089ns
360140 300 ns

1.5 2 3 5.25 ms

1.75 2.25 3.25 5.5 ms
2 2.5 3.5 5.75 ms

1.6mA

TO OUTPUT

PIN

IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C

OF 10pF; OTHERWISE THE LOAD IS 60pF MAXIMUM.

L

C

L

60pF

500mA

I

OL

1.4V

I

OH

Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF

0.8V

t

DELAY

2V

0.8V

2V

t

DELAY

2V

0.8V

Figure 2. Voltage Reference Levels for Timing

REV. A

–5–

AD15700

14-BIT DAC ELECTRICAL CHARACTERISTICS

(TA = –40C to +85C, VDD_DAC = 5 V, V

= 2.5 V, unless otherwise noted.)

REF

Parameter Condition Min Typ Max Unit

STATIC PERFORMANCE

Resolution 1 LSB = V

when V

/214 = 153 mV

REF

= 2.5 V 14 Bits

REF

Relative Accuracy, INL ± 0.15 ± 1.0 LSB
Differential Nonlinearity Guaranteed Monotonic ± 0.15 ± 0.8 LSB
Gain Error –1.75 –0.3 0 LSB
Gain Error Temperature Coefficient

± 0.1 ppm/∞C

Zero Code Error 0 0.1 0.5 LSB
Zero Code Temperature Coefficient

± 0.05 ppm/∞C

OUTPUT CHARACTERISTICS

Output Voltage Range 0 V
Output Voltage Settling Time

To 1/2 LSB of FS, CL = 10 pF

1 ms

–1 LSB V

REF

Digital-to-Analog Glitch Impulse 1 LSB Change around the

Major Carry 10 nV–s

Digital Feedthrough All 1s Loaded to DAC,

= 2.5 V 0.05 nV–s

V

REF

DAC Output Impedance Tolerance Typically 20% 6.25 kW
Power Supply Rejection Ratio DVDD ± 10% ± 1.0 LSB

DAC REFERENCE INPUT

Reference Input Range 2 V

DD

V

Reference Input Resistance* 9kW

LOGIC INPUTS

Input Current ± 1.0 mA
VINL, Input Low Voltage 0.8 V
VINH, Input High Voltage 2.4 V
Input Capacitance 10 pF
Hysteresis Voltage 0.4 V

REFERENCE

Reference –3 dB Bandwidth All 1s Loaded 1.3 MHz
Reference Feedthrough All 0s Loaded,

= 1 V p-p at 100 kHz 1 mV p-p

V

REF

Signal-to-Noise Ratio 92 dB
Reference Input Capacitance Code 0000

Code 3FFF

H

H

75 pF
120 pF

POWER REQUIREMENTS

V

DD

I

DD

4.5 5.50 V

0.3 1.1 mA

Power Dissipation 1.5 6.05 mW

*Reference input resistance is code-dependent, minimum at 2555H.

Specifications subject to change without notice.

REV. A–6–

AD15700

(VDD = 5 V, 5%, V

1, 2

14-BIT DAC TIMING CHARACTERISTICS

Parameter Limit at T

f

SCLK

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

NOTES

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90%
of 3 V and timed from a voltage level of 1.6 V).

Specifications subject to change without notice.

25 MHz max SCLK Cycle Frequency
40 ns min SCLK Cycle Time
20 ns min SCLK High Time
20 ns min SCLK Low Time
15 ns min CS_DAC Low to SCLK High Setup
15 ns min CS_DAC High to SCLK High Setup
35 ns min SCLK High to CS_DAC Low Hold Time
20 ns min SCLK High to CS_DAC High Hold Time
15 ns min Data Setup Time
0 ns min Data Hold Time
30 ns min CS_DAC High Time between Active Periods

SCLK

CS_DAC

DIN

MIN

, T

All Versions Unit Description

MAX

t

6

t

4

t

10

t

8

t

9

DB13

TA = T

t

2

to T

MIN

MAX

t

1

t

3

DB0

= 2.5 V, AGND = DGND = 0 V. All Specifications

REF

, unless otherwise noted).

t

5

t

7

REV. A

Figure 3. Timing Diagram

–7–

AD15700

[5 V Supply (TA = 25C, VS = 5 V, RL = 1 k to 2.5 V, RF = 2.5 k,

AMPLIFIER ELECTRICAL CHARACTERISTICS

Parameter Condition Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = +1, V
Slew Rate G = –1, VO = 2 V Step 27 32 V/ms
Settling Time to 0.1% G = –1, V

DISTORTION/NOISE PERFORMANCE

Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p, G = +2 –62 dBc

= 100 kHz, VO = 2 V p-p, G = +2 –86 dBc

f

C

Input Voltage Noise f = 1 kHz 15
Input Current Noise f = 100 kHz 2.4 pA

f = 1 kHz 5 pA
Differential Gain RL = 1 kW 0.17 %
Differential Phase R

= 1 kW 0.11

L

DC PERFORMANCE

Input Offset Voltage VCM = VCC/2; V

T

MIN

Offset Drift VCM = VCC/2; V
Input Bias Current VCM = VCC/2; V

T

MIN

Input Offset Current 50 350 nA
Open-Loop Gain VCM = VCC/2; V

T

MIN

INPUT CHARACTERISTICS

Common-Mode Input Resistance 40 MW
Differential Input Resistance 280 kW
Input Capacitance 1.6 pF
Input Voltage Range –0.5 to +5.5 V
Input Common-Mode Voltage Range –0.2 to +5.2 V
Common-Mode Rejection Ratio VCM = 0 V to 5 V 56 70 dB

VCM = 0 V to 3.8 V 66 80 dB
Differential/Input Voltage 3.4 V

OUTPUT CHARACTERISTICS

Output Voltage Swing Low RL = 10 kW 0.05 0.02 V
Output Voltage Swing High 4.95 4.98 V
Output Voltage Swing Low RL = 1 kW 0.2 0.1 V
Output Voltage Swing High 4.8 4.9 V
Output Current 15 mA
Short Circuit Current Sourcing 28 mA

Sinking –46 mA
Capacitive Load Drive G = +2 15 pF

POWER SUPPLY

Operating Range 2.7 12 V
Quiescent Current per Amplifier 800 1400 mA
Power Supply Rejection Ratio VS– = 0 V to –1 V or 75 86 dB

VS+ = 5 V to 6 V

OPERATING TEMPERATURE RANGE

Specifications subject to change without notice.

< 0.4 V p-p 54 80 MHz

O

= 2 V Step, CL = 10 pF 125 ns

O

to T

to T

to T

OUT

MAX

OUT

OUT

MAX

OUT

MAX

unless otherwise noted.)]

nV/÷Hz

/÷Hz
/÷Hz

Degrees

= 2.5 V ± 1 ± 6mV

± 6 ± 10 mV
= 2.5 V 5 mV/∞C
= 2.5 V 0.45 1.2 mA

2.0 mA

= 1.5 V to 3.5 V 76 82 dB

74 dB

–40 +85 ∞C

REV. A–8–

AD15700

[5 V Supply (TA = 25C, VS = 5 V, RL = 1 k to 0 V, RF = 2.5 k,

AMPLIFIER ELECTRICAL CHARACTERISTICS

Parameter Condition Min Typ Max Unit

DYNAMIC PERFORMANCE

–3 dB Small Signal Bandwidth G = +1, V
Slew Rate G = –1, V
Settling Time to 0.1% G = –1, V

DISTORTION/NOISE PERFORMANCE

Total Harmonic Distortion fC = 1 MHz, VO = 2 V p-p, G = +2 –62 dBc

f

= 100 kHz, VO = 2 V p-p, G = +2 –86 dBc

C

Input Voltage Noise f = 1 kHz 15 nV
Input Current Noise f = 100 kHz 2.4 pA

f = 1 kHz 5 pA
Differential Gain RL = 1 kW 0.15 %
Differential Phase R

= 1 kW 0.15

L

DC PERFORMANCE

Input Offset Voltage VCM = 0 V; V

T

MIN

Offset Drift VCM = 0 V; V
Input Bias Current VCM = 0 V; V

T

MIN

Input Offset Current 50 350 nA
Open-Loop Gain VCM = 0 V; V

T

MIN

INPUT CHARACTERISTICS

Common-Mode Input Resistance 40 MW
Differential Input Resistance 280 kW
Input Capacitance 1.6 pF
Input Voltage Range –5.5 to +5.5 V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio VCM = –5 V to +5 V 60 80 dB

VCM = –5 V to +3.5 V 66 90 dB
Differential/Input Voltage 3.4 V

OUTPUT CHARACTERISTICS

Output Voltage Swing Low RL = 10 kW –4.94 –4.98 V
Output Voltage Swing High +4.94 +4.98 V
Output Voltage Swing Low RL = 1 kW –4.7 –4.85 V
Output Voltage Swing High +4.7 +4.75 V
Output Current 15 mA
Short Circuit Current Sourcing +35 mA

Sinking –50 mA
Capacitive Load Drive G = +2 15 pF

POWER SUPPLY

Operating Range ± 1.35 ± 6 V
Quiescent Current per Amplifier 900 1600 mA
Power Supply Rejection Ratio VS– = –5 V to –6 V or 76 86 dB

VS+ = +5 V to +6 V

OPERATING TEMPERATURE RANGE

Specifications subject to change without notice.

< 0.4 V p-p 54 80 MHz

O

= 2 V Step 30 35 V/ms

O

= 2 V Step, CL = 10 pF 125 ns

O

to T

to T

to T

OUT

MAX

OUT

OUT

MAX

OUT

MAX

unless otherwise noted.)]

/÷Hz
/÷Hz
/÷Hz

Degrees

= 0 V ± 1 ± 6 mV

± 6 ± 10 mV
= 0 V 5 mV/∞C
= 0 V 0.45 1.2 mA

2.0 mA

= ± 2 V 76 80 dB

74 dB

–5.2 to +5.2 V

–40 +85 ∞C

REV. A

–9–

AD15700

RESISTOR DIVIDER ELECTRICAL CHARACTERISTICS

(@ TA = 25C, unless otherwise noted.)

Parameter Condition Min Typ Max Unit

Resistance 2.97 3.00 3.03 kW
Temperature Coefficient of Resistance 50 ppm/∞C
Resistance Ratio of Two Halves 0.99 1.0 1.01
Resistance Ratio Tracking 2 ppm/∞C
Power Dissipation TA = 70∞C 250* mW

At higher temperatures, linearly derates to 0 mW at 175∞ C.

*

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS*

Analog Inputs

IND, INC, INB . . . . . . . . . . . . . . . . . . . . . . –11 V to +30 V

INA, REF, INGND, REFGND, AGND . . .

–0.3 V to AVDD + 0.3 V

ADC Ground Voltage Differences

AGND_ADC, DGND_ADC, OGND . . . . . . . . . . . . ± 0.3 V

ADC Supply Voltages

AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . . . ± 7 V

DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V

ADC Digital Inputs . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

VDD_DAC to AGND_DAC . . . . . . . . . . . . . . . –0.3 V to +6 V

DAC Digital Input Voltage to

DGND_DAC . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V

VOUT_DAC to AGND_DAC . . . . –0.3 V to DVDD + 0.3 V

AGND_DAC to DGND_DAC . . . . . . . . . . . –0.3 V to +0.3 V

DAC Input Current to Any DAC Pin Except Supplies . . ± 10 mA

Amplifier Supply Voltage (VS1, VS2) . . . . . . . . . . . . . . 12.6 V

Amplifier Input Voltage (Common Mode) . . . . . . ± V

± 0.5 V

S

Amplifier Differential Input Voltage . . . . . . . . . . . . . . . ± 3.4 V

Amplifier Output Short Circuit

Duration . . . . . . . . . . . . . . Observe Power Derating Curves

Resistor Instantaneous Voltage Drop . . . . . . . . . . . . . . . ± 50 V

Internal Power Dissipation . . . . . . . . . . . . . (T

Thermal Resistance ␪

JA

Max – TA)/␪

J

10 mm CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . 42∞C/W

Maximum Junction Temperature (T

Max) . . . . . . . . . . 150∞C

J

Operating Temperature Range . . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature . . . . . . . . . . . . . . . . . . . . . . . 225∞C, 15 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

JA

ORDERING GUIDE

Model Temperature Range Package Option

AD15700BCA –40∞C to +85∞C 144-Lead CSPBGA
AD15700/PCB 25∞C Evaluation Board
ADDS-2191-EZLITE

™

25∞C Evaluation Kit*

ADDS-21535-EZLITE
ADDS-21160M-EZLITE
ADDS-21161N-EZLITE

*One of the DSP Evaluation Kits is required for operation of the AD15700/PCB Evaluation Board.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD15700 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A–10–

AD15700

ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)

Pin No. Mnemonic Type Description

H9, J8, AGND_ADC P Analog Power Ground Pin
J9, M12

M6 AVDD P Input Analog Power Pin. Nominally 5 V.

L7 BYTESWAP DI Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB

is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is
output on D[7:0].

L8 OB/2C DI Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output

is straight binary; when LOW, the MSB is inverted, resulting in a twos complement
output from its internal shift register.

M7 WARP DI Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,

the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.

L9 IMPULSE DI Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.

In this mode, the power dissipation is approximately proportional to the sampling rate.

M8 SER/PAR DI Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH,

the Serial Interface Mode is selected and some bits of the DATA bus are used as a
serial port.

M9, L10 D[0:1] DO Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these

outputs are in high impedance.

M10, L11 D[2:3] or DI/O When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the

DIVSCLK[0:1] serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial

Port, are used to slow down, if desired, the internal serial clock that clocks the data output.
In the other serial modes, these inputs are not used.

M11 D[4] or EXT/INT DI/O When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital
select input for choosing the internal or an external data clock, called, respectively, Master
and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK
output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input and the external clock is gated by CS_ADC.

L12 D[5] or INVSYNC DI/O When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.

K11 D[6] or INVSCLK DI/O When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the
SCLK signal. It is active in both Master and Slave Mode.

K12 D[7] or RDC/SDIN DI/O When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an
external data input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain
the conversion results from two or more ADCs onto a single SDOUT line. The digital
data level on SDIN is output on DATA with a delay of 16 SCLK periods after the
initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select
the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT
during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.

J10 OGND P Input/Output Interface Digital Power Ground

J11 OVDD P Input/Output Interface Digital Power. Nominally at the same supply as the supply of

the host interface (5 V or 3.3 V).

J12 DVDD P Digital Power. Nominally at 5 V.

REV. A

–11–

AD15700

ADC PIN FUNCTION DESCRIPTIONS (continued)

Pin No. Mnemonic Type Description

H10 DGND_ADC P Digital Power Ground
H12 D[8] or SDOUT DO When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a serial data
output synchronized to SCLK. Conversion results are stored in an on-chip register.
The ADC provides the conversion result, MSB first, from its internal shift register.
The DATA format is determined by the logic level of OB/2C. In Serial Mode, when
EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In Serial Mode, when
EXT/INT is HIGH: If INVSCLK is LOW, SDOUT is updated on SCLK rising edge
and valid on the next falling edge. If INVSCLK is HIGH, SDOUT is updated on
SCLK falling edge and valid on the next rising edge.

H11 D[9] or SCLK DI/O When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a serial
data clock input or output, dependent upon the logic state of the EXT/INT pin. The
active edge where the data SDOUT is updated depends upon the logic state of the
INVSCLK pin.

G12 D[10] or SYNC DO When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital
output frame synchronization for use with the internal data clock (EXT/INT = Logic
LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH
and remains HIGH while SDOUT output is valid. When a read sequence is initiated
and INVSYNC is High, SYNC is driven LOW and remains LOW while SDOUT output
is valid.

G11 D[11] or RDERROR DO When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output

Bus. When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial
Port, is used as an incomplete read error flag. In Slave Mode, when a data read is started
and not complete when the following conversion is complete, the current data is lost
and RDERROR is pulsed high.

F12, F11, D[12:15] DO Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/PAR is HIGH,
E12, E11 these outputs are in high impedance.

G10 BUSY DO Busy Output. Transitions HIGH when a conversion is started, and remains HIGH

until the conversion is complete and the data is latched into the on-chip shift register.
The falling edge of BUSY could be used as a data ready clock signal.

G9 DGND_ADC P Must be Tied to Digital Ground
E10 RD DI Read Data. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled.

K10 CS_ADC DI Chip Select. When CS_ADC and RD are both LOW, the interface parallel or serial

output bus is enabled. CS_ADC is also used to gate the external serial clock.

D12 RESET DI Reset Input. When set to a logic HIGH, reset the ADC. Current conversion, if any,

is aborted. If not used, this pin could be tied to DGND.

K9 PD DI Power-Down Input. When set to a logic HIGH, power consumption is reduced and

conversions are inhibited after the current one is completed.

E7 CNVST DI Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold

state and initiates a conversion. In impulse mode (IMPULSE HIGH and WARP LOW),
if CNVST is held low when the acquisition phase (t
sample/hold is put into the hold state and a conversion is immediately started.

H8 AGND_ADC P Must be Tied to Analog Ground

G5 REF AI Reference Input Voltage

H5 REFGND AI Reference Input Analog Ground

J7 INGND P Analog Input Ground

J5, K5, INA, INB, AI Analog Inputs. Refer to Table I for input range configuration.
L5, M5 INC, IND

) is complete, the internal

8

REV. A–12–

AD15700

DAC PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

A6 VOUT_DAC AO Analog Output Voltage from the DAC
A3, C3, C4 AGND_DAC P Ground Reference Point for Analog Circuitry
A2 VREF AI This is the voltage reference input for the DAC. Connect to external reference

ranges from 2 V to VDD.

B1 CS_DAC DI This is an active low logic input signal. The chip select signal is used to frame

the serial data input.

E1 SCLK DI

E2 DIN DI Serial Data Input. This device accepts 14-bit words. Data is clocked into the

E3 DGND_DAC P Digital Ground. Ground reference for digital circuitry.
C6 VDD_DAC P Analog Supply Voltage, 5 V ± 10%

AMPLIFIER PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

C9 (J1) +IN1(2) AI Positive Input Voltage

A9 (G1) –IN1(2) AI Negative Input Voltage

B12 (K4) VOUT1(2) AO Amplifier Output Voltage

A11 (F3) +VS1(2) P Analog Positive Supply Voltage

B10, B11 –VS1(2) P Analog Negative Supply Voltage
(G3, H3)

Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Duty cycle must be between 40% and 60%.

input register on the rising edge of SCLK.

RESISTOR PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

B9 (L4) RA1(2) AI/O Resistor End Terminal
A8 (M4) RB1(2) AI/O Resistor Center Tap
D9 (L1) RC1(2) AI/O Resistor End Terminal
A7 (M3) RPAD1(2) P Resistor Die Pad. Tie to Analog Ground.

COMMON PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Type Description

A1, A4, A5, A10, A12, B2–B8, C1, COMMON P Common Floating Net Connecting 69 Pins. Not electrically
C2, C5, C7, C8, C10–C12, D1–D8, connected within the module. Tie at least one of these pins
D10, D11, E4–E6, E8, E9, F1, F2, to Analog Ground.
F4–F10, G2, G4, G6–G8, H1, H2,
H4, H6, H7, J2–J4, J6, K1–K3,
K6–K8, L2, L3, L6, M1, M2

NOTES
AI = Analog Input
AI/O = Bidirectional Analog
AO = Analog Output
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power

REV. A

–13–

AD15700

ADC DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)

Linearity error refers to the deviation of each individual code
from a line drawn from “negative full scale” through “positive
full scale.” The point used as negative full scale occurs 1/2 LSB
before the first code transition. Positive full scale is defined as a
level 1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value.
It is often specified in terms of resolution for which no missing
codes are guaranteed.

Full-Scale Error

The last transition (from 011...10 to 011...11 in twos comple­ment coding) should occur for an analog voltage 1 1/2 LSB
below the nominal full scale (2.499886 V for the ± 2.5 V range).
The full-scale error is the deviation of the actual level of the last
transition from the ideal level.

Bipolar Zero Error

The difference between the ideal midscale input voltage (0 V)
and the actual voltage producing the midscale output code.

Unipolar Zero Error

In unipolar mode, the first transition should occur at a level
1/2 LSB above analog ground. The unipolar zero error is the
deviation of the actual transition from that point.

Spurious Free Dynamic Range (SFDR)

The difference, in decibels (dB), between the rms amplitude of
the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

A measurement of the resolution with a sine wave input. It is
related to S/(N + D) by the following formula:

ENOB S N D

and is expressed in bits.

Total Harmonic Distortion (THD)

The rms sum of the first five harmonic components to the rms
value of a full-scale input signal; expressed in decibels.

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist frequency,
excluding harmonics and dc. The value for SNR is expressed in
decibels.

Signal-to-(Noise + Distortion) Ratio (S/[N + D])

The ratio of the rms value of the actual input signal to the rms
sum of all other spectral components below the Nyquist frequency,
including harmonics but excluding dc. The value for S/(N + D)
is expressed in decibels.

Aperture Delay

A measure of the acquisition performance, measured from the
falling edge of the CNVST input to when the input signal is
held for a conversion.

Transient Response

The time required for the ADC to achieve its rated accuracy
after a full-scale step function is applied to its input.

=+

/–./.176 602

[]

()

()

dB

DAC DEFINITION OF SPECIFICATIONS
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation in LSBs from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in TPC 16.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB maximum
ensures monotonicity. TPC 19 illustrates a typical DNL versus
code plot.

Gain Error

Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from ideal.

Gain Error Temperature Coefficient

This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/∞C.

Zero Code Error

Zero code error is a measure of the output error when zero code
is loaded to the DAC register.

Zero Code Temperature Coefficient

This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/∞C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV–s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in Figure 28.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. CS_DAC is
held high, while the CLK and DIN signals are toggled. It is
specified in nV–s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typical
plot of digital feedthrough is shown in Figure 27.

Power Supply Rejection Ratio

This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power supply rejection
ratio is quoted in terms of percent change in output per percent
change in V
by ± 10%.

Reference Feedthrough

This is a measure of the feedthrough from the V
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1Vp-p is applied to V
in mV p-p.

for full-scale output of the DAC. VDD is varied

DD

input to the

REF

. Reference feedthrough is expressed

REF

REV. A–14–