116 dB Min, 120 dB Typical @ 1 ms
117 dB Typical @ 0.5 ms
Low Input Noise: 80 nV rms @ 4 ms with
Gain of 34,128
Low Distortion: –111 dB Max, –120 dB Typical
Low Intermodulation: 122 dB
Sampling Rate at 256 kSPS
Very High Jitter Tolerance
No External Antialias Filter Required
Programmable Gain Front End
Input Range: 2.25 V
Robust Inputs
Gain Settings: 1, 2.5, 8.5, 34, 128
Common-Mode Rejection (DC to 1 kHz)
93 dB Min, 101 dB Typical @ Gain of 1
77 mW Typical Low Power Dissipation
Standby Modes
AD1556
FIR Digital Filter/Decimator
Serial or Parallel Selection of Configuration
Output Word Rates: 250 SPS to 16 kSPS
6.2 mW Typ Low Power Dissipation
70 W in Standby Mode
Reference Design and Evaluation Board with
Software Available
APPLICATIONS
Seismic Data Acquisition Systems
Chromatography
Automatic Test Equipment
GENERAL DESCRIPTION
The AD1555 is a complete sigma-delta modulator, combined
with a programmable gain amplifier intended for low frequency,
with Low Noise PGA
AD1555/AD1556
high dynamic range measurement applications. The AD1555
outputs a ones-density bitstream proportional to the analog
input. When used in conjunction with the AD1556 digital filter/
decimator, a high performance ADC is realized.
The continuous-time analog modulator input architecture avoids
the need for an external antialias filter. The programmable gain
front end simplifies system design, extends the dynamic range,
and reduces the system board area. Low operating power and
standby modes makes the AD1555 ideal for remote battery-powered data acquisition systems.
The AD1555 is fabricated on Analog Devices’ BiCMOS process
that has high performance bipolar devices along with CMOS
transistors. The AD1555 and AD1556 are packaged, respectively,
in 28-lead PLCC and 44-lead MQFP packages and are specified
from –55°C to +85°C (AD1556 and AD1555 B Grade) and from
0°C to 85°C (AD1555 A Grade).
Figure 1. FFT Plot, Full-Scale AIN Input, Gain of 1
FUNCTIONAL BLOCK DIAGRAM
REFINREFCAP2 REFCAP1 AGND3
MODE CONTROL
OVERVOLTAGE
DETECTION
–V
A
LOGIC
CLOCK
GENERATION
L
AIN (+)
AIN (–)
TIN (+)
TIN (–)
MUX
PGA
REF DIVIDER
DAC
LOOP
FILTER
AD1555
+V
AGND2MODINPGAOUTAGND1CLKIN SYNC BW0...BW2 RESET PWRDN GND V
A
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
(+VA = +5 V; –VA = –5 V; VL = 5 V; AGND = DGND = 0 V; MCLK = 256 kHz; TA = T
T
AD1555–SPECIFICATIONS
ParameterNotesMinTypMaxMinTypMaxUnit
PGA Gain Settings1, 2.5, 8.5, 34, 128
AC ACCURACY
Dynamic Range
Total Harmonic Distortion
Jitter Tolerance
Intermodulation Distortion
DC ACCURACY
Absolute Gain Error
Gain Stability Over Temperature
5, 6
Offset
Offset Drift
ANALOG INPUT
Full-Scale Nondifferential InputMODIN±2.25±2.25V
Input ImpedanceMODIN2020k⍀
Full-Scale Differential InputPGA Gain of 1±2.25±2.25V
Differential Input ImpedanceAIN, TIN Inputs140140MΩ
Common-Mode Range±2.25±2.25V
Common-Mode Rejection RatioV
Power Supply Rejection Ratio
AIN to TIN Crosstalk Isolationf
Differential Input Current130130nA
TEMPERATURE RANGE
Specified PerformanceT
REFERENCE INPUT
Input Voltage Range2.9903.03.0102.9903.03.010V
Input Current130130µA
DIGITAL INPUTS OUTPUTS
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
5, 6
1
PGA Gain of 1116.5120116120dB
PGA Gain of 2.5116119.5115.5119.5dB
PGA Gain of 8.5114117.5114117.5dB
PGA Gain of 34104.5109.5104.5109.5dB
2
PGA Gain of 1289898dB
PGA Gain of 1–120–111–120–107dB
PGA Gain of 2.5–116–108–116–107dB
PGA Gain of 8.5–116–106–116–105dB
PGA Gain of 34–115–101–115–101dB
3
4
5
PGA Gain of 128–108–108dB
PGA Gain of 1122122dB
PGA Gain of 1, 2.5–3.5+3.5–3.5+3.5%
PGA Gain of 8.5–4.5+4.5–4.5+4.5%
PGA Gain of 34–10+10–10+10%
5
All PGA Gain–60–60mV
Other PGA Gain Settings
= ±2.25 V, fIN = 200 Hz
CM
PGA Gain of 19310191101dB
PGA Gain of 2.59510291.5102dB
PGA Gain of 8.5, 3495.510894.5108dB
PGA Gain of 128108108dB
Tested at the output word rate FO = 1 kHz. FO is the AD1556 output word rate, the inverse of the sampling rate. See Tables I, Ia, Ib for other output
word rates.
2
Tested with a full-scale input signal at approximately 24 Hz.
3
This parameter is guaranteed by design.
4
Tested at the output word rate FO = 1 kHz with input signals of 30 Hz and 50 Hz, each 6 dB down full scale.
5
This specification is for the AD1555 only and does not include the errors from external components as, for instance, the external reference.
6
This offset specification is referred to the modulator output.
7
Characterized with a 100 mV p-p sine wave applied separately to each supply.
8
Contact factory for extended temperature range.
9
Recommended Reference: AD780BR.
10
Specified with analog inputs grounded.
11
See Table III for configuration conditions.
12
Specified with MCLK input grounded.
Specifications subject to change without notice.
4.7555.254.7555.25V
–5.25–5–4.75–5.25–5–4.75V
4.7555.254.7555.25V
810810mA
89.589.5mA
77967796mW
56705670mW
AD1556–SPECIFICATIONS
(VL = 2.85 V to 5.25 V; CLKIN = 1.024 MHz; TA = T
MIN
to T
unless otherwise noted.)
MAX
AD1556AS
ParameterNotesMinTypMaxUnit
FILTER PERFORMANCES
Pass-Band Ripple–0.05+0.05dB
Stop-Band AttenuationAll Filters Except F
(+VA = +5 V 5%; –VA = –5 V 5%; AD1555 VL = 5 V 5%, AD1556 VL = 2.85 V to 5.25 V;
TIMING SPECIFICATIONS
CLKIN Frequency
CLKIN Duty Cycle Error4555%
MCLK Output Frequency
SYNC Setup Timet
SYNC Hold Timet
CLKIN Rising to MCLK Output Falling on SYNCt
CLKIN Falling to MCLK Output Risingt
CLKIN Falling to MCLK Output Fallingt
MCLK Input Falling to MDATA Fallingt
MCLK Input Rising to MDATA and MFLG Validt
TDATA Setup Time after SYNCt
TDATA Hold Timet
RESET Setup Timet
RESET Hold Timet
CLKIN Falling to DRDY Risingt
CLKIN Rising to DRDY Falling
CLKIN Rising to ERROR Fallingt
RSEL to Data Validt
RSEL Setup to SCLK Fallingt
DRDY to Data Validt
DRDY High Setup to SCLK Fallingt
R/W to Data Validt
R/W High Setup to SCLK Fallingt
CS to Data Validt
CS Low Setup to SCLK Fallingt
SCLK Rising to DOUT Validt
SCLK High Pulsewidtht
SCLK Low Pulsewidtht
SCLK Periodt
SCLK Falling to DRDY Falling
CS High or R/W Low to DOUT Hi-Zt
R/W Low Setup to SCLK FallingtCS Low Setup to SCLK Fallingt
Data Setup Time to SCLK Fallingt
Data Hold Time after SCLK Fallingt
R/W Hold Time after SCLK Fallingt
NOTES
1
The gain of the modulator is proportional to f
2
With DRDYBUF low only. When DRDYBUF is high, this timing also depends on the value of the external pull-down resistor.
Specifications subject to change without notice.
1
1
CLKIN = 1.024 MHz; AGND = DGND = 0 V; CL = 50 pF; TA = T
SymbolMinTypMaxUnit
f
CLKIN
1
2
3
4
5
6
7
8
9
10
11
2
2
and MCLK frequency.
CLKIN
12
t
13
14
15
16
17
18
19
20
21
22
23
24
25
26
t
27
28
29
30
31
32
33
to T
MIN
, unless otherwise noted)
MAX
0.9751.0241.075MHz
f
/4
CLKIN
10ns
10ns
20ns
20ns
20ns
30ns
100ns
5ns
5ns
15ns
15ns
20ns
20ns
50ns
25ns
10ns
25ns
10ns
25ns
10ns
25ns
10ns
25ns
25ns
25ns
70ns
20ns
20ns
10ns
10ns
10ns
10ns
10ns
REV. B
TO OUTPUT
PIN
50pF
1.6mA
C
L
500A
I
OL
1.4V
I
OH
Figure 2. Load Circuit for Digital Interface Timing
–5–
AD1555/AD1556
CLKIN
SYNC
MCLK
(FS)
t
t
1
t
3
2
t
4
t
5
MDATA
TDATA
RESET
CLKIN
SYNC
DRDY
DATA VALIDDATA VALID
t
6
t
t
8
9
t
7
VALIDVALID
Figure 3. AD1555/AD1556 Interface Timing
t
t
10
11
t
t
1
2
t
t
12
13
t
12
ERROR
Figure 4. AD1556 RESET, DRDY, and Overwrite Timings
–6–
t
14
REV. B
RSEL
DRDY
R/W
DOUT
SCLK
CS
AD1555/AD1556
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
MSBMSB–1LSB+1LSB
t
23
t
t
t
24
25
26
Figure 5. Serial Read Timing
t
27
t
28
HI-Z
CS
R/W
SCLK
DIN
t
29
t
30
t
t
t
32
31
MSBMSB–1LSB+1LSB
26
t
24
t
25
Figure 6. Serial Write Timing
t
33
REV. B
–7–
AD1555/AD1556
ABSOLUTE MAXIMUM RATINGS
1
Analog Inputs
Pins 7, 8, 23, 24, 25, 28 . . . . . . –V
– 0.3 V to +VA + 0.3 V
A
AIN(+), AIN(–) DC Input Current . . . . . . . . . . . ± 100 mA
AIN(+), AIN(–) 2 µs Pulse Input Current . . . . . . . . ± 1.5 A
Supply Voltages
to –VA . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +14 V
+V
A
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
+V
A
–VA to AGND . . . . . . . . . . . . . . . . . . . . . . . –7 V to +0.3 V
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AD1555AP 0°C to 85°C Plastic Lead Chip Carrier P-28A
AD1555APRL 0°C to 85°C Plastic Lead Chip Carrier P-28A
AD1555BP –55°C to +85°C Plastic Lead Chip Carrier P-28A
AD1555BPRL –55°C to +85°C Plastic Lead Chip Carrier P-28A
AD1556AS –55°C to +85 °C Plastic Quad Flatpack S-44A
AD1556ASRL –55°C to +85 °C Plastic Quad Flatpack S-44A
EVAL-AD1555/AD1556EB
AD1555/56-REF Reference Design
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1555/AD1556 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–8–
REV. B
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