ANALOG DEVICES AD15252 Service Manual
A
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12-Bit, 65 MSPS, Dual ADC
FEATURES
12-bit, 65 MSPS dual ADC
Differential input with 100 Ω input impedance
Full-scale analog input: 296 mV p-p
170 MHz, 3 dB bandwidth
SNR (−9 dBFS): 64 dBFS (70 MHz AIN), 64 dBFS (140 MHz AIN)
SFDR (−9 dBFS): 77 dBFS (70 MHz AIN), 73 dBFS (140 MHz AIN)
435 mW per channel
Dual parallel output buses
Out-of-range indicators
Independent clocks
Duty cycle stabilizer
OBSOLETE
Twos complement or offset binary data format
APPLICATIONS
Antijam GPS receivers
Wireless and wired broadband communications
Communications test equipment
OTR_A
PDWN
OEB_A
PDWNB
OEB_B
OTR_B
FUNCTIONAL BLOCK DIAGRAM
CLKA
INA
DFS
CLKB
INB
LPF
LPF
Figure 1.
AD15252
AD15252
DATA
BUS A
DATA
BUS B
05154-001
GENERAL DESCRIPTION
The AD15252 is a dual, 12-bit, 65 MSPS, analog-to-digital
converter (ADC). It features a differential front-end
amplification circuit followed by a sample-and-hold amplifier
and multistage pipeline ADC. It is designed to operate with a
3.3 V analog supply and a 2.5 V/3.3 V digital supply. Each input
is fully differential, ac-coupled, and terminated in 100 Ω input
impedances. The full-scale differential signal input range is
296 mV p-p.
Two parallel, 12-bit digital output buses provide data flow from
t
he ADCs. The digital output data is presented in either straight
binary or twos complement format. Out-of-range (OTR) signals
indicate an overflow condition, which can be used with the
most significant bit to determine low or high overflow. Dual
single-ended clock inputs control all internal conversion cycles.
A duty cycle stabilizer allows wide variations in the clock duty
cycle while maintaining excellent performance. The AD15252 is
optimized for applications in antijam global positioning
receivers and is well suited for communications applications.
PRODUCT HIGHLIGHTS
1. Dual 12-bit, 65 MSPS ADC with integrated analog signal
conditioning optimized for antijam global positioning
system receiver (AJ-GPS) applications.
perates from a single 3.3 V power supply and features a
2. O
separate digital output driver supply to accommodate 2.5 V
and 3.3 V logic families.
ackaged in a space-saving 8 mm × 8 mm chip scale
3. P
package ball grid array (CSP_BGA) and is specified over
the industrial temperature range (–40°C to +85°C).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
AD15252
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TABLE OF CONTENTS
Electrical Characteristics................................................................. 3
Clock Input and Considerations .............................................. 11
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Analog Input ............................................................................... 11
Volt a ge R e fe r e nc e ....................................................................... 11
OBSOLETE
REVISION HISTORY
8/05—Revision 0: Initial Version
Power Dissipation and Standby Mode .................................... 11
Digital Outputs........................................................................... 12
Timing ......................................................................................... 12
Data Format ................................................................................ 12
PCB and Evaluation Board............................................................ 13
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
Rev. 0 | Page 2 of 20
AD15252
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ELECTRICAL CHARACTERISTICS
AVDD = 3.3 V, DRVDD = 2.5 V, encode = 65 MSPS, CLK_A = CLK_B, AIN = −9 dBFS differential input, TA= 25°C, unless otherwise
noted.
Table 1.
Parameter Temp Test Level Min Typ Max Unit
RESOLUTION 12 Bits
ACCURACY
No Missing Codes 25°C IV Guaranteed
Offset Error 25°C I −6 ±1.7 +6 % FSR
Gain Error 25°C I −12.5 ±2.0 +12.5 % FSR
Differential Nonlinearity (DNL) Full V ±0.35 LSB
Integral Nonlinearity (INL) Full V ±0.8 LSB
TEMPERATURE DRIFT
Offset Error Full V ±9 ppm/°C
Gain Error Full V ±172 ppm/°C
MATCHING CHARACTERISTICS
OBSOLETE
Offset Error Full V ±2.0 % FSR
Gain Error Full V ±1.0 % FSR
Input Referred Noise Full V 0.87 LSB rms
ANALOG INPUT
Input Range Full IV 296 mV p-p
Input Resistance (RIN)
Input Capacitance (CIN)
CLOCK INPUTS
High Level Input Voltage (VIH) Full IV 2.0 V
Low Level Input Voltage (V
High Level Input Current (IIH) Full IV −10 +10 μA
Low Level Input Current (IIL) Full IV −10 +10 μA
Input Capacitance (CIN) Full V 2 pF
LOGIC OUTPUTS
High Level Output Voltage (VOH) Full IV 2.49 V
Low Level Output Voltage (VOL) Full IV 0.2 V
INTERFACE TIMING
Maximum Conversion Rate Full VI 65 MSPS
Minimum Conversion Rate Full IV 1 MSPS
Clock Period (tC) Full V 15.4 ns
Clock Width High (tCH) Full IV 6.2 ns
Clock Width Low (tCL) Full IV 6.2 ns
Clock to Data (tOD) Full IV 2 6 ns
Pipeline Delay (Latency) Full V 7 Cycles
POWER SUPPLIES
Supply Voltages
AVDD Full IV 3.0 3.3 3.6 V
DRVDD Full IV 2.25 2.5 3.6 V
Supply Currents
AVDD Full VI 254 280 mA
DRVDD Full VI 12 15 mA
Total Power Dissipation Full VI 0.87 1.0 W
1
1
IL)
25°C V 100 Ω
25°C V 1.8 pF
Full IV 0.8 V
Rev. 0 | Page 3 of 20
AD15252
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Parameter Temp Test Level Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
f
= 70 MHz 25°C I 62.7 64.2 dBFS
INPUT
f
= 110 MHz 25°C V 64.1 dBFS
INPUT
f
= 140 MHz 25°C I 62.5 64 dBFS
INPUT
SINAD
f
= 70 MHz 25°C I 62.4 63.9 dBFS
INPUT
f
= 110 MHz 25°C V 63.7 dBFS
INPUT
f
= 140 MHz 25°C I 61.9 63.3 dBFS
INPUT
THD
f
= 70 MHz Full V −76 dBFS
INPUT
f
= 110 MHz Full V −74 dBFS
INPUT
f
= 140 MHz Full V −72 dBFS
INPUT
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
= 70 MHz 25°C I 72.7 77.8 dBFS
INPUT
f
= 110 MHz 25°C V 75.9 dBFS
INPUT
f
= 140 MHz 25°C I 68 73.8 dBFS
INPUT
OBSOLETE
CROSSTALK 25°C V −70 dB
1
Input resistance and capacitance shown as differential.
Table 2. Explanation of Test Levels
Test Level Description
I 100% production tested.
II 100% production tested at 25°C, and sample tested at specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization testing.
V Parameter is a typical value only.
VI
All devices are 100% production tested at 25°C, guaranteed by design and characterization testing for industrial
ature range; 100% production tested at temperature extremes for military devices.
temper
Rev. 0 | Page 4 of 20
AD15252
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
AVDD to AGND −0.3 V, +3.9 V
DRVDD to DRGND −0.3 V, +3.9 V
DRGND to AGND −0.3 V, +0.3 V
DRVDD to AVDD −3.9 V, +3.9 V
Analog Inputs −0.3 V, AVDD + 0.3 V
Digital Outputs −0.3 V, DRVDD + 0.3 V
CLK −0.3 V, AVDD + 0.3 V
Operational Case Temperature −40°C to 85°C
Storage Temperature Range −65°C to 150°C
Lead Temperature: Infrared, 15 sec 230°C
OBSOLETE
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 20
AD15252
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
87654321
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
A1 VINA Analog Input Pin (+) for Channel A.
OBSOLETE
A2 VINA Analog Input Pin (−) for Channel A.
H1 VINB
H2
B4 CLK_A
G4 CLK_B Clock Input Pin for Channel B.
C4 PDWN_A Power-Down Function Selection for Channel A (Active High).
F4 PDWN_B Power-Down Function Selection for Channel B (Active High).
A4 OTR_A Out-of-Range Indicator for Channel A.
E8 OTR_B Out-of-Range Indicator for Channel B.
A3 VCM_A Channel A Common Mode.
H3 VCM_B Channel B Common Mode.
D4 OEB_A Output Enable for Channel A. Logic 0 enables Data Bus A; Logic 1 sets outputs to high-Z.
E4 OEB_B Output Enable for Channel B. Logic 0 enables Data Bus B; Logic 1 sets outputs to high-Z.
C5 D11_A(MSB) Channel A Data Output Bit 11 (MSB).
A5 D10_A Channel A Data Output Bit 10.
B5 D09_A Channel A Data Output Bit 9.
A6 D08_A
B6 D07_A Channel A Data Output Bit 7.
A7 D06_A
B7 D05_A
A8 D04_A
C6 D03_A
B8 D02_A
C7 D01_A Channel A Data Output Bit 1.
C8 D00_A(LSB)
E3 DFS
E7 D11_B(MSB)
F8 D10_B Channel B Data Output Bit 10.
F7 D09_B
G8 D08_B Channel B Data Output Bit 8.
VINB
Analog Input Pin (+) for Channel B.
Analog Input Pin (−) for Channel B.
Clock Input Pin for Channel A.
Channel A Data Output Bit 8.
Channel A Data Output Bit 6.
Channel A Data Output Bit 5.
Channel A Data Output Bit 4.
Channel A Data Output Bit 3.
Channel A Data Output Bit 2.
Channel A Data Output Bit 0 (LSB).
Data Output Format Select Bit (Logic 0 for offset binary, Logic 1 for twos complement).
Channel B Data Output Bit 11 (MSB).
Channel B Data Output Bit 9.
BOTTOM VIEW
(Not to Scale)
A
B
C
D
E
F
G
H
05154-003
Rev. 0 | Page 6 of 20
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