Analog Devices AD14160L, AD14160 Datasheet

Quad-SHARC

®

a

PERFORMANCE FEATURES

...

ADSP-21060 Core Processor (
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle

Instruction Execution–Each of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two

from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended

Precision IEEE Floating Point Data Formats, or

32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation
PACKAGING FEATURES

452-Lead Ceramic Ball Grid Array (CBGA)

1.85" (47 mm) Body Size

0.200" Max Height

0.050" Ball Pitch
29 Grams (typical)

= 0.368C/W

u

JC

34)

ID

2-0

CPA
SPORT 1
SPORT 0
TDI

AD14160/

AD14160L

ID

2-0

CPA
SPORT 1
SPORT 0
TDO

CS

LINK 1

TIMEXP

SHARC_A

EMU

EBOOT,

LBOOT, BMS

EMU

EBOOT,

LBOOT, BMS

SHARC_D

CS

TIMEXP

LINK 1

DSP Multiprocessor Family

AD14160/AD14160L

FUNCTIONAL BLOCK DIAGRAM

3-0

2-0

LINK 0

IRQ

LINK 2

LINK 3

LINK 4

FLAG

LINK 5

TDO

CLKIN

RESET

CLKIN

RESET

LINK 2

TCK, TMS, TRST

SHARC BUS (

SBTS, HBR, HBG, REDY, BR

LINK 3

LINK 4

ADDR

LINK 0

TCK, TMS, TRST

LINK 5

3-0

2-0

TDI

IRQ

FLAG

31-0

,

DATA

CS

LINK 0

LINK 5
TDI

47-0

LINK 0

LINK 5
TDO

MS

,

LINK 1

TIMEXP

SHARC_B

EMU

CLKIN

EBOOT,

3-0

EBOOT,

RESET

LBOOT, BMS

,

RD, WR, PAGE, ADRCLK, SW, ACK,

, RPBA, DMAR

6-1

EMU

CLKIN

RESET

LBOOT, BMS

SHARC_C

CS

TIMEXP

LINK 1

LINK 2

LINK 3

LINK 2

LINK 3

2-0

IRQ

LINK 4

SPORT 1
SPORT 0

TCK, TMS, TRST

, DMAG

1.2

1.2

SPORT 1

TCK, TMS, TRST

SPORT 0

2-0

LINK 4

IRQ

3-0

ID

FLAG

CPA

)

ID
CPA

3-0

FLAG

2-0

TDO

TDI

2-0

GENERAL DESCRIPTION

The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi­processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance—density and lowest
cost— performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.

The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on­chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.

SHARC is a registered trademark of Analog Devices, Inc.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.

Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti­mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.

s

s

s

s

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1998

AD14160/AD14160L

DETAILED DESCRIPTION
Architectural Features

ADSP-21060 Core

The AD14160/AD14160L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on­chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess­ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith­metic/ logic unit (ALU), multiplier and shifter all perform single­cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.

The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro­gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch­ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which

CORE PROCESSOR

INSTRUCTION

DAG1

8 x 4 x 32

BUS

CONNECT

(PX)

DAG2

8 x 4 x 24

TIMER

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

CACHE

32 x 48-BIT

PROGRAM

SEQUENCER

24PM ADDRESS BUS

32

48

40/32

PROCESSOR PORT I/O PORT

ADDR DATA ADDR

ADDR DATA

is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC’s core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex­ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.

The SHARCs contain 4 Mbits of on-chip SRAM each, orga­nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16­bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con­troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.

DUAL-PORTED SRAM

TWO INDEPENDENT

DUAL-PORTED BLOCKS

DATA

DATA

IOD
48

ADDR

IOA
17

BLOCK 0

BLOCK 1

JTAG

TEST AND

EMULATION

EXTERNAL

PORT

ADDR BUS

MUX

MULTIPROCESSOR

INTERFACE

DATA BUS

MUX

HOST PORT

7

32

48

DATA

REGISTER

FILE

16 x 40-BIT

BARREL
SHIFTER

IOP

REGISTERS

(

ALUMULTIPLIER

MEMORY MAPPED)

CONTROL,

STATUS, AND

DATA BUFFERS

DMA

CONTROLLER

SERIAL PORTS

(2)

LINK PORTS

(6)

4
6

6

36

I/O PROCESSOR

Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)

–2–

REV. A

AD14160/AD14160L

INTERNAL

MEMORY

SPACE

(INDIVIDUAL

SHARCs)

MULTIPROCESSOR

MEMORY SPACE

IOP REGISTERS

NORMAL WORD ADDRESSING

SHORT WORD ADDRESSING

INTERNAL MEMORY SPACE

OF SHARC_A

ID=001

INTERNAL MEMORY SPACE

OF SHARC_B

INTERNAL

TO AD14160x

EXTERNAL

TO AD14160x

NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS

SHORT WORD ADDRESSING: 16-BIT DATA WORDS

INTERNAL MEMORY SPACE

INTERNAL MEMORY SPACE

INTERNAL MEMORY SPACE

INTERNAL MEMORY SPACE

ID=010

OF SHARC_C

ID=011

OF SHARC_D

ID=100

OF ADSP-2106x

WITH ID=101

OF ADSP-2106x

WITH ID=110

BROADCAST WRITE

TO ALL

ADSP-2106xs

0x0000 0000

0x0002 0000

0x0004 0000

0x0008 0000

0x0010 0000

0x0018 0000

0x0020 0000

0x0028 0000

0x0030 0000

0x0038 0000

0x003F FFFF

EXTERNAL

MEMORY

SPACE

BANK 0

DRAM

(OPTIONAL)

BANK 1

BANK 2

BANK 3

NONBANKED

0x0040 0000

MS

0

MS

1

MS

2

MS

3

BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.

0xFFFF FFFF

Figure 2. AD14160/AD14160L Memory Map

SYSTEM EXPANSION

1X CLOCK

CLKIN

RESET

BOOTSELECT A
BOOTSELECT BCD

DMAR1,2

DMAG1,2

SPORT0
SPORT1

JTAG

SHARC_A

LINKS 1, 2, 3, & 4;

IRQ

2-0

FLAG
TIMEXP,

SPORT1

CPA

ID

-0

2

SHARC_D

LINKS 1, 2, 3, & 4;

IRQ

2-0

FLAG
TIMEXP,

SPORT1

CPA

ID

-0

2

;

;

3-0

(QUAD PROCESSOR

;

;

3-0

SHARC_B

LINKS 1, 2, 3, & 4;

IRQ

2-0

FLAG
TIMEXP,

SPORT1

CPA

ID

-0

2

AD14160/

AD14160L

CLUSTER)

SHARC_C

LINKS 1, 2, 3, & 4;

IRQ

2-0

FLAG
TIMEXP,

SPORT1

CPA

ID

-0

2

ADDR

31-0

DATA

;

;

3-0

;

;

3-0

47-0

RD

WR

ACK

MS

PAGE

SBTS

SW

ADRCLK

CS

HBR

HBG

REDY

BR

RPBA

3-0

1-6

Figure 3. Complete Shared Memory Multiprocessing System

REV. A

–3–

AD14160/AD14160L

Shared Memory Multiprocessing

The AD14160/AD14160L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14160/AD14160L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified ad­dress space of the SHARCs allows direct interprocessor ac­cesses of each SHARCs’ internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multi-processor memory space (see Fig­ure 2)—this is called a direct read or direct write.

Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1–BR4 are used within the AD14160/AD14160L, while BR5
and BR6 can be used for expansion. All bus requests (BR1–BR6)
are included in the module I/O.

Two different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitra­tion is selected, and when RPBA is low, fixed priority is selected.

Table I. Rotating Priority Arbitration Example

Hardware Processor IDs

Cycle ID1 ID2 ID3 ID4 ID5 ID6

1M12 BR345Initial Priority Assignments
2 4 5 BR M-BR 1 2 3
3 4 5 BR M 1 2 3
4 5 BR M 1 2 3 4 BR
51 BR23 45MFinal Priority Assignments

NOTES
1–5 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.

Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can therefore re­tain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is as­serted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in Table I.

Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. The AD14160/AD14160L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the implemen­tation of reflective semaphores.

The bus master can communicate with slave SHARCs by writ­ing messages to their internal IOP registers. The MSRG0–
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource shar­ing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave’s VIRPT
register. This causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the speci­fied service routine.

Off-Module Memory and Peripherals Interface

The AD14160/AD14160L’s external port provides the interface to
off-module memory and peripherals (see Figure 5). This port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.

The 4-gigaword off-module address space is included in the
AD14160/AD14160L’s unified address space. Addressing of
external memory devices is facilitated by each SHARC inter­nally decoding the high order address lines to generate memory
bank select signals. Separate control lines are also generated for
simplified addressing of page-mode DRAM. The AD14160/
AD14160L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.

Link Port I/O

Each individual SHARC features six 4-bit link ports that facili­tate SHARC-to-SHARC communication and external I/O inter­facing. Each link port can be configured for either 1× or 2×
operation, allowing each to transfer either 4 or 8 bits per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.

The AD14160/AD14160L provides additional link port I/O
beyond that of the AD14060. Internally, two links from each
SHARC form a ring connection among the four. The remaining
four link ports from each SHARC are brought out indepen­dently from each SHARC. A maximum of 640 MBytes/s link
port bandwidth is then available off of the AD14160/AD14160L.
The link port connections are detailed in Figure 4.

1
2

SHARC_A SHARC_B

3
4

0

0
1
2

SHARC_D SHARC_C

3

4

55

55

1
2

3
4

0

0

1
2

3
4

Figure 4. Link Port Connections

–4–

REV. A

1x

CLOCK

RESET

CLKIN

RESET

RPBA

3

ID

CONTROL

SERIALS
LINKS
DISCRETES

ADSP-2106x #5

CLKIN

RESET

RPBA

3

ID

AD14160/

AD14160L

ADDR
DATA

ADRCLK

(OPTIONAL)

ADDR
DATA

31–0
47–0

WR

ACK

MS

BMS

PAGE

SBTS

HBR

HBG

REDY

CPA

BR

BR

31–0
47–0

RD

3–0

SW

CS

2–6

AD14160/AD14160L

ADDR

OE
WE

ACK

CS

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

BOOT

EPROM

(OPTIONAL)

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

DATA

CS

ADDR
DATA

5

1

ADDR
DATA

CONTROL

CPA

BR

BR

31–0
47–0

CPA

1–5

BR

5

5

5

6

ADSP-2106x #6

CLKIN

RESET

RPBA

3

ID

CONTROL

BR

1

(OPTIONAL)

ADDR
DATA

, 2, 3, 4, 6

Figure 5. Optional System Interconnections

REV. A

–5–

AD14160/AD14160L

Link port 4, the boot link port, is brought off independently
from each SHARC. Individual booting is then allowed, or
chained link port booting is possible as described under “Link
Port Booting.”

Link port data is packed into 32-bit or 48-bit words, and can be
directly read by the SHARC core processor or DMA-transferred
to on-SHARC memory.

Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.

Serial Ports

The SHARC serial ports provide an inexpensive interface to a
wide variety of digital and mixed-signal peripheral devices. Each
SHARC has two serial ports. All eight of the AD14160/AD14160L
serial ports are brought off-module.

The serial ports can operate at the full clock rate of the module,
providing each with a maximum data rate of 40 Mbit/s. Inde­pendent transmit and receive functions provide more flexible
communications. Serial port data can be automatically trans­ferred to and from on-SHARC memory via DMA, and each of
the serial ports offers time division multiplexed (TDM) multi­channel mode.

The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.

Program Booting

The AD14160/AD14160L supports automatic downloading of
programs following power-up or a software reset. The SHARC
offers four options for program booting: 1) from an 8-bit
EPROM; 2) from a host processor; 3) through the link ports;
and 4) no-boot. In no-boot mode, the SHARC starts executing
instructions from address 0x0040 0004 in external memory.
The boot mode is selected by the state of the following signals:
BMS, EBOOT, and LBOOT.

On the AD14160/AD14160L, SHARC_A’s boot mode is sepa­rately controlled, while SHARCs B, C, and D are controlled as
a group. With this flexibility, the AD14160/AD14160L can be
configured to boot in any of the following methods.

Multiprocessor Host Booting

To boot multiple ADSP-21060 processors from a host, each
ADSP-21060 must have its EBOOT, LBOOT and BMS pins
configured for host booting: EBOOT = 0, LBOOT = 0, and
BMS = 1. After system power-up, each ADSP-21060 will be in
the idle state and the BRx bus request lines will be deasserted.
The host must assert the HBR input and boot each ADSP-21060
by asserting its CS pin and downloading instructions.

Multiprocessor EPROM Booting

There are two methods of booting the multiprocessor system
from an EPROM.

SHARC_A Is Booted, Which Then Boots the Others. The
EBOOT pin on the SHARC_A must be set high for EPROM
booting. All other ADSP-21060s should be configured for host
booting (EBOOT = 0, LBOOT = 0, and BMS = 1), which
leaves them in the idle state at start-up and allows SHARC_A

to become bus master and boot itself. Only the BMS pin of
SHARC_A is connected to the chip select of the EPROM.
When SHARC_A has finished booting, it can boot the re­maining ADSP-21060s by writing to their external port DMA
buffer 0 (EPB0) via multiprocessor memory space.

All ADSP-21060s Boot in Turn From a Single EPROM.

The BMS signals from each ADSP-21060 may be wire-ORed
together to drive the chip select pin of the EPROM. Each
ADSP-21060 can boot in turn, according to its priority. When
the last one has finished booting, it must inform the others (which
may be in the idle state) that program execution can begin.

Multiprocessor Link Port Booting

Booting can also be accomplished from a single source through
the link ports. Link Buffer 4 must always be used for booting.
To simultaneously boot all of the ADSP-21060s, a parallel
common connection is available through Link Port 4 on each of
the processors. Or, using the daisy chain connection that exists
between the processors’ link ports, each ADSP-21060 can boot
the next one in turn. In this case, the Link Assignment Register
(LAR) must be programmed to configure the internal link ports
with Link Buffer 4.

Multiprocessor Booting From External Memory

If external memory contains a program after reset, then
SHARC_A should be set up for no boot mode; it will begin ex­ecuting from address 0x0040 0004 in external memory. When
booting has completed, the other ADSP-21060s may be booted
by SHARC_A if they are set up for host booting, or they can
begin executing out of external memory if they are set up for no
boot mode. Multiprocessor bus arbitration will allow this booting
to occur in an orderly manner.

Host Processor Interface

The AD14160/AD14160L’s host interface allows for easy con­nection to standard microprocessor buses, both 16-bit and 32­bit, with little additional hardware required. Asynchronous
transfers at speeds up to the full clock rate of the module are
supported. The host interface is accessed through the AD14160/
AD14160L external port and is memory-mapped into the uni­fied address space. Four channels of DMA are available for the
host interface; code and data transfers are accomplished with
low software overhead.

The host processor requests the AD14160/AD14160L’s external
bus with the host bus request (HBR), host bus grant (HBG),
and ready (REDY) signals. The host can directly read and write
the internal memory of the SHARCs, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.

Direct Memory Access (DMA) Controller

The SHARCs on-chip DMA control logic allows zero-over­head data transfers without processor intervention. The DMA
controller operates independently and invisibly to each SHARCs
processor core, allowing DMA operations to occur while the core
is simultaneously executing its program instructions.

DMA transfers can occur between SHARC internal memory
and either external memory, external peripherals, or a host
processor. DMA transfers can also occur between the SHARC’s
internal memory and its serial ports or link ports. DMA trans­fers between external memory and external peripheral devices are
another option. External bus packing to 16-, 32- or 48-bit words
is performed during DMA transfers.

–6–

REV. A

AD14160/AD14160L

Ten channels of DMA are available on the SHARCs—two via
the link ports, four via the serial ports, and four via the processor’s
external port (for either host processor, other SHARCs, memory,
or I/O transfers). Four additional link port DMA channels are
shared with serial port 1 and the external port. Programs can be
downloaded to the SHARCs using DMA transfers. Asynchro­nous off-module peripherals can control two DMA channels
using DMA Request/Grant lines (DMAR1-2, DMAG1-2).
Other DMA features include interrupt generation upon comple­tion of DMA transfers and DMA chaining for automatic linked
DMA transfers.

Development Tools

The AD14160/AD14160L is supported with a complete set
of software and hardware development tools, including an
EZ-LAB

®

In-Circuit Emulator, and development software.

Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
an Assembly Library/Librarian, a Linker, an Instruction-Level
Simulator, an ANSI C optimizing Compiler, the CBug™ C
Source-Level Debugger, and a C Runtime Library including
DSP and mathematical functions. The Optimizing Compiler
includes Numerical C extensions based on the work of the ANSI
Numerical C Extensions Group. Numerical C provides exten­sions to the C language for array selection, vector math op­erations, complex data types, circular pointers and variably
dimensioned arrays. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.

The SHARC EZ-KIT combines the ADSP-21000 Family De­velopment Software for the PC and the EZ-LAB Development
Board in one package.

The ADSP-2106x EZ-ICE

®

Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x processor to monitor
and control the target board processor during emulation. The

EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers and processor stacks.

Nonintrusive in-circuit emulation is assured by the use of the
processor’s JTAG interface—the emulator does not affect target
system loading or timing.

Further details and ordering information are available in the

ADSP-21000 Family Hardware & Software Development Tools

data sheet (ADDS-2100xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor,
or from the Literature Center.

In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard­ware tools include SHARC PC plug-in cards, multiprocessor
SHARC VME boards, and daughter card modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.

Other Package Details

The AD14160/AD14160L contains 14 on-module 0.1 micro­farad bypass capacitors. It is recommended that in the target
system at least four additional capacitors, of 0.018 microfarad
value, be placed around the module—one near each of the four
corners.

The top surface, lid, of the AD14160/AD14160L is electrically
connected to GND.

Additional Information

This data sheet provides a general overview of the AD14160/
AD14160L architecture and functionality. For detailed infor­mation on the ADSP-2106x SHARC and the ADSP-21000
Family core architecture and instruction set, refer to the
ADSP-2106x SHARC User’s Manual.

EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
CBug and SHARCPAC are trademarks of Analog Devices, Inc.

REV. A

–7–

AD14160/AD14160L

PIN FUNCTION DESCRIPTIONS

AD14160/AD14160L pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing requirements
with respect to CLKIN (or with respect to TCK for TMS,
TDI). Inputs identified as asynchronous (A) can be asserted
asynchronously to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to V
for ADDR

, DATA

31-0

, FLAG

47-0

, SW, and inputs that have

2-0

or GND, except

DD

TCLKx, RCLKx, LxDAT
TDI)—these pins can be left floating. These pins have a logic­level hold circuit that prevents the input from floating internally.

A = Asynchronous O = Output (A/D) = Active Drive
G = Ground P = Power Supply (O/D) = Open Drain
I = Input S = Synchronous
T = Three-State (when SBTS is asserted, or when the AD14160/
AD14160L is a bus slave)

, LxCLK, LxACK, TMS and

3-0

internal pull-up or pull-down resistors (CPA, ACK, DTx, DRx,

Pin Type Function

ADDR

31-0

I/O/T External Bus Address. (Common to all SHARCs) The AD14160/AD14160L outputs addresses for

external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs ad­dresses for read/writes on the internal memory or IOP registers of slave ADSP-2106xs. The AD14160/
AD14160L inputs addresses when a host processor or multiprocessing bus master is reading or writing
the internal memory or IOP registers of internal ADSP-21060s.

DATA

47-0

I/O/T External Bus Data. (Common to all SHARCs) The AD14160/AD14160L inputs and outputs data and

instructions on these pins. 32-bit single-precision floating-point data and 32-bit fixed-point data is trans­ferred over bits 47-16 of the bus. 40-bit extended-precision floating-point data is transferred over bits 47­8 of the bus. 16-bit short word data is transferred over bits 31-16 of the bus. In PROM boot mode, 8-bit
data is transferred over bits 23-16. Pull-up resistors on unused DATA pins are not necessary.

MS

3-0

O/T Memory Select Lines. (Common to all SHARCs) These lines are asserted (low) as chip selects for the

corresponding banks of external memory. Memory bank size must be defined in the individual ADSP­21060’s system control registers (SYSCON). The MS
change at the same time as the other address lines. When no external memory access is occurring the MS

lines are decoded memory address lines that

3-0

3-0

lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether
or not the condition is true. MS
(Bank 0). In a multiprocessing system, the MS

can be used with the PAGE signal to implement a bank of DRAM memory

0

lines are output by the bus master.

3-0

RD I/O/T Memory Read Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/

AD14160L reads from external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert RD to read from the AD14160/
AD14160L’s internal memory. In a multiprocessing system, RD is output by the bus master and is input
by all other ADSP-2106xs.

WR I/O/T Memory Write Strobe. (Common to all SHARCs) This pin is asserted (low) when the AD14160/

AD14160L writes to external devices or when the internal memory of internal ADSP-2106xs is being
accessed. External devices (including other ADSP-2106xs) must assert WR to write to the AD14160/
AD14160L’s internal memory. In a multiprocessing system WR is output by the bus master and is input by all
other ADSP-2106xs.

PAGE O/T DRAM Page Boundary. (Common to all SHARCs) The AD14160/AD14160L asserts this pin to signal

that an external DRAM page boundary has been crossed. DRAM page size must be defined in the indi­vidual ADSP-21060’s memory control register (WAIT). DRAM can only be implemented in external
memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses. In a multiprocessing system,
PAGE is output by the bus master.

ADRCLK O/T Clock Output Reference. (Common to all SHARCs) In a multiprocessing system, ADRCLK is output

by the bus master.

SW I/O/T Synchronous Write Select. (Common to all SHARCs) This signal is used to interface the AD14160/

AD14160L to synchronous memory devices (including other ADSP-2106xs). The AD14160/AD14160L
asserts SW (low) to provide an early indication of an impending write cycle, which can be aborted if WR
is not later asserted (e.g., in a conditional write instruction). In a multiprocessing system, SW is output
by the bus master and is input by all other ADSP-2106xs to determine if the multiprocessor memory
access is a read or write. SW is asserted at the same time as the address output. A host processor using
synchronous writes must assert this pin when writing to the AD14160/AD14160L.

ACK I/O/S Memory Acknowledge. (Common to all SHARCs) External devices can deassert ACK (low) to add

wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other pe­ripherals to hold off completion of an external memory access. The AD14160/AD14160L deasserts ACK,
as an output, to add wait states to a synchronous access of its internal memory. In a multiprocessing
system, a slave ADSP-2106x deasserts the bus master’s ACK input to add wait state(s) to an access of its
internal memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level
it was last driven to.

–8–

REV. A

AD14160/AD14160L

Pin Type Function

SBTS I/S Suspend Bus Three-State. (Common to all SHARCs) External devices can assert SBTS (low) to

place the external bus address, data, selects, and strobes in a high impedance state for the following cycle.
If the AD14160/AD14160L attempts to access external memory while SBTS is asserted, the processor
will halt and the memory access will not be completed until SBTS is deasserted. SBTS should only be
used to recover from host processor/AD14160/AD14160L deadlock, or used with a DRAM controller.

HBR I/A Host Bus Request. (Common to all SHARCs) Must be asserted by a host processor to request control

of the AD14160/AD14160L’s external bus. When HBR is asserted in a multiprocessing system, the
ADSP-2106x that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the
ADSP-2106x places the address, data, select, and strobe lines in a high impedance state. HBR has priority
over all ADSP-2106x bus requests (BR

HBG I/O Host Bus Grant. (Common to all SHARCs) Acknowledges an HBR bus request, indicating that the

host processor may take control of the external bus. HBG is asserted (held low) by the AD14160/
AD14160L until HBR is released. In a multiprocessing system, HBG is output by the ADSP-2106x bus
master and is monitored by all others.

CSA I/A Chip Select. Asserted by host processor to select SHARC_A.
CSB I/A Chip Select. Asserted by host processor to select SHARC_B.
CSC I/A Chip Select. Asserted by host processor to select SHARC_C.
CSD I/A Chip Select. Asserted by host processor to select SHARC_D.

REDY (O/D) O Host Bus Acknowledge. (Common to all SHARCs) The AD14160/AD14160L deasserts REDY (low)

to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain
output (O/D) by default; can be programmed in ADREDY bit of SYSCON register of individual ADSP­21060s to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.

BR

6-1

I/O/S Multiprocessing Bus Requests. (Common to all SHARCs) Used by multiprocessing ADSP-2106xs to

arbitrate for bus mastership. An ADSP-2106x only drives its own BRx line (corresponding to the value of
its ID2-0 inputs) and monitors all others. In a multiprocessor system with less than six ADSP-2106xs, the
unused BRx pins should be pulled high; BR

IDy2-0 I Multiprocessing ID. (Individual ID2–0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D.)

Determines which multiprocessing bus request (BR1–BR6) is used by individual ADSP-2106x’s. ID =
001 corresponds to BR1, ID = 010 corresponds to BR2, etc. ID = 000 is reserved for single processor
systems. These lines are a system configuration selection, which should be hardwired or only changed at
reset.

RPBA I/S Rotating Priority Bus Arbitration Select. (Common to all SHARCs) When RPBA is high, rotating

priority for multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-2106x. If the
value of RPBA is changed during system operation, it must be changed in the same CLKIN cycle on
every ADSP-2106x.

CPAy (O/D) I/O Core Priority Access. (y = SHARC_A, B, C, D) Asserting its CPA pin allows the core processor of an

ADSP-2106x bus slave to interrupt background DMA transfers and gain access to the external bus.
CPA is an open drain output that is connected to all ADSP-2106x in the system if this function is
required. The CPA pin of each internal ADSP-21060 is brought out individually. The CPA pin has
an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, the CPA pin
should be left unconnected.

DTy0 O/T Data Transmit (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DT

pin has a 50 kΩ internal pull-up resistor.

DRy0 I Data Receive (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). DR pin

has a 50 kΩ internal pull-up resistor.

TCLKy0 I/O Transmit Clock (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).

TCLK pin has a 50 kΩ internal pull-up resistor.

RCLKy0 I/O Receive Clock (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D). RCLK

pin has a 50 kΩ internal pull-up resistor.

TFSy0 I/O Transmit Frame Sync (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).
RFSy0 I/O Receive Frame Sync (Serial Port 0 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D).

) in a multiprocessing system.

6-1

must not be pulled high or low because they are outputs.

4-1

REV. A

–9–

AD14160/AD14160L

Pin Type Function

DTy1 O/T Data Transmit (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DT pin

has a 50 kΩ internal pull-up resistor.

DRy1 I Data Receive (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) DR pin

has a 50 kΩ internal pull-up resistor.

TCLKy1 I/O Transmit Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) TCLK

pin has a 50 kΩ internal pull-up resistor.

RCLKy1 I/O Receive Clock (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D) RCLK

pin has a 50 kΩ internal pull-up resistor.

TFSy1 I/O Transmit Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
RFSy1 I/O Receive Frame Sync (Serial Port 1 individual from SHARC_A, SHARC_B, SHARC_C, SHARC_D)
FLAGy3-0 I/O/A Flag Pins. (Individual FLAG3-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Each is

configured via control bits as either an input or output. As an input, it can be tested as a condition. As an
output, it can be used to signal external peripherals.

IRQy2-0 I/A Interrupt Request Lines. (Individual IRQ2-0 from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D)

May be either edge-triggered or level-sensitive.

DMAR1 I/A DMA Request 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAR2 I/A DMA Request 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG1 O/T DMA Grant 1 (DMA Channel 7). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.
DMAG2 O/T DMA Grant 2 (DMA Channel 8). Common to SHARC_A, SHARC_B, SHARC_C, SHARC_D.

LyxCLK I/O Link Port Clock (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)

internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register, of the
ADSP-20160.

LyxDAT3-0 I/O Link Port Data (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)

50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.

LyxACK I/O Link Port Acknowledge (y = SHARC_A, B, C, D; x = Link Ports 1, 2, 3, 4)

50 kΩ internal pull-down resistor which is enabled or disabled by the LPDRD bit of the LCOM register,
of the ADSP-21060.

EBOOTA I EPROM Boot Select. (SHARC_A) When EBOOTA is high, SHARC_A is configured for booting from

an 8-bit EPROM. When EBOOTA is low, the LBOOTA and BMSA inputs determine booting mode for
SHARC_A. See the following table. This signal is a system configuration selection which should be hardwired.

LBOOTA I Link Boot. When LBOOTA is high, SHARC_A is configured for link port booting. When LBOOTA is

low, SHARC_A is configured for host processor booting or no booting. See the following table. This
signal is a system configuration selection which should be hardwired.

BMSA I/O/T

2

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTA = 1,
LBOOTA = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates
that no booting will occur and that SHARC_A will begin executing instructions from external memory.
See the following table. This input is a system configuration selection which should be hardwired.

EBOOTBCD I EPROM Boot Select. (Common to SHARC_B, SHARC_C, SHARC_D) When EBOOTBCD is high,

SHARC_B, C, D are configured for booting from an 8-bit EPROM. When EBOOTBCD is low, the
LBOOTBCD and BMSBCD inputs determine booting mode for SHARC_B, C and D. See the following
table. This signal is a system configuration selection which should be hardwired.

LBOOTBCD I LINK Boot. (Common to SHARC_B, SHARC_C, SHARC_D) When LBOOTBCD is high, SHARC_B, C,

D are configured for link port booting. When LBOOTBCD is low, SHARC_B, C, D are configured for
host processor booting or no booting. See the following table. This signal is a system configuration selec­tion which should be hardwired.

1

. Each LyxCLK pin has a 50 kΩ

1

. Each LyxDAT pin has a

1

. Each LyxACK pin has a

–10–

REV. A

AD14160/AD14160L

Pin Type Function

2

BMSBCD I/O/T

TIMEXPy O Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted

CLKIN I Clock In. (Common to all SHARCs) External clock input to the AD14160/AD14160L. The instruction

RESET I/A Module Reset. (Common to all SHARCs) Resets the AD14160/AD14160L to a known state. This input

TCK I Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary

TMS I/S Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has

TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.

TDO O Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.

TRST I/A Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted

EMU (O/D) O Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target

V

DD

P Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (50 pins).

GND G Power Supply Return. (64 pins).

NOTES

1

LINK PORTS 0 and 5 are connected internally as described earlier in Link Port I/O.

2

Three-statable only in EPROM boot mode (when BMS is an output).

Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1,
LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. This input is a system configuration selection which should be
hardwired.

EBOOT LBOOT BMS Booting Mode
1 0 Output EPROM (Connect BMS to EPROM chip select)

0 0 1 (Input) Host Processor
0 1 1 (Input) Link Port
0 0 0 (Input) No Booting. Processor executes from external memory.
0 1 0 (Input) Reserved
1 1 x (Input) Reserved

for four cycles when the timer is enabled and TCOUNT decrements to zero.

cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.

must be asserted (low) at power-up.

scan.

a 20 kΩ internal pull-up resistor.

TDI has a 20 kΩ internal pull-up resistor.

(pulsed low) after power-up or held low for proper operation of the AD14160/AD14160L. TRST has a
20 kΩ internal pull-up resistor.

board connector only.

REV. A

–11–

AD14160/AD14160L

TARGET BOARD CONNECTOR FOR EZ-ICE PROBE

The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and con­trol the target board processor during emulation. The EZ-ICE
probe requires that the AD14160/AD14160L’s CLKIN (op­tional), TMS, TCK, TRST, TDI, TDO, EMU and GND signals
be made accessible on the target system via a 14-pin connector
(a pin strip header) such as that shown in Figure 6. The EZ­ICE probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The
length of the traces between the connector and the AD14160/
AD14160L’s JTAG pins should be as short as possible.

GND

KEY (NO PIN)

BTMS

BTCK

BTRST

BTDI

GND

12

34

56

78

910

9

11 12

13 14

TOP VIEW

EMU

CLKIN (OPTIONAL)

TMS

TCK

TRST

TDI

TDO

Figure 6. Target Board Connector for ADSP-2106x EZ-ICE
Emulator (Jumpers in Place)

The 14-pin, 2-row pin strip header is keyed at the Pin 3 location;
Pin 3 must be removed from the header. The pins must be

0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.

The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins as shown in
Figure 6. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
V

. The TRST pin must be asserted after power-up (through

DD

BTRST on the connector) or held low for proper operation of
the AD14160/AD14160L. None of the Bxxx pins (Pins 5, 7, 9,

11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:

Signal Termination

TMS Driven through 22 Ω Resistor (16 mA/3.2 mA Driver)
TCK Driven at 10 MHz through 22 Ω Resistor (16 mA/

3.2 mA Driver)

TRST Driven by Open-Drain Driver* (Pulled Up by On-Chip

20 kΩ Resistor)

TDI Driven by 16 mA/3.2 mA Driver
TDO One TTL Load, No Termination
CLKIN One TTL Load, No Termination (Optional Signal)
EMU 4.7 kΩ Pull-Up Resistor, One TTL Load (Open-Drain

Output from ADSP-2106x)

*TRST is driven low until the EZ-ICE probe is turned on by the EZ-ICE

software (after the invocation command).

Figure 7 shows JTAG scan path connections for the multi­processor system.

OTHER

JTAG

CONTROLLER

EZ-ICE

JTAG

CONNECTOR

TCK
TMS

EMU

TRST

TDO

CLKIN

TDI

SHARC_A

TDI TDO

TCK

TMS

OPTIONAL

EMU

TRST

SHARC_B

TDI TDO

TCK

TMS

EMU

TRST

SHARC_C

TDI TDO

TCK

TMS

EMU

TRST

SHARC_D

TDI TDO

TCK

TMS

EMU

TRST

Figure 7. JTAG Scan Path Connections for the AD14160/AD14160L

JTAG DEVICE

(OPTIONAL)

TDI TDO

TCK

TMS

TRST

ADSP-2106x

#n

TDI TDO

TCK

TMS

EMU

TRST

–12–

REV. A

AD14160/AD14160L

Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op­erations such as starting, stopping and single-stepping multiple
ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces­sors, simply tie Pin 4 of the EZ-ICE header to ground.

If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the AD14160/
AD14160L and the CLKIN pin on the EZ-ICE header must be
minimal. If the skew is too large, synchronous operations may
be off by one cycle between processors. For synchronous multi­processor operation TCK, TMS, CLKIN and EMU should be

TDI TDO TDI TDO

5kV

*

TDI

EMU

TCK
TMS

TRST

TDO

CLKIN

TDI TDO

5kV

*

*

OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,

TDI

treated as critical signals in terms of skew, and should be laid
out as short as possible on your board. If TCK, TMS and
CLKIN are driving a large number of ADSP-2106xs (more than
eight) in your system, then treat them as a “clock tree” using
multiple drivers to minimize skew. (See Figure 8 JTAG Clock
Tree and Clock Distribution in the “High Frequency Design
Considerations” section of the ADSP-2106x User’s Manual).

If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina­tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.

TDI TDO

TDO

TDI

EMU

TDO

SYSTEM
CLKIN

Figure 8. JTAG Clocktree for Multiple ADSP-2106x Systems

REV. A

–13–

AD14160/AD14160L–SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

Parameter Min Max Min Max Units

B Grade K Grade

V

T

DD

CASE

Supply Voltage (5 V) 4.75 5.25 4.75 5.25 V
Supply Voltage (3.3 V) 3.15 3.6 3.15 3.6 V
Case Operating Temperature –40 +100 0 +85 °C

ELECTRICAL CHARACTERISTICS (5 V, 3.3 V SUPPLY)

Parameter Temp Level Test Condition Min Typ Max Min Typ Max Units

V

IH1

V

IH2

V

IL

V

OH

V

OL

I

IH

I

IHX4

I

IL

I

ILX4

I

ILP

I

ILPX4

I

OZH

I

OZHX4

I

OZL

I

OZLX4

I

OZHP

I

OZLC

I

OZLAR

I

OZLA

I

OZLS

I

DDIN

I

DDIDLE

C

IN

High Level Input Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
High Level Input Current
Low Level Input Current
Low Level Input Current
Low Level Input Current
Low Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current

Three-State Leakage Current
Supply Current (Internal)
Supply Current (Idle)
Input Capacitance

1
2

1, 2

3, 4

3, 4
5, 6
7, 8

5
7
6
8

9, 10, 11
12
9, 13
12
13
14
11
15

10

16

17

18, 19

EXPLANATION OF TEST LEVELS
Test Level

I 100% Production Tested

20

.

II 100% Production Tested at +25°C, and Sample Tested at Specified Temperatures.
III Sample Tested Only.
IV Parameter is guaranteed by design and analysis, and characterization testing on discrete SHARCs.
V Parameter is typical value only.
VI All devices are 100% production tested at +25°C; sample tested at temperature extremes.

NOTES

1

Applies to input and bidirectional pins: DATA
RPBA, CPAy, TFSy0, TFSy1, RFSy0, RFSy1, LyxDAT
TDI, TCK, HBR, DRy0, DRy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1.

2

Applies to input pins: CLKIN, RESET, TRST.

3

Applies to output and bidirectional pins: DATA

DMAG2, BR
BMSBCD, TDO, EMU.

4

See Output Drive Currents for typical drive current capabilities.

5

Applies to input pins: IRQy

6

Applies to input pins with internal pull-ups: DRy0, DRy1, TDI.

7

Applies to bussed input pins: SBTS, HBR, DMAR1, DMAR2, RPBA, EBOOTBCD, LBOOTBCD, CLKIN, RESET, TCK.

8

Applies to bussed input pins with internal pull-ups: TRST, TMS.

9

Applies to three-statable pins: FLAGy0-3, BMSA, TDO.

10

Applies to three-statable pins with internal pull-ups: DTy0, TCLKy0, RCLKy0, DTy1, TCLKy1, RCLKy1.

11

Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
ADSP-2106x is not requesting bus mastership.)

12

Applies to bussed three-statable pins: DATA

that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID
HBG and EMU are not tested for leakage current.)

, CPAy, DTy0, DTy1, TCLKy0, TCLKy1, RCLKy0, RCLKy1, TFSy0, TFSy1, RFSy0, RFSy1 LyxDAT

6-1

, CSy, IDy0-2, EBOOTA, LBOOTA.

2-0

Case Test 5 V 3.3 V

Full I @ VDD = max 2.0 VDD + 0.5 2.0 VDD + 0.5 V
Full I @ VDD = max 2.2 VDD + 0.5 2.2 VDD + 0.5 V
Full I @ VDD = min 0.8 0.8 V
Full I @ VDD = min, IOH = –2.0 mA44.1 2.4 V
Full I @ VDD = min, IOL = 4.0 mA

4

0.4 0.4 V
Full I @ VDD = max, VIN = VDD max 10 10 µA
Full I @ VDD = max, VIN = VDD max 40 40 µA
Full I @ VDD = max, VIN = 0 V 10 10 µA
Full I @ VDD = max, VIN = 0 V 40 40 µA
Full I @ VDD = max, VIN = 0 V 150 150 µA
Full I @ VDD = max, VIN = 0 V 600 600 µA
Full I @ VDD = max, VIN = VDD max 10 10 µA
Full I @ VDD = max, VIN = VDD max 40 40 µA
Full I @ VDD = max, VIN = 0 V 10 10 µA
Full I @ VDD = max, VIN = 0 V 40 40 µA
Full I @ VDD = max, VIN = VDD max 350 350 µA
Full I @ VDD = max, VIN = 0 V 1.5 1.5 mA
Full I @ VDD = max, VIN = 0 V 4.2 4.2 mA
Full I @ VDD = max, VIN = 2 V (3.3 V),

1.5 V (5 V) 350 350 µA

Full I @ VDD = max, VIN = 0 V 150 150 µA
Full IV tCK = 25 ns, VDD = max 1.4 3.4 1 2.2 A
Full I VDD = max 800 760 mA

47-0

, ADDR

47-0

, ADDR

47-0

, ADDR

+25°CV

, RD, WR, SW, ACK, SBTS, IRQy

31-0

, LyxCLK, LyxACK, EBOOTA, LBOOTA, EBOOTBCD, LBOOTBCD, BMSA, BMSBCD, TMS,

3-0

, MS

RD, WR, PAGE, ADRCLK, SW, ACK, FLAGy0-3, TIMEXPy, HBG, REDY, DMAG1,

3-0

, RD, WR, PAGE, ADRCLK, SW, ACK, REDY, HBG, DMAG1, DMAG2, BMSBCD, EMU. (Note

3-0

31-0

31-0

, MS

, FLAGy0-3, HBG, CSy, DMAR1, DMAR2, BR

2-0

= 001 and another ADSP-2106x is not requesting bus mastership.

2-0

15 15 pF

, LyxCLK, LyxACK, BMSA,

3-0

= 001 and another

2-0

, IDy0-2,

6-1

–14–

REV. A

AD14160/AD14160L

13

Applies to three-statable pins with internal pull-downs: LyxDAT

14

Applies to CPAy pin.

15

Applies to ACK pin when keeper latch enabled.

16

Applies to VDD pins. Conditions of operation: each processor executing radix-2 FFT butterfly with instruction in cache, one data operand fetched from each inter­nal memory block, and one DMA transfer occurring from/to internal memory at tCK = 25 ns.

17

Applies to VDD pins. Idle denotes AD14160/AD14160L state during execution of IDLE instruction.

18

Applies to all signal pins.

19

Guaranteed but not tested.

20

Link and Serial Ports: All are 100% tested at die level prior to assembly. All are 100% ac tested at module level; Link-4 and Serial-0 are also dc tested at the module
level. See Timing Specifications.

Specifications subject to change without notice.

, LyxCLK, LyxACK.

3-0

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage (5 V) . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Supply Voltage (3.3 V) . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to V

Output Voltage Swing . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

DD

+ 0.5 V

DD

*Stresses greater than those listed above may cause permanent damage to the

device. These are stress ratings only; functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF

Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Solder Ball Temperature (5 seconds) . . . . . . . . . . . . . +230°C

ESD SENSITIVITY

The AD14160/AD14160L modules are ESD (electrostatic discharge) sensitive devices. Electro­static charges readily accumulate on the human body and equipment and can discharge without
detection. Permanent damage may occur to devices subjected to high energy electrostatic
discharges.

The ADSP-21060 processors include proprietary ESD protection circuitry to dissipate high
energy discharges. Per method 3015 of MIL-STD-883, the ADSP-21060 processors have been
classified as a Class 2 device.

Proper ESD precautions are recommended to avoid performance degradation or loss of function­ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination socket before devices are removed.

While addition or subtraction would yield meaningful results for

TIMING SPECIFICATIONS

GENERAL NOTES

This data sheet represents production released specifications for
the AD14160L (3.3 V), and the AD14160 (5 V). The ADSP­21060 die components are 100% tested, and the assembled
AD14160/AD14160L units are again extensively tested at­speed, and across-temperature. Parametric limits were estab­lished from the ADSP-21060 characterization followed by
further design/analysis of the AD14160/AD14160L package char­acteristics. The specifications shown are based on a CLKIN
frequency of 40 MHz (t
specifications at other CLKIN frequencies (within the min-max
range of the t

specification; see “Clock Input” below). DT is the

CK

difference between the actual CLKIN period and a CLKIN period
of 25 ns:

Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.

= 25 ns). The DT derating allows

CK

DT = t

– 25 ns

CK

an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.

Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.

Timing Requirements apply to signals that are controlled by cir­cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.

(O/D) = Open Drain
(A/D) = Active Drain

WARNING!

ESD SENSITIVE DEVICE

REV. A

–15–

AD14160/AD14160L

40 MHz–5 V 40 MHz–3.3 V

Parameter Min Max Min Max Units
Clock Input

Timing Requirements:

t

CK

t

CKL

t

CKH

t

CKRF

CLKIN Period 25 100 25 100 ns
CLKIN Width Low 7 8.75 ns
CLKIN Width High 5 5 ns
CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 ns

t

CK

CLKIN

t

CKH

t

CKL

Figure 9. Clock Input

40 MHz–5 V 40 MHz–3.3 V

Parameter Min Max Min Max Units
Reset

Timing Requirements:

t

WRST

t

SRST

NOTES

1

Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).

2

Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after
reset.

RESET Pulsewidth Low
RESET Setup Before CLKIN High214.5 + DT/2 t

CLKIN

RESET

1

4t

CK

t

WRST

CK

4t

CK

14.5 + DT/2 t

t

SRST

CK

ns
ns

Figure 10. Reset

40 MHz–5 V 40 MHz–3.3 V

Parameter Min Max Min Max Units
Interrupts

Timing Requirements:

t

SIR

t

HIR

t

IPW

NOTES

1

Only required for IRQx recognition in the following cycle.

2

Applies only if t

SIR

IRQ

Setup Before CLKIN High118 + 3DT/4 18 + 3DT/4 ns

2-0

IRQ

Hold Before CLKIN High

2-0

IRQ

Pulsewidth

2-0

and t

requirements are not met.

HIR

2

CLKIN

IRQ

1

2 + t

CK

2-0

t

IPW

12 + 3DT/4 12 + 3DT/4 ns

2 + t

CK

t

SIR

t

HIR

ns

Figure 11. Interrupts

–16–

REV. A