ALTERA HardCopy IV GX Service Manual

HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

Preliminary

Preliminary PCG-01009-1.0

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The pin connection guidelines are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera.

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Disclaimer Page 1 of 18

HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

Preliminary

Preliminary PCG-01009-1.0

You should create a Quartus II design, enter your device I/O assignments and compile the design. The Quartus II software will check your pin connections with respect to I/O assignment and placement rules to ensure proper device operation. These rules are dependent on device density, package, I/O assignments, voltage assignments and other factors that are not fully described in this document or the device handbook.

HardCopy IV GX Pin Name HardCopy IV E Pin Name

Clock and PLL Pins

CLK[1,3,8,10]p CLK[1,3,8,10]p Clock, Input Dedicated high speed clock input pins 1, 3, 8,

CLK[1,3,8,10]n CLK[1,3,8,10]n Clock, Input Dedicated negative clock input pins for

CLK[0,2,9,11]p CLK[0,2,9,11]p I/O, Clock These pins can be used as I/O pins or clock

CLK[0,2,9,11]n CLK[0,2,9,11]n I/O, Clock These pins can be used as I/O pins or negativ

CLK[4:7, 12:15]p CLK[4:7, 12:15]p I/O, Clock These pins can be used as I/O pins or clock

CLK[4:7, 12:15]n CLK[4:7, 12:15]n I/O, Clock These pins can be used as I/O pins or negativ

PLL_[L1, L4, R1, R4]_CLKp PLL_[L1, L4, R1, R4]_CLKp Clock, Input Dedicated clock input pins to PLL L1, L4, R1,

PLL_[L1, L4, R1, R4]_CLKn PLL_[L1, L4, R1, R4]_CLKn Clock, Input Dedicated negative clock input pins for

PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n

PLL_[L1, L2, L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p

PLL_[T1, T2, B1, B2]_FBp/CLKOUT1 PLL_[T1, T2, B1, B2]_FBp/CLKOUT1 I/O, Clock These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software

PLL_[T1, T2, B1, B2]_FBn/CLKOUT2 PLL_[T1, T2, B1, B2]_FBn/CLKOUT2 I/O, Clock These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software

PLL_[T1, T2, B1, B2]_CLKOUT[3,4] PLL_[T1, T2, B1, B2]_CLKOUT[3,4] I/O, Clock These pins can be used as I/O pins or two

PLL_[L1, L2, L3, L4]_CLKOUT0n PLL_[R1, R2, R3, R4]_CLKOUT0n

PLL_[L1, L2, L3, L4]_FB_CLKOUT0p PLL_[R1, R2, R3, R4]_FB_CLKOUT0p

Pin Type (1st and 2nd Function)

I/O, Clock These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software

Pin Description Connection Guidelines

and 10 that can also be used for data inputs. OCT Rd is not supported on these pins.

differential clock input that can also be used fo data inputs. OCT Rd is not supported on these pins.

input pins. OCT Rd is supported on these pins.

clock input pins for differential clock inputs. OCT Rd is supported on these pins.

input pins. OCT Rd is not supported on these pins.

clock input pins for differential clock inputs. OCT Rd is not supported on these pins.

and R4 respectively. OCT Rd is not supported on these pins.

differential clock input to PLL L1, L4, R1, and R4 respectively. OCT Rd is not supported on these pins.

Each left and right PLL supports 2 clock I/O pins, configured either as 2 single ended I/O or one differential I/O pair. When using both pins as single ended I/Os, PLL_#_CLKOUT0n can be the clock output while the PLL_#_FB_CLKOUT0p is the external feedback input pin.

Dual purpose I/O pins that can be used as two single-ended outputs or one differential external feedback input pin.

single-ended clock output pins.

Connect unused pins to GND.

These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

Connect unused pins to GND.

programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND. These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

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HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

Preliminary

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HardCopy IV GX Pin Name HardCopy IV E Pin Name

PLL_[T1, T2, B1, B2]_CLKOUT0p PLL_[T1, T2, B1, B2]_CLKOUT0p I/O, Clock These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software

PLL_[T1, T2, B1, B2]_CLKOUT0n PLL_[T1, T2, B1, B2]_CLKOUT0n I/O, Clock These pins can be tied to GND or left unconnected. If unconnected, use Quartus II software

Dedicated Configuration / JTAG Pins

nIO_PULLUP nIO_PULLUP Input Dedicated input that chooses whether the

TEMPDIODEp TEMPDIODEp Input Pin used in conjunction with the temperature

TEMPDIODEn TEMPDIODEn Input Pin used in conjunction with the temperature

MSEL[0:2] MSEL[0:2] Input Pins are configuration inputs for Stratix IV

nCE nCE Input Dedicated active-low chip enable. When nCE

nCONFIG nCONFIG Input Dedicated power up block control input. Pulling

CONF_DONE CONF_DONE Bidirectional

Pin Type (1st and 2nd Function)

(open-drain)

Pin Description Connection Guidelines

I/O pins that can be used as two single-ended clock output pins or one differential clock output pair.

internal pull-up resistors on the user I/O pins are on or off during power up. A logic high turns off the weak pull-ups, while a logic low turns them on.

sensing diode (bias-high input) inside the HardCopy IV device.

sensing diode (bias-low input) inside the HardCopy IV device.

FPGA only, they set the FPGA prototype configuration scheme. MSEL[0:2] are NC (No Connection) pins for HardCopy IV devices, but they preserve the pin assignment and direction from the Stratix IV prototype, allowing drop-in replacement.

is low, the device is enabled. When nCE is high, the device is disabled.

this pin low during user-mode will cause the HardCopy IV to enter a reset state and tri-state all I/O pins. Returning this pin to a logic high level will initiate the power up and initialization sequence. It is not available as a user I/O pin.

This is a dedicated power up block status pin. As a status output, the CONF_DONE pin drives low before and during initialization. When this pin is driven high it indicates that th device is entering user mode.

programmable options to internally bias these pins. They can be reserved as inputs tristate with weak pull-up resistor enabled, or as outputs driving GND.

The nIO-PULLUP can be tied directly to VCCPGM, use a 1 KΩ pull-up resistor or tied directly to GND depending on the use desired for the device. The user I/O pins with internal pull-ups controlled by the nIO_PULLUP are nCSO, ASDO, DATA[7:0], CLKUSR, INIT_DONE, DEV_OE, and DEV_CLRn.

If the temperature sensing diode is not used then connect this pin to GND.

The connection to the board on these pins are "don't care" for HardCopy IV.

In the prototype stage using the Stratix IV these pins are internally connected through a 5-KΩ resistor t GND. Do not leave these pins floating. When these pins are unused connect them to GND. Depending on the configuration scheme used these pins should be tied to VCCPGM or GND. Refer to the "Configuring Stratix IV Devices" chapter in the Stratix IV Handbook. If only JTAG configuration is used, connect these pins to GND. See Note 15.

If multi-devices are on a board, the configuration data stored in the FPGA device must be updated to exclude the configuration data for the HardCopy device. The nCE pin of the HardCopy IV device must be connected to GND. The nCE pin of the FPGA that was driven by the HardCopy IV nCEO pin must now be driven by the nCEO pin of the FPGA that precedes the HardCopy IV device in the chain. In single HardCopy device, nCE pin must be connected to GND.

In the prototype stage using the Stratix IV in a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. However, in single device configuration and JTAG programming, nCE should be connected to GND. See Note 15.

For HardCopy IV devices, the nCONFIG pin is designed with weak internal resistor pulled up to VCCPGM. The board can be designed to have additional switching capability to this pin to allow pulsing the nCONFIG in order to restart the HardCopy IV device.

In the prototype stage using the Stratix IV nCONFIG should be connected directly to the configuration controller when the FPGA uses a passive configuration scheme, or through a 10-KΩ resistor tied to VCCPGM when using an active serial configuration scheme. If this pin is not used, it requires a connection directly or through a 10-KΩ resistor to VCCPGM. See Note 15.

For HardCopy IV devices, the CONF_DONE pin is designed with weak internal resistor pulled up to VCCPGM.

In the prototype stage using the Stratix IV when internal pull-up resistors on the configuration controller or enhanced configuration device are used, external 10-KΩ pull-up resistors should not be used on this pin. Otherwise an external 10-KΩ pull-up resistor to VCCPGM should be used. When using Passive configuration schemes this pin should also be monitored by the configuration controller. See Note 15.

Pin Connection Guidelines Page 3 of 18

HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

Preliminary

Preliminary PCG-01009-1.0

HardCopy IV GX Pin Name HardCopy IV E Pin Name

nCEO nCEO Output Output that drives low when device

nSTATUS nSTATUS Bidirectional

PORSEL PORSEL Input Dedicated input which selects between a POR

TCK TCK Input Dedicated JTAG test clock input pin. Connect this pin to a 1-KΩ pull-down resistor to GND. TMS TMS Input Dedicated JTAG test mode select input pin. Connect this pin to a 10-KΩ pull-up resistor to VCCPD. To disable the JTAG circuitry connect TMS to

TDI TDI Input Dedicated JTAG test data input pin. Connect this pin to a 10-KΩ pull-up resistor to VCCPD. To disable the JTAG circuitry connect TDI to

TDO TDO Output Dedicated JTAG test data output pin. The JTAG circuitry can be disabled by leaving TDO unconnected. TRST TRST Input Dedicated active low JTAG test reset input pin.

Optional/Dual Purpose Configuration Pins

nCSO nCSO Output Dedicated control signal from the Stratix IV

ASDO ASDO Output Dedicated control signal from the Stratix IV

DCLK DCLK Input(PS, FPP)

Pin Type (1st and 2nd Function)

(open-drain)

Output (AS)

Pin Description Connection Guidelines

configuration is complete.

This is a dedicated power up block status pin. When the HardCopy IV device drives nSTATUS low, it indicates that the device is being initialized. As a status output, the nSTATUS is pulled low if an error occurs during initialization. As a status input, this pin delays the completion of the Initialization phase when nSTATUS is driven low by an external source during initialization. It is not available as a user I/O pin.

time of 12 ms or 100 ms. A logic high selects a POR time of 12 ms and a logic low selects POR time of 100 ms.

TRST is used to asynchronously reset the JTAG boundary-scan circuit.

device to the serial configuration device in AS mode that enables the configuration device. This pin is kept in HardCopy IV for compatibility reasons.

device to the serial configuration device in AS mode used to read out configuration data. This pin is kept in HardCopy IV for compatibility reasons.

Dedicated configuration clock pin on the Stratix IV device. In PS and FPP configuration, DCLK is used to clock configuration data from an external source into the FPGA. In AS mode, DCLK is an output from the FPGA that provides timing for the configuration interface. This pin is kept in HardCopy IV for compatibility reasons.

nCEO is left floating for HardCopy IV devices.

In the prototype stage using the Stratix IV with multi-device configuration, this pin feeds the nCE pin of a subsequent device. During single device configuration, leave this pin unconnected. See Note 15. For HardCopy IV devices, nSTATUS pin is designed with weak internal resistor pulled up to VCCPGM.

In the prototype stage using the Stratix IV if internal pull-up resistors on the enhanced configuration device are used, external 10-KΩ pull-up should not be used on these pins. Otherwise, an external 10-KΩ pull-up resistors to VCCPGM should be used. When using Passive configuration schemes this pin should also be monitored by the configuration controller. See Note 15.

The PORSEL pin should be tied directly to VCCPGM or GND.

VCCPD via a 1-KΩ resistor.

Utilization of TRST is optional. When using this pin ensure that TMS is held high or TCK is static when TRST is changed from low to high. If not using TRST, tie this pin to a 1-KΩ pull-up resistor to VCCPD. To disable the JTAG circuitry, tie this pin to GND.

When this pin is not used as an output then it is recommended to leave the pin unconnected. If Erasable Programmable Configuration Serial (EPCS) is used in user mode as a boot-up RAM or data access for a Nios II processor, DCLK, DATA[0], ASDO, and nCSO need to be connected to the EPCS device.

For HardCopy IV leave this pin unconnected. If Erasable Programmable Configuration Serial (EPCS) is used in user mode as a boot-up RAM or data access for a Nios II processor, DCLK, DATA[0], ASDO, and nCSO need to be connected to the EPCS device.

In the prototype stage using the Stratix IV do not leave this pin floating. Drive this pin ether high or low. See Note 15.

Pin Connection Guidelines Page 4 of 18

HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

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HardCopy IV GX Pin Name HardCopy IV E Pin Name

CRC_ERROR CRC_ERROR I/O, Output

DEV_CLRn DEV_CLRn I/O, Input Optional pin for Stratix IV FPGA that allows

DEV_OE DEV_OE I/O, Input Optional pin for Stratix IV FPGA that allows

DATA[0] DATA[0] I/O, Input Dual-purpose configuration data input pin for

DATA[1:7] DATA[1:7] I/O, Input Dual-purpose configuration data input pin for

INIT_DONE INIT_DONE I/O, Output

CLKUSR CLKUSR I/O, Input Optional user-supplied clock input in Stratix IV

Pin Type (1st and 2nd Function)

(open-drain)

Pin Description Connection Guidelines

Active high signal that indicates that the error detection circuit has detected errors in the configuration SRAM bits on the Stratix IV device. This pin is optional and is used when the CRC error detection circuit is enabled in the Stratix IV FPGA.

designers to override all clears on all device registers. In this case, when this pin is driven low, all registers are cleared; when this pin is driven high (VCCPGM), all registers behave as programmed.

designers to override all tri-states on the device. In this case, when the pin is driven low, all I/O pins are tri-stated; when this pin is driven high (VCCPGM), all I/O pins behave as defined in the design.

Stratix IV FPGA. In this case, the DATA0 pin can be used for bit-wide configuration or as an I/O pin after configuration is complete.

Stratix IV FPGA. In this case the DATA[0:7] pins can be used for byte-wide configuration or as regular I/O pins. These pins can also be used as user I/O pins after configuration.

This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE in Stratix IV FPGA. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

FPGA. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin.

For HardCopy IV, the pin retains the same I/O functions from Stratix IV prototype, but not CRC_ERROR because no device programming is needed. See Note 10.

In the prototype stage using the Stratix IV connect this pin to an external 10-KΩ pull-up resistor to VCCPGM. See Note 15.

For HardCopy IV, this pin is an I/O function only. See Note 10.

In the prototype stage using the Stratix IV when DEV_CLRn is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground. See Note 15.

For HardCopy IV, this pin is an I/O function only. See Note 10.

In the prototype stage using the Stratix IV when DEV_OE is not used and this pin is not used as an I/O then it is recommended to tie this pin to ground. See Note 15.

In the prototype stage using the Stratix IV when DATA0 is not used and this pin is not used as an I/O then it is recommended to leave this pin unconnected. See Note 15.

For HardCopy IV, these pins are I/O functions only. See Note 10.

In the prototype stage using the Stratix IV when DATA[1:7] is not used and this pin is not used as an I/O then it is recommended to leave these pins unconnected. See Note 15.

For HardCopy IV, this pin is an I/O function only. See Note 10.

In the prototype stage using the Stratix IV connect this pin to an external 10-KΩ pull-up resistor to VCCPGM. See Note 15.

For HardCopy IV, this pin is an I/O function only. See Note 10.

In the prototype stage using the Stratix IV if the CLKUSR is not used as a configuration clock input and this pin is not used as an I/O then it is recommended to leave this pin to GND. See Note 15.

Pin Connection Guidelines Page 5 of 18

HardCopy® IV GX and HardCopy IV E Device Family Pin Connection Guidelines

Preliminary

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HardCopy IV GX Pin Name HardCopy IV E Pin Name

Differential I/O Pins

DIFFIO_RX[##]p, DIFFIO_RX[##]n

DIFFIO_TX[##]p, DIFFIO_TX[##]n

DIFFOUT_[##]p, DIFFOUT_[##]n

External Memory Interface Pins

DQS[1:38][T,B], DQS[1:34][L,R]

DQSn[1:38][T,B], DQSn[1:34][L,R]

DIFFIO_RX[##]p, DIFFIO_RX[##]n

DIFFIO_TX[##]p, DIFFIO_TX[##]n

DIFFOUT_[##]p, DIFFOUT_[##]n

DQS[1:38][T,B], DQS[1:34][L,R]

DQSn[1:38][T,B], DQSn[1:34][L,R]

Pin Type (1st and 2nd Function)

I/O, RX channel These are true LVDS receiver channels on

I/O, TX channel These are true LVDS transmitter channels on

I/O, TX channel These are emulated LVDS output channels.

I/O, DQS Optional data strobe signal for use in external

I/O, DQSn Optional complementary data strobe signal for

Pin Description Connection Guidelines

side and column I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

side I/O banks. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers. However, all column user I/Os, including I/Os with true LVDS input buffers, can be configured as emulated LVDS output buffers. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with a "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins.

memory interfacing. These pins drive to dedicated DQS phase shift circuitry. The shifted DQS signal can also drive to internal logic.

use in external memory interfacing. These pins drive to dedicated DQS phase shift circuitry.

Connect unused pins as defined in Quartus II software.

DQ[1:38][T,B], DQ[1:34][L,R]

CQ[1:38][T,B], CQ[1:34][L,R]

DQ[1:38][T,B], DQ[1:34][L,R]

CQ[1:38][T,B], CQ[1:34][L,R]

I/O, DQ Optional data signal for use in external

memory interfacing. The order of the DQ bits within a designated DQ bus is not important; however, use caution when making pin assignments if you plan on migrating to a different memory interface that has a different DQ bus width. Analyze the available DQ pins across all pertinent DQS columns in the pin list.

DQS Optional data strobe signal for use in QDR II

SRAM. These are the pins for echo clocks.

Pin Connection Guidelines Page 6 of 18

Connect unused pins as defined in Quartus II software.

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Disclaimer Page 1 of 18

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