ALTERA HardCopy IV Service Manual

January 2011
HIV51001-2.3

HIV51001-2.3

1. HardCopy IV Device Family Overview

This chapter provides an overview of features available in the HardCopy®IV device
family. More details about these features can be found in their respective chapters.

HardCopy IV ASICs are the only 40-nm system-capable ASICs designed with an
FPGA design flow. Altera's fifth generation of HardCopy IV ASICs deliver low-cost
and high-performance at low-power. Based on a 0.9-V, 40-nm process, the
HardCopy IV family is supported by Stratix®IV FPGAs, which have complementary
pin-outs, densities, and architectures that deliver in-system, at-speed prototyping—
resulting in first-time-right ASICs. The Quartus®II software provides a complete set
of tools for designing the Stratix IV FPGA prototypes and HardCopy IV ASICs. One
design, one RTL, one set of intellectual property, and one tool deliver both ASIC and
FPGA implementations. Other front-end design tools from Synopsys and Mentor
Graphics® are also supported.

To reduce risk, HardCopy IV device features, such as phase-locked loops (PLLs),
embedded memory, transceivers, and I/O elements (IOEs), are functionally and
electrically equivalent to the Stratix IV FPGA features. To reduce cost, Altera®
HardCopy IV devices are customized using only two metal and three via layers. The
combination of the Quartus II software for design, Stratix IV FPGAs for in-system
prototype and design verification, and HardCopy IV devices for high-volume
production provides the fastest time to market, lowest total cost, and lowest risk
system design and production solution to meet your business needs.

The HardCopy IV device family contains two variants optimized to meet different
application needs:

■ HardCopy IV GX transceiver ASICs—up to 11.5 M usable ASIC equivalent gates,

20,736 Kbits dedicated RAM, 1,288 18 × 18-bit multipliers, and 36 full-duplex clock
data recovery (CDR)-based transceivers at up to 6.5 Gbps

■ HardCopy IV E ASICs—up to 14.6 M usable ASIC equivalent gates, 18,792 Kbits

dedicated RAM, and 1,288 18 × 18 bit multipliers

© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or li ab ility aris ing out of the app lic atio n or us e of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.

HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration
January 2011

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1–2 Chapter 1: HardCopy IV Device Family Overview

Features

Features

HardCopy IV devices offer the following features:

■ General

■ Fine-grained HCell architecture resulting in a low-cost, high-performance,

low-power ASIC

■ Fully tested production-quality samples typically available 14 weeks from the

date of your design submission

■ Design functionality the same as the Stratix IV FPGA prototype

■ System performance and power

■ Core logic performance up to 50% faster than the Stratix IV FPGA prototype

■ Power consumption reduction of typically 50% from the Stratix IV FPGA

prototype

■ Robust on-chip hot socketing and power sequencing support

■ Support for instant-on or instant-on-after-50 ms power-up modes

■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for

robust signal integrity

1 The actual performance and power consumption improvements described

in this data sheet are design-dependent.

■ Transceivers (HardCopy IV GX family)

■ Up to 36 full-duplex CDR-based transceivers in HardCopy IV GX devices

supporting data rates up to 6.5 Gbps

■ Dedicated circuitry to support physical layer functionality for popular serial

protocols, such as PCI Express (PIPE) Gen1 and Gen2, Gigabit Ethernet, Serial
RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre
Channel, SFI-5, and Interlaken

■ Complete PCI Express (PIPE) protocol solution with embedded PCI Express

hard IP blocks that implement PHY-MAC layer, Data Link layer, and
Transaction layer functionality

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to

compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at

3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ Logic and Digital Signal Processing (DSP)

■ 3.8 to 15 million usable gates for both logic and DSP functions (as shown in

Table 1–1)

■ High-speed DSP functions supporting 9 × 9, 12 × 12, 18 × 18, and 36 × 36

multipliers, multiple accumulate functions, and finite impulse response (FIR)
filters

HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation

Chapter 1: HardCopy IV Device Family Overview 1–3

Features

■ Internal memory

■ TriMatrix memory, consisting of three RAM block sizes to implement true

dual-port memory and first-in first-out (FIFO) buffers

■ Up to 20, 736 Kbits RAM in embedded RAM blocks (including parity bits)

■ Memory logic array blocks (MLAB) implemented in HCell logic fabric

■ Clock resources PLLs

■ Up to 16 global clocks, 88 regional clocks, and 88 peripheral clocks per device

■ Clock control block supporting dynamic clock network enable/disable and

dynamic global clock network source selection

■ Up to 12 PLLs per device supporting PLL reconfiguration, clock switchover,

programmable bandwidth, clock synthesis, and dynamic phase shifting

■ I/O standards, external memory interface, and intellectual property (IP)

■ Support for numerous single-ended and differential I/O standards, such as

LVTTL, LVCMOS, PCI, PCI-X, SSTL, HSTL, and LVDS

■ High-speed differential I/O support with serializer/deserializer (SERDES) and

dynamic phase alignment (DPA) circuitry for 1.25 Gbps performance

■ Support for high-speed networking and communications bus standards,

including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSLI,
Rapid I/O, and NPSI

■ Memory interface support with dedicated DQS logic on all I/O banks

■ Dynamic On-Chip Termination (OCT) with auto-calibration support on all I/O

banks

■ Support for high-speed external memory interfaces, including DDR, DDR2,

DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 20 modular
I/O banks

■ Support for multiple intellectual property megafunctions from Altera

MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)

■ Nios

■ JTAG—IEEE 1149.1 boundary scan testing (BST) support

■ Packaging

■ Pin-compatible with Stratix IV FPGA prototypes

■ Up to 880 user I/O pins available

■ Flip chip, space-saving FineLine BGA packages available (Table 1–5)

®

II embedded processor support

January 2011 Altera Corporation HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration

1–4 Chapter 1: HardCopy IV Device Family Overview

Features

Table 1–1 and Table 1–2 list the HardCopy IV ASIC devices and available features.

Table 1–1. HardCopy IV GX ASIC Features

Tot al

Hard Copy IV G X

ASIC

Stratix IV GX

FPGA

Prototy pe

ASIC

Equivalent

Gates (1)

Transceivers

6.5 Gbps (2)

M9K

Blocks

M144K
Blocks

Dedicated

RAM Bits

(not including

18 × 18-Bit
Multi pliers
(FIR Mode)

PLLs

MLABs) (3)

EP4SGX70 2.8 M 8, 0 462 16 6,462 Kb 384 3

EP4SGX110 3.8 M 8, 0 660 16 8,244 Kb 512 3

EP4SGX180 6.7 M 8, 0 660 20 8,820 Kb 920 3

HC4GX15

EP4SGX230 9.2 M 8, 0 660 22 9,108 Kb 1,288 3

EP4SGX290 7.7 M 8, 0 660 24 9,396 Kb 832 2

EP4SGX360 9.4 M 8, 0 660 24 9,396 Kb 1,040 2

EP4SGX110 3.8 M 16, 0 660 16 8,244 Kb 512 4

EP4SGX180 6.7 M 16, 8 (6) 936 20 11,304 Kb 920 6

EP4SGX230 9.2 M 16, 8 (6) 936 22 11,592 Kb 1,288 6

HC4GX25

EP4SGX290 7.7 M 16, 8 (6) 936 36 13,608 Kb 832 6 (4)

EP4SGX360 9.4 M 16, 8 (6) 936 36 13,608 Kb 1,040 6 (4)

EP4SGX530 11.5 M 16, 8 (6) 936 36 13,608 Kb 1,024 6

EP4SGX180 6.7 M 24, 12 (7) 950 20 11,430 Kb 920 8

EP4SGX230 9.2 M 24, 12 (7) 1,235 22 14,283 Kb 1,288 8 (5)

EP4SGX290 7.7 M 24, 12 (7) 936 36 13,608 Kb 832 8

HC4GX35

EP4SGX360 9.4 M 24, 12 (7) 1,248 48 18,144 Kb 1,040 8 (5)

EP4SGX530 11.5 M 24, 12 (7) 1,280 64 20,736 Kb 1,024 8 (5)

Notes to Tab le 1– 1:

(1) This is the number of ASIC- equivalent gates ava ilable in the HardCopy IV base array, shared between both adaptive logic module (ALM) logic and

DSP functions from a Stratix IV FPGA prototype. The number of usable ASIC-equivalent gates is bounded by the number of ALMs in the
companion Stratix IV FPGA device.

(2) The first number indicates the number of transceivers with PMA and PCS; the second number indicates the number of CMU (PMA Only)

transceivers.
(3) MLAB RAMs are implemented with HCells in the HardCopy IV ASICs.
(4) This device has six PLLs in the F1152 package and four PLLs in the F780 package.
(5) This device has eight PLLs in the F1517 package and six PLLs in the F1152 package.
(6) Devices in the cost-optimized LF780 and LF1152 packages have 16 transceivers and no CMU transceiver. Devices in the performance-optimized

FF1152 package have 16 transceivers and eight CMU transceivers.
(7) Devices in the F1152 package have 16 transceivers a nd eight CMU t ransceivers. Devices in the performance-optimized F F1517 package have 24

transceivers and 12 CMU transceivers.

Table 1–2. HardCopy IV E ASIC Features (Part 1 of 2)

HardCopy IV E

ASIC

HC4E25

Stratix IV E

Prot otype

Device

EP4SE230 9.2 M 864 22 10,944 Kb 1,288 4

EP4SE360 9.4 M 864 32 12,384 Kb 1,040 4

ASIC

Equivalent

Gates (1)

M9K

Blocks

M144K
Blocks

Total Dedicated

RAM Bits (excluding

MLABs) (2)

18 × 18-Bit
Multipliers
(FIR Mode)

PLLs

HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation

Chapter 1: HardCopy IV Device Family Overview 1–5

January 2011 Altera Corporation HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration

Table 1–2. HardCopy IV E ASIC Features (Part 2 of 2)

Features

HardCopy IV E

ASIC

HC4E35

Notes to Ta bl e 1– 2:

(1) This is the number of ASIC-equivalent gates available in the HardCopy IV E base array, shared between both adaptive logic module (ALM) logic and DSP functions

from a Stratix IV E FPGA prototype. The number of usable ASIC-equivalent gates is bounded by the number of ALMs in the companion Stratix IV E FPGA device.
(2) MLAB RAMs are implemented with HCells in the HardCopy IV ASICs.
(3) This device has 12 PLLs in the F1517 package and eight PLLs in the F1152 package.

Stratix IV E

Prototype

Device

EP4SE360 9.4 M 1,248 48 18,144 Kb 1,040 8

EP4SE530 11.5 M 1,280 48 18,432 Kb 1,024 12 (3)

EP4SE820 14.6 M 1,320 48 18,792 Kb 960 12 (3)

ASIC

Equivalent

Gates (1)

M9K

Blocks

M144K
Blocks

Total Dedicated

RAM Bits (excludin g

MLABs) (2)

18 × 18-Bit
Multipliers
(FIR Mode)

PLLs

HardCopy IV ASIC and Stratix IV FPGA Mapping Paths

HardCopy IV devices offer pin-to-pin compatibility with the Stratix IV prototype, making them drop-in replacements for the
FPGAs. Therefore, the same system board and software developed for prototyping and field trials can be retained, enabling the
lowest risk and fastest time-to-market for high-volume production.

HardCopy IV devices also offer non-socket replacement mapping paths to smaller standard or customized packages. For
example, you can map the EP4SE230 device in the 780-pin FBGA package to the HC4E25 device in the 484-pin FBGA standard
package, or to the 400-pin FBGA customized package. Because the pin-out for the two packages are not the same, you need a
separate board design for the Stratix IV device and the HardCopy IV device.

The non-socket replacement offerings extend cost reduction further and allow for a smaller foot print occupied by the
HardCopy IV device. The non-socket replacement to a standard package is supported in the Quartus II software. The
customized package option is not visible in the Quartus II software. For more information, refer to “HardCopy IV Package

Pro” on page 1–9.

For the non-socket replacement to a standard package, select I/Os in the Stratix IV device that can be mapped to the
HardCopy IV device. Not all I/Os in the Stratix IV device are available in the HardCopy IV non-socket replacement device.
Check the pin-out information for both the Stratix IV device and HardCopy IV device to ensure that the I/Os can be mapped,
and select the companion device in the Quartus II project setting during design development. By selecting the companion
device, the Quartus II software ensures that common resources and compatible I/Os are used during the mapping from the
Stratix FPGA to the HardCopy ASIC.

There are a number of FPGA prototype choices for each HardCopy IV device, as listed in Table 1–3 and Table 1–4. To obtain the
best value and the lowest system cost, architect your system to maximize silicon resource utilization.

HardCopy IV Device Handbook Volume 1: Device Interfaces and Integration January 2011 Altera Corporation

1–6 Chapter 1: HardCopy IV Device Family Overview

Table 1–3. Stratix IV GX FPGA Prototy pe-to-HardCopy IV GX ASIC Mapping Paths

HardCopy IV GX ASIC

Device Package

HC4GX15

780-pin

FineLine BGA

780-pin

HC4GX25

FineLine BGA

1152-pin

FineLine BGA

1152-pin

HC4GX35

FineLine BGA

1517-pin

FineLine BGA

Note to Tab le 1 –3 :

(1) The Hybrid FBGA package for Stratix IV GX FPGAs requires additional unused board space along the edges beyond the footprint, but its foot print is compatible with the regular FBGA package. HardCopy IV GX

ASICs are in the regular FBGA packages.

EP4SGX70 EP4SGX110 EP4SGX180 EP4SGX230 EP4SGX290 EP4SGX360 EP4SGX530

F780 F780 F1152 F780 F1152 F1517 F780 F1152 F1517 H780 F1152 F1517 H780 F1152 F1517 H1152 H1517

vv — v — — v ——

— ————————

—— v — v —— v —— v ——v —

— ——————v —————

— ————v ——v ——v —

Stratix IV GX FPGA Prototype and Package

v

(1)

v

(1)

——

——

v

(1)

v

(1)

——— —

——— —

v

—

—

v

v

(1)

v

(1)

—

—

—

v

Table 1– 4. Stratix IV E FPGA Prototy pe-to-HardCopy IV E ASIC Mapping Paths

HardCopy IV E ASIC

EP4SE230 EP4SE360 EP4SE530 EP4SE820

Stratix IV E FPGA Prototype and Package

Device Package

HC4E25

HC4E35

Notes to Table 1 –4:

(1) This mapping is a non-socket replacement path that requires a different board design for the Stratix IV E device and the HardCopy IV E device.
(2) The Hybrid FBGA package for the Stratix IV E FPGAs requires additional unused board space along the edges beyond the footprint, but its footprint is c ompatible with the regular FBGA

package. The HardCopy IV E ASICs are in the regular FBGA packages.

484-pin FineLine BGA v (1) — — ————

780-pin FineLine BGA vv (2) —————
1152-pin FineLine BGA — — vv (2) — v (2) —
1517-pin FineLine BGA — — — — v (2) — v

F780 H780 F1152 H1152 H1517 H1152 H1517

Features