Altera DisplayPort MegaCore Function User Manual

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DisplayPort IP Core User Guide

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TOC-2

DisplayPort IP Core Quick Reference................................................................ 1-1

About This IP Core..............................................................................................2-1

Getting Started.................................................................................................... 3-1

Device Family Support................................................................................................................................2-2

IP Core Verification.....................................................................................................................................2-2

Performance and Resource Utilization.....................................................................................................2-2

Installing and Licensing IP Cores..............................................................................................................3-1

OpenCore Plus IP Evaluation........................................................................................................ 3-1

Specifying IP Core Parameters and Options............................................................................................3-2

Simulating the Design................................................................................................................................. 3-2

Simulating with the ModelSim Simulator....................................................................................3-3

Compiling the Full Design and Programming the FPGA......................................................................3-3

DisplayPort Source..............................................................................................4-1

Source Overview...........................................................................................................................................4-1

Source Functional Description.................................................................................................................. 4-2

Main Data Path.................................................................................................................................4-3

Embedded DisplayPort (eDP) Support.........................................................................................4-5

Source Parameters........................................................................................................................................4-5

Source Interfaces..........................................................................................................................................4-7

Controller Interface.......................................................................................................................4-11

AUX Interface.................................................................................................................................4-12

Video Interface...............................................................................................................................4-12

TX Transceiver Interface.............................................................................................................. 4-13

Transceiver Reconfiguration Interface....................................................................................... 4-14

Transceiver Analog Reconfiguration Interface..........................................................................4-14

Secondary Stream Interface..........................................................................................................4-14

Audio Interface...............................................................................................................................4-16

MSA Interface.................................................................................................................................4-18

Source Clock Tree......................................................................................................................................4-19

DisplayPort Sink..................................................................................................5-1

Sink Overview...............................................................................................................................................5-1

Sink Functional Description.......................................................................................................................5-1

Embedded DisplayPort (eDP) Support.........................................................................................5-4

Sink Parameters ...........................................................................................................................................5-4

Sink Interfaces.............................................................................................................................................. 5-6

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Controller Interface.......................................................................................................................5-13

AUX Interface.................................................................................................................................5-13

Debugging Interface...................................................................................................................... 5-14

Video Interface...............................................................................................................................5-16

RX Transceiver Interface.............................................................................................................. 5-19

Transceiver Reconfiguration Interface....................................................................................... 5-19

Secondary Stream Interface..........................................................................................................5-19

Audio Interface...............................................................................................................................5-21

MSA Interface.................................................................................................................................5-22

Sink Clock Tree..........................................................................................................................................5-24

DisplayPort IP Core Hardware Demonstration.................................................6-1

Clock Recovery Core...................................................................................................................................6-4

Clock Recovery Core Parameters.................................................................................................. 6-5

Clock Recovery Interface................................................................................................................ 6-6

Transceiver and Clocking.........................................................................................................................6-11

Required Hardware................................................................................................................................... 6-14

Design Walkthrough.................................................................................................................................6-22

Set Up the Hardware..................................................................................................................... 6-23

Copy the Design Files to Your Working Directory.................................................................. 6-23

Build the FPGA Design.................................................................................................................6-25

Load, and Run the Software......................................................................................................... 6-25

View the Results.............................................................................................................................6-26

DisplayPort IP Core Simulation Example..........................................................7-1

Design Walkthrough................................................................................................................................... 7-3

Copy the Simulation Files to Your Working Directory..............................................................7-3

Generate the IP Simulation Files and Scripts, and Compile and Simulate..............................7-6

View the Results...............................................................................................................................7-8

DisplayPort API Reference................................................................................. 8-1

Using the Library......................................................................................................................................... 8-1

btc_dprx_syslib API Reference..................................................................................................................8-3

btc_dprx_aux_get_request......................................................................................................................... 8-3

btc_dprx_aux_handler................................................................................................................................8-4

btc_dprx_aux_post_reply...........................................................................................................................8-5

btc_dprx_baseaddr...................................................................................................................................... 8-6

btc_dprx_dpcd_gpu_access........................................................................................................................8-6

btc_dprx_edid_set........................................................................................................................................8-7

btc_dprx_hpd_get........................................................................................................................................8-8

btc_dprx_hpd_pulse....................................................................................................................................8-8

btc_dprx_hpd_set........................................................................................................................................ 8-9

btc_dprx_syslib_add_rx..............................................................................................................................8-9

btc_dprx_syslib_info.................................................................................................................................8-10

btc_dprx_syslib_init..................................................................................................................................8-11

btc_dprx_syslib_monitor..........................................................................................................................8-11

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TOC-4

btc_dptx_syslib API Reference................................................................................................................ 8-12

btc_dptx_aux_i2c_read.............................................................................................................................8-12

btc_dptx_aux_i2c_write............................................................................................................................8-13

btc_dptx_aux_read....................................................................................................................................8-13

btc_dptx_aux_write...................................................................................................................................8-14

btc_dptx_baseaddr.....................................................................................................................................8-15

btc_dptx_edid_block_read.......................................................................................................................8-15

btc_dptx_edid_read...................................................................................................................................8-16

btc_dptx_fast_link_training.....................................................................................................................8-16

btc_dptx_link_training............................................................................................................................. 8-17

btc_dptx_set_color_space.........................................................................................................................8-18

btc_dptx_syslib_init.................................................................................................................................. 8-18

btc_dptx_syslib_monitor..........................................................................................................................8-19

btc_dptx_test_autom.................................................................................................................................8-19

btc_dptx_video_enable.............................................................................................................................8-20

btc_dpxx_syslib Additional Types.......................................................................................................... 8-20

btc_dprx_syslib Supported DPCD Locations........................................................................................8-20

DisplayPort Source Register Map and DPCD Locations................................... 9-1

Source General Registers.............................................................................................................................9-1

DPTX_TX_CONTROL...................................................................................................................9-1

DPTX_TX_STATUS....................................................................................................................... 9-3

Source MSA Registers..................................................................................................................................9-4

DPTX0_MSA_MVID......................................................................................................................9-4

DPTX0_MSA_NVID.......................................................................................................................9-4

DPTX0_MSA_HTOTAL................................................................................................................9-4

DPTX0_MSA_VTOTAL................................................................................................................ 9-5

DPTX0_MSA_HSP..........................................................................................................................9-5

DPTX0_MSA_HSW........................................................................................................................9-5

DPTX0_MSA_HSTART.................................................................................................................9-6

DPTX0_MSA_VSTART................................................................................................................. 9-6

DPTX0_MSA_VSP..........................................................................................................................9-6

DPTX0_MSA_VSW........................................................................................................................9-7

DPTX0_MSA_HWIDTH...............................................................................................................9-7

DPTX0_MSA_VHEIGHT..............................................................................................................9-7

DPTX0_MSA_MISC0.....................................................................................................................9-8

DPTX0_MSA_MISC1.....................................................................................................................9-8

DPTX0_MSA_COLOUR................................................................................................................9-8

Source Link Voltage and Pre-Emphasis Controls...................................................................................9-9

DPTX_PRE_VOLT0........................................................................................................................9-9

DPTX_PRE_VOLT1..................................................................................................................... 9-10

DPTX_PRE_VOLT2..................................................................................................................... 9-10

DPTX_PRE_VOLT3..................................................................................................................... 9-10

DPTX_RECONFIG.......................................................................................................................9-11

Source Timestamp.....................................................................................................................................9-11

Source Audio Registers............................................................................................................................. 9-12

Source CRC Registers................................................................................................................................9-13

Source MST Registers................................................................................................................................9-14

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DPTX_MST_VCPTAB0...............................................................................................................9-15

DPTX_MST_VCPTAB1...............................................................................................................9-15

DPTX_MST_VCPTAB2...............................................................................................................9-16

DPTX_MST_VCPTAB3...............................................................................................................9-17

DPTX_MST_VCPTAB4...............................................................................................................9-17

DPTX_MST_VCPTAB5...............................................................................................................9-18

DPTX_MST_VCPTAB6...............................................................................................................9-18

DPTX_MST_VCPTAB7...............................................................................................................9-19

DPTX_MST_TAVG_TS...............................................................................................................9-20

Source AUX Controller Interface............................................................................................................9-20

DPTX_AUX_CONTROL.............................................................................................................9-20

DPTX_AUX_CMD....................................................................................................................... 9-21

DPTX_AUX_BYTE0.....................................................................................................................9-22

DPTX_AUX_BYTE1.....................................................................................................................9-22

DPTX_AUX_BYTE2.....................................................................................................................9-22

DPTX_AUX_BYTE3.....................................................................................................................9-23

DPTX_AUX_BYTE4.....................................................................................................................9-23

DPTX_AUX_BYTE5.....................................................................................................................9-23

DPTX_AUX_BYTE6.....................................................................................................................9-24

DPTX_AUX_BYTE7.....................................................................................................................9-24

DPTX_AUX_BYTE8.....................................................................................................................9-24

DPTX_AUX_BYTE9.....................................................................................................................9-25

DPTX_AUX_BYTE10...................................................................................................................9-25

DPTX_AUX_BYTE11...................................................................................................................9-25

DPTX_AUX_BYTE12...................................................................................................................9-26

DPTX_AUX_BYTE13...................................................................................................................9-26

DPTX_AUX_BYTE14...................................................................................................................9-27

DPTX_AUX_BYTE15...................................................................................................................9-27

DPTX_AUX_BYTE16...................................................................................................................9-27

DPTX_AUX_BYTE17...................................................................................................................9-28

DPTX_AUX_BYTE18...................................................................................................................9-28

DPTX_AUX_RESET.....................................................................................................................9-28

Source-Supported DPCD Locations....................................................................................................... 9-29

DisplayPort Sink Register Map and DPCD Locations.....................................10-1

Sink General Registers...............................................................................................................................10-1

DPRX_RX_CONTROL.................................................................................................................10-1

DPRX_RX_STATUS.....................................................................................................................10-3

DPRX_BER_CONTROL.............................................................................................................. 10-5

DPRX_BER_CNT0........................................................................................................................10-7

DPRX_BER_CNT1........................................................................................................................10-7

Sink Timestamp......................................................................................................................................... 10-7

Sink Bit-Error Counters............................................................................................................................10-7

DPRX_BER_CNTI0...................................................................................................................... 10-7

DPRX_BER_CNTI1...................................................................................................................... 10-8

Sink MSA Registers....................................................................................................................................10-8

DPRX0_MSA_MVID....................................................................................................................10-9

DPRX0_MSA_NVID.................................................................................................................... 10-9

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DPRX0_MSA_HTOTAL..............................................................................................................10-9

DPRX0_MSA_VTOTAL.............................................................................................................. 10-9

DPRX0_MSA_HSP..................................................................................................................... 10-10

DPRX0_MSA_HSW....................................................................................................................10-10

DPRX0_MSA_HSTART.............................................................................................................10-10

DPRX0_MSA_VSTART.............................................................................................................10-11

DPRX0_MSA_VSP......................................................................................................................10-11

DPRX0_MSA_VSW....................................................................................................................10-11

DPRX0_MSA_HWIDTH...........................................................................................................10-12

DPRX0_MSA_VHEIGHT..........................................................................................................10-12

DPRX0_MSA_MISC0.................................................................................................................10-12

DPRX0_MSA_MISC1.................................................................................................................10-13

DPRX0_VBID.............................................................................................................................. 10-13

Sink Audio Registers............................................................................................................................... 10-14

DPRX0_AUD_MAUD................................................................................................................10-14

DPRX0_AUD_NAUD................................................................................................................10-14

DPRX0_AUD_AIF0....................................................................................................................10-14

DPRX0_AUD_AIF1....................................................................................................................10-15

DPRX0_AUD_AIF2....................................................................................................................10-15

DPRX0_AUD_AIF3....................................................................................................................10-15

DPRX0_AUD_AIF4....................................................................................................................10-16

Sink MST Registers..................................................................................................................................10-16

DPRX_MST_VCPTAB0.............................................................................................................10-17

DPRX_MST_VCPTAB1.............................................................................................................10-18

DPRX_MST_VCPTAB2.............................................................................................................10-19

DPRX_MST_VCPTAB3.............................................................................................................10-19

DPRX_MST_VCPTAB4.............................................................................................................10-20

DPRX_MST_VCPTAB5.............................................................................................................10-20

DPRX_MST_VCPTAB6.............................................................................................................10-21

DPRX_MST_VCPTAB7.............................................................................................................10-22

Sink AUX Controller Interface..............................................................................................................10-22

DPRX_AUX_CONTROL...........................................................................................................10-22

DPRX_AUX_STATUS................................................................................................................10-23

DPRX_AUX_COMMAND........................................................................................................10-24

DPRX_AUX_BYTE0...................................................................................................................10-24

DPRX_AUX_BYTE1...................................................................................................................10-25

DPRX_AUX_BYTE2...................................................................................................................10-25

DPRX_AUX_BYTE3...................................................................................................................10-25

DPRX_AUX_BYTE4...................................................................................................................10-26

DPRX_AUX_BYTE5...................................................................................................................10-26

DPRX_AUX_BYTE6...................................................................................................................10-26

DPRX_AUX_BYTE7...................................................................................................................10-27

DPRX_AUX_BYTE8...................................................................................................................10-27

DPRX_AUX_BYTE9...................................................................................................................10-27

DPRX_AUX_BYTE10.................................................................................................................10-28

DPRX_AUX_BYTE11.................................................................................................................10-28

DPRX_AUX_BYTE12.................................................................................................................10-29

DPRX_AUX_BYTE13.................................................................................................................10-29

DPRX_AUX_BYTE14.................................................................................................................10-29

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TOC-7

DPRX_AUX_BYTE15.................................................................................................................10-30

DPRX_AUX_BYTE16.................................................................................................................10-30

DPRX_AUX_BYTE17.................................................................................................................10-30

DPRX_AUX_BYTE18.................................................................................................................10-31

DPRX_AUX_I2C0.......................................................................................................................10-31

DPRX_AUX_I2C1.......................................................................................................................10-31

DPRX_AUX_RESET...................................................................................................................10-32

DPRX_AUX_HPD...................................................................................................................... 10-32

Sink-Supported DPCD Locations......................................................................................................... 10-33

Additional Information......................................................................................A-1

Document Revision History......................................................................................................................A-1

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DisplayPort IP Core Quick Reference

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This document describes the Altera® DisplayPort MegaCore®function, which provides support for nextgeneration video display interface technology.

The DisplayPort IP core is part of the MegaCore IP Library, which is distributed with the Quartus® II software and is downloadable from the Altera website at www.altera.com.

Note:

For system requirements and installation instructions, refer to the Altera Software Installation and Licensing Manual.

Item Description

Version 15.0

Release Date May 2015

Release Information

Ordering Code IP-DP

Product ID 0109

Vendor ID 6AF7

2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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DisplayPort IP Core Quick Reference

Item Description

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IP Core Information

Core Features

• Conforms to the Video Electronics Standards Association (VESA) specifica‐ tion version 1.2a

• Scalable main data link

• 1, 2, or 4 lane operation

• 1.62, 2.7, and 5.4 gigabits per second

(Gbps) per lane with an embedded clock

• Color support

• RGB 18, 24, 30, 36, or 48 bits per pixel

(bpp) color depths

• YCbCr 4:4:4 24, 30, 36, or 48 bpp color

depths

• YCbCr 4:2:2 16, 20, 24, or 32 bpp color

depths

• 40-bit (quad symbol) and 20-bit (dual symbol) transceiver data interface

• Support for 1, 2, or 4 parallel pixels per clock

• Multi-stream support (MST)

• 4Kp60 resolution support

• Source

• Embedded controller AUX channel

operation

• Accepts standard H-sync/V-sync/data

enable RGB and YCbCr input video formats

• Supports audio and video streams

• Sink

• Finite state machine (FSM) or

embedded controller AUX channel operation

• Produces a proprietary video output

• Auxiliary channel for 2-way communica‐ tion (link and device management)

• Hot plug detect (HPD)

• Sink announces its presence

• Sink requests the source’s attention

• AC coupling and low EMI

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DisplayPort IP Core Quick Reference

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DisplayPort IP Core Quick Reference

Item Description

Typical Application • Interfaces within a PC or monitor

• External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display

Device Family Support Arria® 10 (preliminary), Arria V GX, Arria V

GZ, Cyclone® V, and Stratix® V FPGA devices.

Refer to the What’s New in Altera IP page of the Altera website for detailed information.

Design Tools • IP Catalog in the Quartus II software for

IP design instantiation and compilation

• TimeQuest timing analyzer in the Quartus II software for timing analysis

• ModelSim-Altera software for design simulation

1-3

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What’s New in Altera IP

DisplayPort IP Core Quick Reference

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Source

Lane 0 Data (1.62, 2.7, or 5.4 Gbps) Lane 1 Data (1.62, 2.7, or 5.4 Gbps) Lane 2 Data (1.62, 2.7, or 5.4 Gbps) Lane 3 Data (1.62, 2.7, or 5.4 Gbps) AUX Channel (1 Mbps) Hot Plug Detect

Sink

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About This IP Core

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This document describes the Altera® DisplayPort MegaCore® function, which provides support for nextgeneration video display interface technology. The Video Electronics Standards Association (VESA) defines the DisplayPort standard as an open digital communications interface for use in internal connections such as:

• Interfaces within a PC or monitor

• External display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display

The Altera DisplayPort source has a scalable main link with 1, 2, or 4 lanes for a total up to 21.6 Gbps bandwidth. A bidirectional AUX channel with 1 Mbps Manchester encoding provides side-band communication. The sink uses a hot plug detect (HPD) signal to announce its presence, and the source uses the same signal to initiate link configuration.

Figure 2-1: DisplayPort Source and Sink Communication

The main link has three selectable data rates: 1.62, 2.7, and 5.4 Gbps.

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Device Family Support

The following table lists the link rate support offered by the DisplayPort IP core for each Altera device family.

Table 2-1: Link Rate Support by Device Family

RBR = Reduced Bit Rate, HBR = High Bit Rate

Device Family 20-bit mode 40-bit mode

Arria 10 RBR, HBR, HBR2 RBR, HBR, HBR2 Arria V GX RBR, HBR RBR, HBR, HBR2 Arria V GZ RBR, HBR, HBR2 RBR, HBR, HBR2 Cyclone V RBR, HBR RBR, HBR Stratix V RBR, HBR, HBR2 RBR, HBR, HBR2

IP Core Verification

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Before releasing a publicly available version of the DisplayPort IP core, Altera runs a comprehensive verification suite in the current version of the Quartus® II software. These tests use standalone methods and the Qsys system integration tool to create the instance files. These files are tested in simulation and hardware to confirm functionality. Altera tests and verifies the DisplayPort IP core in hardware for different platforms and environments.

The DisplayPort IP core has been tested at VESA Plugtest events and passes the Unigraf DisplayPort Link Layer CTS tests.

Performance and Resource Utilization

This section contains tables showing IP core variation size and performance examples. The following table lists the resources and expected performance for selected variations. The results were

obtained using the Quartus II software v15.0 for the following devices:

• Arria V (5AGXFB3H4F40C5)

• Cyclone V (5CGTFD9E5F35C7)

• Stratix V (5SGXEA7K2F40C2)

• Arria 10 (10AX115S2F45I2SGES)

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Performance and Resource Utilization

Table 2-2: DisplayPort IP Core FPGA Resource Utilization

The table below shows the resource information for Arria V and Cyclone V devices using M10K; Arria 10 and Stratix V devices using M20K. The resources were obtained using the following parameter settings:

• Mode = duplex

• Maximum lane count = 4 lanes

• Maximum video input color depth = 24 bits per pixel (bpp)

• Pixel input mode = 1 pixel per clock

2-3

Device Streams Direction

Arria 10

Single stream (SST)

SST

TX Arria V GX

MST

(2 streams)

RX Cyclone V GX

SST

Symbol per

Clock

ALMs

Logic Registers Memory

Primary Secondary Bits M10K or

Dual 7,087 9,580 1,001 16,576 30

Quad 9,957 11,121 1,153 31,424 30

Dual 16,075 10,205 465 27,424 27

Quad 29,075 13,605 646 39,776 40

Dual 7,176 9,432 1,015 16,576 30

Quad 9,881 10,793 1,221 31,424 30

Dual 16,340 10,213 499 27,424 27

Quad 29,258 13,568 715 39,776 40

Dual 13,337 15,901 1,650 30,336 52

Quad 20,913 19,551 1,952 57,472 52

Dual 31,790 20,095 879 47,680 54

Quad 58,333 27,433 1,357 65,472 80

Dual 7,137 9,446 1,035 16,576 30

Quad 9,817 10,886 1,229 31,424 30

Dual 16,343 10,157 604 27,424 27

Quad 29,326 13,537 825 39,776 40

M20K

Stratix V GX

Related Information

Fitter Resources Reports

More information about Quartus II resource utilization reporting.

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Dual 7,006 9,569 966 15,552 28

Quad 9,967 11,087 1,065 30,400 28

SST

Dual 16,340 10,213 499 27,424 27

Quad 29,258 13,568 715 39,776 40

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acds

quartus - Contains the Quartus II software ip - Contains the Altera IP Library and third-party IP cores

altera - Contains the Altera IP Library source code

<IP core name> - Contains the IP core source files

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Getting Started

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This chapter provides a general overview of the Altera IP core design flow to help you quickly get started with the DisplayPort IP core. The IP core is installed as part of the Quartus II installation process. You can select and parameterize any Altera IP core from the library. Altera provides an integrated parameter editor that allows you to customize the DisplayPort IP core to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports.

Installing and Licensing IP Cores

The Altera IP Library provides many useful IP core functions for your production use without purchasing an additional license. Some Altera MegaCore IP functions require that you purchase a separate license for production use. However, the OpenCore® feature allows evaluation of any Altera IP core in simulation and compilation in the Quartus II software. After you are satisfied with functionality and perfformance, visit the Self Service Licensing Center to obtain a license number for any Altera product.

Figure 3-1: IP Core Installation Path

Note:

The default IP installation directory on Windows is <drive>:\altera\<version number>; on Linux it is <home directory>/altera/ <version number>.

Related Information

• Altera Licensing Site

• Altera Software Installation and Licensing Manual

OpenCore Plus IP Evaluation

Altera's free OpenCore Plus feature allows you to evaluate licensed MegaCore IP cores in simulation and hardware before purchase. You need only purchase a license for MegaCore IP cores if you decide to take your design to production. OpenCore Plus supports the following evaluations:

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Specifying IP Core Parameters and Options

• Simulate the behavior of a licensed IP core in your system.

• Verify the functionality, size, and speed of the IP core quickly and easily.

• Generate time-limited device programming files for designs that include IP cores.

• Program a device with your IP core and verify your design in hardware. OpenCore Plus evaluation supports the following two operation modes:

• Untethered—run the design containing the licensed IP for a limited time.

• Tethered—run the design containing the licensed IP for a longer time or indefinitely. This requires a connection between your board and the host computer.

Note: All IP cores that use OpenCore Plus time out simultaneously when any IP core in the design times

out.

Specifying IP Core Parameters and Options

Follow these steps to specify the DisplayPort IP core parameters and options.

1. Create a Quartus II project using the New Project Wizard available from the File menu.

2. On the Tools menu, click IP Catalog.

3. Under Installed IP, double-click Library > Interface > Protocols > Audio&Video > DisplayPort.

The parameter editor appears.

4. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the targeted Altera device family and output file HDL preference. Click OK.

5. Specify parameters and options in the DisplayPort parameter editor:

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• Optionally select preset parameter values. Presets specify all initial parameter values for specific

applications (where provided).

• Specify parameters defining the IP core functionality, port configurations, and device-specific

features.

• Specify options for generation of a timing netlist, simulation model, testbench, or example design

(where applicable).

• Specify options for processing the IP core files in other EDA tools.

6. Click Generate to generate the IP core and supporting files, including simulation models.

7. Click Close when file generation completes.

8. Click Finish.

9. If you generate the DisplayPort IP core instance in a Quartus II project, you are prompted to add

Quartus II IP File (.qip) and Quartus II Simulation IP File (.sip) to the current Quartus II project.

Simulating the Design

You can simulate your DisplayPort IP core variation using the simulation model that the Quartus II software generates. The simulation model files are generated in vendor-specific subdirectories of your project directory. The DisplayPort IP core includes a simulation example.

The following sections teach you how to simulate the generated DisplayPort IP core variation with the generated simulation model.

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Related Information

DisplayPort IP Core Simulation Example on page 7-1

The Altera DisplayPort simulation example allows you to evaluate the functionality of the DisplayPort IP Core and provides a starting point for you to create your own simulation. This example targets the ModelSim SE simulator.

Simulating with the ModelSim Simulator

To simulate using the Mentor Graphics ModelSim simulator, perform the following steps:

1. Start the ModelSim simulator.

2. In ModelSim, change directory to the project simulation directory <variation>_sim/mentor.

3. Type the following commands to set up the required libraries and compile the generated simulation

model:

do msim_setup.tcl

run -all

Simulating with the ModelSim Simulator

3-3

Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Quartus II software to compile your design. After successfully compiling your design, program the targeted Altera device with the Programmer and verify the design in hardware.

Related Information

• Quartus II Incremental Compilation for Hierarchical and Team-Based Design Provides more information about compiling the design.

• Quartus II Programmer Provides more information about programming the device.

Getting Started

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Source

Lane 0 Data (1.62, 2.7, or 5.4 Gbps) Lane 1 Data (1.62, 2.7, or 5.4 Gbps) Lane 2 Data (1.62, 2.7, or 5.4 Gbps) Lane 3 Data (1.62, 2.7, or 5.4 Gbps) AUX Channel (1 Mbps) Hot Plug Detect

Sink

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101 Innovation Drive, San Jose, CA 95134

DisplayPort Source

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Source Overview

The DisplayPort source has a scalable main link with 1, 2, or 4 lanes for a total up to 21.6 Gbps bandwidth. A bidirectional AUX channel with 1 Mbps Manchester encoding provides side-band communication.

Figure 4-1: DisplayPort Source

The main link has three selectable data rates: 1.62, 2.7, and 5.4 Gbps. The source device sets the lane count and link rate combination (referred to as the policy) according to the sink’s capabilities and required video bandwidth. The IP core transmits the video and audio streams on the main link with embedded clocking.

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The IP core transmits data in a scrambled ANSI 8B/10B format. The data transmission includes redundancy for error detection. The secondary data stream, such as an audio stream, uses a ReedSolomon encoder for error correction.

The AUX channel is an AC-coupled differential pair for bidirectional communication. The signaling is a self-clocked Manchester encoding at 1 Mbps. As in the 100-T Ethernet protocol, the encoder uses a preceding synchronization pattern in each 16-byte maximum packet.

The AUX channel uses a master-slave hierarchy in which the source (master) initiates all communication.

ISO 9001:2008 Registered

DisplayPort Source

Encoder

txN_video_in

txN_vid_clk

txN_audio

txN_audio_clk

tx_aux

aux_clk

txN_ss

tx_ss_clk

txN_msa_conduit

tx_aux_debug

tx_xcvr_interface

Video Input Video Clock

Audio Input Audio Clock

AUX Interface AUX Clock

Secondary Stream (Avalon-ST Interface)

MSA Input

AUX Debug Stream

(Avalon-ST Interface

TX Transceiver Interface

Transceiver Management

tx_analog_reconfig

Controller Interface

tx_mgmt_interruptInterrupt

xcvr_mgmt_clkTransceiver Management Clock

tx_reconfigTX Reconfiguration

tx_mgmt

clk

Avalon-MM Interface Avalon-MM Interface Clock

TX Analog Reconfiguration

clk_calCalibration Clock

4-2

Source Functional Description

The DisplayPort source has a complete set of parameters for optimizing device resources. The DisplayPort source consists of a DisplayPort encoder block, a transceiver management block, and a

controller interface block with an Avalon-MM interface for connecting with an embedded controller such as a Nios II processor. You configure the ports using an RTL wrapper instantiation or by implementing the IP core as a Qsys component.

Figure 4-2: DisplayPort Source Top-Level Block Diagram

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8B/10B

Encoder

Multiplexer

Fixed MSA

(txN_msa)

Avalon-MM

(tx_mgmt)

Bidirectional AUX Data AUX Debug Stream HPD

40-Bit (Quad Symbol) or 20-Bit (Dual Symbol) Data to Transceiver

Secondary Data

(txN_ss)

Video Input

(txN_video_in)

Audio Stream

(txN_audio)

Gearbox FIFO Packetize

Throttle

Measure

Video

MSA

Generator

Blank Start

Generator

Video Data

Packet

Generator

Pixel Steer

Secondary

Stream Encoder

DCFIFO

Controller

Registers

AUX

Controller

tx_ss_clk clk txN_vid_clk aux_clk txN_audio_clk

Legend

Audio

Encoder

DCFIFO

Training

Pattern 1

Training

Pattern 2

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Figure 4-3: DisplayPort Source Functional Block Diagram

Main Data Path

4-3

DisplayPort Source

The source accepts a standard H-sync, V-sync, and data enable video stream for encoding. The IP core latches and processes the video data before processing it using the txN_video_in input. N represents the stream number: tx_video_in (Stream 0), tx1_video_in (Stream 1), tx2_video_in (Stream 2), and

tx3_video_in (Stream 3).

The video data width supports 6 to 16 bits per color (bpc) and is user selectable. If you set the Pixel input mode option to Dual or Quad, the video input can accept two or four pixels per clock, thereby extending

the pixel clock rate capability.

Main Data Path

The main data path consists of the packetizer, measurement, and blank generator paths. The IP core multiplexes data from these three paths and outputs it through an 8B/10B encoder.

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Packetizer Path

The packetizer path provides video data resampling and packetization, and consists of the following steps:

1. The pixel steer block decimates the data to the requested lane count (1, 2, or 4).

2. The DCFIFO crosses the data into the main link clock domain (tx_ss_clk, generated by the

transceiver), which can be 270, 135, 81, 67.5, or 40.5 MHz depending on the actual main link rate requested and the symbols per clock.

3. The gearbox resamples the video data according to the specified color depth. You can optimize the

gearbox by implementing fewer color depths. For example, you can reduce the resources required to implement the system by supporting only the color depths you need instead of the complete set of color depths specified in the DisplayPort specification.

4. The IP core packetizes the re-sampled data. The DisplayPort specification requires data to be sent in a

transfer unit (TU), which can be 32 to 64 link symbols long. To reduce complexity, the DisplayPort source uses a fixed 64-symbol TU. The specification also requires that the video data be evenly distrib‐ uted within the TUs composing a full active video line. A throttle function distributes the data and regulates it to ensure that the TUs leaving the IP core are evenly packed.

Note: A minimal DisplayPort system should support both 6 and 8 bpc. The VESA DisplayPort specifica‐

The packetizer punctuates the outgoing 16-bit data stream with the correct packet comma codes. Internally, the packetizer uses a symbol and a TU counter to ensure that it respects the TU boundaries.

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tion requires support for a mandatory VGA fail-safe mode (640 x 480 at 6 bpc).

Measurement Path

The measurement path determines the video geometry required for the DisplayPort main stream attributes (MSA), which are sent once every vertical blanking interval. Optionally, the IP core can import a fixed MSA data parameter from an external port, removing the measurement logic. This feature is useful for embedded systems that only use known resolutions and synchronous pixel clocks.

Blank Generator Path

The blank generator path determines when to send the blank start comma codes with their corresponding video data packets. This path can operate in enhanced or standard framing mode.

Multiplexer

The IP core multiplexes the packetized data, MSA data, and blank generator data into a single stream. The combined data goes through 8B/10B encoding and is available as a 20-bit double-rate or a 40-bit quadrate DisplayPort encoded video port. The 20- or 40-bit port connects directly to the Altera high-speed output transceiver.

During training periods, the source can send the DisplayPort clock recovery and symbol lock test patterns (training pattern 1, training pattern 2, and training pattern 3, respectively), upon receiving the request from downstream DisplayPort sink.

The source also implements an AUX channel controller, which you access using an embedded controller. The embedded controller acts as an Avalon-MM master and sends read/write commands to the Avalon-MM slave interface. The IP core clocks the AUX channel using a 16 MHz clock input (aux_clk).

Related Information

Controller Interface on page 4-11

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Embedded DisplayPort (eDP) Support

The DisplayPort IP core is compliant with eDP version 1.3. eDP is based on the VESA DisplayPort standard. It has the same electrical interface and can share the same video port on the controller. The DisplayPort IP core supports:

• Full (normal) link training—default

• Fast link training—mandatory eDP feature

Source Parameters

You set parameters for the source using the DisplayPort parameter editor.

Table 4-1: Source Parameters

Parameter Description

Device family Select the targeted device family—Arria 10, Arria V

Embedded DisplayPort (eDP) Support

GX, Arria V GZ, Cyclone V, or Stratix V—matches the project device family.

4-5

Support DisplayPort source Turn on to enable DisplayPort source.

Maximum video input color depth Select the video input interface port bits per color.

Determines top-level video input port width (for example, 6 bpc = 18 bpp, 16 bpc = 48 bpp).

TX maximum link rate Select the the maximum link rate. 5.4 Gbps, 2.7

Gbps, 1.62 Gbps. Note: Cyclone V devices do not support 5.4

Gbps.

Maximum lane count Select the maximum lanes desired (1, 2, or 4).

Symbol output mode Specify how many symbols are transferred during

each clock cycle: dual or quad symbol, or TX transceiver data width: dual (20 bits) or quad (40 bits).

Dual symbol mode saves logic resource but requires the core to run at twice the clock frequency of quad symbol mode. If timing closure is a problem in the device, you should consider using quad symbol mode.

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Source Parameters

Parameter Description

Pixel input mode Select the number of pixels per clock (single, dual, or

quad symbol).

• If you select dual pixels per clock, the pixel clock is ½ of the full rate clock and the video port becomes two times wider.

• If you select four pixels per clock, the pixel clock is ¼ of the full rate clock and the video port becomes four times wider.

Scrambler seed value Specify the initial seed for the scrambler block. Use

16’hFFFF for normal DP and 16’hFFFE for eDP.

Enable AUX debug stream Turn on to send source AUX traffic output to an

Avalon-ST port.

Import fixed MSA Turn on to enable the source to accept a fixed MSA

value from an external port.

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Support CTS test automation Turn on to support CTS test automation.

Support secondary data channel Turn on to enable secondary data.

Support audio data channel Turn on to enable audio packet encoding.

Note: To use this parameter, you must turn on

the Support secondary data channel parameter.

Number of audio data channels Specify the number of audio channels supported.

6-bpc RGB or YCbCr 4:4:4 (18 bpp) Turn on to support 18 bpp encoding.

8-bpc RGB or YCbCr 4:4:4 (24 bpp) Turn on to support 24 bpp encoding.

10-bpc RGB or YCbCr 4:4:4 (30 bpp) Turn on to support 30 bpp encoding.

12-bpc RGB or YCbCr 4:4:4 (36 bpp) Turn on to support 36 bpp encoding.

16-bpc RGB or YCbCr 4:4:4 (48 bpp) Turn on to support 48 bpp decoding.

8-bpc YCbCr 4:2:2 (16 bpp) Turn on to support 16 bpp encoding.

10-bpc YCbCr 4:2:2 (20 bpp) Turn on to support 20 bpp encoding.

12-bpc YCbCr 4:2:2 (24 bpp) Turn on to support 24 bpp encoding.

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16-bpc YCbCr 4:2:2 (32 bpp) Turn on to support 32 bpp encoding.

Support MST Turn on to enable multi-stream support.

Max stream count Select the maximum amount of streams supported

Source Interfaces

The following tables list the source’s port interfaces. Your instantiation contains only the interfaces that you have enabled.

Table 4-2: Controller Interface

Interface Port Type Clock Domain Port Direction Description

Source Interfaces

Parameter Description

(1-4).

4-7

clk Clock N/A clk

reset Reset

tx_mgmt AV-MM clk

tx_mgmt_

IRQ

clk

reset

tx_mgmt_address[8:0] Input

tx_mgmt_chipselect

tx_mgmt_read Input tx_mgmt_write Input

tx_mgmt_ writedata[31:0]

tx_mgmt_readdata[31:0] Outp

tx_mgmt_waitrequest Outp

tx_mgmt_irq

irq

Input

Clock for embedded controller

Input

Reset for embedded controller

Input

Avalon-MM interface

Input

for embedded controller

ut Output Interrupt for

embedded controller

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Source Interfaces

Table 4-3: Transceiver Management Interface

n is the number of TX lanes.

Interface Port Type Clock Domain Port Direction Description

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xcvr_

Clock N/A

mgmt_clk

clk_cal Clock N/A

tx_ analog_ reconfig

Conduit

xcvr_mgmt_ clk

xcvr_mgmt_clk Input

clk_cal Input

tx_vod[2n - 1:0] Output tx_emp[2n - 1:0] Outp

tx_analog_reconfig_req Outp

tx_analog_reconfig_ack Input

tx_analog_reconfig_ busy

Input

Transceiver management clock

A 50-MHz calibration clock input. This clock must be synchronous to the clock used for the Transceiver Reconfiguration block (xvcr_mgmt_clk), external to the Display‐ Port sink.

Transceiver analog reconfiguration handshaking

tx_link_rate[1:0] Output

tx_ reconfig

Conduit

xcvr_mgmt_ clk

tx_link_rate_ 8bits[7:0]

tx_reconfig_req Input tx_reconfig_ack Input tx_reconfig_busy Input

Outp ut

Transceiver link rate reconfiguration handshaking

Note: Value of tx_link_rate[1:0]: 0=1.62Gbps, 1=2.70Gbps, 2=5.40Gbps; value of tx_link_rate_8bits[7:0]:

0×06=1.62Gbps, 0×0a=2.70Gbps, 0×14=5.40Gbps.

Note: For devices using a 50-MHz xcvr_mgmt_clk clock, connect the same clock directly also to the

clk_cal signal. For devices using a 100-MHz xcvr_mgmt_clk clock, connect the same clock to clk_cal signal through a by-2 divider.

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Source Interfaces

Table 4-4: Video Interface

v is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad). N is the stream

number; for example, tx_vid_clk represents Stream 0, tx1_vid_clk represents Stream 1, and so on.

Interface Port Type Clock Domain Port Direction Description

4-9

txN_vid_

Clock N/A

txN_vid_clk Input

Video clock

clk

txN_vid_data[3v*p-1:0] Input

Video data and standard H/V synchro‐ nization video port input

txN_ video_in

Conduit txN_vid_clk

txN_vid_v_sync[p-1:0] Input txN_vid_h_sync[p-1:0] Input txN_vid_f[p-1:0] Input txN_vid_de[p-1:0] Input

Table 4-5: AUX Interface

Interface Port Type Clock Domain Port Direction Description

aux_clk Clock N/A

aux_reset Reset

aux_clk aux_reset Input

tx_aux Conduit aux_clk

aux_clk Input

tx_aux_in Input tx_aux_out Outp

tx_aux_oe Outp

AUX channel clock

AUX channel reset

AUX channel interface

tx_aux_ debug

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AV-ST aux_clk

tx_hpd Input

tx_aux_debug_ data[31:0]

tx_aux_debug_valid Outp

Output

tx_aux_debug_sop Outp

tx_aux_debug_eop Outp

tx_aux_debug_err Outp

tx_aux_debug_cha Outp

Avalon-ST stream of AUX data for debugging

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Source Interfaces

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Table 4-6: Secondary Interface

N is the stream number; for example, tx_msa_conduit represents Stream 0, tx1_msa_conduit represents Stream

1, and so on.

Interface Signal Type Clock Domain Port Direction Description

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tx_ss_clk Clock N/A

MSA

Conduit

(txN_ msa_ conduit)

Secondary Stream

AV-ST tx_ss_clk

(txN_ss)

Table 4-7: Audio Interface

tx_ss_clk Output

tx_ss_clk txN_msa[191:0] Input

txN_ss_data[127:0] Input txN_ss_valid Input txN_ss_ready Outp

txN_ss_sop Input txN_ss_eop Input

TX transceiver clock out and clock for secondary stream

Input port for fixed MSA parameters

Secondary stream interface

m is the number of TX audio channels. N is the stream number; for example, tx_audio represents Stream 0, tx1_audio represents Stream 1, and so on.

Interface Signal Type Clock

Domain

Port Direction Description

Clock N/A txN_audio_clk Input Audio clock

Audio (txN_audio)

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Conduit

txN_audio_ clk

txN_audio_lpcm_data [m*32-1:0]

txN_audio_valid Input txN_audio_mute Input

Input

Audio sample data interface

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Table 4-8: TX Transceiver Interface

n is the number of TX lanes, s is the number of symbols per clock.

Note: Connect the DisplayPort signals to the Native PHY signals of the same name.

Controller Interface

4-11

Interface Port Type Clock

Clock N/A tx_std_clkout[n–1:0] Input TX transceiver clock

Conduit tx_std_

clkout

Conduit N/A tx_pll_powerdown Output PLL power down for

Conduit xcvr_mgmt_

TX transceiver

clk

interface

Conduit N/A tx_analogreset[n–

Conduit N/A tx_cal_busy[n–1:0] Input Calibration in

Conduit N/A tx_pll_locked Input PLL locked signal

Domain

Port Direction Description

tx_parallel_ data[n*s*10–1:0]

tx_digitalreset[n– 1:0]

1:0]

out

Output Parallel data for TX

transceiver

TX transceiver

Output Resets the digital TX

portion of TX transceiver

Output Resets the analog TX

portion of TX transceiver

progress signal from TX transceiver

from TX transceiver

Controller Interface

The controller interface allows you to control the source from an external or on-chip controller, such as the Nios II processor. The controller can control the DisplayPort link parameters and the AUX channel controller.

The AUX channel controller interface works with a simple serial-port-type peripheral that operates in a polled mode. Because the DisplayPort AUX protocol is a master-slave interface, the DisplayPort source (the master) starts a transaction by sending a request and then waits for a reply from the attached sink.

The controller interface includes a single interrupt source. The interrupt notifies the controller of an HPD signal state change. Your system can interrogate the DP_TX_STATUS register to determine the cause of the interrupt. Writing to the DP_TX_STATUS register clears the pending interrupt event.

Related Information

• Multiplexer on page 4-4

• DisplayPort Source Register Map and DPCD Locations on page 9-1

DisplayPort source instantiations require an embedded controller (Nios II processor or another controller) to act as the policy maker.

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AUX Interface

The IP core has three ports that control the serial data across the AUX channel:

• Data input (tx_aux_in)

• Data output (tx_aux_out)

• Output enable (tx_aux_oe). The output enable port controls the direction of data across the bidirec‐ tional link.

These ports are clocked by the source’s 16 MHz clock (aux_clk). The AUX channel’s physical layer is a bidirectional 2.5 V SSTL Class II interface.

The source’s AUX controller allows you to capture all bytes sent from and received by the AUX channel, which is useful for debugging. The IP core provides a standard stream interface that you can use to drive an Avalon-ST FIFO component directly.

Table 4-9: Source AUX Debug Interface Ports

Port Comments

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tx_aux_debug_data[31:0]

tx_aux_debug_valid

tx_aux_debug_sop

tx_aux_debug_eop

tx_aux_debug_err

tx_aux_debug_cha

Related Information

AN 522: Implementing Bus LVDS Interface in Supported Altera Device Families

Video Interface

The core sends video to be encoded through the txN_video_in interface, which provides a standard Hsync and V-sync input with support for interlaced or progressive video. You specify the data input width via a parameter. The same input port transfers RGB and YCbCr data in either 4:4:4 or 4:2:2 color format. Data is most-significant bit aligned and formatted for 4:4:4.

The source AUX debug interface inserts a 1 µs timestamp counter in bits [31:8]; bits [7:0] represent the byte received or transmitted.

Qualifies valid stream data.

Indicates the message packet’s first byte.

Indicates the message packet’s last byte. The last byte should be ignored and is not part of the message.

Indicates if the IP core detects an error in the current byte.

Indicates the direction of the current byte. 1 = byte transmitted by the source, 0 = byte received from the sink.

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47 32 31 16 15 0

txN_vid_data[47:0]

18 bpp RGB

24 bpp RGB/YCBCr444 (8 bpc)

30 bpp RGB/YCBCr444 (10 bpc)

36 bpp RGB/YCBCr444 (12 bpc)

48 bpp RGB/YCBCr444 (16 bpc)

n/2-1 0n - 1 n/2 txN_vid_data[n - 1:0]

71 48 47 24 23 0

txN_vid_data[95:0]

95 72

Pixel 3 Pixel 2 Pixel 1 Pixel 0

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TX Transceiver Interface

Figure 4-4: Video Input Data Format

18 bpp to 48 bpp port width when txN_video_in port width is 48 (16 bpc, 1 pixel per clock)

The following figure shows the sub-sampled 4:2:2 color format for a video port width of n. The mostsignificant half of the video port always transfers the Y component while the least-significant half of the video port transfers the alternate Cr or Cb component. If the Y/Cb/Cr component widths are less than n/2, they must be most-significant bit aligned with respect to the n and n/2-1 boundaries.

Figure 4-5: Sub-Sampled 4:2:2 Color Format Video Port

4-13

If you set the Pixel input mode option to Dual or Quad, the IP core sends two or four pixels in parallel, respectively. To support video resolutions with horizontal active, front porch or back porch of a length not divisible by 2 or 4, the following signals are widened:

• Horizontal and vertical syncs

• Data enable

The following figure shows the pixel data order from least significant bits to most significant bits.

Figure 4-6: Video Input Data Alignment

For RGB 18 bpp when txN_video_in port width is 96 (8 bpc, 4 pixels per clock)

TX Transceiver Interface

The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core. The DisplayPort IP uses a soft 8B/10B encoder. This interface provides TX encoded video data

(tx_parallel_data) in either dual symbol (20-bit) or quad symbol (40-bit) mode and drives the digital

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Transceiver Reconfiguration Interface

reset (tx_digitalreset), analog reset (tx_analogreset), and PLL powerdown signals (tx_pll_powerdown) of the transceiver.

Transceiver Reconfiguration Interface

You can reconfigure the transceiver to accept single reference clock. The single reference clock is a 135MHz clock for all bit rates: RBR, HBR, and HBR2.

• During run-time, you can reconfigure the transceiver to operate in either one of the bit rate by changing TX CMU PLL divide ratio.

When the IP core makes a request, the tx_reconfig_req port goes high. The user logic asserts

tx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds tx_reconfig_busy high. The user logic drives it low when reconfiguration completes.

Note: The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon

power-up.

Related Information

• AN 645: Dynamic Reconfiguration of PMA Controls in Stratix V Devices Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Stratix V Physical Media Attachment (PMA) controls dynamically.

• Altera Transceiver PHY IP Core User Guide Provides more information about how to reconfigure the transceiver for 28-nm devices.

• AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in

Arria V and Cyclone V Devices

Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Arria V Physical Media Attachment (PMA) controls dynamically.

• AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry Provides more information about link tuning.

• Arria 10 Transceiver PHY User Guide Provides more information about how to reconfigure the transceiver for Arria 10 devices.

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Transceiver Analog Reconfiguration Interface

The tx_analog_reconfig interface uses the tx_vod and tx_emp transceiver management control ports. You must map these ports for the device you are using. To change these values, the core drives

tx_analog_reconfig_req high. Then, the user logic sets tx_analog_reconfig_ack high to acknowledge

and drives tx_analog_reconfig_busy high during reconfiguration. When reconfiguration completes, the user logic drives tx_analog_reconfig_busy low.

Secondary Stream Interface

You can transmit the secondary stream data over the DisplayPort main link through the secondary stream (txN_ss) interface. This interface uses handshaking and back pressure to control packet delivery. Internally, the core uses a FIFO to store packets until a slot becomes available on the main link. If the FIFO fills up, the secondary stream interface stops accepting packets and applies back pressure. The packet must be available at the time of sending because the txN_ss port does not support forward pressure.

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nb0

nb1

nb2

nb3

nb4

nb5

nb6

nb7

nb0

nb1

15-Nibble Code Word

for Packet Payload

15-Nibble Code Word

for Packet Header

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Secondary Stream Interface

The txN_ss interface input data format corresponds to four, 15-nibble code words as specified by the DisplayPort version 1.2a specification section 2.2.6.3. The upstream Reed-Solomon encoder supplies these 15-nibble code words. The format differs for header and payload as shown in the following figure.

Figure 4-7: Secondary Stream Input Data Format

4-15

DisplayPort Source

The following figure shows a typical secondary stream packet with a four-byte header (HB0, HB1, HB2 and HB3) and a 32-byte payload (DB0 … DB31). The core calculates the associated parity bytes. The secondary stream interface uses the start-of-packet (SOP) and end-of-packet (EOP) to determine if the current input is a header or payload.

Payloads that only contain the first 16 bytes can assert the EOP on the second cycle to terminate the packet sequence. Data is clocked in to the secondary stream interface through the tx_ss_clk. This clock is the same phase and frequency as the main-link lane 0 clock.

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HB2

HB3

HB1

DB15

DB10

DB9

DB8

DB7

DB14

DB13

DB12

DB11

DB6

DB5

DB4

DB3

DB2

DB1

HB0 DB0

DB31

DB26

DB25

DB24

DB23

DB30

DB29

DB28

DB27

DB22

DB21

DB20

DB19

DB18

DB17

DB16

Data[127:0]

End of Packet

Start of Packet

Valid

4-16

Audio Interface

Figure 4-8: Typical Secondary Stream Packet

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Audio Interface

The audio encoder is upstream of the secondary stream encoder. It generates the Audio InfoFrame, Timestamp, and Audio sample packets from the incoming audio sample data stream. Then, it sends the three packet types to the secondary stream encoder before they are transmitted to the downstream sink device.

The audio port is parameterized for the number of audio channels required in the design. You can use 2 or 8 channels. Each channel’s audio data is sent to the txN_audio_lpcm_data port.

The IP core requires a txN_audio_valid signal for designs in which the txN_audio_clk signal is higher than the actual sample clock. The txN_audio_valid signal qualifies the audio data on the

txN_audio_lpcm_data input.

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7 B3 0 7 B2 0 7 B1 0 7 B0 0

31 24 23 16 15 8 7 0

SP R PR P C U V

MSB Audio Sample Word [23:0] LSB

31 29 28 25 2430 27 26 23 0

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Table 4-10: Audio Signals

Signal Comments

Audio Interface

4-17

txN_audio_clk

txN_audio_valid

txN_audio_mute

txN_audio_lpcm_data[m*321:0]

Audio interface input clock.

Audio input data valid.

When asserted, indicates that audio muting is enabled.

m-channel, 32-bit audio sample data.

Figure 4-9: Audio Sample Data Bits

The packing format uses an IEC-60958-type encoding.

Table 4-11: Audio Sample Bit Field Definitions

Bit Name Bit Position Description

Audio sample word

Byte 2, bits 7:0 Byte 1, bits 7:0 Byte 0, bits 7:0

Audio data. The data content depends on the audio coding type. For LPCM audio, the audio most significant bit (MSB) is placed in byte 2, bit 7. If the audio data size is less than 24 bits, unused least signifi‐ cant bits (LSB) must be zero padded.

V Byte 3, bit 0 Validity flag.

U Byte 3, bit 1 User bit.

C Byte 3, bit 2 Channel status.

P Byte 3, bit 3 Parity bit.

PR Byte 3, bits 4 - 5 Preamble code and its correspondence with IEC-60958 preamble:

00: Subframe 1 and start of the audio block (11101000 preamble) 01: Subframe1 (1110010 preamble) 10: Subframe 2 (1110100 preamble)

R Byte3, bit 6 Reserved bit; must be 0.

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MSA Interface

Bit Name Bit Position Description

SP Byte 3, bit 7 Sample present bit:

1: Sample information is present and can be processed. 0: Sample information is not present. All one-sample channels, used or unused, must have the same

sample present bit value. This bit is useful for situations in which 2-channel audio is

transported over a 4-lane main link. In this operation, main link lanes 2 and 3 may or may not have the audio sample data. This bit indicates whether the audio sample is present or not.

The source automatically generates the Audio InfoFrame and fills it with only information about the number of channels used. Use the audio channel status to provide any information about the audio stream needed by downstream devices.

MSA Interface

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For applications that use a known video source signal, you can remove the added resource of video measurement. In this scenario, the DisplayPort source uses the MSA values presented on the txN_msa_conduit signal bundle shown below:

wire [191:0] txN_msa_conduit = {Mvid[23:0], Nvid[23:0], Htotal[15:0], Vtotal[15:0], HSP, HSW[14:0], Hstart[15:0], Vstart[15:0], VSP, VSW[14:0], Hwidth[15:0], Vheight[15:0], MISC0[7:0], MISC1[7:0]};

Table 4-12: txN_msa_conduit Port Signals

Bit Signal Comments

191:168

167:144

143:128

127:112

111

Mvid[23:0] Mvid for the main video stream. Used for stream clock recovery

Nvid[23:0]

Htotal[15:0] Horizontal total of received video stream in pixels

Vtotal[15:0] Vertical total of received video stream in lines

HSP H-sync polarity 0 = Active high, 1 = Active low

from link symbol clock.

Nvid for the main video stream. Used for stream clock recovery from link symbol clock.

110:96

95:80

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HSW[14:0] H-sync width in pixels

Hstart[15:0] Horizontal active start from H-sync start in pixels (H-sync width

+ Horizontal back porch)

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Bit Signal Comments

Source Clock Tree

4-19

79:64

62:48

47:32

31:16

15:8

7:0

Vstart[15:0] Vertical active start from V-sync start in lines (V-sync width +

Vertical back porch)

VSP V-sync polarity 0 = Active high, 1 = Active low

VSW[14:0] V-sync width in lines

Hwidth[15:0] Active video width in pixels

Vheight[15:0] Active video height in lines

MISC0[7:0] The MISC0[7:1] and MISC1[7] fields indicate the color encoding

format. The color depth is indicated in MISC0[7:5]:

MISC1[7:0]

• 000 - 6 bpc

• 001 - 8 bpc

• 010 - 10 bpc

• 011 - 12 bpc

• 100 - 16 bpc For details about the encoding format, refer to the DisplayPort

v1.2 specification.

Source Clock Tree

The source uses the following clocks:

• Local pixel clock (txN_vid_clk), which clocks video data into the IP core.

• Main link clock (tx_ss_clk), which clocks data out of the IP core and into the high-speed serial output (HSSI) components. The main link clock is the output of the CMU PLL clock. You can supply the CMU PLL with the single reference clock (135 MHz). You can use other frequencies by changing the CMU PLL divider ratios and/or reconfiguring the transceiver. The 20- or 40- bit data fed to the HSSI is synchronized to a single HSSI[0] clock. If you select the dual symbol mode option, this clock is equal to the link rate divided by 20 (270, 135, or 81 MHz). If you turn on quad symbol mode, this clock is equal to the link rate divided by 40 (135, 67.5, or 40.5 MHz).

• 16 MHz clock (aux_clk), which the IP core requires to encode or decode the AUX channel. A separate clock (clk) clocks the Avalon-MM interface.

• txN_audio_clk for the audio interface.

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Front-End

Audio FIFO

Audio

Encoder

Secondary

Stream

Encoder

Front-End Video FIFO

AUX

Controller

Interface

Sync

Back-End

Encoder

Sync

HSSIO0

HSSIO1

HSSIO2

HSSIO3

CMU PLL

tx_ss_clk clk txN_vid_clk aux_clk txN_audio_clk

Legend

Recovered Clock

from Transceiver

(tx_ss_clk) Audio Clock

(txN_audio_clk)

Pixel Clock

(txN_vid_clk)

Secondary

Stream Data

Video Data

clk

aux_clk

DisplayPort Encoder Transceiver Block

270/135/81/67.5/40.5 MHz

Main Link 0

Main Link 1

Main Link 2

Main Link 3

Transceiver Reference Clock Signal(s) from PLL or Dedicated Pin } 135 MHz

Audio Data

4-20

Source Clock Tree

Figure 4-10: Source Clock Tree

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Source

Lane 0 Data (1.62, 2.7, or 5.4 Gbps) Lane 1 Data (1.62, 2.7, or 5.4 Gbps) Lane 2 Data (1.62, 2.7, or 5.4 Gbps) Lane 3 Data (1.62, 2.7, or 5.4 Gbps) AUX Channel (1 Mbps) Hot Plug Detect

Sink

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101 Innovation Drive, San Jose, CA 95134

DisplayPort Sink

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Sink Overview

The DisplayPort sink has a scalable main link with 1, 2, or 4 lanes for a total up to 21.6 Gbps bandwidth. A bidirectional AUX channel with 1 Mbps Manchester encoding provides side-band communication. The sink drives a hot plug detect (HPD) signal to notify the source that a sink is present. Additionally, it provides an interrupt mechanism so that the sink can get the source’s attention.

Figure 5-1: DisplayPort Sink Block Diagram

The AUX channel is an AC-coupled differential pair for bidirectional communication. The signaling is a self-clocked Manchester encoding at 1 Mbps. Like 100-T Ethernet, the encoder uses a preceding synchro‐ nization pattern in each 16-byte maximum packet. The AUX channel uses a master/slave hierarchy in which the source (master) initiates all communication.

Sink Functional Description

The DisplayPort sink has a complete set of parameters for optimizing device resources. The DisplayPort sink consists of a DisplayPort decoder block, a transceiver management block, and a

controller interface block with an Avalon-MM interface for connecting with an embedded controller such as the Nios II processor. You can configure the ports using an RTL wrapper instantiation or implementing the IP core as a Qsys component.

ISO 9001:2008 Registered

DisplayPort Sink

Decoder

rxN_ss rxN_ss_clk

rxN_audio

rxN_video_out rxN_vid_clk

rxN_msa_conduit

rxN_stream

rx_aux aux_clk

rx_params

rx_aux_debug

Secondary Stream

(Avalon-ST Interface)

Audio Output

Video Output

Video Clock

MSA Output

Stream Debug

AUX Interface

AUX Clock

Link Parameters

AUX Debug Stream

(Avalon-ST Interface)

rx_edid EDID Interface

rx_xcvr_interface RX Transceiver Interface

Transceiver Management

clk_cal xcvr_mgmt_clk rx_reconfig

Calibration Clock

Transceiver Management Clock

RX Reconfiguration

Controller Interface

rx_mgmt_interruptInterrupt

rx_mgmt

clk

Avalon-MM Interface Avalon-MM Interface Clock

5-2

Sink Functional Description

Figure 5-2: DisplayPort Sink Top-Level Block Diagram

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Video Output (rxN_video_out)

20-Bit (Dual Symbol)

or 40-Bit (Quad Symbol)

Data from Transceiver

(rx_xcvr_interface)

Bidirectional AUX Data (rx_aux)

AUX Debug Stream (rx_aux_debug)

Avalon-MM (rx_mgmt)

AUX

Controller

HPD

Controller Registers

De-Scrambler DP2ST Gearbox

Decoder

IRQ

Control

VB-ID

Decoder

MSA

Decoder

8B/10B Aligner

DCFIFO

Steering

Secondary Stream (rxN_ss)

HPD

rx_ss_clk clk rxN_vid_clk aux_clk

Legend

Deskew

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Figure 5-3: DisplayPort Sink Functional Block Diagram

Sink Functional Description

5-3

The device transceiver sends 20-bit (dual symbol) or 40-bit (quad symbol) parallel DisplayPort data to the sink. Each data lane is clocked in to the IP core by its own respective clock output from the transceiver. Inside the sink, the four independent clock domains are synchronized to the lane 0 clock. Then, the IP core performs the following actions:

1. The IP core aligns the data stream and performs 8B/10B decoding.

2. The IP core deskews the data and then descrambles it.

3. The IP core splits the unscrambled data stream into parallel paths. a. The SS decoder block performs secondary stream decoding, which the core transfers into the

rx_ss_clk domain through a DCFIFO.

b. The main data path extracts all pixel data from the incoming stream. Then, the gearbox block

resamples the pixel data into the current bit-per-pixel data width. Next, the IP core crosses the pixel data into the rxN_vid_clk domain through a DCFIFO. Finally, the IP core steers the data into a single, dual, or quad pixel data stream.

c. MSA decode path. d. Video decode path.

You configure the sink to output the video data as a proprietary data stream. You specify the output pixel data width at 6, 8, 10, 12, or 16 bpc. This format can interface with downstream Altera Video and Image Processing (VIP) Suite components.

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The AUX controller can operate in an autonomous mode in which the sink controls all AUX channel activity without an external embedded controller. The IP core outputs an AUX debugging stream so that you can inspect the activity on the AUX channel in real time.

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Embedded DisplayPort (eDP) Support

• Full (normal) link training—default

• Fast link training—mandatory eDP feature

Sink Parameters

You set parameters for the sink using the DisplayPort parameter editor.

Table 5-1: Sink Parameters

Parameter Description

Device family Select the targeted device family—Arria V GX,

Arria V GZ, Cyclone V, or Stratix V—matches the project device family.

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Support DisplayPort sink Turn on to enable DisplayPort sink.

Maximum video output color depth Specify the video output interface port bits per color.

Determines top level video output port width (for example, 6 bpc = 18 bits, 16 bpc = 48 bits).

RX maximum link rate Select the maximum link rate. 5.4 Gbps, 2.7 Gbps,

1.62 Gbps Note: Cyclone V devices do not support 5.4

Gbps.

Maximum lane count Select the maximum lanes desired (1, 2, or 4).

Symbol input mode Specify how many symbols are transferred during

each clock cycle (dual or quad symbol), or RX transceiver data width; dual (20 bits) or quad (40 bits).

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Sink Parameters

Parameter Description

Pixel output mode Select the number of pixels per clock (single, dual, or

quad symbol).

• If you select dual pixels per clock, the pixel clock is ½ of the full rate clock and the video port becomes two times wider.

• If you select four pixels per clock, the pixel clock is ¼ of the full rate clock and the video port becomes four times wider.

Sink scrambler seed value Specify the initial seed value for the scrambler block.

Use 16’hFFFF for DP and 16’hFFFFE for eDP.

Invert transceiver polarity Turn on to invert the transceiver polarity.

Export MSA Turn on to enable the sink to export the MSA

interface to the top-level port interface.

5-5

IEEE OUI Specify an IEEE organizationally unique identifier

(OUI) as part of the DPCD registers.

Enable GPU control Turn on to use an embedded controller to control

the sink.

Enable AUX debug stream Turn on to enable AUX traffic output to an

Avalon-ST port.

Support CTS test automation Turn on to support automated test features.

Support secondary data channel Turn on to enable secondary data.

Support audio data channel Turn on to enable audio packet decoding.

Number of audio data channels Specify the number of audio channels supported.

Note: To use this parameter, you must turn on

the Support secondary data channel parameter.

6-bpc RGB or YCbCr 4:4:4 (18 bpp) Turn on to support 18 bpp decoding.

8-bpc RGB or YCbCr 4:4:4 (24 bpp) Turn on to support 24 bpp decoding.

10-bpc RGB or YCbCr 4:4:4 (30 bpp) Turn on to support 30 bpp decoding.

12-bpc RGB or YCbCr 4:4:4 (36 bpp) Turn on to support 36 bpp decoding.

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Sink Interfaces

Parameter Description

16-bpc RGB or YCbCr 4:4:4 (48 bpp) Turn on to support 48 bpp decoding.

8-bpc YCbCr 4:2:2 (16 bpp) Turn on to support 16 bpp decoding. Reserved for

future use.

10-bpc YCbCr 4:2:2 (20 bpp) Turn on to support 20 bpp decoding. Reserved for

future use.

12-bpc YCbCr 4:2:2 (24 bpp) Turn on to support 24 bpp decoding. Reserved for

future use.

16-bpc YCbCr 4:2:2 (32 bpp) Turn on to support 32 bpp decoding. Reserved for

future use.

Support MST Turn on to enable multi-stream support.

You have to turn on Enable GPU control to support MST.

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Max stream count

Select the maximum amount of streams supported (1-4).

Sink Interfaces

The following tables summarize the sink’s interfaces. Your instantiation contains only the interfaces that you have enabled.

Table 5-2: Controller Interface

Interface Port Type Clock Domain Port Direction Description

clk Clock N/A

reset Reset

clk reset

clk

Input Clock for embedded

controller

Input Reset for embedded

controller

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Sink Interfaces

Interface Port Type Clock Domain Port Direction Description

5-7

rx_mgmt_address[8:0]

rx_mgmt_chipselect

rx_mgmt_read

rx_mgmt_write

rx_mgmt AV-MM clk

rx_mgmt_

IRQ clk

rx_mgmt_ writedata[31:0]

rx_mgmt_readdata[31:0]

rx_mgmt_waitrequest

rx_mgmt_irq

irq

Table 5-3: Transceiver Management Interface

Input

Avalon-MM interface for embedded

Input

controller

Outp ut

Output Interrupt for

embedded controller

Interface Port Type Clock Domain Port Direction Description

xcvr_

Clock N/A

mgmt_clk

clk_cal Clock N/A

rx_ reconfig

Conduit

xcvr_mgmt_ clk

xcvr_mgmt_clk

clk_cal Input

rx_link_rate[1:0]

rx_link_rate_ 8bits[7:0]

rx_reconfig_req

Input Transceiver

Output

Outp ut

rx_reconfig_ack

rx_reconfig_busy

Input

management clock

Calibration clock

Transceiver link rate reconfiguration handshaking

Note: Value of rx_link_rate[1:0]: 0=1.62Gbps, 1=2.70Gbps, 2=5.40Gbps; value of rx_link_rate_8bits[7:0]:

0×06=1.62Gbps, 0×0a=2.70Gbps, 0×14=5.40Gbps

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Table 5-4: Video Interface

v is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad), and N is the stream

number.

Interface Port Type Clock Domain Port Direction Description

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rxN_vid_ clk

rxN_ video_out

Clock N/A

Conduit rx_vid_clk

rxN_vid_clk

rxN_vid_valid[p-1:0]

rxN_vid_sol

rxN_vid_eol

rxN_vid_sof

rxN_vid_eof

rxN_vid_locked

rxN_vid_overflow

Input Video clock

Output

Outp ut

Outp

Video output

Outp ut

Table 5-5: AUX Interface

Interface Port Type Clock Domain Port Direction Description

aux_clk Clock N/A

aux_reset Reset

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rxN_vid_data[3v*p-1:0]

aux_clk

aux_clk aux_reset

Outp ut

Input AUX channel clock

Input AUX channel reset

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Sink Interfaces

Interface Port Type Clock Domain Port Direction Description

5-9

rx_aux Conduit aux_clk

rx_aux_ debug

AV-ST aux_clk

rx_aux_in

rx_aux_out

rx_aux_oe

rx_hpd

rx_cable_detect

rx_pwr_detect

rx_aux_debug_ data[31:0]

rx_aux_debug_valid

rx_aux_debug_sop

rx_aux_debug_eop

Input

Outp ut

Input

Output

Outp ut

AUX channel interface

Avalon-ST stream of AUX data for debugging

DisplayPort Sink

rx_aux_debug_err

rx_aux_debug_cha

Outp ut

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Sink Interfaces

Interface Port Type Clock Domain Port Direction Description

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rx_edid_address[7:0]

rx_edid_read

rx_edid_write

EDID

AV-MM aux_clk

(rx_edid)

rx_edid_writedata[7:0]

rx_edid_readdata[7:0]

rx_edid_waitrequest

Table 5-6: Debugging Interface

s is the number of symbols per clock and N is the stream number.

Interface Signal Type Clock

Domain

Port Direction Description

Output

Outp ut

Input

Avalon-MM master interface to external on-chip memory for EDID

Link Parameters (rx_params)

Debugging (rxN_stream)

Conduit

Conduit rx_ss_clk

aux_clk rx_lane_count[4:0]

rxN_stream_ data[4*8*s–1:0]

rxN_stream_ctrl[4*s– 1:0]

rxN_stream_valid

Output Sink current link lane

count value

Output

Outp ut

Raw symbol output

Outp

stream

rxN_stream_clk

Outp ut

Table 5-7: Secondary Interface

N is the stream number; for example, rx_msa_conduit represents Stream 0, rx1_msa_conduit represents Stream

1, and so on .

Interface Signal Type Clock Domain Port Direction Description

rx_ss_clk Clock N/A

rx_ss_clk

Output Clock

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Sink Interfaces

Interface Signal Type Clock Domain Port Direction Description

5-11

MSA (rxN_ msa_ conduit)

Secondary Stream (rxN_ss)

Conduit

AV-ST rx_ss_clk

rx_ss_clk rxN_msa[216:0]

rxN_ss_data[159:0] Output

rxN_ss_valid Outp

rxN_ss_sop Outp

rxN_ss_eop Outp

Output Output for current

MSA parameters received from the source

Secondary stream interface

Table 5-8: Audio Interface

m is the number of RX audio channels. N is the stream number; for example, rx_audio represents Stream 0, rx1_audio represents Stream 1, and so on .

Interface Signal Type Clock

Domain

Port Direction Description

Audio (rxN_audio)

Conduit rx_ss_clk

rxN_audio_lpcm_ data[m*32–1:0]

rxN_audio_valid

rxN_audio_mute

rxN_audio_ infoframe[39:0]

Output

Outp ut

Decoded audio data

Outp ut

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Sink Interfaces

Table 5-9: RX Transceiver Interface

n is the number of RX lanes, s is the number of symbols per clock.

Note: Connect the DisplayPort signals to the Native PHY signals of the same name.

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Interface Port Type Clock

Clock

N/A

Conduit rx_std_

clkout

Conduit

N/A

Conduit rx_xcvr_

clkout

RX transceiver interface

Conduit

N/A

Domain

Port Direction Description

rx_std_clkout[n–1:0]

rx_parallel_ data[n*s*10–1:0]

rx_is_lockedtoref[n– 1:0]

rx_is_ lockedtodata[n–1:0]

rx_bitslip[n–1:0]

rx_cal_busy[n–1:0]

Input RX transceiver

recovered clock

Input Parallel data from RX

transceiver

Input When asserted,

indicates that the RX CDR PLL is locked to the reference clock

Input When asserted,

indicates that the RX CDR PLL is locked to the incoming data

Output Use to control bit

slipping manually

Input Calibration in

progress signal from RX transceiver

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Conduit xcvr_mgmt_

clk

Conduit xcvr_mgmt_

clk

Conduit xcvr_mgmt_

clk

Conduit xcvr_mgmt_

clk

rx_analogreset[n– 1:0]

rx_digitalreset[n– 1:0]

rx_set_locktoref[n– 1:0]

rx_set_locktodata[n– 1:0]

Output When asserted, resets

the RX CDR

Output When asserted, resets

the RX PCS

Output Forces the RX CDR

circuitry to lock to the phase and frequency of the input reference clock

Output Forces the RX CDR

circuitry to lock to the received data

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Controller Interface

The controller interface allows you to control the sink from an external or on-chip controller, such as the Nios II processor for debugging. The controller interface is an Avalon-MM slave that also allows access to the sink’s internal status registers.

The sink asserts the rx_mgmt_irq port when issuing an interrupt to the controller.

Related Information

DisplayPort Sink Register Map and DPCD Locations on page 10-1

AUX Interface

The IP core has three ports to control the serial data across the AUX channel:

• Data input (rx_aux_in)

• Data output (rx_aux_out)

• Output enable (rx_aux_oe). The output enable port controls the direction of data across the bidirec‐ tional link.

The AUX channel’s physical layer is a bidirectional 2.5 V SSTL Class II interface. A state machine decodes the incoming AUX channel’s Manchester encoded data using the 16 MHz clock.

The message parsing drives the state machine input directly. The state machine performs all lane training and EDID link-layer services.

Controller Interface

5-13

The sink’s AUX interface also generates appropriate HPD IRQ events. These events occur if the sink’s main link decoder detects a signal loss.

The sink core uses the rx_cable_detect signal to detect when a source (upstream) device is physically connected and the rx_pwr_detect signal to detect when a source device is powered. These signals are only used with MST mode. You should tie the signals to VCC when the sink is not in MST mode. The sink core keeps the rx_hpd signal deasserted if both the rx_cable_detect and rx_pwr_detect signals are not asserted.

AUX Debug Interface

The AUX controller lets you capture all bytes sent from and received by the AUX channel, which is useful for debugging. The IP core supports a standard stream interface that can drive an Avalon-ST FIFO component directly.

Table 5-10: Sink AUX Debug Interface Ports

The table below describes the stream ports.

Port Comments

rx_aux_debug_data[31:0]

rx_aux_debug_valid

The sink AUX debug interface inserts a 1 µs timestamp counter in bits [31:8]. Bits [7:0] represent the bytes received or transmitted.

Qualifies valid stream data.

rx_aux_debug_sop

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Indicates the message packet’s first byte.

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EDID Interface

Port Comments

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rx_aux_debug_eop

rx_aux_debug_err

rx_aux_debug_cha

EDID Interface

You can use the Avalon-MM EDID interface to access an on-chip memory region containing the sink’s EDID data. The AUX sink controller reads and writes to this memory region according to traffic on the AUX channel.

The Avalon-MM interface uses an 8-bit address with an 8-bit data bus. The interface assumes a read latency of 1.

Note: The IP core does not instantiate this interface if your design uses a controller to control the sink;

for instance when you turn on the Enable GPU control parameter.

Refer to the VESA Enhanced Extended Display Identification Data Implementation Guide for more information.

Indicates the message packet’s last byte. The last byte should be ignored and is not part of the message.

Indicates if the core detects an error in the current byte.

Indicates the direction of the current byte. 1 = byte transmitted by the source. 0 = byte received from the sink.

Debugging Interface

Link Parameters Interface

The sink provides link level data for debugging and configuring external components using the

rx_lane_count port.

Video Stream Out Interface

This interface provides access to the post-scrambler DisplayPort data, which is useful for low-level debugging source equipment. The 8-bit symbols received are organized as shown in the following tables, where n increases with time (at each main link clock cycle, by 2 for dual-symbol mode or by 4 for quadsymbol mode).

Table 5-11: rxN_stream_data Dual-Symbol Mode

Bit Comments

63:56 Lane 3 symbol n + 1

55:48 Lane 3 symbol n

47:40 Lane 2 symbol n + 1

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Bit Comments

39:32 Lane 2 symbol n

31:24 Lane 1 symbol n + 1

23:16 Lane 1 symbol n

15:8 Lane 0 symbol n + 1

7:0 Lane 0 symbol n

Table 5-12: rxN_stream_data Quad-Symbol Mode

Bit Comments

127:120 Lane 3 symbol n + 3

Video Stream Out Interface

5-15

119:112 Lane 3 symbol n + 2

111:104 Lane 3 symbol n + 1

103:96 Lane 3 symbol n

95:88 Lane 2 symbol n + 3

87:80 Lane 2 symbol n + 2

79:72 Lane 2 symbol n + 1

71:64 Lane 2 symbol n

63:56 Lane 1 symbol n + 3

55:48 Lane 1 symbol n + 2

47:40 Lane 1 symbol n + 1

39:32 Lane 1 symbol n

31:24 Lane 0 symbol n + 3

23:16 Lane 0 symbol n + 2

15:8 Lane 0 symbol n + 1

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Line[0]

Line[n]

rxN_vid_data

rxN_vid_valid

rxN_vid_sol

rxN_vid_eol

rxN_vid_sof

rxN_vid_eof

5-16

Video Interface

Bit Comments

7:0 Lane 0 symbol n

When data is received, data is produced on lane 0, lanes 0 and 1, or on all four lanes according to how many lanes are currently used and link trained on the main link. The IP core provides the data output immediately after the data passes through the descrambler and features all control symbols, data, and original timing. As data is always valid at each and every clock cycle, the rxN_stream_valid signal remains asserted.

Video Interface

This interface (rxN_video_out) allows access to the video data as a non-Avalon-ST stream. You can use this stream to interface with an external pixel clock recovery function. The stream provides synchroniza‐ tion pulses at the start and end of active lines, and at the start and end of active frames.

Figure 5-4: Video Out Image Port Timing Diagram

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The rxN_vid_overflow signal is always valid, regardless of the logical state of rxN_vid_valid.

rxN_vid_overflow is asserted for at least one clock cycle when the sink core internal video data FIFO

runs into an overflow condition. This condition can occur when the rxN_vid_clk frequency is too low to transport the received video data successfully.

You specify the maximum data color depth in the DisplayPort parameter editor. The same output port transfers both RGB and YCbCr data in either 4:4:4 or 4:2:2 color format. Data is most-significant bit aligned and formatted for 4:4:4.

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47 32 31 16 15 0

rxN_vid_data[47:0]

18 bpp RGB

24 bpp RGB/YCBCr444 (8 bpc)

30 bpp RGB/YCBCr444 (10 bpc)

36 bpp RGB/YCBCr444 (12 bpc)

48 bpp RGB/YCBCr444 (16 bpc)

n/2-1 0n - 1 n/2 rxN_vid_data[n - 1:0]

71 48 47 24 23 0

rxN_vid_data[95:0]

95 72

Pixel 3 Pixel 2 Pixel 1 Pixel 0

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Video Interface

Figure 5-5: Video Output Data Format

18 bpp to 48 bpp Port Width when rxN_video_out port width is 48 (16 bpc, 1 Pixel per Clock)

The following figure shows the sub-sampled 4:2:2 color format for a video port width of n. The mostsignificant half of the video port always transfers the Y component while the least-significant half of the video port transfers the alternate Cr or Cb component. If the Y/Cb/Cr component widths are less than n/2, they are most-significant bit aligned with respect to the n and n/2-1 boundaries.

Figure 5-6: Sub-Sampled 4:2:2 Color Format Video Port

5-17

If you set the Pixel output mode option to Dual or Quad, the IP core outputs two or four pixels in parallel, respectively. To support video resolutions with horizontal active, front and pack porches with lengths that are not divisible by two or four, rxN_vid_valid is widened. For example, for two pixels per clock, rxN_vid_valid[0] is asserted when pixel N belongs to active video and rxN_vid_valid[1] is asserted when pixel n + 1 belongs to active video.

The following figure shows the pixel data order from least significant bits to most significant bits.

Figure 5-7: Video Output Alignment

For RGB 18 bpp when rxN_video_out Port Width is 96 (8 bpc, 4 Pixels per Clock)

Related Information

Video and Image Processing Suite User Guide

Provides more information about Clocked Video Input.

DisplayPort Sink

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5-18

Clocked Video Input Interface

The rxN_video_out interface may interface with a clocked video input (CVI). CVI accepts the following video signals with a separate synchronization mode: datavalid, de, h_sync, v_sync, f, locked, and data.

The DisplayPort rxN_video_out interface has the following signals: rxN_vid_valid, rxN_vid_sol,

rxN_vid_eol, rxN_vid_sof, rxN_vid_eof, rxN_vid_locked, and rxN_vid_data.

The following table describes how to connect the CVI and DisplayPort sink signals.

Table 5-13: Connecting CVI Signals to DisplayPort Sink Stream 0 Signals

CVI Signal DisplayPort Sink Signal Comment

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vid_data rx_vid_data

vid_datavalid

vid_f

vid_locked rx_vid_locked

vid_de rx_vid_valid

vid_h_sync rx_vid_eol

vid_v_sync rx_vid_eof

– Drive high because the video data is not oversam‐

– Drive low because the video data is progressive.

Video data

pled.

The core asserts this signal when a stable stream is present.

Indicates the active picture region of a line.

The rx_vid_eol signal generates the vid_h_sync pulse by delaying it (by 1 clock cycle) to appear in the horizontal blanking period after the active video ends (rx_vid_valid is deasserted).

The rx_vid_eof signal generates the vid_v_sync pulse by delaying it (by 1 clock cycle) to appear in the vertical blanking period after the active video ends (rx_vid_valid is deasserted).

Example 5-1: Verilog HDL CVI — DisplayPort Sink Example

// CVI V-sync and H-sync are derived from delayed versions of the eol and eof signals

assign vid_data = rx_vid_data;

assign vid_datavalid = 1’b1;

assign vid_f = 1’b0;

assign vid_locked = rx_vid_locked;

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always @ (posedge clk_video) begin rx_vid_h_sync <= rx_vid_eol; rx_vid_v_sync <= rx_vid_eof; end

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assign vid_h_sync = rx_vid_h_sync;

assign vid_de = rx_vid_valid;

assign vid_v_sync = rx_vid_v_sync;

RX Transceiver Interface

The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort IP core. The DisplayPort IP core uses a soft 8B/10B decoder. This interface receives RX transceiver recovered data (rx_parallel_data) in either dual symbol (20-bit) or quad symbol (40-bit) mode, and drives the digital reset (rx_digitalreset), analog reset (rx_analogreset), and controls the CDR circuitry locking mode.

Transceiver Reconfiguration Interface

You can reconfigure the transceiver to accept a single reference clock of 135 MHz for all bit rates: RBR, HBR, and HBR2.

During run-time, you can reconfigure the transceiver to operate in either one of the bit rate by changing RX CDR PLLs divider ratio.

When the IP core makes a request, the rx_reconfig_req port goes high. The user logic asserts

rx_reconfig_ack, and then reconfigures the transceiver. During reconfiguration, the user logic holds rx_reconfig_busy high. The user logic drives it low when reconfiguration completes.

RX Transceiver Interface

5-19

Note:

The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon power-up.

Related Information

• Altera Transceiver PHY IP Core User Guide Provides more information about how to reconfigure the transceiver for 28-nm devices.

• AN 676: Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguration in

Arria V and Cyclone V Devices

Provides more information about using the Transceiver Reconfiguration Controller to reconfigure the Arria V Physical Media Attachment (PMA) controls dynamically.

• AN 678: High-Speed Link Tuning Using Signal Conditioning Circuitry Provides more information about link tuning.

• Arria 10 Transceiver PHY User Guide Provides more information about how to reconfigure the transceiver for Arria 10 devices.

Secondary Stream Interface

The secondary streams data can be received through the rxN_ss interfaces. The interfaces do not allow for back-pressure and assume the downstream logic can handle complete packets. The rxN_ss interface does not distinguish between the types of packets it receives.

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The format of the rxN_ss interface output corresponds to four 15-nibble code words as specified by the DisplayPort 1.2a specification section 2.2.6.3. These 15-nibble code words are typically supplied to the

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nb0

nb1

nb2

nb3

nb4

nb5

nb6

nb7

nb0

nb1

15-Nibble Code Word

for Packet Payload

15-Nibble Code Word

for Packet Header

5-20

Secondary Stream Interface

downstream Reed-Solomon decoder. The format differs for both header and payload, as shown in the following figure.

Figure 5-8: rxN_ss Input Data Format

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The following figure shows a typical secondary stream packet with the four byte header (HB0, HB1, HB2, and HB3) and 32-byte payload (DB0, ..., DB31). Each symbol has an associated parity nibble (PB0, ..., PB11). Downstream logic can use the start-of-packet and end-of-packet to determine if the current input is a header or payload symbol.

Data is clocked out of the rxN_ss port using the rx_ss_clk signal. This signal is the same phase and frequency as the main link lane 0 clock.

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HB2

HB3

HB1

DB15

DB10

DB9

DB8

DB7

DB14

DB13

DB12

DB11

DB6

DB5

DB4

DB3

DB2

DB1

HB0 DB0

DB31

DB26

DB25

DB24

DB23

DB30

DB29

DB28

DB27

DB22

DB21

DB20

DB19

DB18

DB17

DB16

Data[127:0]

End of Packet

Start of Packet

Valid

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Figure 5-9: Typical Secondary Stream Packet

Audio Interface

5-21

Audio Interface

The audio interfaces are downstream from the secondary stream decoder. They extract and decode the audio infoframe packets, audio timestamp packets, and audio sample data.

The audio timestamp packet payload contains M and N values, which the sink uses to recover the source’s audio sample clock. The rxN_audio port uses the values to generate the rxN_audio_valid signal according to sample audio data. Data is clocked out using the rx_ss_clk signal. The rx_ss_clk signal comes from the rx parallel clock from the RX transceiver. This clock runs at link data rate/20 for dual symbol mode and link data rate/40 for quad symbol mode.

The sink generates the rxN_audio_valid signal using the M and N values, and asserts it at the current audio sample clock rate. The rxN_audio_mute signal indicates whether audio data is present on the DisplayPort interface.

DisplayPort Sink

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Audio Sample Period

rxN_audio_lpcm_data

rx_ss_clk

rxN_audio_valid

5-22

MSA Interface

Figure 5-10: rxN_audio Data Output

The captured audio infoframe is available on the audio port. The 5-byte port corresponds to the 5 bytes used in the audio infoframe (refer to CEA-861-D). The audio infoframe describes the type of audio content.

MSA Interface

The rxN_msa_conduit ports allow designs access to the MSA and VB-ID parameters on a top-level port. The following table shows the 217-bit port bundle assignments. The prefixes msa and vbid denote parameters from the MSA and Vertical Blank ID (VB-ID) packets, respectively.

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The sink asserts bit msa_valid when all msa_ signals are valid and deasserts during MSA update. The sink assigns the MSA parameters to zero when it is not receiving valid video data.

The sink asserts the msa_lock bit when the MSA fields have been correctly formatted for the last 15 video frames. Because msa_lock changes state only when msa_valid = 1, you can use its rising edge to strobe new MSA values following an idle video period; for example, when the source changes video resolution. You can use its deasserted state to invalidate received video data.

The sink asserts bit vbid_strobe for one clock cycle when it detects the VB-ID and all vbid_ signals are valid to be read.

Table 5-14: rxN_msa_conduit Port Signals

Bit Signal Comments

216

215

msa_lock

vbid_strobe

0 = MSA fields format error. 1 = MSA fields correctly formatted.

0 = VB-ID fields invalid, 1 = VB-ID fields valid.

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Bit Signal Comments

MSA Interface

5-23

214:209

208:201

200:193

192

191:168

167:144

vbid_vbid[5:0]

VB-ID bit field:

• vbid[0] - VerticalBlanking_Flag

• vbid[1] - FieldID_Flag (for progressive video, this remains

• vbid[2] - Interlace_Flag

• vbid[3] - NoVideoStream_Flag

• vbid[4] - AudioMute_Flag

• vbid[5] - HDCP SYNC DETECT

vbid_Mvid[7:0] Least significant 8 bits of Mvid for the video stream

vbid_Maud[7:0] Least significant 8 bits of Maud for the audio stream

msa_valid 0 = MSA fields are invalid or being updated, 1 = MSA fields

are valid

msa_Mvid[23:0] Mvid value for the main video stream. Used for stream clock

recovery from link symbol clock.

msa_Nvid[23:0]

Nvid value for the main video stream. Used for stream clock recovery from link symbol clock.

143:128

127:112

111

110:96

95:80

79:64

62:48

47:32

31:16

msa_Htotal[15:0] Horizontal total of received video stream in pixels

msa_Vtotal[15:0] Vertical total of received video stream in lines

msa_HSP H-sync polarity 0 = Active high, 1 = Active low

msa_HSW[14:0] H-sync width in pixel count

msa_Hstart[15:0] Horizontal active start from H-sync start in pixels (H-sync

width + Horizontal back porch)

msa_Vstart[15:0] Vertical active start from V-sync start in lines (V-sync width

+ Vertical back porch)

msa_VSP V-sync polarity 0 = Active high, 1 = Active low

msa_VSW[14:0] V-sync width in lines

msa_Hwidth[15:0] Active video width in pixels

msa_Vheight[15:0] Active video height in lines

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5-24

Sink Clock Tree

Bit Signal Comments

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15:8

7:0

msa_MISC0[7:0] The MISC0[7:1] and MISC1[7] fields indicate the color

msa_MISC1[7:0]

Sink Clock Tree

The IP core receives DisplayPort serial data across the high-speed serial interface (HSSI). The HSSI requires a 135 MHz clock for correct data locking. You can supply this frequency to the HSSI using a reference clock provided by an Altera PLL or pins. .

The IP core synchronizes HSSI 20- or 40-bit data to a single HSSI[0] clock that clocks the data into the DisplayPort front-end decoder.

• If you select dual symbol mode, this clock is equal to the link rate divided by 20 (270, 135, or 81 MHz).

• If you turn on quad symbol mode, this clock is equal to the link rate divided by 40 (135, 67.5, or 40.5 MHz).

encoding format. The color depth is indicated in MISC0[7:5]:

• 000 - 6 bpc

• 001 - 8 bpc

• 010 - 10 bpc

• 011 - 12 bpc

• 100 - 16 bpc For details about the encoding format, refer to the Display‐

Port v1.2 specification.

The IP core crosses the reconstructed pixel data into a local pixel clock (rxN_vid_clk) through an output DCFIFO, which drives the pixel stream output. The rxN_vid_clk must be higher than or equal to the pixel clock in the up-stream source. If rxN_vid_clk is slower than the up-stream pixel clock, the DCFIFO overflows. If the rxN_vid_clk is faster than the up-stream source pixel clock, the output port experiences a de-assertion of the valid port on cycles in which pixel data is not available. The optimum frequency is the exact clock rate in the up-stream source. You require pixel clock recovery techniques to determine this clock frequency.

Secondary stream data is clocked by rx_ss_clk. The sink IP core also requires a 16-MHz clock (aux_clk) to drive the internal AUX controller and an Avalon clock for the Avalon-MM interface (clk).

Altera Corporation

DisplayPort Sink

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Audio

Decoder

Back-End

Video FIFO

AUX

Controller

Interface

DCFIFO

Front-End

Decoder

DCFIFO

HSSIO0

HSSIO1

HSSIO2

HSSIO3

rx_ss_clk clk rxN_vid_clk aux_clk

Legend

Recovered Clock from Transceiver (rx_ss_clk)

Audio Data

Pixel Clock (rxN_vid_clk)

Secondary Stream Data

Video Data

clk

aux_clk

DisplayPort DecoderTransceiver Block

270/135/81/67.5/40.5 MHz

Main

Link 0

Main

Link 1

Main

Link 2

Main

Link 3

135 MHz Transceiver Reference Clock Signals from PLL or Dedicated Pin

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Figure 5-11: Sink Clock Tree

Sink Clock Tree

5-25

DisplayPort Sink

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Related Information

Clock Recovery Core on page 6-4

Provides more information about determining the optimum frequency.

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www.altera.com

101 Innovation Drive, San Jose, CA 95134

DisplayPort IP Core Hardware Demonstration

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The Altera DisplayPort hardware demonstration evaluates the functionality of the DisplayPort IP core and provides a starting point for you to create your own design. The example design uses a fully functional OpenCore Plus evaluation version, giving you the freedom to explore the core and understand its performance in hardware.

The design is 4Kp60 capable and performs a loop-through for a standard DisplayPort video stream. You connect a DisplayPort-enabled device—such as a graphics card with DisplayPort interface—to the Transceiver Native PHY RX, and the DisplayPort sink input. The DisplayPort sink decodes the port into a standard video stream and sends it to the clock recovery core. The clock recovery core synthesizes the original video pixel clock to be transmitted together with the received video data. You require the clock recovery feature to produce video without using a frame buffer. The clock recovery core then sends the video data to the DisplayPort source, and the Transceiver Native PHY TX. The DisplayPort source port of the HSMC daughter card transmits the image to a monitor.

If you use another Altera development board, you must change the device assignments and the pin

Note:

assignments. You make these changes in the assignments.tcl file. If you use another DisplayPort daughter card, you must change the pin assignments, Qsys system, and software.

ISO 9001:2008 Registered

DisplayPort IP Core

(Source)

Clock

Recovery

DisplayPort IP Core

(Sink)

User LEDs

Bitec HSMC DisplayPort

Daughter Card

FPGA

FPGA Development Board

Nios II Processor

DisplayPort Source

(nVidia, ATI)

DisplayPort-Enabled

Display

Transceiver Native PHY

(TX)

Transceiver Native PHY

(RX)

6-2

DisplayPort IP Core Hardware Demonstration

Figure 6-1: Hardware Demonstration Overview

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The DisplayPort sink uses its internal state machine to negotiate link training upon power up. A Nios II embedded processor performs the source link management; software performs the link training management.

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DisplayPort IP Core Hardware Demonstration

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Nios II

Processor

Transceiver

Reconfiguration

RX TX

DisplayPort IP Core

Bitec

DisplayPort Core

Qsys System (control .qsys)

Native

PHY

FSM

Management RX/TX (Avalon-MM)

AUX Debug RX/TX (Avalon-ST)

Transceiver

PLL

Video

PLL

Video Clock

160 MHz

AUX Clock 16 MHz

135 MHz

Clock

Recovery

RX TX

Control Clock 60 MHz

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Figure 6-2: Hardware Demonstration Block Diagram

DisplayPort IP Core Hardware Demonstration

6-3

During operation, you can adjust the DisplayPort source resolution (graphics card) from the PC and observe the effect on the IP core. The Nios II software prints the source and sink AUX channel activity. Press a push-button to print the current TX and RX MSAs.

Table 6-1: LED Function

The development board user LEDs illuminate to indicate the function described in the table below.

USER_LED[0]

Arria V/Cyclone V/Stratix V/ Function

USER_LED[1]

USER_LED[2]

USER_LED[3]

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This LED indicates that source is successfully lane-trained and is sending video. rxN_vid_locked drives this LED.

This LED turns off if the source is not driving good video.

This LED illuminates for 1-lane designs.

This LED illuminates for 2-lane designs.

This LED illuminates for 4-lane designs.

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DisplayPort

IP Core

Clock Recovery

IP Core

RX Video

Clock

Video Output Image Port

RX MSA RX Link Rate

RX Link Clock

Video Output Recovered Video Clock

Recovered Video Clock x2

Control

Clock

6-4

Clock Recovery Core

Arria V/Cyclone V/Stratix V/ Function

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USER_LED[7:6]

These LEDs indicate the RX link rate.

• 00 = RBR

• 01 = HBR

• 10 = HBR2

Tip: When creating your own design, note the following design tips:

• The Bitec daughter card has inverted transceiver polarity. When creating your own sink (RX) design,

use the Invert transceiver polarity option to enable or disable inverted polarity.

• The DisplayPort standard reverses the RX and TX transceiver channels to minimize noise for one- or two-lane applications. If you create your own design targeting the Bitec daughter card, ensure that the following signals share the same transceiver channel:

• TX0 and RX3

• TX1 and RX2

• TX2 and RX1

• TX3 and RX0

Refer to the assignments.tcl file for an example of how the channels are assigned in the hardware demonstration.

Clock Recovery Core

The clock recovery core is a single encrypted module called bitec_clkrec.

Figure 6-3: Clock Recovery Core Integration Diagram

The figure below shows the integration diagram of the clock recovery core.

To synthesize the video pixel clock from the link clock, the clock recovery core gathers information about the current MSA and the currently used link rate from the DisplayPort sink.

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Video Timing

Generator

Altera fPLL

Reconfiguration

Controller

fPLL

Reconfiguration

Avalon Master

fPLL

Controller

Loop

Controller

FIFO

Altera fPLLRX Link

Clock

Fill Status

RX Video Clock

Video Input Data Video Output Data

Recovered Video Clock x2

Recovered Video Clock

RX MSA Video Output Syncs

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Clock Recovery Core Parameters

The clock recovery core produces resynchronized video data together with the following clocks:

• Recovered video pixel clock

• Second clock with twice the recovered pixel clock frequency

The video output data is synchronous to the recovered video clock. You can use the second clock as a reference clock for the TX transceiver, which is optionally used to serialize the video output data.

Figure 6-4: Clock Recovery Core Functional Diagram

The following shows a simplified functional diagram of the clock recovery core.

6-5

The clock recovery core clocks the video data input gathered from the DisplayPort sink into a dual-clock FIFO at the received video clock speed. The core reads from the video data input using the recovered video clock.

• Video Timing Generator: This block uses the received MSA to create h-sync, v-sync, and data

enable signals that are synchronized to the recovered video clock.

• Loop Controller: This block monitors the FIFO fill level and regulates its throughput by altering the original Mvid value read from the MSA. The block feeds the modified Mvid to the fPLL Controller, which calculates a set of parameters suitable for the fPLL Controller. This set of parameters provides the value to create a recovered video clock frequency corresponding to the new Mvid value. The calculated fPLL parameters are written by the fPLL Reconfiguration Avalon Master to the Altera fPLL

Clock Recovery Core Parameters

Reconfiguration Controller internal registers.

• Reconfiguration Controller: This block serializes the parameter values and writes them to the Altera fPLL IP core.

• Altera fPLL: Generates the recovered video clock and a second clock with twice the frequency.

You can use these parameters to configure the clock recovery core.

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Clock Recovery Interface

Table 6-2: Clock Recovery Core Parameters

Parameter Default Value Description

SYMBOLS_PER_CLOCK 4 Specifies the configuration of the DisplayPort

RX transceiver used. Set to 2 for 20-bit mode (2 symbols per clock)

or to 4 for 40-bit mode (4 symbols per clock).

CLK_PERIOD_NS 10 Specifies the period (in nanoseconds) of the

clock signal connected to the port. Altera recommends that you set about 60 MHz to achieve timing closure.

DEVICE_FAMILY Arria V Identifies the family of the device used. The

values are Arria V, Stratix V, and Cyclone V.

FIXED_NVID 1* Specifies the configuration of the DisplayPort

RX received video clocking used. Set to 0 for synchronous clocking, where the

value of Nvid is variable. Set to 1 for asynchronous clocking, where the Nvid value is fixed to 32’h8000 (32,768).

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PIXELS_PER_CLOCK 1 Specifies how many pixels in parallel (for

each clock cycle) are gathered from the DisplayPort RX.

Set to 1 for single pixel, 2 for dual, or 4 for four pixels per clock cycle.

BPP 24 Specifies the width (in bits) of a single pixel.

Set to 18 for 6-bit color, 24 for 8-bit color, and so on up to 48 for 16-bit color.

Note: Most DisplayPort source devices transmit video using asynchronous clocking. For optimized

resource usage, Altera recommends you to set parameter FIXED_NVID to 1.

Clock Recovery Interface

The following table lists the signals for the clock recovery core.

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Table 6-3: Clock Recovery Interface Signals

Interface Port Type Clock Domain Port Direction Description

control clock Clock N/A clk Input Control logic clock. This

Clock Recovery Interface

clock runs the loop controller and fPLL reconfiguration related blocks.

Note: Altera

recommends that you set about 60 MHz to achieve timing closure. Set the CLK_

PERIOD_NS

parameter accordingly.

6-7

RX link clock Clock N/A rx_link_clk Input DisplayPort transceiver

link clock. This clock is a divided version of the RX main link clock. , or divided by 4.

• Divided by 2 when the sink core is instantiated in 20-bit mode (2 symbols per clock)

• Divided by 4 when the sink core is instantiated in 40-bit mode (4 symbols per clock)

reset Reset

clk

areset Input Asynchronous reset. This

is an active-high signal.

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Clock Recovery Interface

Interface Port Type Clock Domain Port Direction Description

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RX link rate Conduit

RX MSA Conduit

asynchronousrx_link_

rate[1:0]

rx_link_clk rx_

msa[216:0]

Input DisplayPort RX link rate.

• 00 = RBR (1.67 Gbps)

• 01 = HBR (2.70 Gbps)

• 10 = HBR2 (5.40 Gbps)

You need this informa‐ tion for the clock recovery clock to correctly calculate the fPLL parameters.

Input A set of different signals

containing the following information:

• MSA attributes and status

• VB-ID attributes and status

• Received video blanking timing

You must connect this set of signals as is from the DisplayPort IP core to the clock recovery core.

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Clock Recovery Interface

Interface Port Type Clock Domain Port Direction Description

6-9

Video Input Conduit vidin_clk

vidin_clk

vidin_data

(BPP*PIXEL S_PER_ CLOCK–1:0)

vidin_valid

vidin_sol

vidin_eol

vidin_sof

vidin_eof

vidin_ locked

Input Pixel clock.

Input Pixel data.

Input You must assert this

signal when all signals on this port are valid.

Input Start of video line.

Input End of video line.

Input Start of video frame.

Input End of video frame.

Input You must assert this

signal when the Display‐ Port RX is locked to a valid received video stream.

• 1 = Video locked

• 0 = Video unlocked

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Video Input Port

Interface Port Type Clock Domain Port Direction Description

rec_clk Output Reconstructed video

clock.

rec_clk_x2 Output Reconstructed video

clock double frequency.

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Video Output Conduit rec_clk

vidout

Output Pixel data. (BPP*PIXEL S_PER_ CLOCK–1:0)

hsync Output Horizontal sync. This

signal can be active-high or active-low depending on the sync polarity from MSA.

vsync Output Vertical sync. This signal

can be active-high or active-low depending on the sync polarity from MSA.

de Output Data enable. This signal

is always active high.

field2 Output The clock recovery core

asserts this signal during the second video field for interlaced timings.

Video Input Port

You must connect the clock recovery core video input port to the DisplayPort sink core video output image port.

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reset_out Output The clock recovery core

asserts this signal when the other video output signals are not valid. This signal is asynchronous.

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vidin_data

vidin_valid

vidin_sol

vidin_eol

vidin_sof

vidin_oef

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Transceiver and Clocking

Figure 6-5: Video Input Port Timing Diagram

When the PIXELS_PER_CLOCK parameter is greater than 1, all input pixels are supposed to be valid when you assert vidin_valid. The parameter only supports timings with horizontal active width divisible by 2 (PIXELS_PER_CLOCK = 2) or 4 (PIXELS_PER_CLOCK = 4).

The clock recovery core video output port produces pixel data with standard hsync, vsync, or de timing. All signals are synchronous to the reconstructed video clock rec_clk, unless mentioned otherwise. For designs using a TX transceiver, you can use rec_clk as its reference clock.

You can use rec_clk_x2 as a reference clock for transceivers that have reference clocks with frequencies lower than the minimum pixel clock frequency received. For example, the Video Graphics Array (VGA) 25-MHz resolution when the transceiver's minimum reference clock is 40 MHz.

6-11

The clock recovery core asserts reset_out when the remaining port signals are not valid. For example, during a recovered video resolution change when the rec_clk and rec_clk_x2 signals are not yet locked and stable. Altera recommends that you use reset_out to reset the downstream logic connected to the video output port.

During the hardware demonstration operation, you can adjust the DisplayPort source resolution (graphics card) from the PC and observe the effect on the IP core. The Nios II software prints the source and sink AUX channel activity. Press one of the push buttons to print the current TX and RX MSA.

Transceiver and Clocking

The device’s Gigabit transceivers operate at 5.4, 2.7, and 1.62 Gbps and require a 135-MHz single reference clock. When the link rate changes, the state machine only reconfigures the transceiver PLL settings.

Table 6-4: Arria V Transceiver Native PHY TX and RX Settings

The table shows the Arria V Transceiver Native PHY settings for TX and RX using a single reference clock.

Parameters Single Reference Clock Settings

Datapath Options

Enable TX datapath

Enable RX datapath

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Transceiver and Clocking

Parameters Single Reference Clock Settings

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Datapath Options

Enable standard PCS

Number of data channels

Bonding mode

Enable simplified data interface

1, 2 or 4

Note: If you select 1 or 2, you must

instantiate the PHY instance multiple times for all data channels as per maximum lane count parameter. These values are for non-bonded mode.

×1* or ×N

Note: If you select ×1, you must instantiate

the PHY instance multiple times for all data channels as per maximum lane count parameter. This value is for non-bonded mode.

PMA

Data rate

TX local clock division factor

Enable TX PLL dynamic reconfiguration

Number of TX PLLs

Main TX PLL logical index

Number of TX PLL reference clock

PLL type

Reference clock frequency

2700 Mbps (when TX maximum link rate = 2.7 Gbps)

2 (when TX/RX maximum link rate = 2.7Gbps)

TX PMA

TX PLL0

CMU

135 MHz

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TX PLL0

Transceiver and Clocking

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Selected reference clock source

×1 or ×N

Note: If you select ×1, you must instantiate

Selected clock network

RX PMA

Enable CDR dynamic reconfiguration On Number of CDR reference clocks

Selected CDR reference clock

Selected CDR reference clock frequency

PPM detector threshold

Enable rx_is_lockedtodata port

135 MHz

1000 ppm

the PHY instance multiple times for all data channels as per maximum lane count parameter. This value is for non-bonded mode.

Enable rx_is_lockedtoref port

Enable rx_set_locktodata and rx_set_locktoref ports

Standard PCS

Standard PCS protocol mode

Standard PCS/PMA interface width

Byte Serializer and Deserializer

Enable TX byte serializer

Enable RX byte deserializer

Basic

20 (when symbol output mode is dual)

Off (when symbol output mode is dual)

Note: Currently, only Arria V GX, Arria V GZ, and Stratix V devices support 5.4 Gbps operation.

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Redriver

DisplayPort

Connector

(Source)

Main Link

AUX

Redriver

DisplayPort

Connector

(Sink)

Main Link

AUX

HSMC

Connector

6-14

Required Hardware

The hardware demonstration requires the following hardware:

• Altera FPGA kit (includes USB cable to connect the board to your PC); the demonstration supports the following kits:

• Stratix V GX FPGA Development Kit

• Arria V GX FPGA Starter Kit

• Cyclone V GT FPGA Development Kit

• Arria 10 FPGA Development Kit

• Bitec DisplayPort HSMC daughter card

• PC with a DisplayPort output

• Monitor with a DisplayPort input

• Two DisplayPort cables

• One cable connects from the graphics card to the FPGA development board

• The other cable connects from the FPGA development board to the monitor

Note: Altera recommends that you first test the PC and monitor by connecting the PC directly to the

monitor to ensure that you have all drivers installed correctly.

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The Bitec HSMC DisplayPort daughter card connects Altera FPGA devices to the DisplayPort source and sink devices. High speed 5.4Gbps DisplayPort redrivers are used on both the source and sink signal paths to improve signal integrity. The redrivers ensure close PHY layer compatibility at the DisplayPort connectors.

Figure 6-6: Bitec HSMC Daughter Card

The figure shows a high level diagram of the Bitec HSMC daughter card.

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The following figures illustrate the schematic diagrams of the Bitec HSMC daughter card.

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Figure 6-7: HSMC Connector Schematic Diagram

Required Hardware

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Figure 6-8: TI Redriver to DisplayPort Source Connector Schematic Diagram

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Required Hardware

Figure 6-9: DisplayPort Sink Connector to TI Redriver Schematic Diagram

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Table 6-5: Bitec DisplayPort Daughter Card Signals

The following table describes the signals of the Bitec DisplayPort daughter card with HSMC connector.

Bitec DP Card Signal Bitec Card I/

HSMA_TX_CP[3..0], HSMA_TX_ CN[3..0

HSMC Connector J4A

Input

TX Main Link lane [3..0] differential signals.

Description

In the demonstration design, TX Main Link redriver’s EQ, VOD and pre-emphasis settings are self-configured based on link training. If necessary, you can customize the settings via I2C program‐ ming.

I2C address for TX Main Link redriver: write=0×5C, read=0×5D

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Bitec DP Card Signal Bitec Card I/

HSMC Connector J4A

HSMA_RX_P[3..0], HSMA_RX_N[3..0] Output

RX Main Link lane[3..0] differential signals. The demonstration software sets the RX Main Link

redriver’s EQ settings. Refer to main.c provided in the demonstration software directory.

Depending on the channel condition, you may want to try various combinations of the EQ, VOD/preemphasis settings to achieve optimal link perform‐ ance.

I2C address for RX Main Link redriver: write=0×58, read=0×59.

SCL_CTL, SDA_CTL I/O I

Link redriver EQ, VOD/pre-emphasis settings.

TDO_TDI Not used —

HSMC Connector J4B

RX_CAD Input

Cable Adapter Detect.

Description

C bus signals to configure the TX and RX Main

RX_SENSE_P Output

This is used to select DisplayPort mode or TMDS mode in the Main Link redrivers.

0=DP mode, 1=TMDS mode. The demonstration design selects the DisplayPort

mode(RX_CAD=0).

The sink uses this to detect the presence of the source device.

• 0=Source DisplayPort cable is plugged.

• 1=Source DisplayPort cable is not plugged. When connecting this to the sink rx_cable_detect

(active high) input, inverted signal should be used. In the demonstration design, the rx_cable_detect

input is set to 1 in the RTL.

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HSMC Connector J4B

RX_SENSE_N Output

The sink uses this to detect the source power.

• 0=Source DisplayPort cable is not powered.

• 1=Source DisplayPort cable is powered. This is connected to the sink rx_pwr_detect input. In the demonstration design, the rx_pwr_detect

input is set to 1 in the RTL.

RX_HPD Input

RX Hot Plug Detect. The sink asserts HPD when both rx_cable_detect

and rx_pwr_detect are set to 1 and HPD is enabled.

TX_HPD Output

TX Hot Plug Detect. The HPD pulse duration is used to determine an

HPD event type: Hot Plugging/Unplugging or HPD IRQ.

RX_ENA Input Device enable for RX Main Link redriver. TX_ENA Input Device enable for TX Main Link redriver. AUX_RX_PC, AUX_RX_NC I/O

AUX_RX_DRV_IN Output

AUX_RX_DRV_OE Input

RX AUX channel differential pair. If the external AUX driver/receiver chip,

SN65MLVD200 (U3), is populated on Bitec card, the FPGA device should not drive these differential signals.

To avoid bus contention, remove the on-chip bidirectional buffer, aux_buffer_rx, in the demonstration top module. Instead, the FPGA device should use AUX_RX_DRV_IN, AUX_RX_DRV_OE, and AUX_RX_DRV_OUT signals.

Note: The rx_aux_in and rx_aux_out signals are inverted. If the external AUX driver/receiver chip is used, undo the inversion.

RX AUX channel input. Use this signal if the external AUX driver/

receiver(U3) is populated.

RX AUX channel output enable. Use this signal if the external AUX driver/

receiver(U3) is populated.

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HSMC Connector J4B

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AUX_RX_DRV_OUT Input

TX_CAD, RX_SDA_DDC, RX_SCL_DDC, TX_SDA_DDC, TX_SCL_DDC, fPLL_CLK_ OUT2p, fPLL_CLK_OUT2n

AUX_TX_PC, AUX_TX_NC I/O

Not used —

HSMC Connector J4C

RX AUX channel output. Use this signal if the external AUX driver/

receiver(U3) is populated.

TX AUX channel differential pair. If the external AUX driver/receiver chip,

SN65MLVD200 (U4), is populated on Bitec card, the FPGA device should not drive these differential signals. To avoid bus contention, remove the onchip bidirectional buffer, aux_buffer_tx, in the demonstration top module. Instead, the FPGA device should use AUX_TX_DRV_IN, AUX_TX_DRV_OE, and AUX_TX_DRV_OUT signals.

Note: The tx_aux_in and tx_aux_out signals are inverted. If the external AUX driver/receiver chip is used, undo the inversion.

AUX_TX_DRV_IN Output

TX AUX channel input. Use this signal if the external AUX driver/

receiver(U4) is populated.

AUX_TX_DRV_OE Input

TX AUX channel output enable. Use this signal if the external AUX driver/

receiver(U4) is populated.

AUX_TX_DRV_OUT Input

TX AUX channel output. Use this signal if the external AUX driver/

receiver(U4) is populated.

DP RX Connector J1

CONFIG1 Input Cable Adapter Detect for dual mode support. CONFIG2 Not used — RTN_PWR Input Return signal for DP_PWR.

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DP RX Connector J1

PWR_OUT Output

DP_PWR 3.3V @ 500mA for sink-side cable adapter.

A standard DisplayPort cable must have no wire for this pin.

DP RX Connector J2

CONFIG1 Input Cable Adapter Detect for dual mode support. CONFIG2 Not used — RTN_PWR Input Return signal for DP_PWR. PWR_OUT Output

DP_PWR 3.3V @ 500mA for source-side cable

adapter. A standard DP cable must have no wire for this pin.

Example 6-1: Main Link Re-driver Programming Example

Bitec DP daughter card has Main Link redriver (SN75DP130) that boosts link performance. In typical applications, the redriver EQ, VOD/pre-emphasis levels can be set automatically based on link training. In some cases, you may want to manually configure the settings. The following is an example code that manually configures the redriver EQ, VOD/Pre-emphasis settings.

The bitec_i2c_write() function is called inside main.c in the demonstration

Note:

software. I2C address 0×58 is the write address for the RX redriver.

//********************************************************* // Disable link training (DP130 reg=0×04, data=0×00) //********************************************************* // Disable DP130 link training to enable I2C programming bitec_i2c_write(0×58, 0×04, 0×00);

//********************************************************* // Program link bandwidth settings to HBR2 (DPCD addr=0×00100, data=0×14) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×00); // DPCD add[7:0]=0×00 bitec_i2c_write(0×58, 0×1f, 0×14); // DPCD data=0×14

//********************************************************* // Program lane count to 4 (DPCD addr=0x00101, data=0x4) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×01); // DPCD addr[7:0]=0×01 bitec_i2c_write(0×58, 0×1f, 0×04); // DPCD data=0×4

//********************************************************* // Program VOD Level 1 and Pre-emphasis Level 0 for lane 0 // (DPCD addr=0×00103, data=0×01) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×03); // DPCD addr[7:0]=0×03 bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01

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//********************************************************* // Program VOD Level 1 and Pre-emphasis Level 0 for lane 1 // (DPCD addr=0×00104, data=0×01) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×04); // DPCD addr[7:0]=0×04 bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01

//********************************************************* // Program VOD Level 1 and Pre-emphasis Level 0 for lane 2 // (DPCD addr=0×00105, data=0×01) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×05); // DPCD addr[7:0]=0×05 bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01

//********************************************************* // Program VOD Level 1 and Pre-emphasis Level 0 for lane 3 // (DPCD addr=0×00106, data=0×01) //********************************************************* bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0 bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01 bitec_i2c_write(0×58, 0×1e, 0×06); // DPCD addr[7:0]=0×06 bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01

//************************************************************** // May want to adjust squelch level (DP130 reg=0x03, data=0×08) //************************************************************** bitec_i2c_write(0×58, 0×03, 0×08); // 40mV

6-21

//*************************************** // Enable EQ (DP130 reg=0×05, data=0×80) //*************************************** bitec_i2c_write(0×58, 0×05, 0×80);

//******************************************************************* // Set EQ level to 13dB(HBR2) for lane 0 (DP130 reg=0×05, data=0×85) //******************************************************************* bitec_i2c_write(0×58, 0×05, 0×85);

//******************************************************************* // Set EQ level to 13dB(HBR2) for lane 1 (DP130 reg=0×07, data=0×05) //******************************************************************* bitec_i2c_write(0×58, 0×07, 0×05);

//******************************************************************* // Set EQ level to 13dB(HBR2) for lane 2 (DP130 reg=0×09, data=0×05) //******************************************************************* bitec_i2c_write(0×58, 0×09, 0×05);

//******************************************************************* // Set EQ level to 13dB(HBR2) for lane 3 (DP130 reg=0×0b, data=0×05) //******************************************************************* bitec_i2c_write(0×58, 0×0b, 0×05);

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Design Walkthrough

Example 6-2: Example Hardware Setup

Figure 6-10: Example Hardware Setup Using FPGA Development Board, Bitec Daughter Card, and Cables.

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Related Information

• Altera Stratix V GX FPGA Development Kit

• Arria V GX FPGA Starter Kit

• Cyclone V GT FPGA Development Kit

• Arria 10 FPGA Development Kit

Design Walkthrough

Setting up and running the DisplayPort hardware demonstration consists of the following steps. A variety of scripts automate these steps.

1. Set up the hardware.

2. Copy the design files to your working directory.

3. Build the FPGA design.

4. Build the software, download it into the FPGA, and run the software.

5. Power-up the DisplayPort monitor and view the results.

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Set Up the Hardware

Set up the hardware using the following steps:

1. Connect the Bitec daughter card to the FPGA development board.

2. Connect the development board to your PC using a USB cable. Note: The FPGA development board has an On-Board USB-Blaster™ II connection. If your version of

the board does not have this connection, you can use an external USB-Blaster cable. Refer to the documentation for your board for more information.

3. Connect a DisplayPort cable from the DisplayPort TX on the Bitec HSMC daughter card to a Display‐ Port monitor (do not power up the monitor).

4. Power-up the development board.

5. Connect one end of a DisplayPort cable to your PC (do not connect the other end to anything).

Copy the Design Files to Your Working Directory

In this step, you copy the hardware demonstration files to your working directory. Copy the files using the command:

cp -r <IP root directory>/ altera / altera_dp / hw_demo /<device_board> <working directory>

Set Up the Hardware

6-23

where <device_board> is av_sk_4k for Arria V GX starter kit, cv for Cyclone V GT development kit, and sv for Stratix V development kit.

Your working directory should contain the files shown in the following table.

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Table 6-6: Hardware Demonstration Files

Files are named with <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices).

File Type File Description

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Verilog HDL design files

top.v

bitec_reconfig_alt_<prefix>.v Reconfiguration manager top-level. This

Top-level design file.

module is a high-level FSM that generates the control signals to reconfigure the VOD and pre-emphasis, selects the PLL reference clock, and reconfigures clock divider setting. It loops through all the channels and transceiver settings.

altera_pll_reconfig_core.v

altera_pll_reconfig_mif_reader.v

altera_pll_reconfig_top.v

bitec_cc_fifo.v

bitec_cc_pulse.v

bitec_clkrev.v

bitec_fpll_cntrl.v

bitec_fpll_reconf.v

Clock recovery core encrypted design files.

bitec_loop_cntrl.v

bitec_vsyncgen.v clkrec_pll_<prefix>.v

IP Catalog files video_pll<prefix>.v

pll_135.v

gxb_reconfig.v

gxb_reset.v

gxb_rx.v

gxb_tx.v

IP Catalog variants for the various helper IP cores.

Qsys system control.qsys Qsys system file.

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Build the FPGA Design

File Type File Description

6-25

Quartus II IP files

Scripts

Miscellaneous

Software files (in the software directory)

bitec_reconfig_alt_<prefix>.qip

bitec_clkrec_dist.qip

bitec_clkrec.qip

runall.tcl Script to set up the project, generate the IP and

Quartus II IP files that list the required submodule files.

Qsys system, and compile.

assignments.tcl Top-level TCL file to create the project

assignments.

build_ip.tcl TCL file to build the DisplayPort example

design IP blocks.

build_sw.sh Script to compile the software.

example.sdc Top-level SDC file.

bitec_clkrec.sdc Clock recovery core SDC file.

dp_demo_src\ Directory containing the example application

source code.

btc_dprx_syslib\ System library for the RX API.

btc_dptx_syslib\ System library for the TX API.

Build the FPGA Design

In this step, you use a script to build and compile the FPGA design. Type the command:

./runall.tcl

This script basically builds the IPs and software, as well as performs Quartus full compilation.

Load, and Run the Software

In this step you load the software into the device, and run the software.

1. In a Windows Command Prompt, navigate to the hardware demonstration software directory.

2. Launch a Nios II command shell. You can launch it using several methods, for example, from the

Windows task bar or within the Qsys system.

3. From within the Nios II command shell execute the following command to program the device, download the Nios II program, and launch a debug terminal:

nios2-configure-sof <project_name>.sof <USB cable number>; nios2-terminal<USB cable

number>

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View the Results

Note: To find <USB cable number>, use the jtagconfig command. Note: Refer to the Nios II Software Build Tools Reference chapter in the Nios II Software Developer’s

Handbook for a description of the commands in these scripts.

View the Results

In this step you view the results of the hardware demonstration in the Nios II command shell and on the DisplayPort monitor.

1. Power-up the connected DisplayPort monitor.

2. Connect the free end of the Display Port cable that you connected to your PC to the DisplayPort RX

on the Bitec HSMC daughter card. The PC now has the DisplayPort monitor available as a second monitor. The hardware demonstration loops through and displays the graphic card output as received by the sink core.

Note: Some PC drivers and graphic card adapters do not enable the DisplayPort hardware automati‐

cally upon hot plug detection. You may need to start the adapter’s control utility (e.g., Catalist Control Center, nVidia Control Panel, etc.) and manually enable the DisplayPort display.

Figure 6-11: Loop-through Hardware Demonstration

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3. You can use your graphic card control panel to adjust the resolution of the DisplayPort monitor,

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which typically results in link training, related AUX channel traffic, and a corresponding new image size on the monitor.

Note:

If you do not see visible output on the monitor, press push button (CPU_RESETN) to generate a reset, causing the DisplayPort TX core to re-train the link.

Press push button 0 (USER_PB[0]) to retrieve MSA statistics from the source and sink connections. The Nios II Command Shell displays the AUX channel traffic during link training with the monitor.

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Figure 6-12: MSA Output

View the Results

6-27

The Nios II AUX printout shows each message packet on a separate line.

• The first field is the incremental timestamp in microseconds.

• The second field indicates whether the message packet is from or to the DisplayPort sink (SNK) or

source (SRC).

• The next two fields show the request and response headers and payloads. The DPCD address field

on request messages are decoded into the respective DPCD location names.

When connected and enabled, USER_PB[0] on the development board illuminates to indicate that the DisplayPort receiver has locked correctly.

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101 Innovation Drive, San Jose, CA 95134

DisplayPort IP Core Simulation Example

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The simulation example instantiates the DisplayPort IP core with default settings, TX and RX enabled, and 8 bits per color. The core has the Support CTS test automation parameter turned on, which is required for the simulation to pass.

The test harness instantiates the design under test (DUT) and a VGA driver. It also generates the clocks and top-level stimulus. The design manipulates the tx_mgmt interface in the main loop to establish a link and send several frames of video data. The test harness checks that the sent data’s CRC matches the received data’s CRC for three frames.

ISO 9001:2008 Registered

DisplayPort IP Core

(a10_dp.qsys)

Native PHY IP Core

(gxb_tx.qsys)

Transceiver PHY Reset

Controller IP Core

(gxb_tx_reset.qsys)

Arria 10 Transceiver

ATX PLL IP Core

(gxb_tx_axt_pll.qsys)

Native PHY IP Core

(gxb_rx.qsys)

Reconfiguration

Management

Design Under Test (a10_dp_example.v)

VGA

tx_mgmt tx_video_in

rx_video_out

tx_aux

rx_aux

tx_serial_data

rx_serial_data

clk16clk100 clk135 tx_vid_clk rx_vid_clk

7-2

DisplayPort IP Core Simulation Example

Figure 7-1: Simulation Example Block Diagram for Arria 10 Devices

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DisplayPort IP Core Simulation Example

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rx_video_out

tx_video_in

Design Under Test (<prefix>_dp_example.v)

DisplayPort IP Core

(<prefix>_dp.v)

VGA

Reconfiguration

Management

Transceiver

Reconfiguration

IP Core

tx_mgmt

clk100 clk16clk162 clk270

tx_serial_data

rx_serial_data

tx_aux

rx_aux

tx_vid_clk rx_vid_clk

Native PHY IP Core

(<prefix>_native_phy_tx.v)

Native PHY IP Core

(<prefix>_native_phy_rx.v)

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Design Walkthrough

Figure 7-2: Simulation Example Block Diagram for Arria V and Stratix V Devices

The files are named <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices and sv for Stratix V devices).

7-3

Design Walkthrough

Setting up and running the DisplayPort simulation example consists of the following steps:

1. Copy the simulation files to your target directory.

2. Generate the IP simulation files and scripts, and compile and simulate.

3. View the results.

You use a script to automate these steps.

Copy the Simulation Files to Your Working Directory

Copy the simulation example files to your working directory using the command:

cp -r <IP root directory>/altera/altera_dp/sim_example/<device> <working directory>

where <device> is a10 for Arria 10 devices, av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices.

Your working directory should contain the files shown below.

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Copy the Simulation Files to Your Working Directory

Table 7-1: Simulation Example Files for Arria 10 Devices

File Type File Description

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System Verilog HDL design files

Verilog HDL design files

a10_dp_harness.sv Top-level test harness.

a10_dp_example.v Design under test (DUT).

dp_analog_mappings.v Table translating VOD and pre-emphasis settings.

a10_dp_reconfig_mgmt.v Reconfiguration manager top-level.

a10_dp_rx_reconfig_mgmt.v Reconfiguration manager FSM for an RX.

a10_dp_txpll_reconfig_mgmt.v Reconfiguration manager FSM for a TX.

a10_dp_tx_reconfig_mgmt.v Reconfiguration manager FSM for a TX analog.

clk_gen.v Clock generation file.

freq_check.sv Top-level file for the frequency checker.

rx_freq_check.sv RX frequency checker.

tx_freq_check.sv TX frequency checker.

IP Catalog files

Scripts

vga_driver.v VGA driver (generates a test image).

a10_dp.qsys IP Catalog variant for the DisplayPort IP Core.

gxb_rx.qsys IP Catalog variant for the RX transceiver.

gxb_tx.qsys

gxb_tx_atx_pll.qsys IP Catalog variant for the Transceiver ATX PLL.

gxb_tx_reset.qsys IP Catalog variant for the PHY Reset Controller.

runall.sh This script generates the IP simulation files and scripts,

IP Catalog variant for the TX transceiver.

and compiles and simulates them.

msim_dp.tcl Compiles and simulates the design in the ModelSim

software.

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File Type File Description

all.do Waveform that shows a combination of all waveforms.

reconfig.do Waveform that shows the signals involved in reconfi‐

guring the transceiver.

7-5

Waveform .do files

Miscellaneous

rx_video_out.do Waveform that shows the rx_video_out signals from

the DisplayPort IP core mapped to the CVI input.

tx_video_in.do Waveform that shows the tx_vid_v_sync, tx_vid_h_

sync, de, tx_vid_de, tx_vid_f, and tx_vid_ data[23:0] signals at 256 pixels per line and 8 bpp, i.

readme.txt Documentation for the simulation example.

files

edid_memory.hex Initial content for the EDID ROM.

Table 7-2: Simulation Example Files for Arria V, Cyclone V, and Stratix V Devices

Files are named <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices).

File Type File Description

System Verilog

<prefix>_dp_harness.sv Top-level test harness.

HDL design files

<prefix>_dp_example.v Design under test (DUT).

dp_mif_mappings.v Table translating MIF mappings for transceiver

dp_analog_mappings.v Table translating VOD and pre-emphasis settings.

reconfig_mgmt_hw_ctrl.v Reconfiguration manager top-level.

Verilog HDL design files

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reconfig_mgmt_write.v Reconfiguration manager FSM for a single write

clk_gen.v Clock generation file.

freq_check.sv Top-level file for the frequency checker.

rx_freq_check.sv RX frequency checker.

tx_freq_check.sv TX frequency checker.

reconfiguration.

command.

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Generate the IP Simulation Files and Scripts, and Compile and Simulate

File Type File Description

vga_driver.v VGA driver (generates a test image).

<prefix>_ dp.v IP Catalog variant for the DisplayPort IP Core.

<prefix>_ xcvr_reconfig.v IP Catalog variant for the transceiver reconfiguration

IP Catalog files

core.

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Scripts

Waveform .do files

Miscellaneous files

<prefix>_ native_phy_rx.v

IP Catalog variant for the RX transceiver.

<prefix>_ native_phy_tx.v IP Catalog variant for the TX transceiver.

runall.sh This script generates the IP simulation files and scripts,

and compiles and simulates them.

msim_dp.tcl Compiles and simulates the design in the ModelSim

software.

all.do Waveform that shows a combination of all waveforms.

reconfig.do Waveform that shows the signals involved in reconfi‐

guring the transceiver.

rx_video_out.do Waveform that shows the rx_video_out signals from

the DisplayPort IP core mapped to the CVI input.

tx_video_in.do Waveform that shows the tx_vid_v_sync, tx_vid_h_

sync, de, tx_vid_de, tx_vid_f, and tx_vid_ data[23:0] signals at 256 pixels per line and 8 bpp, i.

readme.txt Documentation for the simulation example.

edid_memory.hex Initial content for the EDID ROM.

Generate the IP Simulation Files and Scripts, and Compile and Simulate

In this step you use a script to generate the IP simulation files and scripts, and compile and simulate them. Type the command:

sh runall.sh

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Generate the IP Simulation Files and Scripts, and Compile and Simulate

This script executes the following commands:

• Generate the simulation files for the DisplayPort, transceivers, and transceiver reconfiguration IP cores:

Arria 10 devices

• qsys-generate a10_dp.qsys -syn -sim

• qsys-generate gxb_rx.qsys -syn -sim

• qsys-generate gxb_tx.qsys -syn -sim

• qsys-generate gxb_tx_atx_pll.qsys -syn -sim

• qsys-generate gxb_tx_reset.qsys -syn -sim

Arria V, Cyclone V, and Stratix V devices; (where <prefix> is av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices)

• qmegawiz -silent <prefix>_xcvr_reconfig.v

• qmegawiz -silent <prefix>_dp.v

• qmegawiz -silent <prefix>_native_phy_rx.v

• qmegawiz -silent <prefix>_native_phy_tx.v

• Merge the four resulting msim_setup.tcl scripts to create a single mentor/msim_setup.tcl: Arria 10 devices

7-7

ip-make-simscript --spd=./a10_dp.spd --spd=./gxb_tx/gxb_tx.spd --spd=./gxb_rx/ gxb_rx.spd --spd=./gxb_tx_atx_pll/gxb_tx_atx_pll.spd --spd=./gxb_tx_reset/ gxb_tx_reset.spd --spd=./gxb_rx_reset/gxb_rx_reset.spd

Arria V, Cyclone V, and Stratix V devices; (where <prefix> is av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices)

ip-make-simscript --spd=./<prefix>_xcvr_reconfig.spd --spd=./<prefix>_dp.spd --spd=./

<prefix>_native_phy_rx.spd --spd=./<prefix>_native_phy_tx.spd

• Compile and simulate the design in the ModelSim software:

vsim -c -do msim_dp.tcl

The simulation sends several frames of video after reconfiguring the DisplayPort source (TX) and sink (RX) to use the HBR (2.7 G) rate. A successful result is seen by the CTS test automation logic’s CRC checks. These checks compare the CRC of the transmitted image with the result measured at the sink. The result is successful if the sink detects three matching frames.

Example 7-1: Example Successful Result

# Testing Link HBR Rate Training Pattern 1 # Testing Video Input Frame Number = 00 # Testing Link HBR Rate Training Pattern 2 # TX Frequency Change Detected, Measured Frequency = 135 MHz # RX Frequency Change Detected, Measured Frequency = 135 MHz # ... # SINK CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40, # SOURCE CRC_R = 9b40, CRC_G = 9b40, CRC_B = 9b40, # Pass: Test Completed

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xcvr_mgmt_clk

rx_link_rate

rx_reconfig_req

rx_reconfig_ack

rx_reconfig_busy

tx_link_rate

tx_vod

tx_emp tx_analog_reconfig_req tx_analog_reconfig_ack

tx_analog_reconfig_busy

tx_reconfig_req

tx_reconfig_ack

tx_reconfig_busy

reconfig_busy

reconfig_mgmt_address

reconfig_mgmt_write

reconfig_mgmt_writedata

reconfig_mgmt_waitrequest

reconfig_mgmt_read

reconfig_mgmt_readdata

7-8

View the Results

You can view the results in the ModelSim GUI by loading various .do files in the Wave viewer.

1. Launch the ModelSim GUI with the vsim command.

2. In the ModelSim Tcl window, execute the dataset open command: dataset open vsim.wlf

3. Select View > Open Wave files.

4. Load the .do files to view the waveforms (refer back to Table 7-1 for a listing of the files).

Figure 7-3: RX Reconfiguration Waveform

In the timing diagram below, rx_link_rate is set to 1 (HBR). When the core makes a request, the

rx_reconfig_req port goes high. The user logic asserts rx_reconfig_ack and then reconfigures the

transceiver. During reconfiguration, the user logic holds rx_reconfig_busy high; the user logic drives it low when reconfiguration completes.

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xcvr_mgmt_clk

rx_link_rate

rx_reconfig_req

rx_reconfig_ack

rx_reconfig_busy

tx_link_rate

tx_reconfig_req

tx_reconfig_ack

tx_reconfig_busy

tx_vod

tx_emp tx_analog_reconfig_req tx_analog_reconfig_ack

tx_analog_reconfig_busy

reconfig_busy

reconfig_mgmt_address

reconfig_mgmt_write

reconfig_mgmt_writedata

reconfig_mgmt_waitrequest

reconfig_mgmt_read

reconfig_mgmt_readdata

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Figure 7-4: TX Reconfiguration Waveform

In the timing diagram below, tx_link_rate is set to 1 (HBR). When the core makes a request, the

tx_reconfig_req port goes high. The user logic asserts tx_reconfig_ack and then reconfigures the

transceiver. During reconfiguration, the user logic holds tx_reconfig_busy high; the user logic drives it low when reconfiguration completes.

View the Results

7-9

DisplayPort IP Core Simulation Example

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xcvr_mgmt_clk

rx_link_rate

rx_reconfig_req

rx_reconfig_ack

rx_reconfig_busy

tx_link_rate

tx_reconfig_req

tx_reconfig_ack

tx_reconfig_busy

tx_vod

tx_emp tx_analog_reconfig_req tx_analog_reconfig_ack

tx_analog_reconfig_busy

reconfig_busy

reconfig_mgmt_address

reconfig_mgmt_write

reconfig_mgmt_writedata

reconfig_mgmt_waitrequest

reconfig_mgmt_read

reconfig_mgmt_readdata

00 00

7-10

View the Results

Figure 7-5: TX Analog Reconfiguration Waveform

In the timing diagram below, tx_vod and tx_emp are both set to 00. When the core makes a request, the tx_analog_reconfig_req port goes high. The user logic asserts tx_analog_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds

tx_analog_reconfig_busy high; the user logic drives it low when reconfiguration completes.

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rx_vid_clk

rx_vid_valid

rx_vid_sol rx_vid_eol rx_vid_sof

ex_vid_eof

rx_vid_data

rx_cvi_datavalid

rx_cvi_f rx_cvi_h_sync rx_cvi_v_sync

rx_cvi_locked

rx_cvi_de

rx_cvi_data

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Figure 7-6: RX Video Waveform

This timing diagram shows an example RX video waveform when interfacing to CVI. The rx_vid_eol signal generates the h_sync pulse by delaying it (by 1 clock cycle) to appear in the horizontal blanking period after the active video ends (VALID is deasserted). The rx_vid_eof signal generates the v_sync pulse by delaying it (by 1 clock cycle) to appear in the vertical blanking period after the active video ends (VALID is deasserted).

Arria 10 Finite-State Machine (FSM)

7-11

DisplayPort IP Core Simulation Example

Arria 10 Finite-State Machine (FSM)

The flow charts show the FSM flow for Arria 10 transceivers.

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FSM_START_RECONFIG

FSM_IDLE

rx_reconfig_req = 1

yes

tx_pll_reconfig_req = 1

yes

A10_dp_txpll_reconfig_mgmt

tx_reconfig_req = 1

yes

A10_dp_tx_reconfig_mgmt

A10_dp_rx_reconfig_mgmt

FSM_END_RECONFIG

rx_reconfig_req | tx_pll_reconfig_req | tx_reconfig_req

7-12

Arria 10 Finite-State Machine (FSM)

Figure 7-7: Reconfiguration Top Manager FSM for Arria 10 Devices

This flow chart shows the reconfiguration FSM flow for Arria 10 transceivers. When the transceiver detects a reconfiguration request (*_reconfig_req), it triggers the reconfiguration manager to reconfigure RX, TX, and TX Analog, and exercise the respective Avalon-MM cycle in sequence.

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DisplayPort IP Core Simulation Example

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Altera DisplayPort MegaCore Function User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

DisplayPort IP Core Quick Reference

About This IP Core

Device Family Support

IP Core Verification

Performance and Resource Utilization

Getting Started

Installing and Licensing IP Cores

OpenCore Plus IP Evaluation

Specifying IP Core Parameters and Options

Simulating the Design

Simulating with the ModelSim Simulator

Compiling the Full Design and Programming the FPGA

DisplayPort Source

Source Overview

Source Functional Description

Main Data Path

Packetizer Path

Measurement Path

Blank Generator Path

Multiplexer

Embedded DisplayPort (eDP) Support

Source Parameters

Source Interfaces

Controller Interface

AUX Interface

Video Interface

TX Transceiver Interface

Transceiver Reconfiguration Interface

Transceiver Analog Reconfiguration Interface

Secondary Stream Interface

Audio Interface

MSA Interface

Source Clock Tree

DisplayPort Sink

Sink Overview

Sink Functional Description

Embedded DisplayPort (eDP) Support

Sink Parameters

Sink Interfaces

Controller Interface

AUX Interface

AUX Debug Interface

EDID Interface

Debugging Interface

Link Parameters Interface

Video Stream Out Interface

Video Interface

Clocked Video Input Interface

RX Transceiver Interface

Transceiver Reconfiguration Interface

Secondary Stream Interface

Audio Interface

MSA Interface

Sink Clock Tree

DisplayPort IP Core Hardware Demonstration

Clock Recovery Core

Clock Recovery Core Parameters

Clock Recovery Interface

Video Input Port

Transceiver and Clocking

Required Hardware

Design Walkthrough

Set Up the Hardware

Copy the Design Files to Your Working Directory

Build the FPGA Design

Load, and Run the Software

View the Results

DisplayPort IP Core Simulation Example

Design Walkthrough

Copy the Simulation Files to Your Working Directory

Generate the IP Simulation Files and Scripts, and Compile and Simulate

View the Results

Arria 10 Finite-State Machine (FSM)