Altera Device-Specific Power Delivery Network User Manual
2015.03.06
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Device-Specific Power Delivery Network (PDN) Tool
2.0 User Guide
UG-01157
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This user guide provides a brief overview of the various tabs in the device-specific PDN tool 2.0. You can
quickly and accurately design a robust power delivery network with the PDN tool 2.0. This is done by
calculating an optimum number of capacitors that meet the target impedance requirements for a given
power supply.
Note: The PDN tool 2.0 only supports Microsoft Excel 2007 and newer, and either US or UK English
language.
Table 1: PDN Tool 2.0 Software Verification
Altera® has tested and verified that the PDN tool 2.0 is compatible with these platforms and software versions.
Operating System Excel Versions
Windows 8 (32-bit) 2007, 2010, 2013
Windows 8 (64-bit) 2010, 2013
Windows 7 (32-bit) 2007, 2010, 2013
Windows 7 (64-bit) 2010, 2013
Windows XP 2007, 2010
Overview
The Altera PDN tool 2.0 helps PCB designers estimate the number, value, and type of decoupling
capacitors needed to develop an efficient PCB decoupling strategy. It allows you to do this during the
early design phase, without going through extensive pre-layout simulations.
The PDN tool 2.0 is a Microsoft Excel-based spreadsheet that calculates an impedance profile based on
your input. For a given power supply, the spreadsheet only requires basic design information to calculate
the impedance profile and the optimum number of capacitors to meet the desired impedance target
(Z
TARGET
specifications, for example. The tool also provides device- and power rail-specific PCB decoupling cut-off
frequency (F
estimate and not as a specification. For an accurate impedance profile, Altera recommends a post-layout
simulation approach using any available EDA tool, such as Sigrity PowerSI, Ansoft SIWave, Cadence
Allegro PCB PI, and so on.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
). Basic design information includes the board stackup, transient current information, and ripple
EFFECTIVE
). The results obtained through the PDN tool 2.0 are intended only as a preliminary
ISO
9001:2008
Registered
Lc1
Cc1
Rc1
Lmnt1
Lc2
Cc2
Rc2
Lmnt2
Lc3
Cc3
Rc3
Lmnt3
Lc N
Cc N
Rc N
Lmnt N
Rp
Cp
Planar
R and C
(4)
Rs Ls
Rv Lv
Spreading R and L
(3)
BGA Via R and L
(3)
Rvrm Lvrm
VRM Model
(1)
Decoupling CAP Model
(2)
Altera
FPGA Device
VRM
Notes:
1. You can define or change VRM parameters in the Library sheet of the PDN tool.
2. You can define or change Decoupling CAPs parameters in the Cap Mount, X2Y Mount, and Library sheets of the PDN tool.
3. Rs and Ls are parasitic capacitances and inductances from BGA balls and PCB traces and connections.
4. Represents PCB layers dedicated to power and ground planes.
2
PDN Decoupling Methodology Review
The device families supported by the Altera device-specific PDN tool 2.0 are shown at the top of the
Release Notes tab and they include:
• Arria® 10
• Arria V
• Arria II GZ
• Cyclone® V
• Cyclone IV E
• Cyclone IV GX
• Stratix® V
• MAX® 10
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The PDN tool 2.0 provides two parameters for guiding PCB decoupling design: Z
PDN Circuit Topology
The PDN tool 2.0 is based on a lumped equivalent model representation of the power delivery network
topology.
Figure 1: PDN Topology Modeled as Part of the Tool
The PDN impedance profile is the impedance-over-frequency looking from the device side.
TARGET
and F
EFFECTIVE
.
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Z
TARGET
=
Voltage Rail ×
100
Die Noise Tolerance%
( )
Maximum Dynamic Current Change
Z
TARGET
=
2 × 0.5
0.09 Ω
=
1.8 × 0.05
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Z
TARGET
3
For first order analysis, the VRM can be simply modeled as a series-connected resistor and inductor as
shown above. The VRM has a very low impedence and can respond to the instantaneous current require‐
ments of the FPGA in the following circumstances:
• At low frequencies up to approximately 50 KHz
• Depending on the voltage regulation module you use
The equivalent series resistance (ESR) and equivalent series inductance (ESL) values can be obtained from
the VRM manufacturer. At higher frequency, the VRM impedance is primarily inductive, making it
incapable of meeting the transient current requirement.
PCB decoupling capacitors are used for reducing the PDN impedance up to 100-150 MHz. The on-board
discrete decoupling capacitors provide the required low impedance. This depends on the capacitorintrinsic parasitics (RcN, CcN, LcN) and the capacitor mounting inductance (L
). The inter-planar
mntN
capacitance between the power-ground planes typically has lower inductance than the discrete decoupling
capacitor network, making it more effective at higher frequencies up to 150 MHz. As frequency increases,
the PCB decoupling capacitors become less effective. The limitation comes from the parasitic inductance
seen with respect to the FPGA. FPGA parasitic inductance includes capacitor mounting inductance, PCB
spreading inductance, ball grid array (BGA) via inductance, and packaging parasitic inductance. All of
these parasitics are modeled in the PDN tool 2.0 to capture the effect of the PCB decoupling capacitors
accurately. To simplify the circuit topology, all parasitics are represented with lumped inductors and
resistors despite the distributed nature of PCB spreading inductance.
Z
TARGET
Figure 2: Z
Figure 3: Z
According to Ohm’s law, voltage drop across a circuit is proportional to the current flow through the
circuit, and impedance of the circuit. The dynamic component of PDN current gives rise to voltage
fluctuation within the PDN, which may lead to logic and timing issues. You can reduce excessive voltage
fluctuation by reducing PDN impedance. One design guideline is target impedance, Z
TARGET
. Z
TARGET
defined using the maximum allowable die noise tolerance and dynamic current change, and is calculated
as follows.
Equation
TARGET
For example, to reliably decouple a 1.8-volt power rail that allows 5% of die noise tolerance and a
maximum 2 A current draw, 50% of which is dynamically changing, the desired target impedance is
calculated as follows.
Example Equation
TARGET
is
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Z
TARGET
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To accurately calculate the Z
TARGET
for any power rail, you must know the following information:
• The maximum dynamic current change requirements for all devices in the system that are powered by
the power rail under consideration. You can obtain this information from manufacturers of the
respective devices. You can calculate the maximum dynamic current change of a device using the
maximum total current and the dynamic current change percentage.
Note: The dynamic current change is intended to parameterize the high-frequency current draws
required to provide the energy for CMOS transistors changing state. In the case of the core rail,
the transients are generated by switching inside the FPGA core. Thus, a design which involves
extensive logical switching generates higher % transients (dynamic current change) than a more
static design. For information about recommended settings, refer to the table in the Introduc‐
tion tab of the PDN tool 2.0.
Note: You can obtain accurate estimations on the maximum total current for Altera devices using the
Altera PowerPlay Early Power Estimator (EPE) tool or the Quartus® II PowerPlay Power
Analyzer tools.
• The maximum allowable die noise tolerance on the power rail is given as a percentage of the supply
voltage.
Device switching activity leads to transient noise (high frequency spikes) seen on the power supply rails.
This noise can cause functionality issues if they are too high. The noise must be damped within a range
defined as a percentage of power supply voltage. The recommended values for the maximum allowable
AC die noise tolerance are listed in the Introduction tab of the PDN tool 2.0. Different rails have different
specifications because of their sensitivity to the transient voltage noise as well as how much current is used
by the power rail.
This AC die noise tolerance differs from the minimum and maximum voltage specifications in the device
datasheet in that the voltage specifications in the device datasheet are DC values. The (DC) ripple of the
voltage regulator module (VRM) is the change in the power supply voltage level. Altera devices are
designed to operate within a specific voltage range, which is considered the DC specification. The DC
specification is, in turn, translated to the requirement for the VRM ripple specification. This DC specifica‐
tion is not included in the die noise tolerance field in the PDN tool 2.0.
Refer to the Introduction tab of the PDN tool 2.0 for more information about Z
TARGET
.
Table 2: Settings for the Arria 10 Device Power Rails
This information is from the PDN tool 2.0 for an Arria 10 device.
Rail Name
(1)
Voltage (V) Die Noise
Tolerance (%)
Dynamic Current
Change (%)
Description
VCC 0.85 - 0.9 5 50 Core
VCCIO 1.2 - 3.0 5 100 I/O Bank
VCCPT 1.8 5 50 I/O Pre-Drivers
VCCPGM 1.2/1.5/1.8 5 50 Programming Power
(1)
For more information about power rail functions, refer to the Pin Connection Guidelines for the selected
device family.
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Z
TARGET
5
Rail Name
(1)
Voltage (V) Die Noise
Tolerance (%)
Dynamic Current
Change (%)
Description
VCCERAM 0.95 5 50 Programmable Power
Tech Aux
VCCBAT 1.2/1.5/1.8 5 100 Battery Back-up Power
Supply
VCCA_PLL 1.8 5 10 PLL (Analog)
VCCA_FPLL 1.8 5 10 FPLL
VCCR_GXB 0.9/1.0/1.1 3 30
XCVR
RX (Analog)
VCCT_GXB 0.9/1.0/1.1 2 60
XCVR
TX (Analog)
VCCA_GXB 0.9/1.0/1.1 5 10
XCVR
/CDB (Analog)
VCCH_GXB 0.9/1.0/1.1 3 15 XCVR I/O Buffer Block
VCCR_GTB 0.9/1.0/1.1 3 30 28 Gbps XCVR RX
(Analog)
VCCT_GTB 0.9/1.0/1.1 2 60 28 Gpbs XCVR TX
(Analog)
VCCP 0.9 5 33 Periphery Supply
Voltage
Related Information
• Altera PowerPlay Early Power Estimator (EPE)
• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines.
• MAX 10 Device Family Pin Connection Guidelines.
• Stratix V E, GS, and GX Device Family Pin Connection Guidelines.
• Stratix V GT Device Family Pin Connection Guidelines.
• Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines.
• Arria II Device Family Pin Connection Guidelines.
• Cyclone V Device Family Pin Connection Guidelines.
• Cyclone IV Device Family Pin Connection Guidelines.
(1)
For more information about power rail functions, refer to the Pin Connection Guidelines for the selected
device family.
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F
EFFECTIVE
F
EFFECTIVE
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As previously illustrated, a capacitor reduces PDN impedance by providing a least-impedance route
between power and ground. Impedance of a capacitor at high frequency is determined by its parasitics
(ESL and ESR). For a PCB-mount capacitor, the parasitics include not only the parasitic from the
capacitors themselves but also those associated with mounting, PCB spreading, and packaging. Therefore,
PCB capacitor parasitics are generally higher than those of on-package decoupling capacitor and on-diecapacitance. Decoupling using PCB capacitors becomes ineffective at high frequency. Using PCB
capacitors for PDN decoupling beyond their effective frequency range brings little improvement to PDN
performance and raises the bill of materials (BOM) cost.
To help reduce over-design of PCB decoupling, this release of the PDN tool provides a suggested PCB
decoupling design cut-off frequency (F
EFFECTIVE
package, and die parasitics. You only need to design PCB decoupling that keeps Z
F
EFFECTIVE
.
) as another guideline. It is calculated using the PCB,
under Z
EFF
TARGET
up to
Refer to Troubleshooting Z
EFF
if the Z
too high.
Note: F
EFFECTIVE
may not be enough when the Altera FPGA device shares a power rail with another
device. The noise generated from other devices propagates along the PDN and affects FPGA device
performance. The frequency of the noise is determined by the transfer impedance between the
noise source and the FPGA device, and can be higher than F
inductance and increasing the isolation between the FPGA device and noise source reduces this
risk. You must perform a transfer impedance analysis to clearly identify any noise interference risk.
Related Information
• Troubleshooting ZEFF on page 27
• For more information about the PDN decoupling methodology behind the Altera PDN design
tool, refer to the Power Distribution Network Design Using Altera PDN Design Tools online
course.
Major Tabs of the PDN Tool 2.0
The tabs at the bottom of the PDN tool 2.0 application help you calculate your impedance profile.
Table 3: PDN Tool 2.0 Tabs
Tab Description
is too high or the number of capacitors for decoupling becomes
EFF
EFFECTIVE
. Reducing PDN parasitic
Release_Notes Provides the legal disclaimers, the revision history of the tool,
Introduction
Altera Corporation
and the user agreement.
Displays the schematic representation of the circuit that is
modeled as part of the PDN tool 2.0. It also provides the
following related information:
• a quick start instruction
• recommended settings for some power rails
• a brief description of decoupling design procedures under
different power supply connection schemes
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System_Decap
Tab Description
System_Decap The principal tab that allows you to decouple your system. It
displays by default when you launch the application. This tab
provides an interface to enter your power sharing scheme for a
selected FPGA device and derive the decoupling based on the
input.
Stackup Provides an interface to enter your stackup information into the
PDN tool.
Library Points to various libraries (capacitor, dielectric materials, and so
on) that are called by other tabs. You can change the default
values listed as part of these libraries.
BGA_Via Provides an interface to calculate the BGA mounting inductance
based on design-specific via parameters and the number of vias.
Plane_Cap Provides an interface to calculate the plane capacitance based on
design-specific parameters.
Cap_Mount Provides an interface to input design-specific parameters for
calculating the capacitor mounting inductance for two different
capacitor orientations (Via on Side [VOS] and Via on End
[VOE]).
7
X2Y_Mount Provides an interface to input design-specific parameters for
calculating the capacitor mounting inductance for X2Y type
capacitors.
Enlarged_Graph Provides an enlarged view of the Z-profile shown in the System_
Decap tab.
System_Decap
You can determine the decoupling of selected FPGA devices based on the power sharing scheme entered
in the System_Decap tab.
The System_Decap tab is divided into the following sections:
• Device selection
• Power rail data and configuration
• VRM Data
• Rail group summary
• VRM Impedance
• BGA Via
• Plane
• Spreading
• F
EFFECTIVE
• Decoupling selection
• Result summary
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Device Selection Section
Device Selection Section
1. Select the Family/Device using the pull-down list.
2. Select your device from the Available Devices pull-down list.
3. Select your desired power rail configuration from the Power Rail Configuration pull-down list.
The pull-down selections are based on examples from the pin connection guidelines for the device. Select
the closest one to your design, and use it as a basis for entering your design data. Refer to the pin
connection guidelines for your device on the Altera website.
The tool updates the list of power rails and the contents in the power rail configuration sections based on
your selections.
Figure 4: Device Selection
Related Information
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• Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines.
• MAX 10 Device Family Pin Connection Guidelines.
• Stratix V E, GS, and GX Device Family Pin Connection Guidelines.
• Stratix V GT Device Family Pin Connection Guidelines.
• Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines.
• Arria II Device Family Pin Connection Guidelines.
• Cyclone V Device Family Pin Connection Guidelines.
• Cyclone IV Device Family Pin Connection Guidelines.
Power Rail Data and Configuration Section
This section of the application is divided into two areas. Area 1 is for the device power rail information,
and Area 2 is for the power rail configuration.
1. Enter the power supply voltage in the Voltage column for each power rail listed in Area 1 by selecting
a value from the pull-down menu, or by manually entering your own value.
Note:
You must enter the total current consumption of related power rails before you can use the
system decoupling function.
You can optionally adjust the recommended number up or down slightly based on knowledge of the
intended application.
2. Enter the current consumption in the I max column for each power rail.
The earliest data from the Altera PowerPlay Early Power Estimator (EPE) can provide good values for
the current entries. The EPE delivers bulk data for the transceiver channels. Each bank of transceiver
channels should be assigned the total EPE value divided by the number of banks. Later in the design
cycle, the Quartus II Power Play Power Analyzer (PPPA) can derive much better data for each bank
rail.
3. Setup your device power sharing scheme in Area 2.
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Power Rail Data and Configuration Section
Figure 5: Power Rail Data and Power Sharing Scheme Section
This configuration is an example of how this section of the spreadsheet should look. Every design will
vary slightly.
9
Each column in Area 2 represents a power group in your system. Add or remove a power group using
the Add Group or Remove Group buttons. The first row of each group is the Regulator/Separator
type. Set the source type for the power group and available options from the pull-down list as switcher,
linear, or filter.
The second row is the Parent Group type. The available options for this row are None and the number
representing all listed power groups. Input your power sharing hierarchy in this column, and set the
power rail connection using the remaining rows.
Note:
The PDN tool 2.0 defines the power rail configuration using the Parent/Child power group. A
power group is a child power group if it attaches to another power group. The other power
group is the parent group in this case. A parent group can have multiple child groups. A parent
power group number is required for the child group. The parent group number of a parent
power group is assigned to None because the group has no parent group.
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