Altera Data Conversion HSMC User Manual
Data Conversion HSMC
Reference Manual
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document Version: 1.1
Document Date: November 2008
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services
.
MNL-01041-1.1
Contents
Chapter 1. Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Components and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Chapter 2. Board Components and Interfaces
Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
A/D Converter Clock Select Jumper (J3, J7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Power Down Select Jumper (J2, J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
D/A Converter Clock Select Jumper (J15, J17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Mode Select Jumper (J11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Gain Select Jumper (J10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Sleep Select Jumper (J13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
External Clock Output Select Jumper (J23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
External Clock Input SMA Connectors (J26, J30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
External Clock Output SMA Connectors (J25, J28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Component Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
A/D Converter (U1, U2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
A/D Converter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
A/D Converter Input SMA Connector (J4, J8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
D/A Converter (U3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11
D/A Converter Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13
D/A Converter Output SMA Connector (J12, J14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Audio CODEC Converter (U5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14
Audio Jacks (J19, J20, J21, J42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
HSMC Connector (J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15
2
I
C Serial EEPROM (U14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
A/D Power Supplies (U6, U7, U8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17
Appendix A. Pin-Out Information for the Cyclone III (3C120) Development Board
Appendix B. Pin-Out Information for the Stratix III (3SL150) Development Board
Appendix C. Pin-Out Information for the Cyclone III (3C25) Starter Board
Additional Information
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
Preliminary
iv Contents
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
Preliminary
General Description
Data Conversion HSMC
Cyclone III FPGA Development Board
This manual provides information about the Data Conversion High-Speed Mezzanine
Card (HSMC). You can use the HSMC to develop digital signal processing (DSP)
applications with Altera
The Data Conversion HSMC provides a set of analog to digital (A/D) and digital to
analog (D/A) interfaces including an audio coder/decoder (CODEC) interface. This
manual describes each of the hardware interfaces on the Data Conversion HSMC.
f For the latest information about HSMC, go to
www.altera.com/products/devkits/kit-index.html.
1. Overview
®
development boards that feature the HSMC connector.
Figure 1–1 shows the Data Conversion HSMC connected to the Cyclone
development board.
Figure 1–1. Data Conversion HSMC Connected to the Cyclone III FPGA Development Board
f For more information, refer to the DSP Development Kit Getting Started User Guide.
®
III FPGA
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
1–2 Chapter 1: Overview
A/D Channel A
External Clock Input
14-Bit - 150 MS/s
A/D Converter
SMA
SI
CKT
XT_CLK
XT_CLK
SI
CKT
A/D Channel B
SI
CKT
CLK
SEL
14-Bit - 150 MS/s
A/D Converter
SI
CKT
DATA
CNTL
ADA_DCO
ADB_DCO
160 Pin
HSMC
Connector
CLK_A
CLK_B
XT_CLK
14-Bit - 250 MS/s
D/A Converter
SI
CKT
SI
CKT
CLK_A
CLK_B
CLK_A
CLK_B
ADA_DCO
ADB_DCO
SI
CKT
SI
CKT
D/A Channel A
D/A Channel B
14-Bit - 250 MS/s
D/A Converter
SI
CKT
DATA
DATA
DATA
CNTL
Stereo Audio
CODEC
Line in
Mic in
Line out
Headphone
SI
CKT
Note: SI Circuit consists of
a BALUN and Terminators
SMA
SMA
SMA
1/8
"
Phone
Jack
1/8
"
Phone
Jack
1/8
"
Phone
Jack
1/8
"
Phone
Jack
SMA
SMA
CLK_A
CLK_B
XT_CLK
CLK_A
CLK_B
XT_CLK
CLK_A
CLK_B
XT_CLK
External Clock Output
DATA
CNTL
Components and Block Diagram
Components and Block Diagram
Components
The Data Conversion HSMC contains the following components:
■ Interfaces
■ HSMC interface
■ Audio CODEC interface
■ External Clock In interface
■ External Clock Out interface
■ A/D Converter Channels A and B Input interface
■ D/A Converter Channels A and B Output interface
■ Power Supply
2
■ I
C Serial EEPROM
Block Diagram
Figure 1–2 shows the functional block diagram of the Data Conversion HSMC.
Figure 1–2. Data Conversion HSMC Block Diagram
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
2. Board Components and Interfaces
Board Overview
This chapter provides operational and connectivity details about the Data Conversion
HSMC’s major components and interfaces.
Board schematics, board layout database, and assembly files for the Data Conversion
HSMC are included in the board_design_files subdirectory of the installed kit
directory. For information about powering up the Data Conversion HSMC and
installing the demo software and examples, refer to the user guide provided with
your kit.
Figure 2–1 shows the layout and components of the Data Conversion HSMC.
Figure 2–1. Data Conversion HSMC Layout and Components
Differential to LVDS
(U9, U10, U11, U12, U13)
Multiplexer
2
IC
Serial
EEPROM (U14)
LVDS Driver
(U15)
LVDS Receiver (U4)
External Clock ln-n
(J30)
External Clock Out-n
(J28)
External Clock ln-p
(J26)
External Clock Out-p
(J25)
Audio
CODEC
Converter
A/D Converter
Channel A (U1)
Channel B (U2)
D/A Converter
Channel A and
Channel B (U3)
A/D Converter Input
Channel A (J4)
Channel B (J8)
D/A Converter Output
Channel A (J12)
Channel B (J14)
Line ln
(J19)
Mic Connecter
(J42)
Headphone
(J21)
Line Out
(J20)
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
2–2 Chapter 2: Board Components and Interfaces
Board Overview
Figure 2–2 shows the back view of the Data Conversion HSMC.
Figure 2–2. Data Conversion HSMC—Back View
HSMC Connector (J1)
Tab le 2– 1 lists the components and their corresponding board references.
Table 2–1. Data Conversion HSMC Feature Overview (Part 1 of 2)
Board Reference Name Description Page
Configuration, Status, and Setup Elements
J3 (Channel A)
J7 (Channel B)
A/D converter clock select
jumper
Controls which of the three input clock signals
(FPGA clock A, B, or the external SMA clock) is routed
to the A/D converter.
J2 (Channel A)
J6 (Channel B)
J15 (Channel A)
J17 (Channel B)
Power down select jumper Controls whether the A/D converter operates in
power down or power up state.
D/A converter clock select
jumper
Controls which of the three input clock signals
(FPGA clock A, B, or the external SMA clock) is routed
to the D/A converter.
J11 Mode select jumper Controls whether the D/A converter operates in dual
bus mode or interleaved mode.
J10 Gain setting select jumper Controls whether the D/A converter channel’s gain is
set through one or two resistors.
J13 Sleep select jumper Controls whether the D/A converter operates in
power down or power up state.
J23 External clock output select
jumper
Selects which of the four input clocks (FPGA clock A, B
or A/D converter Data Clock Output) is routed to the
SMA clock out (J28).
Clock
J26 (External Clock In-p)
J30 (External Clock In-n)
External clock input SMA
connectors
SMA connectors for a differential clock input. 2–6
2–3
2–4
2–4
2–5
2–5
2–5
2–6
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
Chapter 2: Board Components and Interfaces 2–3
Configuration, Status, and Setup Elements
Table 2–1. Data Conversion HSMC Feature Overview (Part 2 of 2)
Board Reference Name Description Page
J25 (External Clock Out-p)
J28 (External Clock Out-n)
Components and Interfaces
U1 (Channel A)
U2 (Channel B)
J4 (Channel A)
J8 (Channel B)
U3 (Channels A and B) D/A converter Texas Instruments DAC5672. 14-bit, 175 MS/s
J12 (Channel A)
J14 (Channel B)
U5 Audio CODEC Texas Instruments TLV320AK23. Stereo Audio CODEC,
J19 Line-in audio jack 3.5-mm audio connector for line-in 2–15
J20 Line-out audio jack 3.5-mm audio connector for line-out 2–15
J21 Headphone jack 3.5-mm audio connector for headphone 2–15
J42 Mic jack 3.5-mm audio connector for microphone 2–15
J1 HSMC Expansion connector used to interface with Altera
U14 I
External clock output SMA
connectors
A/D converter Analog Devices AD9254. 14-bit, 150 MS/s ADC 2–7
A/D converter input SMAs SMAs that drive the A/D converter inputs 2–11
D/A converter output SMAs SMA outputs for the D/A converters 2–14
2
C EEPROM ISSI EEPROM IS24C02B, 2 Kbits 2–16
SMA connectors for a differential clock output 2–7
2–11
D/A converter
2–14
96 KHz, with integrated headphone amplifier
2–15
development boards
Configuration, Status, and Setup Elements
This section describes configuration, status, and setup elements.
A/D Converter Clock Select Jumper (J3, J7)
Tab le 2– 2 lists the J3 (channel A) and J7 (channel B) jumper settings used to select the
A/D converter clock.
Table 2–2. A/D Converter Clock Select Jumper (J3, J7) Settings (Part 1 of 2)
Schematic Signal Name
Clock Source Board Reference
FPGA Clock HSMC Connector FPGA_CLK_A_P
FPGA Clock HSMC Connector FPGA_CLK_B_P
External Clock External Clock Input SMA XT_IN_P
(1), (2), (3)
FPGA_CLK_A_N
FPGA_CLK_B_N
XT_IN_N
A/D Converter Clock Select (J3 or J7)
Jumper Setting
Pins 3 and 5
Pins 4 and 6
Pins 1 and 3
Pins 4 and 6
Pins 3 and 5
Pins 2 and 4
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
2–4 Chapter 2: Board Components and Interfaces
Configuration, Status, and Setup Elements
Table 2–2. A/D Converter Clock Select Jumper (J3, J7) Settings (Part 2 of 2)
Schematic Signal Name
Clock Source Board Reference
(1), (2), (3)
No Clock — NO_CLK_P
NO_CLK_N
Notes to Table 2–2:
(1) Refer to the appendices for FPGA pin numbers for specific development boards.
(2) On the schematic, MUX (U9) output signal names are ADA_CLK_SEL_P and ADA_CLK_SEL_N.
(3) On the schematic, MUX (U10) output signal names are ADB_CLK_SEL_P and ADB_CLK_SEL_N.
A/D Converter Clock Select (J3 or J7)
Jumper Setting
Pins 1 and 3
Pins 2 and 4
Power Down Select Jumper (J2, J6)
The power down configuration of the A/D converter is selectable through J2 (channel
A) or J6 (channel B). Table 2–3 lists the jumper settings for power down options. A/D
converters should be powered down when not used to reduce spurious noise output.
Table 2–3. Power Down Select Jumper Settings for AD9254 A/D Converter (U1, U2)
A/D Converter Jumper Settings (1) Description
U1 (Channel A) J2 Jumper OFF A/D converter channel A in normal (operational) state
U1 (Channel A) J2 Jumper ON A/D converter channel A in power down
U2 (Channel B) J6 Jumper OFF A/D converter channel B in normal (operational) state
U2 (Channel B) J6 Jumper ON A/D converter channel B in power down
Note to Table 2–3:
(1) If jumper pins are left open, A/D converter will be in normal state.
D/A Converter Clock Select Jumper (J15, J17)
Tab le 2– 4 lists the J15 (channel A) and J17 (channel B) jumper settings used to select
the D/A converter clock.
Table 2–4. D/A Converter Clock Select Jumper (J15, J17) Settings
Schematic Signal Name
Clock Source Board Reference
FPGA Clock HSMC Connector FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA Clock HSMC Connector FPGA_CLK_B_P
FPGA_CLK_B_N
External Clock External Clock Input SMA XT_IN_P
XT_IN_N
No Clock — NO_CLK_P
NO_CLK_N
Notes to Table 2–4:
(1) On the schematic, MUX (U11) output signal names are DAC_CLK_1_P and DAC_CLK_1_N.
(2) On the schematic, MUX (U12) output signal names are DAC_CLK_2_P and DAC_CLK_2_N.
(1) , (2)
D/A Converter Clock Select (J15
or J17) Jumper Setting
Pins 3 and 5
Pins 4 and 6
Pins 1 and 3
Pins 4 and 6
Pins 3 and 5
Pins 2 and 4
Pins 1 and 3
Pins 2 and 4
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
Chapter 2: Board Components and Interfaces 2–5
Configuration, Status, and Setup Elements
Mode Select Jumper (J11)
The mode select jumper is used to put the D/A converter in either dual bus or
interleaved mode. It is selectable through J11 (channel A and channel B). Tab le 2– 5
lists the jumper settings for mode select options.
Table 2–5. Mode Select Jumper (J11) Settings for DAC5672 D/A Converter
Jumper Settings (J11) Description
Jumper ON Interleaved mode
Jumper OFF Dual bus mode
Gain Select Jumper (J10)
The gain setting select jumper is used to set gain of the D/A converter’s channels. It is
selectable through J10 (channel A and channel B). Table 2–6 lists the jumper settings
for gain settings options.
Table 2–6. Gain Select Jumper (J10) Settings for DAC5672 D/A Converter
Jumper Settings
(J10) Description
Jumper ON Sets gain of channel A through RSET on BiasJ_A pin, and of channel B
through RSET on BiasJ_B pin.
Jumper OFF Gain of channels A and B is set through RSET on BiasJ_A pin only and
RSET on BiasJ_B pin is ignored.
Sleep Select Jumper (J13)
The sleep select jumper is used to put the D/A converter in power down mode. It is
selectable through J13 (channel A and channel B). Table 2–7 lists the jumper settings
for sleep select options. The D/A converter when not in use should be put in sleep
mode.
Table 2–7. Sleep Select Jumper (J13) Settings for DAC5672 D/A Converter
Jumper Settings
(J13) Description
Jumper ON Puts D/A converter in power down mode
Jumper OFF D/A converter in normal state
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
2–6 Chapter 2: Board Components and Interfaces
External Clock In
J26 LTI-SASF54GT
XT_CK_IN_N
J30
54
3
2
XT_CK_IN_P
1
54
3
2
R75
1
Unipolar
XT_CK_IN_UNI
R111
0
R112
Bipolar
0
XT_CK_IN_BI
4
5
6
T6
3
2
1
TT1_8_KK91
PS
VTT_XCK
XT_IN_P
1.00K, 1%
XT_IN_N
1.00K, 1%
3.3 V
R78
C70
0.1µF
LTI-SASF54GT
Clocks
External Clock Output Select Jumper (J23)
Tab le 2– 8 lists the external clock output select jumper (J23) settings.
Table 2–8. External Clock Output Select Jumper (J23) Settings
Schematic Signal Name
Clock Source Board Reference
(1)
FPGA Clock HSMC Connector FPGA_CLK_A_P
FPGA_CLK_A_N
FPGA Clock HSMC Connector FPGA_CLK_B_P
FPGA_CLK_B_N
A/D A DCO A/D Channel A ADA_DCO_P
ADA_DCO_N
A/D B DCO A/D Channel B ADB_DCO_P
ADB_DCO_N
Note to Table 2–8:
(1) On the schematic, MUX (U13) output signal names are RX_CLK_P and RX_CLK_N.
Clocks
This section describes the external clock input and output SMA connectors.
External Clock Input SMA Connectors (J26, J30)
The CLK SMA connector (J26 or J30) provides an external clock input. It can be
selected to be the input to U1, U2, and U3 (Figure 2–3). An external clock input
provides (while using a particular design) the flexibility to use the same external clock
source for the entire system under test. If you choose to use a single-ended clock, R112
must be removed and R111 be installed.
External Clock Output Select
Jumper (J23) Settings
Pins 3 and 5
Pins 4 and 6
Pins 1 and 3
Pins 4 and 6
Pins 3 and 5
Pins 2 and 4
Pins 1 and 3
Pins 2 and 4
Figure 2–3. External Clock Input Schematic
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
Chapter 2: Board Components and Interfaces 2–7
Component Interfaces
External Clock Output SMA Connectors (J25, J28)
The CLK SMA connector (J25 or J28) provides an external clock output. Different
clocks can be selected by using differential LVDS multiplexer (U13) and clock select
jumper (J23) (Figure 2–4). The external clock source provides (while using a particular
design) the flexibility to alter the input frequency to verify f
choose to use a single-ended clock, R110 must be removed and R109 be installed.
Figure 2–4. External Clock Output Schematic
External Clock Out
tolerances. If you
MAX
RX_CLK_P
RX_CLK_N
Component Interfaces
This section describes the user interfaces, which consist of the A/D converter, D/A
converter, audio CODEC converter, HSMC connector, and I
A/D Converter (U1, U2)
The Data Conversion HSMC contains two AD9254 14-bit 150 MS/s A/D converters.
This device is designed for high-speed and high-performance applications.
The inputs to these A/D converters are transformer-coupled in order to create a
balanced input. The signal-to-noise ratio for the system is up to 72 dB for input signals
from 1 MHz to the Nyquist frequency of the converter. The maximum differential
input voltage to the converter is 2 VPP. Usable voltage input to the SMA connector is
approximately 512 mV when driven from a 50-Ω source.
4
5
NC
6
ADT1_1WT
T7
1
PS
XT_CK_OUT_UNI
2
XT_CK_OUT_BI
3
Bipolar
R110
0
XT_CK_OUT_P
R109
Unipolar
0
LTI-SASF54GT
XT_CK_OUT_N
2
J25LTI-SASF54GT
1
5432
J28
1
5432
C Serial EEPROM.
Tab le 2– 9 lists the A/D converter board reference and manufacturing information.
Table 2–9. A/D Converter Component Reference
Board Reference Device Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U1, U2 14-bit, 150 MS/s A/D converter Analog Device AD9254 www.analog.com
© November 2008 Altera Corporation Data Conversion HSMC Reference Manual
2–8 Chapter 2: Board Components and Interfaces
Component Interfaces
Tab le 2– 10 provides the pin-out details of the A/D converter channel A.
Table 2–10. A/D converter Channel A (U1) Pin-Out Information
Device
HSMC Signal HSMC Pin Device Signal
Pin Number Description
ADA_D0 79 D0 45 Data Output Bit 0
ADA_D1 77 D1 46 Data Output Bit1
ADA_D2 73 D2 1 Data Output Bit 2
ADA_D3 71 D3 2 Data Output Bit 3
ADA_D4 67 D4 3 Data Output Bit 4
ADA_D5 65 D5 4 Data Output Bit 5
ADA_D6 61 D6 5 Data Output Bit 6
ADA_D7 59 D7 6 Data Output Bit 7
ADA_D8 55 D8 9 Data Output Bit 8
ADA_D9 53 D9 10 Data Output Bit 9
ADA_D10 49 D10 11 Data Output Bit 10
ADA_D11 47 D11 12 Data Output Bit 11
ADA_D12 43 D12 13 Data Output Bit 12
ADA_D13 41 D13 14 Data Output Bit 13
ADA_OR 83 OR 15 Out-of-Range Indicator
AD_SDIO 91 SDIO/DCS 18 Serial Port Interface (SPI) Data
Input/Output (Serial Port Mode)
AD_SCLK 92 SCLK/DFS 19 Serial Port Interface Clock (Serial Port
Mode)
ADA_SPI_CS 89 CSB 20 Serial Port Interface Chip Select
(Active Low)
ADA_OE 85 OEB 43 Output Enable (Active Low)
ADA_DCO 156 DCO 44 Data Clock Output
——ADA_CLK_P 38 (1) Clock Input
——ADA_CLK_N 39 (2) Clock Input
——ADA_PWDN
Notes to Table 2–10:
(1) This pin is connected to Multiplexer pin U9.15.
(2) This pin is connected to Multiplexer pin U9.14.
(3) This pin is connected to Jumper pin J2.2.
36 (3) Power-Down Function Select
Tab le 2– 11 provides the pin-out details of the A/D converter channel B.
Table 2–11. A/D Converter Channel B (U2) Pin-Out Information (Part 1 of 2)
Device
HSMC Signal HSMC Pin Device Signal
Pin Number Description
ADB_D0 80 D0 45 Data Output Bit 0
ADB_D1 78 D1 46 Data Output Bit1
ADB_D2 74 D2 1 Data Output Bit 2
ADB_D3 72 D3 2 Data Output Bit 3
Data Conversion HSMC Reference Manual © November 2008 Altera Corporation
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